On-chip Timers of

Microcontroller 8051
 D Flip-Flop and Counters

D Flip Flop One bit counter

Clock State Next State
(Qn)
0 Qn-1
1 D
(At negative
clock edge)

Function table of D Flip Flop Timing Diagram for a one-bit counter

 State Timer
Output
(Q2Q1Q0)
Introduction to Timers
0 000
1 001
2 010
3 011 Timer
4 100 Running

5 101
6 110
7 111
0 000 Timer
Overflow
(Flag=1)
1 001 Timer
Running…
… …
Timers/Counters: Introduction
 A timer/counter is a series of divide-by-2 flip flops that receives an input signal as a
clocking source (or clock signal). The clock signal causes the output of timer to change
 Each negative edge of clocking source causes a state change.
 The clock signal is applied to the first flip-flop which divides the frequency of input clock
signal by 2.
 When the output of one flip-flop is used to clock the second flip-flop, a series of such
successive n-stages will divide the applied input clock frequency by 2n.
 The frequency of the output pulse from the last stage is then Fclk/2n. Where Fclk is the
frequency of input clock signal to the timer.
 In timers, individual steady output status for each count is known as a state. For example in
a 3 bit counter there are 8 states (State0-State7). In state 7 the output lines of all the flip-
flops is 1. (111 for a 3 bit counter/timer).
 After state 7, when the next input clock arrives, state 0 again reappears. Technically, at this
moment, the counter/timer hardware is said to have “Overflown”.
 Timer overflow is an event when all the output pins of timer has changed to all 0’s from all
1’s
 It may be observed that the applied clock input causes timer overflow after 2n clock
transitions, where n=bit size of timer/counter hardware (in our example n=3)
Timers: Introduction
 Considering the input clock frequency to be of Fclk; The time required for
each state change is 1/Fclk.
 In case of an N bit counter; there are total 2N states, after which the timer overflow
occurs (Assuming the starting state to be state0).
 Thus 2N/Fclk amount of time elapses and then the timer overflow event occurs,
(Assuming the starting state to be state0)
 For an 8 bit timer with input clock of 1 MHz; the timer overflow will occur after 28/1
µs, or 256 µs. (Assuming the starting state to be state0)
 For a 16 bit timer with input clock of 1 MHz, the timer overflow will occur after
216/1 µs, or 65536 µs (Assuming the starting state to be state0)
 In case of an N bit counter; there are total (2N–S) states before timer overflow occurs
(Assuming the starting state to be state S).
 Thus (2N – S)/Fclk amount of time elapses before timer overflow event occurs,
(Assuming the starting state to be state S)
 For an 8 bit timer with input clock of 1 MHz; the timer overflow will occur after (28 -
255)/1 µs, or 1 µs. (Assuming the starting state to be state 255 or FFH)
 For a 16 bit timer with input clock of 16 MHz, the timer overflow will occur after
(216 -65535)/1 µs, or 1 µs (Assuming the starting state to be state 65535 or state
FFFFH in hex)
Timers/Counters: Applications
 Interval Timing Applications (or Timing signal generation)
 The internal clock pulse is used for input clocking source to the counter hardware
 The timer is programmed to overflow at a regular interval of time and the user
gets notified via the timer overflow flag (it gets set whenever timer overflow
occurs)
 To Implement timing generation tasks: Timed switching operations, to introduce
time delay between two events, digital timers
 External Event counting applications (or counting tasks)
 An external event is an external stimulus/reason that provides a 1-0 signal
transition (via a properly designed circuit) at the clock input of the hardware
counter.
 Event counting is a process to count the number of times an event has occurred
 Examples: Counting applications, Pulse width measurements, frequency
measurement etc.
 Baud rate generation for serial communication
On-chip timers of 8051

 Microcontroller applications require the counting of external events, or

generation of precise time delays between computer actions.
 Both these tasks can be accomplished by using software techniques, but
software loops for counting or timing may miss the timing events and also it
hogs the processor to prevent it from performing something more
important.
 Hardware Timer/counters are provided in 8051 to perform timing/counting
tasks in a dedicated and accurate manner.
 There are Two 16 bit timers/counter hardware; Timer 0 and Timer 1
 Four operational modes for timers are available.
 The clocking source is derived from either processor clock (timer operation) or
from external pulsing source (Counter operation)
On-chip timers of 8051
 Two 16 bit timers/counter hardware
 Timer Registers
 Timer 0: TH0 (8 bit), TL0 (8 Bit)
 Timer 1: TH1 (8 bit), TL1 (8 Bit)
 Control Registers
 TMOD: Contains timer mode control bits
 TCON: Contains timer run bits and Timer overflow interrupt bits
 Counter pins
 T0 (P3.4)
 T1 (P3.5)
 Interrupt flags
 Timer 0 (TF0)
 Timer 1 (TF1)
TCON register
TMOD register
Timer/counter Logic diagram
Operational modes of timer: Mode 0 and Mode 1
𝟏
𝑻𝑫 = 𝑻𝑶𝑽 (µs)= 𝒇𝒐𝒔𝒄(𝑴𝑯𝒛) × (𝟐𝑵 − 𝑰), 𝑰 = 𝟐𝑵 −
𝑻𝑫 ×𝒇𝒐𝒔𝒄(𝑴𝑯𝒛)
ൗ𝟏𝟐 𝟏𝟐
where ,
fosc(MHz) = Frequency of oscillator in MHz
N= Bit size of the counter
I = Initial state of Timer
 MODE 0: 13 bit timer/counter mode
𝑇𝐷 𝑚𝑎𝑥 = 213 µ𝑠
= 8192 µ𝑠
For fosc(MHz)=12 MHz

 Mode 1: 16-bit timer/counter mode

𝑇𝐷 𝑚𝑎𝑥 = 216 µ𝑠
= 65536 µ𝑠
For fosc(MHz)=12 MHz
Operational modes of timer: Mode 2

 8-bit auto reload mode

Operational modes of timer: Mode 3

 Split timer counter mode (Only Timer 0)

Methods to produce delay in 8051

 Software delay (using delay loop)

 Polling method (software polling of a hardware flag)
 Hardware delay (Using ISR of timer overflow interrupt to perform events)
 Software Delay
Instruction Machine Instruction Machine
cycles cycles
required required
PUSH A 2 MOV R0, #n 1

POP A 2 BACK: PUSH A 2

NOP 1 POP A 2

NOP 1 NOP 1
NOP 1

Time required: 6 (m/c)×12 clock DJNZ R0, BACK 2

pulses/(12 MHz Clock frequency)
Machine cycles required: 8 ×n+1
= 6 µ sec
Time required: (8n+1) ×12 clock pulses/(12 MHz
Clock frequency)
= (8n+1) µ sec
= 1001 µ sec (for n=125D)
Software Delay
• Machine cycles required M:
Instruction Machine • (8 × n1+1+2) × n2+1
cycles • Time required: Mx12 clock pulses/(12 MHz Clock
required frequency)

MOV R1, #n2 1 = 10,011 µ sec (for n1=125D, n2=10 and 12 MHz
clock)
BACK2: MOV R0, #n1 1 • Toverhead= (10,011-10,000)=11 µ sec
• % error = (Toverhead) ×100/Tdesired = 0.11%
BACK1: PUSH A 2
POP A 2
NOP 1
NOP 1
DJNZ R0, BACK1 2
DJNZ R1, BACK2 2
Software Delay subroutine
• Machine cycles required M:
Instruction Machine • 2 (LCALL)+(8 × n1+1+2) × n2+1+2(RET)
cycles • Time required: Mx12 clock pulses/(12 MHz Clock
required frequency)

DELAY: MOV R1, #n2 1 = (8n+1) µ sec = 10,015 µ sec (for n1=125D,
n2=10 and 12 MHz clock)
BACK2: MOV R0, #n1 1 • Toverhead= (10,015-10,000)=15 µ sec
• % error = Toverhead×100/Tdesired = 0.15%
BACK1: PUSH A 2
POP A 2
NOP 1
NOP 1
DJNZ R0, BACK1 2
DJNZ R1, BACK2 2
RET 2
A program to toggle a port pin every 10 ms by
using software delay program. Assume fclk=12 MHz
ORG 0000H
MOV SP, #2FH
MOV P0, #00H
SETB P0.0
MOV A, #10
BACK: LCALL DELAYSOFT_MS
CPL P0.0
SJMP BACK

ORG 00F0H
DELAYSOFT_MS: MOV R1, A Delay (uS)= 2 (LCALL)+(8 × n1+1+2) × n2+1+2(RET)
BACK1: MOV R2, #125 Assuming n1=125
BACK2: PUSH A Calculate n2= ?
POP A Then round off n2
NOP
NOP
DJNZ R2, BACK2
DJNZ R1, BACK1
RET
END
Producing a delay using software polling method
IE: Interrupt Enable
register
 In this method execution delay
between two instructions is produced TCON
by restricting the program execution
to continuously check a hardware TMOD
flag till it attains a desired value.
 In this method, a timer is initialized, ORG 0000H
configured, and started. The program MOV P0,#00H ; Make port 0 as output
control is then made to repeatedly
check the overflow flag (effectively, MOV IE, #00H ; Disable timer 0 overflow interrupt
the program control is made to wait) MOV TMOD, #01H; Configure Timer 0 in mode 1
as long as the timer overflow flag ITER: MOV TH0, #0D8H; Load MSB of initial count value
remains at logic 0 state (i.e. while the
timer keeps running). MOV TL0,#0F0H; Load LSB of initial count value
 Only when timer overflow flag MOV TCON, #10H; Timer 0 is started and TF0 is
becomes 1 (timer overflows), the manually reset
program control proceeds to HERE: JNB TF0, HERE ; 10 ms software polled timer delay
execute next instructions.
MOV TCON, #00H; Stop the Timer and Reset TF0
 Consider the program to CPL A ; Complement A
complement Port 0 after 10 ms using
timer 0 software polling method for MOV P0, A
12 MHz clock SJMP ITER; Continue infinitely
END
Write a program to produce a delay of 500ms by
software polling method (with interrupts enabled)
ORG 0000H
MOV P0,#00H IE: Interrupt Enable register
MOV IE, #82H
MOV TMOD, #01H
TCON
SETB P0.0
ITER: MOV R0,#50
TMOD
BACK: MOV TH0, #0D8H
MOV TL0,#0F0H
MOV TCON, #10H ; TIMER STARTED
HERE: JNB TF0, HERE ; 10 ms software polled timer delay
CLR TF0 ; This step is not required as interrupt is enabled
CLR TR0 ; TIMER STOPPED 𝟏
𝑻𝑫 = 𝑻𝑶𝑽 (µs)= 𝒇𝒐𝒔𝒄(𝑴𝑯𝒛) × (𝟐𝑵 − 𝑰),
DJNZ R0, BACK ൗ𝟏𝟐
where ,
CPL P0.0 ; As an example, the primary operation
f (MHz) = Frequency of oscillator in MHz
osc
; is to complement pin 0 of port 0 N= Bit size of the counter
SJMP ITER I = Initial state of Timer
END
Write a program to produce a delay of 500ms by
software polling method (with interrupts disabled)
ORG 0000H
LJMP 0080H
IE: Interrupt Enable register
ORG 0080H
MAIN: MOV P1, #00H ; Configuring All pins of port 1 as output
MOV IE, #80H ;disable timer 0 overflow interrupts, other interrupts may be enabled
MOV TMOD, #01H
SETB P1.2 ; Setting the initial state of pin 2 of port 1
ITER: MOV R0, #0AH
BACK: MOV TH0, #3CH
MOV TL0, #0B0H
SETB TR0 ;Start Timer 0
HERE: JNB TF0, HERE ; 50 ms software polled timer delay
CLR TF0 ; Check that TF0 is 1 now since no ISR is executed (interrupts disabled)!! so clear it
;manually!!
CLR TR0 ; Stop Timer 0
DJNZ R0, BACK
CPL P1.2 ; COMPLEMENTING THIRD PIN (PIN 2) OF PORT 1 AFTER EVERY 500ms
SJMP ITER
END
Hardware delay Method
 In this method, Timer overflow interrupt is enabled and the primary action is executed
within the ISR for the corresponding timer overflow event. So in this method, timer
overflow interrupt must be enabled
 MOV IE, #82H
IE: Interrupt Enable register
 Or
 SETB ET0 ; Timer overflow interrupt enable bit for timer 0
 SETB EA; Enable the interrupt bits

 The main advantage of this method is that the primary timing action will continue
without tying up the processor for trivial tasks like continuously checking overflow flag
(as in software polling technique) or wasting clock cycles in loop(as in software delay
loop) to produce delay.
 Steps of implementation:
 ISR of timer overflow is implemented so that the primary action is implemented within the ISR
 The corresponding interrupt bits are enabled in IE register
 Timer overflow flag TFx must be initialized to 0 beforehand.
 The timer is configured, and initialized
 Timer is started in the main program.
How does this method works?
 When timer overflows:
 TFx flag becomes 1
 The microcontroller completes current instruction cycle
 Since bit ETx of IE register is enabled, control will branch to the corresponding ISR (must be
implemented beforehand) for the concerned timer.
 The return address is pushed into the stack (Internally PUSH PC operation is executed)
 The PC gets loaded with branching address of 000BH for timer 0 or 001BH for timer 1 during
branching process. Thus program control branches to corresponding ISR vector address
 IE will be automatically reset to zero once the program control branches to ISR (to
prevent interrupts to occur when in ISR execution)
 TFx flag will be reset to 0 when the ISR execution starts.
 The ISR will get executed (hence the primary action will be executed)
 The program control will return to the main program when the instruction RETI is
encountered at the end of ISR (RETI: internally POP PC operation is executed and
initial status of register IE is restored)
 The main program will continue to onwards to execute the instruction present next
to the instruction from which branch had occurred.
Write a program to toggle P0.0 by using hardware
delay method (10 ms delay)
ASSEMBLER LABEL INSTRUCTIONS COMMENTS
DIRECTIVES
ORG 0000H
LJMP 00FFH ;Branch to main program
ORG 000BH ;Start implementing the ISR for Timer 0 overflow event
CLR TF0 ;This is not necessary, the system will reset it once ISR is
hit, just to highlight that it is safe to do so, for other
hardware flags LIKE RI or TI
MOV TH0, #0D8H ;Load count for 10 ms OVERFLOW time for timer
(MSByte)
MOV TL0, #0F0H ;Load count for 10 ms OVERFLOW time for timer
(LSByte)
SETB TR0 ;No need to do this as timer will continue to run even
after overflow and will not stop until TR0 is made 0
CPL P0.0 ; Perform primary operation
RETI ;Return to main program
ASSEMBLER LABEL INSTRUCTIONS COMMENTS
DIRECTIVES
ORG 00FFH ; Implement main program from
00FFH
SETB P0.0 ; Set pin P0.0
MOV IE, #82H ; enable timer overflow interrupt
MOV TMOD, #01H ; Set mode of timer 0 to 16 bit timer
(Mode 1)
MOV TH0, #0D8H ;Load count for 10 ms OVERFLOW
time for timer (MSByte)
MOV TL0, #0F0H ;Load count for 10 ms OVERFLOW
time for timer (LSByte)
MOV TCON, #10H ; Start the timer
HERE: SJMP HERE ; Some meaningful operation can be
performed although only for demo
purpose we are sticking to a loop
operation
END
Write a program to toggle P0.0 by after 10 ms and P0.1 at 20 ms Interval both using hardware
delay method

0040H ISR_T0 00A0H ISR_T1

Initialize Timer 0 after overflow Initialize Timer 1 after overflow
for 10 ms overflow duration for 20 ms overflow duration
Complement P0.0 Complement P0.1
RETI RETI

ORG 0000H ORG 00FFH

LJMP 00FFH MAIN: …
00FFh MAIN ORG 000BH …
LJMP 0040H END
Enable overflow interrupts for timer 0 and timer 1
ORG 001BH
Configure timers LJMP 00A0H
Configure and initialize port pins
ORG 0040H
Initialise Timer 0 to overflow after 10 ms for the first time
ISR_T0: …
Initialise Timer 1 to overflow after 20 ms for the first time …
Start the timers RETI
ORG 00A0H
Continue to do something ISR_T1: …
…
RETI
Solution: Address allocation of program modules and implementation of ISR
for Timer 0 overflow
ASSEMBLER LABEL INSTRUCTIONS COMMENTS
DIRECTIVES
ORG 0000H
LJMP 00FFH ;Branch to main program first
ORG 000BH ;Vector address for timer 0 overflow
LJMP 0040H ; Branch to a desired location where ISR codes will be
implemented, as ISR will not fit in 16 byte space
ORG 001BH ;Vector address for timer 1 overflow
LJMP 00A0H ; Branch to a desired location where ISR codes will be
implemented, as ISR will not fit in 16 byte space
ORG 0040H ; Implement ISR for Timer 0 overflow
ISR_T0: MOV TH0, #0D8H ;Load count for 10 ms OVERFLOW time for timer
(MSByte)
MOV TL0, #0F0H ;Load count for 10 ms OVERFLOW time for timer
(LSByte)
CPL P0.0 ; Perform primary operation
RETI ;Return to main program
 Solution: Implementation of ISR for Timer 1 overflow

ASSEMBLER LABEL INSTRUCTIONS COMMENTS

DIRECTIVES
ORG 00A0H ; Implement codes for ISR for timer 1 overflow
ISR_T1: MOV TH1, #0B1H ;Load count for 20 ms OVERFLOW time for timer
1(MSByte)
MOV TL1, #0E0H ;Load count for 20 ms OVERFLOW time for timer
1(LSByte)
CPL P0.1 ; Perform primary operation
RETI ;Return to main program
ASSEMBLER LABEL INSTRUCTIONS COMMENTS
DIRECTIVES
ORG 00FFH ; Implement main program from 00FFH
MAIN: MOV IE, #8AH ; enable EA bit, timer0, and timer1 overflow interrupt
MOV TMOD, #11H ; set mode of timer 0 and timer 1 to 16 bit timer (Mode
1)
SETB P0.0 ; Initial state: Set pin P0.0
CLR P0.1 ; Initial state: Clear pin P0.1
MOV TH0, #0D8H ;Load count for 10 ms OVERFLOW time for timer
0(MSByte)
MOV TL0, #0F0H ;Load count for 10 ms OVERFLOW time for timer
0(LSByte)
MOV TH1, #0B1H ;Load count for 20 ms OVERFLOW time for timer
1(MSByte)
MOV TL1, #0E0H ;Load count for 20 ms OVERFLOW time for timer
1(LSByte)
MOV TCON, #50H ; Start the timers
HERE: SJMP HERE ; Do something in main program
END
Write a program to toggle P0.0 after 10 ms, P0.1 after 55 ms Interval both using hardware delay
method and P0.2 after 25 ms using software delay technique

0030H ISR_T0 0060H ISR_T1 0090H DELAYSOFT_MS

Initialize Timer 0 after overflow Initialize Timer 1 after overflow Read register A for required
for 10 ms overflow duration for 55 ms overflow duration amount of delay in ms
Complement P0.0 Complement P0.1 Implement delay loop
RETI RETI RET

00FFh MAIN ORG 0000H ORG 0090H

LJMP 00FFH DELAYSOFT_MS: …
Enable overflow interrupts for timer 0 and timer 1
ORG 000BH …
Configure timers LJMP 0030H RET
Configure and initialize port pins ORG 001BH
LJMP 0060H ORG 00FFH
Initialise Timer 0 to overflow after 10 ms for the first time MAIN: …
Initialise Timer 1 to overflow after 55 ms ORG 0030H …
Start the timers ISR_T0: … END
…
Set-up required software delay of 25 ms RETI
Call software delay subroutine DELAYSOFT_MS ORG 0060H
ISR_T1: …
Complement P0.2 bit
…
Continue complementing forever after every 25 ms RETI
 Solution
Address allocation of program modules and implementation of ISR for Timer 0 overflow

ASSEMBLER LABEL INSTRUCTIONS COMMENTS

DIRECTIVES
ORG 0000H
LJMP 00FFH ;Branch to main program first
ORG 000BH ;Vector address for timer 0 overflow
LJMP 0030H ; Branch to a desired location where ISR codes will be
implemented, as ISR will not fit in 16 byte space
ORG 001BH ;Vector address for timer 1 overflow
LJMP 0060H ; Branch to a desired location where ISR codes will be
implemented, as ISR will not fit in 16 byte space
ORG 0030H ; Implement ISR for Timer 0 overflow
ISR_T0: MOV TH0, #0D8H ;Load count for 10 ms OVERFLOW time for timer
(MSByte)
MOV TL0, #0F0H ;Load count for 10 ms OVERFLOW time for timer
(LSByte)
CPL P0.0 ; Perform primary operation
RETI ;Return to main program
 Solution Continued…
Codes for ISR of Timer 1 overflow interrupt

ASSEMBLER LABEL INSTRUCTIONS COMMENTS

DIRECTIVES
ORG 0060H ; Implement codes for ISR for timer 1 overflow
ISR_T1: MOV TH1, #29H ;Load count for 55 ms OVERFLOW time for timer
1(MSByte)
MOV TL1, #28H ;Load count for 55 ms OVERFLOW time for timer
1(LSByte)
CPL P0.1 ; Perform primary operation
RETI ;Return to main program
 Solution Continued: The Codes for implementing Software
Delay Subroutine

ASSEMBLER LABEL INSTRUCTIONS COMMENTS

DIRECTIVES
ORG 0090H
DELAYSOFT_MS: MOV R1, A
BACK1: MOV R2, #125

BACK2: PUSH A
POP A
NOP
NOP
DJNZ R2, BACK2
DJNZ R1, BACK1
RET
 Solution Continued: The Codes for Main Program
ASSEMBLER LABEL INSTRUCTIONS COMMENTS
DIRECTIVES
ORG 00FFH ; Implement main program from 00FFH

MAIN: MOV IE, #8AH ; enable EA bit, timer0, and timer1 overflow interrupt
MOV TMOD, #11H ; set mode of timer 0 and timer 1 to 16 bit timer (Mode 1)

SETB P0.0 ; Initial state: Set pin P0.0

CLR P0.1 ; Initial state: Clear pin P0.1
SETB P0.2 ; Initial state: Set pin P0.2
MOV TH0, #0D8H ;Load count for 10 ms OVERFLOW time for timer 0(MSByte)

MOV TL0, #0F0H ;Load count for 10 ms OVERFLOW time for timer 0(LSByte)

MOV TH1, #29H ;Load count for 55 ms OVERFLOW time for timer 1(MSByte)

MOV TL1, #28H ;Load count for 55 ms OVERFLOW time for timer 1(LSByte)

MOV TCON, #50H ; Start the timers

 Solution Continued: The Codes for Main Program
Calling Software Delay subroutine

ASSEMBLER LABEL INSTRUCTIONS COMMENTS

DIRECTIVES
MOV A, #25

BACK: LCALL DELAYSOFT_MS

CPL P0.2
SJMP BACK
END
Write a program to toggle P0.0 by using pure hardware
delay and P0.1 using software polled method at an interval
of 10ms using only one Timer module
ORG 0000H ORG 00FFH
MAIN: MOV P0, #00H
LJMP 00FFH MOV IE, #82H
MOV TMOD, #01H
ORG 000BH ; ISR for timer0 overflow SETB P0.0
MOV TH0, #0D8H ;10 ms OVERFLOW time CLR P0.1
; for timer0 CLR F0
MOV TL0, #0F0H MOV TH0, #0D8H ;10 ms OVERFLOW
CPL P0.0 ; time for timer 0
SETB F0 MOV TL0, #0F0H
RETI MOV TCON, #10H
HERE: JNB F0, HERE
CPL P0.1
CLR F0
SJMP HERE
END
 Write a program to design a 3 digit decimal up counter where the count
value is shown on SS displays connected in P0, P1 and P2
ORG 0000H %% Read values in data registers and send to
LJMP MAIN_PROG ports after translation to SS code ORG 0040H
ORG 000BH
LJMP ISR_C0
CONT: MOV R0, TR0 ISR_C0:

ORG 0030H MOV A, R0 % Overflow has happened the higher

LCALL CONV_SSC
MAIN_PROG: MOV P0, A
registers values need to be incremented and
%%Initialization lower register cleared
MOV A, R1 % TF0 will be automatically cleared
%Reset all Ports for output
CLR A
LCALL CONV_SSC
MOV P1, A CLR R0
MOV R0,A INC R1
MOV R1, A MOV A, R2
MOV R2, A LCALL CONV_SSC
MOV P2, A CJNE R1, #0AH, END_ISR
MOV P0, R0 CLR R1
MOV P1, R1
MOV P2, R2
SJMP CONT INC R2

% Initialize and Configure Timer/counter registers and CONV_SSC: MOV DPTR, #LUT CJNE R2, #0AH, END_ISR
enable interrupts MOVC A, @A+DPTR
RET
CLR R2
MOV TMOD, #06H SETB P3.1 %Indicate overflow of counter digits
MOV TCON, A LUT DB SSC_01, SSC_02, ..., SSC_09
MOV IE, #82H
END_ISR: RETI
MOV TL0, A
MOV TH0, 246D

%%Start the counter

SETB TR0