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    Numerical Questions

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    Vaibhav Chaudhary
    This document contains 7 questions about cache memory organization, addressing, and performance. Question 1 asks about the number of address bits needed for a main memory and cache configuration. Question 2 describes a cache setup and asks about tag, set, and word field sizes. Question 3 asks about the tag field size for a given cache configuration.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Numerical Questions

    Uploaded by

    Vaibhav Chaudhary
    42 views1 page
    This document contains 7 questions about cache memory organization, addressing, and performance. Question 1 asks about the number of address bits needed for a main memory and cache configuration. Question 2 describes a cache setup and asks about tag, set, and word field sizes. Question 3 asks about the tag field size for a given cache configuration.

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    This document contains 7 questions about cache memory organization, addressing, and performance. Question 1 asks about the number of address bits needed for a main memory and cache configuration. Question 2 describes a cache setup and asks about tag, set, and word field sizes. Question 3 asks about the tag field size for a given cache configuration.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    42 views1 page

    Numerical Questions

    Uploaded by

    Vaibhav Chaudhary
    This document contains 7 questions about cache memory organization, addressing, and performance. Question 1 asks about the number of address bits needed for a main memory and cache configuration. Question 2 describes a cache setup and asks about tag, set, and word field sizes. Question 3 asks about the tag field size for a given cache configuration.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 1

    1.

    A block-set associative cache memory consists of 128 blocks divided into four block sets
    . The main memory consists of 16,384 blocks and each block contains 256 eight bit words.

    A. How many bits are required for addressing the main memory?
    B. How many bits are needed to represent the TAG, SET and WORD fields?

    2. A computer has a 256 KB, 4-way set associative, write back data cache with block size of 32 bytes.
    The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains
    in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.
    3. A 4-way set associative cache memory unit with a capacity of 16 KB is built using a block size of
    8 words. The word length is 32 bits. The size of the physical address space is 4 GB. The number of
    bits for the TAG field will be?
    4. Consider a direct mapped cache with 8 cache blocks (0-7). If the memory block requests
    are in the order-

    3, 5, 2, 8, 0, 6, 3, 9, 16, 20, 17, 25, 18, 30, 24, 2, 63, 5, 82, 17, 24

    Which of the following memory blocks will not be in the cache at the end of the sequence?

    5. We want to speed up computer performance with an additional unit for calculating in floating point
    format. This unit is 20 times faster than the same operations without unit. What percentage of a
    total computer time must this unit be active to achieve an overall increase in computer speed for
    2.5 times?
    6. On a computer with a 32-bit memory address and the length of the memory location of 1 byte is
    installed set-associative cache. Cache size is 16 KB, block (line) size is 16 Bytes, set associative c
    cache is 4-way. Computer with virtual memory has the following features:
    • length of the virtual address is 38 bits,
    • the page size is 16 KB,
    • length of the physical address is 32 bits.
    a) How many bits is the length of page descriptor, if in addition to the frame number (FN),
    additional parameters occupy another 6 bits?
    b) What is the maximum size of the page-table in bytes?

    7. Consider a main memory consisting of four memory modules with 256 words per module. Assume
    16 words in each cache block. The cache has a total capacity of 256 words. Set- associative mapping
    is used to allocate cache blocks to block frames. The cache is divided into four sets Bus, Cache,
    and Shared Memory 241
    (a) Show the address assignment for all 1024 words in a four-way low-order interleaved
    organization of the main memory.
    (b) How many blocks are there in the main memory? How many block frames are there in the
    cache?
    (c) Explain the bit fields needed for addressing each word in the two-level memory system.
    (d) Show the mapping from the blocks in the main memory to the sets in the cache and explain how
    to use the tag field to locate a block frame within each set.

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