BQ24715 Acok Low

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bq24715
SLUSBD1B – MARCH 2013 – REVISED SEPTEMBER 2016
bq24715 2-3 Cell NVDC-1 Battery Charger Controller

with Ultra-Fast Transient Response and High Light-Load Efficiency
1 Features 3 Description
1• 6-24V Input SMBus NVDC-1 2-3S Battery The bq24715 is a NVDC-1 synchronous battery
Charger Controller charge controller with low quiescent current, high light
load efficiency for 2S or 3S Li-ion battery charging
• System Instant-on Operation with No Battery or applications, offering low component count.
Deeply Discharged Battery
The power path management allows the system to be
• Ultra-Fast Transient Response of 100 µs
regulated at battery voltage but does not drop below
• Ultra-Low Quiescent Current of 500 µA and High the programmable system minimum voltage.
PFM Light Load Efficiency 80% at 20mA load to
Meet Energy Star and ErP Lot6 The bq24715 provides N-channel ACFET and RBFET
drivers for the power path management. It also
• Switching Frequency: 600kHz/800kHz/1MHz provides driver of the external P-channel battery FET.
• Programmable System/Charge Voltage (16 The loop compensation is fully integrated.
mV/step), Input/Charge Current (64 mA/step) with The bq24715 has programmable 11-bit charge
High Accuracy voltage, 7-bit input/charge current and 6-bit minimal
– ±0.5% Charge Voltage Regulation system voltage with very high regulation accuracies
– ±3% Input/Charge Current Regulation through the SMBus communication interface.
– ±2% 40x Input/16x Discharge Current Monitor The v monitors adapter current or battery discharge
Output current through the IOUT pin allowing the host to
• Support Battery LEARN Function throttle down CPU speed when needed.
• Maximize CPU Performance with Deeply The bq24715 provides extensive safety features for
Discharged Battery or No Battery over current, over voltage and MOSFET short circuit.
• Integrated NMOS ACFET and RBFET Driver Device Information(1)
• 20-pin 3.5 x 3.5 mm2 QFN Package PART NUMBER PACKAGE BODY SIZE (NOM)
bq24715 VQFN (20) 3.50 mm × 3.50 mm
2 Applications
(1) For all available packages, see the orderable addendum at
• Ultrabook, Notebook, and Tablet PC the end of the datasheet.
• Industrial and Medical Equipment
• Portable Equipment
4 Simplified Application Diagram

Ultra-Fast Ultra-Low Quiescent
DPM Current Support CPU Turbo Mode
Adaptor
To System
6-24V Iin Enhanced Safety
Features
Optional OCP, OVP,
N-FET FET Short
Driver
bq24715
Adaptor Detection
Ichg
PMOS BAT
NVDC-1 FET Driver
SMBus Controls V and I Charger
with High Accuracy Controller
SMBus 2S-3S
HOST
Iin, Idischarge Integrated Compensation Internal Soft Start
Copyright © 2016, Texas Instruments Incorporated

1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24715
SLUSBD1B – MARCH 2013 – REVISED SEPTEMBER 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 16
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 18
3 Description ............................................................. 1 8.5 Programming........................................................... 21
4 Simplified Application Diagram............................ 1 9 Application and Implementation ........................ 28
9.1 Application Information............................................ 28
5 Revision History..................................................... 2
9.2 Typical Application ................................................. 28
6 Pin Configuration and Function ........................... 3
10 Power Supply Recommendations ..................... 34
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4 11 Layout................................................................... 35
11.1 Layout Guidelines ................................................. 35
7.2 ESD Ratings.............................................................. 4
11.2 Layout Example .................................................... 36
7.3 Recommended Operating Conditions ...................... 5
7.4 Thermal Information .................................................. 5 12 Device and Documentation Support ................. 37
7.5 Electrical Characteristics........................................... 6 12.1 Third-Party Products Disclaimer ........................... 37
7.6 Timing Requirements .............................................. 10 12.2 Receiving Notification of Documentation Updates 37
7.7 SMBus Timing Characteristics................................ 11 12.3 Community Resources.......................................... 37
7.8 Typical Characteristics ............................................ 13 12.4 Trademarks ........................................................... 37
12.5 Electrostatic Discharge Caution ............................ 37
8 Detailed Description ............................................ 14
12.6 Glossary ................................................................ 37
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 15 13 Mechanical, Packaging, and Orderable
Information ........................................................... 37
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (February 2014) to Revision B Page
• Added Full Production Data specifications to data sheet ...................................................................................................... 4
Changes from Original (March 2013) to Revision A Page
• Added device number to the title and added Device Info table per the new data sheet template......................................... 1
• Changed comment for Address 0x15H in Table 2 from "Any value below 4.096V results in 4.096V" to "Any value
below 4.096V results in default value".................................................................................................................................. 22
• Changed Setting Input Current description text string from "Thereafter, all input current goes to system load and
input current increases" to "Keep increasing the system current and the battery will run into supplement mode." ............ 27
• Changed conditions statement for Figure 16 ....................................................................................................................... 33
• Changed conditions statement forFigure 17......................................................................................................................... 33
2 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated
Product Folder Links: bq24715

bq24715
www.ti.com SLUSBD1B – MARCH 2013 – REVISED SEPTEMBER 2016
6 Pin Configuration and Function
RGR Package
20-Pin VQFN
(Top View)
PHASE
HIDRV
REGN
BTST
VCC
20 19 18 17 16
ACN 1 15 LODRV
ACP 2 14 GND
CMSRC 3 13 SRP
ACDRV 4 12 SRN
ACOK 5 11 BATDRV
6 7 8 9 10
IOUT
ACDET
CELL
SDA
Pin Descriptions SCL
PIN NAME I/O DESCRIPTION
Input current sense resistor negative input. Place an optional 0.1µF ceramic capacitor from ACN to GND for common-
1 ACN I
mode filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential mode filtering.
Input current sense resistor positive input. Place a 1µF ceramic capacitor from ACP to GND for common-mode
2 ACP I
filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential-mode filtering.
ACDRV charge pump source input. Place a 4kΩ resistor from CMSRC to the common source of ACFET (Q1) and
3 CMSRC I
RBFET (Q2) limits the in-rush current on CMSRC pin.
Charge pump output to drive both adapter input n-channel MOSFET (ACFET) and reverse blocking n-channel
MOSFET (RBFET). ACDRV voltage is 6.1V above CMSRC when voltage on ACDET pin is higher than 2.4V, voltage
4 ACDRV O on VCC pin is above UVLO but lower than 26V and voltage on VCC pin is 675mV above voltage on SRN pin so that
ACFET and RBFET can be turned on to power the system by AC adapter. Place a 4kΩ resistor from ACDRV to the
gate of ACFET and RBFET limits the in-rush current on ACDRV pin.
AC adapter detection open drain output. It is pulled HIGH to external pull-up supply rail by external pull-up resistor
when voltage on ACDET pin is above 2.4V, VCC above UVLO but lower than 26V and voltage on VCC pin is 675mV
5 ACOK O above voltage on SRN pin, indicating a valid adapter is present to start charge. If any one of the above conditions can
not meet, it is pulled LOW to GND by internal MOSFET. Connect a 10kΩ pull up resistor from ACOK to the pull-up
supply rail.
Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter input to
6 ACDET I ACDET pin to GND pin. When ACDET pin is above 0.6V and VCC is above UVLO, REGN LDO is present, ACOK
comparator and IOUT are both active.
Buffered 40 times adapter or 16 times discharge current output - the differential voltage across sense resistor;
7 IOUT O selectable with SMBus command ChargeOption(). Place a 100pF or less ceramic decoupling capacitor from IOUT pin
to GND.
SMBus open-drain data I/O. Connect to SMBus data line from the host controller or smart battery. Connect a 10kΩ
8 SDA I/O
pull-up resistor according to SMBus specifications.
SMBus open-drain clock input. Connect to SMBus clock line from the host controller or smart battery. Connect a
9 SCL I
10kΩ pull-up resistor according to SMBus specifications.
Cell selection pin. For bq24715, set CELL pin Float for 2-cell, and HIGH for 3-cell. Pulling CELL to GND will provide a
hardware exit function from LEARN mode, disable the input DPM function, reset the bit[5] and bit[1] in chargeoption(),
10 CELL I
and reset Maxchargevoltage() to previous CELL pin default setting value and chargecurrent() to zero. Release CELL
from GND, charger will recheck CELL pin voltage and lock the new CELL pin selection.
P-channel battery FET gate driver output. This pin can go high to turn off the battery FET, go low to turn on the
battery FET, or operate battery FET in linear mode to regulate the minimum system voltage when battery is depleted.
11 BATDRV O
Connect the source of the BATFET to the system load voltage node. Connect the drain of the BATFET to the battery
pack positive node. There is an internal pull-down resistor of 50k on BATDRV to ground.
Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN pin with a
12 SRN I 0.1µF ceramic capacitor to GND for common-mode filtering and connect to current sensing resistor. Connect a 0.1µF
ceramic capacitor between current sensing resistor to provide differential mode filtering.
Charge current sense resistor positive input. Connect a 0.1µF ceramic capacitor between current sensing resistor to
13 SRP I
provide differential mode filtering.
IC ground. On PCB layout, connect to analog ground plane, and only connect to power ground plane through the
14 GND I
power pad underneath IC.
Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 3

bq24715
Pin Descriptions (continued)

PIN NAME I/O DESCRIPTION
15 LODRV O Low side power MOSFET driver output. Connect to low side n-channel MOSFET gate.
Linear regulator output. REGN is the output of the 6V linear regulator supplied from VCC. The LDO is active when
16 REGN O voltage on ACDET pin is above 0.6V and voltage on VCC is above UVLO. Connect a 1µF ceramic capacitor from
REGN to GND.
High side power MOSFET driver power supply. Connect a 0.047µF-0.1µF capacitor from BTST to PHASE. Connect a
17 BTST I
bootstrap Schottky diode from REGN to BTST.
18 HIDRV O High side power MOSFET driver output. Connect to the high side n-channel MOSFET gate.
19 PHASE I High side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET.
20 VCC I Input supply. Use 10Ω resistor and 1µF capacitor to ground as low pass filter to limit inrush current.
Exposed pad beneath the IC. Analog ground and power ground star-connected only at the PowerPad plane. Always
PowerPAD™ I solder PowerPad to the board, and have vias on the PowerPad plane connecting to analog ground and power ground
planes. It also serves as a thermal pad to dissipate the heat.
7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
SRN, SRP, ACN, ACP, CMSRC, VCC –0.3 30
PHASE –2.5 30
ACDET, SDA, SCL, LODRV, REGN, IOUT, ACOK, CELL –0.3 7
Voltage range LODRV (20ns) –2.5 7 V
BTST, HIDRV, ACDRV –0.3 36
HIDRV (20ns) –2.5 36
BATDRV –0.3 30
Maximum difference voltage SRP–SRN, ACP–ACN –0.5 +0.5 V
Junction temperature, TJ –40 155 °C
Storage temperature, Tstg –55 155 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
±2000 V
JS-001, all pins (1)
V(ESD) Electrostatic discharge
Charged device model (CDM), per JEDEC
±500 V
specification JESD22-C101, all pins (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

bq24715
7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
SRN, SRP, ACN, ACP, CMSRC, VCC 0 24 V
PHASE –2 24 V
Voltage range ACDET, SDA, SCL, LODRV, REGN, IOUT, ACOK, CELL 0 6.5 V
BTST, HIDRV, ACDRV 0 30 V
BATDRV –0.3 16 V
Maximum
SRP–SRN, ACP–CAN –0.2 0.2 V
difference range
TJ Junction temperature range –20 125 °C
TA Operating free-air temperature range –20 85 °C
7.4 Thermal Information

bq24715
(1) RGR Package
THERMAL METRIC UNIT
(QFN)
20 PINS
RθJA Junction-to-ambient thermal resistance 34.6 °C/W
RθJCtop Junction-to-case (top) thermal resistance 49.3 °C/W
(2)
RθJB Junction-to-board thermal resistance 12.5 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 12.7 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
(2) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.

bq24715
7.5 Electrical Characteristics

6V ≤ VVCC ≤ 24V, –20°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
INPUT OPERATING CONDITIONS
VVCC_OP VCC Input Voltage Operating Range 6 24 V
MIN SYSTEM VOLTAGE REGULATION (0x3E register)
VSYSMIN_RNG MinSystem Voltage Regulation Range 4.096 14.5 V
9.216 V
MinsystemVoltage() = 0x2400H (3S)
Default minimum system voltage and accuracy at –2% 1.2%
VSYSMIN_REG and
charge enable and battery voltage lower than
VSYSMIN_REG_ACC 6.144 V
VSYSMIN_REG
MinsystemVoltage() = 0x1800H (2S)
–3% 1.5%
MAX SYSTEM VOLTAGE REGULATION (0x15 register charge disable)
VSYSMAX_RNG MaxSystem Voltage Regulation Range 4.096 14.5 V
13.504 V
MaxChargeVoltage() = 0x34C0H (3S)
VSYSMAX_REG and Default maximum system voltage and accuracy –2% 1.2%
VSYSMAX_REG_ACC at charge disable 9.008 V
MaxChargeVoltage() = 0x2330H (2S)
–3% 1.5%
MAX CHARGE VOLTAGE REGULATION (0-85C; 0x15 register charge enable)
VBAT_REG_RNG Battery voltage range 4.096 14.5 V
12.529 12.592 12.655 V
MaxChargeVoltage() = 0x3130H
–0.5% 0.5%
VBAT_REG_ACC Charge voltage regulation accuracy
8.35 8.4 8.45 V
MaxChargeVoltage() = 0x20D0H
–0.6% 0.6%
CHARGE CURRENT REGULATION (0-85C)
Charge current regulation differential voltage
VIREG_CHG_RNG VIREG_CHG = VSRP - VSRN 0 81.28 mV
range RSNS = 10mΩ
3937 4096 4219 mA
ChargeCurrent() = 0x1000H
–3% 3%
1946 2048 2150 mA
–5% 5%
921 1024 1127 mA
–10% 10%
410 512 614 mA
Charge current regulation accuracy –20% 20%
ICHRG_REG_ACC
10mΩ current sensing resistor, VBAT>VSYSMIN 288 384 480 mA
–25% 25%
172 256 340 mA
–33% 33%
115 192 269 mA
ChargeCurrent() = 0x00C0H
–40% 40%
64 128 192 mA
–60% 60%

bq24715
Electrical Characteristics (continued)

PRECHARGE CURRENT REGULATION (0-85C)
268.8 384 499.2 mA
ChargeCurrent() >= 0x0180H
–30% 30%
153.6 256 358.4 mA
Charge current regulation accuracy 10mΩ current –40% 40%
IPRECHRG_REG_ACC sensing resistor,
VBAT<VSYSMIN, chargeoption(2)=1 96 192 288 mA
ChargeCurrent() = 0x00C0H
–50% 50%
25.6 128 230.4 mA
–80% 80%
INPUT CURRENT REGULATION
Input current regulation differential voltage range
VDPM_REG_RNG VIREG_DPM = VACP – VACN 0 80.64 mV
RAC = 10mΩ
3973 4096 4219 mA
InputCurrent() = 0x1000H
–3% 3%
1946 2048 2150 mA
Input current regulation accuracy 10 mΩ current –5% 5%
IDPM_REG_ACC
sensing resistor 870 1024 1178 mA
–15% 15%
358.4 512 665.6 mA
–30% 30%
INPUT CURRENT OR DISCHARGE CURRENT SENSE AMPLIFIER
VACP/N_OP Input common mode range Voltage on ACP/ACN 4.5 24 V
VSRP/N_OP Output common mode range Voltage on SRP/SRN 14.5 V
IIOUT IOUT Output current 0 40 µA
V(IOUT)/V(SRN-SRP) , 0x12H[15]=1,
16 V/V
0x12H[4]=1 and 0x12H[3]=1
AIOUT Current sense amplifier gain
V(IOUT)/V(ACP-ACN), 0x12H[4]=0 and
40 V/V
0x12H[3]=1
VSRN-SRP_OFF Input current amplifier offset voltage 1 mV
VIOUT_ACC Current sense output accuracy V(SRN-SRP) or V(ACP-ACN) = 40.96mV –2% 2%
V(SRN-SRP) or V(ACP-ACN) = 20.48mV –3% 3%
CIOUT_MAX Maximum output load capacitance For stability with 0 to 1mA load 100 pF
REGN REGULATOR
VVCC > 6.5V, VACDET>0.6V (0-50mA
VREGN_REG REGN Regulator voltage 5.5 6 6.5 V
load)
VREGN = 0V, VVCC > UVLO, Converter
50 75 mA
enabled and not in TSHUT
IREGN_LIM REGN Current limit
VREGN = 0V, VVCC > UVLO, Converter
7 14 mA
disabled or in TSHUT
CREGN REGN Output capacitor required for stability ILOAD = 100 µA to 50 mA 1 μF
UNDER VOLTAGE LOCKOUT COMPARATOR (UVLO)
Under-voltage rising threshold VVCC rising 3 3.2 3.4 V
VUVLO_VCC
Under-voltage hysteresis, falling VVCC falling 400 mV
Under-voltage rising threshold VSRN rising 3 3.3 3.6 V
VUVLO_BAT
Under-voltage hysteresis, falling VSRN falling 400 mV

bq24715

QUIESCENT CURRENT
VBAT = 12.6V, VSRN >UVLO, BATFET
turns on,
13.3 20 μA
ACDET<0.6 V, TJ = –20°C to 85°C,
Standby mode. System powered by battery. 0x12[15]=1 (low power mode enabled)
IBAT_BATFET_ON BATFET ON.
ISRN+ISRP+IPHASE+IBTST+IACP+IACN+ICMSRC VBAT = 12.6V, VSRN>UVLO, BATFET
turns on,
50 70 μA
ACDET<0.6 V, TJ = –20°C to 85°C,
0x12[15]=0 (low power mode disabled)
ACN=ACP=CMSRC=VCC=20 V, VBAT =
Adapter standby quiescent current, 12.6V, VACDET> 2.4V,
ISTANDBY 540 700 µA
IVCC+IACP+IACN+ICMSRC CELL pull up, TJ = –20°C to 85°C. No
switching.
ISTANDBY plus supply current in PFM,
200mW output; Reg0x12[10]=0; MOSFET 1.5
Qg=4 nC;
IAC_SWLIGHT Adapter current, IVCC+IACP+IACN+ICMSRC mA
ISTANDBY plus supply current in PFM,
200mW output; Reg0x12[10]=1; MOSFET 5
Qg=4 nC;
Charge enable, 800kHz switching
IAC_SW Adapter current, IVCC+IACP+IACN+ICMSRC 10 mA
frequency MOSFET Qg=4 nC
ACOK COMPARATOR
VACOK_RISE ACOK Rising threshold VVCC>UVLO, VACDET rising 2.376 2.4 2.424 V
VACOK_FALL_HYS ACOK Falling hysteresis VVCC>UVLO, VACDET falling 35 55 75 mV
VWAKEUP_RISE WAKEUP Detect rising threshold VVCC>UVLO, VACDET rising 0.52 0.6 V
VWAKEUP_FALL WAKEUP Detect falling threshold VVCC>UVLO, VACDET falling 0.35 0.46 V
VCC to SRN COMPARATOR (VCC_SRN), SLEEP
VVCC-SRN_FALL VCC-SRN Falling threshold VVCC falling towards VSRN 120 250 375 mV
VVCC-SRN _RHYS VCC-SRN Rising hysteresis VVCC rising above VSRN 300 mV
INPUT OVER-CURRENT COMPARATOR
ACP to ACN Rising Threshold, respect to input
ACOC ChargeOption() bit [7] = 1 330% IDPM
current().
ACOC floor 50 mV
ACOC ceiling 180 mV
LIGHT LOAD COMPARATOR
ACP to ACN Falling Threshold, average Converter CCM-DCM, current decrease 1.25 mV
ACP to ACN Rising Threshold, average 2.5 mV
CONVERTER OVER-CURRENT COMPARATOR (ILIM_HI), CYCLE-BY-CYCLE
Chargeoption() bit [6] =0 250 mV
ILIM_HI Converter over current limit, measure GND-PH
Chargeoption() bit [6] =1 (default) 350 mV
CONVERTER UNDER-CURRENT COMPARATOR (ILIM_LOW) , CYCLE-BY-CYCLE
Converter over current limit, measure GND-PH –2 0 6 mV
INPUT OVER-VOLTAGE (ACOVP)
VACOVP VCC Over-Voltage Rising Threshold VCC rising 24 26 28 V
VACOV_HYS VCC Over-Voltage Falling Hysteresis VCC falling 1 V

bq24715

BAT OVER-VOLTAGE COMPARATOR (BAT_OVP)
Over-voltage rising threshold as percentage of
VOVP_RISE VSRN rising 102.5% 104% 106%
VBAT_REG
Over-voltage falling threshold as percentage of
VOVP_FALL VSRN falling 102%
VBAT_REG
Discharge current during OVP, SRP pin Charge enable, BATFET ON 4 mA
SYSTEM OVER-VOLTAGE COMPARATOR (SYS_OVP)
VSRN rising, chargeoption bit[12]=0 default 15.1
VSYSOVP_RISE_3S 3S System over-voltage rising threshold V
VSRN rising, chargeoption bit[12]=1 17.0
VSYSOVP_FALL_3S 3S System over-voltage falling threshold VSRN falling 13.2 V
VSRN rising, chargeoption bit[12]=0 default 10.1
VSYSOVP_RISE_2S 2S System over-voltage rising threshold V
VSRN rising, chargeoption bit[12]=1 11.3
VSYSOVP_FALL_2S 2S System over-voltage falling threshold VSRN falling 8.8 V
Discharge current during OVP 4 mA
THERMAL SHUTDOWN COMPARATOR (TSHUT)
TSHUT Thermal shutdown rising temperature Temperature rising 155 °C
TSHUT_HYS Thermal shutdown hysteresis, falling Temperature falling 20 °C
LOGIC INPUT (SDA, SCL)
VIN_ LO Input low threshold 0.8 V
VIN_ HI Input high threshold 2.1 V
IIN_ LEAK Input bias current V=7V –1 1 μA
LOGIC OUTPUT OPEN DRAIN (ACOK, SDA)
VOUT_ LO Output saturation voltage 5 mA drain current 500 mV
IOUT_ LEAK Leakage current V=7V –1 1 μA
ANALOG INPUT (ACDET)
IIN_ LEAK Input bias current V=7V –1 1 μA
Offset –10 10 mV
ANALOG INPUT (CELL)
GND 1.0 V
Float (2S setting) 1.2 1.8 V
High (3S setting) 2.5 V
Internal pull up resistor to REGN 405 kΩ
Internal pull down resistor to GND 141 kΩ
PWM OSCILLATOR
ChargeOption () bit [9:8] = 00 –10% 600 10% kHz
FSW PWM Switching frequency ChargeOption() bit [9:8] = 01 (Default) –10% 800 10% kHz
ChargeOption() bit [9:8] = 10 –10% 1000 10% kHz
FSW_min Audio frequency limit, PFM ChargeOption() bit [10] = 1 40 kHz
ACFET GATE DRIVER (ACDRV)
IACFET ACDRV Charge pump current limit 40 60 μA
VACFET Gate drive voltage on ACFET VACDRV – VCMSRC when VVCC > UVLO 5.5 6.1 6.7 V
Minimum load resistance between ACDRV and
RACDRV_LOAD 500 kΩ
CMSRC
RACDRV_OFF ACDRV Turn-off resistance I = 30 μA 5 6.2 7.4 kΩ
ACDRV Turn-off when Vgs voltage is lower than
VACFET_LOW The voltage below VACFET 0.2 V
VACFET (Specified by design)
BATTERY FET GATE DRIVER (BATDRV)
RDS_BAT_OFF BATFET Turn-off resistance 100µA current into BATDRV 2 kΩ
RDS_BAT_ON BATFET Turn-on resistance 100µA current from BATDRV 5 kΩ
VBATDRV_REG =VSRN – VBATDRV
VBATDRV_REG BATFET Drive voltage 4.2 8 V
when VAVCC > 5 V and BATFET is on

bq24715

PWM HIGH SIDE DRIVER (HIDRV)
RDS_HI_ON High side driver turn-on resistance VBTST – VPH = 5.5 V, I = 10 mA 4 5.5 Ω
RDS_HI_OFF High side driver turn-off resistance VBTST – VPH = 5.5 V, I = 10 mA 0.65 1.3 Ω
VBTST – VPH when low side refresh pulse is
VBTST_REFRESH Bootstrap refresh comparator threshold voltage 3.85 4.15 4.7 V
requested
PWM LOW SIDE DRIVER (LODRV)
RDS_LO_ON Low side driver turn-on resistance VREGN=6V, I=10mA 4 6.2 Ω
RDS_LO_OFF Low side driver turn-off resistance VREGN=6V, I=10mA 0.9 1.4 Ω
INTERNAL SOFT START
In CCM mode 10 mΩ current sensing
ISTEP Soft start current step 64 mA
resistor
7.6 Timing Requirements

ACOK COMPARATOR
VACOK_RISE_DEG ACOK Rising deglitch (Specified by design) VVCC>UVLO, VACDET rising above 2.4V 2 3 ms
VCC to SRN COMPARATOR (VCC_SRN), SLEEP
VCC-SRN falling delay VCC falling towards VSRN 95 160 237 µs
Resume time VVCC rising above VSRN 0.76 1.28 1.9 ms
INPUT OVER-CURRENT COMPARATOR
Relax time, No latch. 300 ms
INPUT OVER-VOLTAGE (ACOVP)
Rising deglitch VCC rising 0.1 ms
Falling deglitch VCC falling 1 ms
BAT OVER-VOLTAGE COMPARATOR (BAT_OVP)
Over voltage deglitch time to fully turn-off
1 ms
BATFET
SYSTEM OVER-VOLTAGE COMPARATOR (SYS_OVP)
System over-voltage deglitch time to turn-off
tSYSOVP_DEG 24 µs
ACDRV
THERMAL SHUTDOWN COMPARATOR (TSHUT)
Rising deglitch 100 µs
Falling deglitch 10 ms
ANALOG INPUT (CELL)
Allowed max delay time to config CELL at POR 72 100 120 ms
PWM DRIVER TIMING
tLOW_HIGH Driver dead time from low side to high side 20 ns
tHIGH_LOW Driver dead time from high side to low side 20 ns
INTERNAL SOFT START
Soft start current step time 24 μs

bq24715
7.7 SMBus Timing Characteristics

4.5 V ≤ V(VCC) ≤ 24 V, 0°C ≤ TJ ≤125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
MIN TYP MAX UNIT
tR SCLK/SDATA rise time 1 µs
tF SCLK/SDATA fall time 300 ns
tW(H) SCLK pulse width high 4 50 µs
tW(L) SCLK Pulse Width Low 4.7 µs
tSU(STA) Setup time for START condition 4.7 µs
tH(STA) START condition hold time after which first clock pulse is generated 4 µs
tSU(DAT) Data setup time 250 ns
tH(DAT) Data hold time 300 ns
tSU(STOP) Setup time for STOP condition 4 µs
t(BUF) Bus free time between START and STOP condition 4.7 µs
FS(CL) Clock Frequency 10 100 kHz
HOST COMMUNICATION FAILURE
(1)
ttimeout SMBus bus release timeout 25 35 ms
tBOOT Deglitch for watchdog reset signal 10 ms
(2)
Watchdog timeout period, ChargeOption() bit [14:13] = 01 35 44 53
(2)
tWDI Watchdog timeout period, ChargeOption() bit [14:13] = 10 70 88 105 s
(2)
Watchdog timeout period, ChargeOption() bit [14:13] = 11 (Default) 140 175 210
(1) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have
detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave
must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
(2) User can adjust threshold via SMBus ChargeOption() REG0x12.
Figure 1. SMBus Communication Timing Waveforms

bq24715
Figure 2. SMBus Writing Timing
A B C D E F G H I J K
tLOW tHIGH
SMBCLK
SMBDATA
tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:DAT tSU:STO tBUF
A = START CONDITION E = SLAVE PULLS SMBDATA LINE LOW I = ACKNOWLEDGE CLOCK PULSE
B = MSB OF ADDRESS CLOCKED INTO SLAVE F = ACKNOWLEDGE BIT CLOCKED INTO MASTER J = STOP CONDITION
C = LSB OF ADDRESS CLOCKED INTO SLAVE G = MSB OF DATA CLOCKED INTO MASTER K = NEW START CONDITION
D = R/W BIT CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO MASTER
Figure 3. SMBus Read Timing

bq24715
7.8 Typical Characteristics
100% 100%
90%
98%
80%
70% 96%
Efficiency
60% VSYS = 13.5 V
Efficiency
94%
50% VSYS = 12.6 V
40%
92%
VSYS = 9 V
30%
20% VSYS = 8.4 V 90%
10% VSYS = 6 V
88%
19.5Vin_12.6Vbat
0%
19.5Vin_8.4Vbat
0 0.02 0.04 0.06 0.08 0.1 86%
System Load Current (A) 0 2 4 6 8 10
VIN = 19.5 V System Load Current (A)

VIN = 19.5 V
Figure 4. Light Load Efficiency vs. System Current
Figure 5. Heavy Load Efficiency vs. System Current

bq24715
8 Detailed Description
8.1 Overview
The bq24715 is a 2-3 cell battery charge controller with power selection for multi-chemistry portable applications
such as notebook and ultrabook. It supports wide input range of input sources from 6 V to 24 V, and 2-3 cell
battery.
The bq24715 supports automatic system power source selection with separate drivers for n-channel MOSFETs
on the adapter side, and p-channel MOSFETs on the battery side.
The bq24715 features Dynamic Power Management (DPM) to limit the input power and avoid AC adapter
overloading. During battery charging, as the system power increases, the charging current will reduce to maintain
total input current below adapter rating. If system power demand is temporarily exceeds adapter rating, the
bq24715 supports NVDC architecture to allow battery discharge energy to supplement system power
The SMBus controls input current, charge current and charge voltage registers with high resolution, high
accuracy regulation limits.

bq24715
8.2 Functional Block Diagram
3.2V
UVLO ACDRV ACDRV
ACDRV_CMSRC CHARGE
VCC 20
CMSRC+5.9V PUMP
EN_REGN
ACGOOD
4 ACDRV
ACDET 6
ACOK_DRV
0.6V WAKEUP
3 CMSRC
SYSOVP
SELECTOR SRN
ACOC
ACOVP LOGIC
26V EN_CHRG
11 BATDRV
ACGOOD EN_PRECHRG
VCC_SRN SRN-6V
EN_FASTCHRG
2.4V EN_SUPPLEMENT
ACOK 5 EN_LDOMODE
ACOK_DRV 2ms Rising
Deglitch
WD_TIMEOUT WATCHDOG EN_CHRG

VREF_IAC TIMER 175s**
FBO
ACP 2
40X
EN_DPM
ACN 1
CHARGE_INHIBIT
IOUT 7 MUX
1X DAC_VALID
IOUT_SEL EN_LEARN
EN_PRECHRG
SRP 13
16X
CONVERTER PWM/PFM EN_FASTCHRG
SRN 12 VREF_ICHG CONTROL
BATOVP or EN_AUDIOFREQ EN_SUPPLEMENT
EN_CHRG
SYSOVP VFB
CELL_LOW
VREF_VREG
4mA 17 BTST
Tj
TSHUT
WAKEUP 155C
18 HIDRV
SRP
GND_PHASE
VREF_SYSMIN ILIM_HI 19 PHASE
350mV**
10uA
GND
ILIM_LOW
PHASE
DAC_VALID EN_REGN
PWM REGN 16 REGN
CHARGE_INHIBIT 1.25mV LDO
LIGHT_LOAD DRIVER
EN_LEARN ACP_ACN LOGIC
SMBUS Interface
VREF_VREG
SDA 8 ACP_ACN
ChargeOption() VREF_ICHG ACOC
ChargeCurrent() 3.33xVREF_IAC**
VREF_IAC
15 LODRV
ChargeVoltage()
InputCurrent() VREF_SYSMIN 4.15V
SCL 9
REFRESH
14 GND
MinsysVoltage() IOUT_SEL BTST_PH
ManufactureID()
DeviceID() EN_DPM SRN
BATOVP
EN_AUDIOFREQ 104%VREF_VREG
EN_LDOMODE
VCC
IOUT_SEL
VCC_SRN
SRN+675mV
bq24715
SRN
SYSOVP ** Threshold is adjustable
VSYSOVP**
CELL_CNT by ChargeOption()
TRI-STAT
CELL 10
BUFFER CELL_LO

bq24715
8.3 Feature Description

8.3.1 Switching Frequency Adjust
The charger switching frequency can be adjusted ±25% to solve EMI issue via SMBus command.
ChargeOption() bit [9:8] can be used to set switching frequency.
If frequency is reduced, the current ripple is increased. Inductor value must be carefully selected so that it will not
trigger cycle-by-cycle peak over current protection even for the worst condition such as higher input voltage, 50%
duty cycle, lower inductance and lower switching frequency.
8.3.2 High Accuracy Current Sense Amplifiers

If LOWPOWER bit is zero (ChargeOption() bit[15] = 0), as an industry standard, high accuracy current sense
amplifiers (CSA) are used to monitor the input current or the discharge current, selectable via SMBUS, see Table
3. Once VCC is above UVLO and ACDET is above 0.6V, input current CSA turns on and the IOUT output
becomes valid. Once SRN is above UVLO and ChargeOption() bit[15] = 0, discharge current CSA turns on and
the IOUT output becomes valid. The CSA senses voltage across the input sense resistor by a factor of 40 or
across the output sense resistor by a factor of 16 through the IOUT pin. To lower the voltage on current
monitoring, a resistor divider from IOUT to GND can be used and accuracy over temperature can still be
achieved.
If LOWPOWER bit is "1" (ChargeOption() bit[15] = 1) and only a valid battery (BAT>UVLO) is connected to
system with an input adaptor (ACDET<0.6V or VCC<UVLO), the IC enter low quiescent current mode, all current
monitoring circuits are turned off.
A 100pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional
RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional response delay.
8.3.3 Charger Timeout

The bq24715 includes a watchdog timer to terminate charging if the charger does not receive a write
ChargeVoltage() or write ChargeCurrent() command within 175s (adjustable via ChargeOption() command). If a
watchdog timeout occurs all register values keep unchanged but charge is suspended. Write ChargeVoltage() or
write ChargeCurrent() commands must be re-sent to reset watchdog timer and resume charging. The watchdog
timer can be disabled, or set to 44s, 88s or 175s via SMBus command (ChargeOption() bit[14:13]). If watchdog is
in timeout, disabling watchdog timer by writing ChargeOption() bit[14:13] also resumes charging.
8.3.4 Input Over-Current Protection (ACOC)

If the input current exceeds the 3.33X of input current DAC set point, ACFET/RBFET is turned-off and charge is
disabled. After 300ms, ACFET/RBFET will be turned on again.
The ACOC function threshold can be set to 3.33X of input DPM current (ChargeOption() bit [7]=1) or function
disable(ChargeOption() bit [7]=0, default) via SMBus command
The bq24715 has a cycle-to-cycle peak over-current protection. It monitors the voltage across Rds_on of the
LSFET or the input current sense resistor, and prevents the converter from over current condition. The high-side
gate drive turns off when the over-current is detected, and resumes automatically when the over-current
condition is gone.
8.3.5 Converter Over-Current Protection

When LODRV pulse is longer than 100ns blanking time, the LSFET OCP is active and the threshold is
automatically set to 350mV (ChargeOption() bit [6]=1, default) or 250mV (ChargeOption() bit [6]=0) via SMBus
command. The blanking time prevents noise when MOSFET just turn on.
When LODRV pulse is shorter than 100ns blanking time, bq24715 uses 2.5 times of InputCurrent() setting
(minimum 45mV) as Vacp-acn protection threshold to turn off the high-side gate drive even the IDPM function is
disabled (0x12[1]=0). Please set InputCurrent() to a right value even IDPM is disabled.

bq24715
Feature Description (continued)

8.3.6 Battery Over-Voltage Protection (BATOVP)
The bq24715 will not allow the BATFET to turn-on when the battery voltage at SRN exceeds 104% of the
regulation voltage set-point. This allows quick response to an over-voltage condition – such as occurs when the
load is removed or the battery is disconnected. A 4mA current sink from SRP to GND is on only during BATOVP
and allows discharging the stored output inductor energy that is transferred to the output capacitors.
8.3.7 System Over-Voltage Protection (SYSOVP)

When system voltage is higher than maximum allowed voltage (VSYSOVP_RISE), it is considered as system
overvoltage. If SYSOVP is detected, it will latch off ACFET, RBFET, and buck converter to prevent any potential
damage to the system due to unexpected short (e.g. high HFET short) or other conditions. Reading chargeoption
bit[11]=1 reflect this latch-off protection and writing chargeoption bit[11]=0 clear the latch. Adapter replug-in can
also clear the latch.
8.3.8 Thermal Shutdown Protection (TSHUT)

The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off for self-
protection whenever the junction temperature exceeds the 155°C. The charger stays off until the junction
temperature falls below 135°C. During thermal shut down, the REGN LDO current limit is reduced to 16mA.
Once the temperature falls below 135°C, charge can be resumed with soft start.
8.3.9 Adapter Over-Voltage Protection (ACOVP)

The bq24715 uses a fixed ACOVP voltage (26V typ). When VCC pin voltage is higher than VACOVP, it is
considered as adapter over voltage. ACOK will be pulled low, and charge will be disabled. ACFET will be turned
off to disconnect high voltage adapter during ACOVP. BATFET will be turned on if turn-on conditions are valid.
See the “ACFET/RBFET and BATFET Control” sections for detail.
When VCC pin voltage falls below 24V and ACDET above 2.4V, it is considered as adapter voltage returns back
to normal voltage. ACOK will be pulled high by external pull up resistor. ACFET and RBFET will be turned on to
power the converter from adapter.
8.3.10 Adapter Detect and ACOK Output

The bq24715 uses an ACOK comparator to determine the present of adapter on VCC pin. An external resistor
voltage divider attenuates the adapter voltage before it goes to ACDET. The VACOK_RISE threshold should make
the adapter voltage greater than the maximum battery voltage plus VCC_SRN (sleep) comparator rising
threshold, but lower than the maximum allowed VACOVP voltage.
The open drain ACOK output requires external pull up resistor to system digital rail for a high level. It can be
pulled to external rail under the following conditions:
• VACOVP > VVCC > UVLO;
• VACDET > 2.4V
• VVCC-VSRN > 675mV (not in sleep mode);
8.3.11 ACFET/RBFET Control

The ACDRV drives a pair of common-source (CMSRC) n-channel power MOSFETs (ACFET: Q1A and RBFET:
Q1B) between adapter and converter. The ACFET separates adapter from converter, and provides a limited di/dt
when plugging in adapter by controlling the ACFET turn-on time. The RBFET provides battery discharge
protection when adapter voltage is lower than battery, and minimizes system power dissipation with its low
RDS(on) compared to a Schottky diode.
When adapter is not present, ACDRV is pulled to CMSRC to keep ACFET and RBFET off. And BATFET is
turned on to discharge battery. After adapter is detected (ACDET pin voltage higher than 2.4V), adapter begins
to provide power to system.
The gate drive voltage on ACFET and RBFET is VCMSRC+6V. If the ACFET and RBFET have been turned on for
20ms, and the voltage across ACDRV and CMSRC is still 0.2V below VACFET, ACFET and RBFET will be turned
off.

bq24715
Feature Description (continued)

To limit the in-rush current on ACDRV pin and CMSRC pin, a 4kΩ resistor is recommended on each of the three
pins.
To limit the adapter inrush current when ACFET is turned on to provide power converter from adapter, the
external Cgs and Cgd capacitor of ACFET must be carefully selected. The larger the Cgs and Cgd capacitance,
the slower turn on of ACFET will be and less inrush current of adapter. However, if Cgs and Cgd is too large, the
ACDRV-CMSRC voltage may still be low after 20ms turn on time window is expired. To make sure ACFET will
not be turned on when adapter is hot plug in, the Cgs value should be 20 times or higher of Cgd.
8.3.12 DPM
When the input current exceeds the input current limit setting and IPM_EN is enabled (ChargeOption() bit [1]=1),
the bq24715 decreases the charge current to provide priority to system load current. As the system current rises,
the available charge current drops linearly to zero. Higher systems loads can be drawn from the battery, battery
discharges and BATFET is turned on when discharge current is higher than 256mA.
To reduce the risk for overcharging battery at battery insertion, please disable charge if the battery is absent.
8.3.13 Buck Converter Power up

After the ACFET is turned on, the converter is enabled and the HSFET and LSFET start switching. Every time
the buck converter is started, the IC automatically applies soft-start (no soft-start when exit LEARN) on buck
output current to avoid any overshoot or stress on the output capacitors or the power converter. The buck output
current starts at 128mA, and the step size is 64mA in CCM mode for a 10mΩ current sensing resistor. Each step
lasts around 24µs in CCM mode, until it reaches the programmed charge current limit. No external components
are needed for this function.
When power up, converter output voltage is default value set by CELL pin configuration. After converter starts
switching about 100ms, CELL pin setting is locked. If CELL pin is pulled to LOW when power-up, converter
output is default 2S for bq24715.
8.4 Device Functional Modes

8.4.1 LDO Mode and Minimum System Voltage
The BATDRV drives a p-channel BATFET between converter output (system node) and battery to provide a
charge and discharge path for battery. When battery voltage is below the minimum system voltage setting, this
BATFET works in linear mode as LDO (default chargeoption() bit[2]=1, the precharge current is set by
ChargeCurrent() and clamped below 384mA) thus to keep system node voltage always higher than the minimum
system voltage setting. If battery voltage reaches the minimum system voltage, BATFET fully turns on. This LDO
function can be optionally disabled by set "LDO Mode Enable" bit low (chargeoption() bit[2]=0) and BATFET is
fully turned on. At this condition, the battery pack internal circuit will maintain battery terminal voltage higher than
system minimum voltage. And the precharge current also determined by battery pack internal circuit.

bq24715
Device Functional Modes (continued)
MaxChargeVoltage
MinSystemVoltage
2.7 V
0 mV
ChargeCurrent
LDO Mode Enable
384 mA
0 mA
LDO Mode Disable

128 mA
0 mA
Figure 6. ChargeOption[2] (LDO Mode)
8.4.2 PWM Mode Converter Operation

The synchronous buck PWM converter uses a fixed frequency voltage control scheme and internal type III
compensation network. The LC output filter gives a characteristic resonant frequency
1
fo =
2p Lo Co (1)
The resonant frequency fo is used to determine the compensation to ensure there is sufficient phase margin for
the target bandwidth. Suggested component value as charge current of 800Hz default switching frequency is
shown in Table 8.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is
applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant
capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data
sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage
rating or nominal capacitance value in order to get the required value at the operating point.
Table 1. Suggested Component Value as Output Current of Default 800-kHz

Switching Frequency
Component Recommended Value
Output Inductor Lo (µH) 3.3 or 2.2
System node capacitor (µF) 47- 350 (1)
SRN node Capacitor Co (µF) 0.1-1
Sense Resistor (mΩ) 10
(1) If system capacitance is higher than 350µF, please contact TI techniclal support.
The bq24715 has four loops of regulation: input current, charge current, charge voltage and minimum system
voltage. The four loops are brought together internally at the error amplifier. The maximum voltage of the four
loops appears at the output of the error amplifier EAO. An internal saw-tooth ramp is compared to the internal
error control signal EAO to vary the duty-cycle of the converter.
When the battery charge voltage approaches the input voltage, EAO signal is allowed to exceed the saw-tooth
ramp peak in order to get a 100% duty-cycle. If voltage across BTST and PHASE pins falls below VBTST_REFRESH,
a refresh cycle starts and low-side n-channel power MOSFET is turned on to recharge the BTST capacitor. It can
achieve duty cycle of up to 99.5% with pulse skip.
bq24715
8.4.3 Continuous Conduction Mode (CCM)

With sufficient charge current, the inductor current never crosses zero, which is defined as Continuous
Conduction Mode. The controller starts a new cycle with ramp coming up from 200mV. As long as EAO voltage
is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds EAO
voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of each switching cycle, ramp gets
reset and LSFET turns off, ready for the next cycle. There is always break-before-make logic during transition to
prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the body-diode
of the low-side power MOSFET conducts the inductor current.
During CCM mode, the inductor current is always flowing and creates a fixed two-pole system. Having the
LSFET turn-on keeps the power dissipation low, and allows safely at high output currents.
8.4.4 Discontinuous Conduction Mode (DCM)

When LSFET is turned on, the inductor current will decrease. If this current goes to zero, the converter enters
Discontinuous Conduction Mode. Every cycle, when the voltage across ACP and ACN falls below 1.25mV
(125mA on 10mΩ), the light-load comparator turns off LSFET to avoid negative inductor current, which may
boost the system via the body diode of HSFET. There is also a cycle-by-cycle converter under-current
comparator monitor the LFET current and prevent it goes negative.
During the DCM mode the loop response automatically changes. It changes to a single pole system and the pole
is proportional to the load current.
8.4.5 PFM Mode

In order to improve converter light-load efficiency, the bq24715 switches to PFM control at light load with charge
disable or charge in LDO mode. The effective switching frequency will decrease accordingly when system load
decreases. The minimum frequency can be limit to 40kHz if set IDPM_EN bit high (ChargeOption() bit[10]=1). To
have higher light load efficiency, set "Audio Frequency Limit" bit low (Chargeoption() bit[10]=0, default).
8.4.6 Learn Mode

A battery LEARN cycle can be activated via SMBus "LEARN Enable" command (ChargeOption() bit[5]=1 enable
Learn Mode). When LEARN is enabled with an adapter connected, the system power switch to battery by turning
off converter and keep ACFET/BATFET on. Learn mode allows the battery to discharge in order to calibrate the
battery gas gauge over a complete discharge/charge cycle. When LEARN is disabled, the system power switch
to adapter by turning on converter in a few hundreds µs.
The bq24715 also supports hardware pin to exist LEARN mode by pulling CELL to GND. When Cell pin is pulled
to GND,bq24715 resets "LEARN Enable" (ChargeOption() bit[5]) and IDPM_EN (ChargeOption() bit[1]), and
reset chargevoltage() and chargecurrent().
8.4.7 IDPM Disable at Battery Removal

CELL pull to GND can also be used to disable IDPM function automatically when battery is removed.
When battery present, IOUT monitors discharge current and CPU can do throttling when IOUT is higher than
battery discharge limit.
When battery is removed, CELL is pulled to GND. IC disables input DPM function and switch IOUT to monitor
input current, thus CPU throttling when IOUT higher than limit.
After insert battery back, EC need set bit[1]=1 to enable IDPM function.
• Customer who has external discharge current monitor can set "FIX IOUT" ChargeOption() bit[3]=1 and "IOUT
Selection" ChargeOption() bit[4]=0 to have fixed IOUT monitoring adapter current.
• Customer who has external adapter current monitor can set "FIX IOUT" ChargeOption() bit[3]=1 and "IOUT
Selection" ChargeOption() bit[4]=1 to have fixed IOUT monitoring discharge current.

bq24715
8.5 Programming
8.5.1 SMBus Communication
8.5.1.1 SMBus Interface

The bq24715 supports SMBus communication interface. Gas gauge broadcasting mode is supported.
The bq24715 operates as a slave, receiving control inputs from the embedded controller host through the SMBus
interface. The device uses a simplified subset of the commands documented in System Management Bus
Specification V1.1, which can be downloaded from www.smbus.org. The bq24715 uses the SMBus Read-Word
and Write-Word protocols (Figure 7) to communicate with the smart battery. The bq24715 performs only as a
SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In
addition, the device has two identification registers a 16-bit device ID register (0xFFH) and a 16-bit manufacturer
ID register (0xFEH).
SMBus communication is enabled with the following conditions:
• VVCC or VSRN is above UVLO;
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose
pull-up resistors (10kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications.
Communication starts when the master signals a START condition, which is a high-to-low transition on SDA,
while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a
low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 2 and
Figure 3 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and
data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is
low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising
edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24715 because either the
master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq24715
supports the charger commands as described in Table 2.
8.5.1.1.1 Write-Word Format
S SLAVE ADDRESS W ACK COMMAND BYTE ACK LOW DATA BYTE ACK HIGH DATA BYTE ACK P
7 BITS 1b 1b 8 BITS 1b 8 BITS 1b 8 BITS 1b
MSB m LSB 0 0 MSB m LSB 0 MSB m LSB 0 MSB m LSB 0
Preset to 0b0001001 ChargeCurrent() = 0x14H D7 m D0 D15mD0

ChargeVoltage() = 0x15H
InputCurrent() = 0x3FH
MinSysVoltage() = 0x3EH
ChargeOption() = 0x12H
8.5.1.1.2 Read-Word Format
SLAVE COMMAND SLAVE LOW DATA HIGH DATA

S W ACK ACK S R ACK ACK NACK P
ADDRESS BYTE ADDRESS BYTE BYTE
7 BITS 1b 1b 8 BITS 1b 8 BITS 1b 1b 8 BITS 1b 8 BITS 1b
MSB m LSB 0 0 MSB m LSB 0 MSB m LSB 1 0 MSB m LSB 0 MSB m LSB 1
Preset to 0b0001001 DeviceID() = 0xFFH Preset to D7mD0 D15mD0

ManufactureID() = 0xFEH 0b0001001
ChargeVoltage() = 0x15H
InputCurrent() = 0x3FH
MinSysVoltage() = 0x3EH
ChargeOption() = 0x12H

bq24715
LEGEND:
S = START CONDITION OR REPEATED START CONDITION P = STOP CONDITION
ACK = ACKNOWLEDGE (LOGIC-LOW) NACK = NOT ACKNOWLEDGE (LOGIC-HIGH)
W = WRITE BIT (LOGIC-LOW) R = READ BIT (LOGIC-HIGH)
MASTER TO SLAVE
SLAVE TO MASTER
Figure 7. SMBus Write-Word and Read-Word Protocols
8.5.1.2 SMBus Commands

The bq24715 supports seven battery-charger commands that use either Write-Word or Read-Word protocols, as
summarized in Table 2. ManufacturerID() and DeviceID() can be used to identify the bq24715. The
ManufacturerID() command always returns 0x0040H and the DeviceID() command always returns 0x0010H.
Table 2. Battery Charger Command Summary

REGISTER
READ/WRITE DESCRIPTION COMMENT
ADDRESS NAME
0x12H ChargeOption() Read or Write Charger Options Control ● Default E144H
● Default 0mA, 64mA Step
● Range:128mA -8.128A
7-Bit Charge Current ● Bit [15] [14][13] value is ignored and counted as zero.
0x14H ChargeCurrent() Read or Write
Setting Any value below 64mA results in zero.
Write 64mA only is ignored
● 0mA disable charge
● Default 2S-9V, 3S-13.5V;
● 16mV Step
11-Bit Charge Voltage
0x15H MaxChargeVoltage() Read or Write ● Range: 4.096V – 14.5V
Setting
● Any value below 4.096V results in default value; not allow
chargervoltage lower than minsystemvoltage
● Default 2S-6.144V, 3S-9.216V;
● 256mV Step
6-Bit Minimum System
0x3EH MinSystemVoltage() Read or Write ● Range: 4.096V – 14.5V
Voltage Setting
● Any value out of range is ignored; not allow minsystemvoltage
higher than chargervoltage.
● Default 3.2A, 64mA Step
0x3FH InputCurrent() Read or Write 7-Bit Input Current Setting ● Range:128mA -8.064A
● Any value out of range is ignored.
0xFEH ManufacturerID() Read Only Manufacturer ID 0x0040H
0xFFH DeviceID() Read Only Device ID 0x0010H

bq24715
8.5.1.3 Setting Charger Options

By writing ChargeOption() command (0x12H or 0b00010010), bq24715 allows users to change several charger
options after POR (Power On Reset) as shown in Table 3.
Table 3. Charge Options Register (0x12H)

BIT BIT NAME DESCRIPTION
[15] LOWPOWER Effective on BAT power only (ACDET<0.6 or VCC<UVLO)
0: turn on discharge current monitoring
1: lower quiescent current, discharge current monitoring are turned off <default @ POR>
[14:13] WATCHDOG Timer Set maximum delay between consecutive SMBus Write charge voltage or charge current command. The
Adjust charge will be suspended if IC does not receive write charge voltage or write charge current command
within the watchdog time period and watchdog timer is enabled.
The charge will be resumed after receive write charge voltage or write charge current command when
watchdog timer expires and charge suspends.
00: Disable Watchdog Timer
01: Enabled, 44 sec
10: Enabled, 88 sec
11: Enable Watchdog Timer (175s) <default @ POR>
[12] SYSOVP Converter latch-off when sysovp is detected.
0: 15.1 V for 3s; 10.1 V for 2s <default @ POR>
1: 17.0 V for 3s, 11.3 V for 2s
[11] SYSOVP status& 0: not OVP (default; write 0 to clear the OVP status)
clear 1: OVP latch (read only)
[10] Audio Frequency 0: No limit of switching frequency <default @ POR>
Limit 1: Set minimum switching frequency to 40 kHz to avoid audio noise
[9:8] Switching Frequency 00:600kHz
Setting 01:800kHz <default @ POR>
10: 1MHz
11: 800 kHz
[7] ACOC setting ACOC protection threshold by detecting the ACP_ACN voltage.
0: function is disable <default @ POR>
1: 333% IDPM
[6] LSFET OCP When LSFET is ON, check the Rdson voltage drop, limit the current cycle-by-cycle
threshold 0: 250mV
1: 350mV <default>
[5] LEARN Enable IC turns off buck converter (ACFET and RBFET still on), and turns on BATFET to support battery
discharge mode. Set this bit 0 will stop LEARN mode and turn on buck converter back. Can be used to
support battery LEARN mode
0: Disable LEARN Mode <default @ POR>
1: Enable LEARN Mode
[4] IOUT Selection When bit[3]=1, bit[4] serve as input
MM 0: IOUT is the 40x adapter current amplifier output
MM 1: IOUT is the 16x discharge current amplifier output
When bit[3]=0, bit[4] serve as output (indicate IOUT selection)
MM 0: IOUT the 40x adapter current amplifier output; when IDPM is disabled <default @ POR>
MM 1: IOUT is the 16x discharge current amplifier output; when IDPM is enabled
[3] FIX IOUT 0: switch IOUT based on IDPM_EN <default @ POR>
1: select IOUT based on bit[4]
[2] LDO Mode Enable 0: Disable LDO mode. BATFET ON. Precharge current is set by battery pack LDO.
1: Enable LDO mode - Precharge current is set by ChargeCurrent() and clamped below 384mA
<default@POR>
[1] IDPM_EN 0: Disable <default @ POR>
1: Enable
[0] Charge Inhibit 0: Enable Charge <default @ POR>
1: Inhibit Charge

bq24715
8.5.1.4 Setting the Charge Current

To set the charge current, write a 16bit ChargeCurrent() command (0x14H or 0b00010100) using the data format
listed in Table 6. With 10mΩ sense resistor, the bq24715 provides a charge current range of 128mA to 8.128A,
with 64mA step resolution. Sending ChargeCurrent() below 64mA clears the register and terminates charging.
Upon POR, charge current is 0 A. A 0.1-µF capacitor between SRP and SRN for differential mode filtering is
recommended, 0.1µF capacitor between SRN and ground for common mode filtering, and an optional 0.1µF
capacitor between SRP and ground for common mode filtering.
The SRP and SRN pins are used to sense RSNS with default value of 10mΩ. However, resistors of other values
can also be used. For a larger sense resistor, a larger sense voltage is given, and a higher regulation accuracy;
but, at the expense of higher conduction loss.
Because writing valid 0x14H will enable charge, even if 0x15H is not changed (0x15H has default value at start-
up). EC needs write 0x15H – (charge voltage) first, then write 0x14H – (charge current). After enable charge, IC
will regulate the charge voltage and current at 0x14H and 0x15H setting to reduce the risk for overcharging
battery. Also, please keep 0x14H register at zero if the battery is absent.
Table 4. Charge Current Register (0x14H), using 10-mΩ Sense Resistor

0 — Not used.
1 — Not used.
2 — Not used.
3 — Not used.
4 — Not used.
5 — Not used.
6 Charge Current, DACICHG 0 0 = Adds 0mA of charger current.
1 = Adds 64mA of charger current.
13 — Not used.
14 — Not used.
15 — Not used.

bq24715
8.5.1.5 Setting the Max Charge Voltage

To set the output charge regulation voltage, write a 16bit MaxChargeVoltage() command (0x15H or 0b00010101)
using the data format listed in Table 5. The bq24715 provides charge voltage range from 4.096 V to 9.6 V (2S
setting) or 14.5 V (3S setting), with 16mV step resolution. Upon POR, Max charge voltage limit is 13.504 V for
3S setting (CELL=HIGH) or 9.008 V for 2S setting (CELL pin floating). Any value below 4.096 V results in default
value.
If enable charge without writing any command to 0x15 register, the MaxChargeVoltage() is automatically
changed to 8.4 V (2S setting) or 12.6 V (3S setting). If disable charge without writing any command to 0x15
register ever, the MaxChargeVoltage() automatically goes back to POR value. Once writing a valid number to
0x15 register, the MaxChargeVoltage() doesn't automatically change between enable charge and disable charge.
The SRN pin is used to sense the battery voltage for voltage regulation and should be connected as close to the
battery as possible, and directly place a decoupling capacitor (0.1 µF recommended) as close to IC as possible
to decouple high frequency noise.
Table 5. Max Charge Voltage Register (0x15H)

0 — Not used.
1 — Not used.
2 — Not used.
3 — Not used.
4 Charge Voltage, DACV 0 0 = Adds 0mV of charger voltage.
1 = Adds 16mV of charger voltage.
15 — Not used.

bq24715
8.5.1.6 Setting the Minimum System Voltage

To set the minimum system voltage, write a 16bit MinSystemVoltage() command (0x3EH or 0b00111110) using
the data format listed in Table 6. The bq24715 provides minimum system voltage range from 4.096 V up to
maximum charge voltage, with 256 mV step resolution. Any MinSystemVoltage() below 4.096 V. Upon POR (set
via CELL), charge voltage limit is 6.144 V for 2S setting and 9.216 V for 3S setting.
Table 6. Minimum System Voltage Register (0x3EH)

0 — Not used.
1 — Not used.
2 — Not used.
3 — Not used.
4 — Not used.
5 — Not used.
6 — Not used.
7 — Not used.
8 Minimum System Voltage, 0 = Adds 0mV of system voltage.
DACMINSV 0 1 = Adds 256mV of system voltage.
14 — Not used.
15 — Not used.

bq24715
8.5.1.7 Setting Input Current

System current normally fluctuates as portions of the system are powered up or put to sleep. With the input
current limit, the output current requirement of the AC wall adapter can be lowered, reducing system cost.
The total input current, from a wall cube or other DC source, is the sum of the system supply current and the
current required by the charger. When the input current exceeds the set input current limit, the bq24715
decreases the charge current to provide priority to system load current. As the system current rises, the available
charge current drops linearly to zero. Keep increasing the system current and the battery will run into supplement
mode.
During DPM regulation, the total input current is the sum of the device supply current IBIAS, the charger input
current, and the system load current ILOAD, and can be estimated as follows:
éI V +I ´ VBATTERY ù
IINPUT = ê LOAD SYS BATTERY ú + IBIAS
ë VIN ´ h û (2)
where η is the efficiency of the charger buck converter (typically 85% to 95%).
To set the input current limit, write a 16-bit InputCurrent() command (0x3FH or 0b00111111) using the data
format listed in Table 7. When using a 10-mΩ sense resistor, the bq24715 provides an input-current limit range
of 128 mA to 8.064 A, with 64 mA resolution. Sending InputCurrent() below 128 mA or above 8.064 A are
ignored. Upon POR, default input current limit is 3.2 A.
The ACP and ACN pins are used to sense RAC with default value of 10 mΩ. However, resistors of other values
can also be used. For a larger sense resistor, larger sense voltage is given, and a higher regulation accuracy;
but, at the expense of higher conduction loss.
Table 7. Input Current Register (0x3FH), Using 10-mΩ Sense Resistor

0 — Not used.
1 — Not used.
2 — Not used.
3 — Not used.
4 — Not used.
5 — Not used.
6 Input Current, DACIIN 0 0 = Adds 0mA of input current.
1 = Adds 64mA of input current.
13 — Not used.
14 — Not used.
15 — Not used.

bq24715
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

The bq24715EVM-115 evaluation module (EVM) is a complete charger module for evaluating the bq24715. The
application curves were taken using the bq24715EVM-115. Refer to the EVM user's guide (SLUUA74) for EVM
information.
9.2 Typical Application
Adapter CSD87312Q3E
D1
Q1A Q1B RAC 10mΩ BAT54
C1 R6
0.1µF 10Ω C6
C5 10µFx2
1µ F
R4 C2 C3 C4
R3 4kΩ 1µF 0.1µF 0.1µF
4kΩ C7:1µF SYSTEM LOAD
ACN VCC
R1 ACP REGN
R5 D2 Csys
430kΩ BAT54 Q4 200 µF
CMSRC BTST 15 Ω
CSD17308Q3
ACDRV HIDRV L: 2.2µH Battery

C8
47nF Pack
ACDET PHASE
R2
+3.3V bq24715 Rsns
66.5kΩ Q3
R7 R8 R9 10mΩ Q2
LODRV
10kΩ 10kΩ 10kΩ C10 CSD25401Q3
CSD17308Q3 C12
SMBus SDA GND 10µFx2
1µF
SCL
HOST Dig I/O
ACOK
SRP
A/D C9
IOUT 0.1µF
C11 SRN
100pF C13 0.1µF
R10 /BATDRV
REGN CELL GND
100kΩ PowerPAD
Fs = 800kHz, IADPT = 3.0A, ICHRG = 2.944A, ISYSTEM = 5A, VCHRG = 12.592V, 65W adapter and 3S2P battery pack
Csys : 200 µF is lumped system bus capacitance
Figure 8. Typical Application Circuit

bq24715
Typical Application (continued)

Table 8. Component List for Figure 8
PART DESIGNATOR QTY DESCRIPTION
C1, C3, C4, C9, C13, 5 Capacitor, Ceramic, 0.1 µF, 25 V, 10%, X7R, 0603
C2, C5, C7, C12 2 Capacitor, Ceramic, 1 µF, 25 V, 10%, X7R, 0603
C6, C10 4 Capacitor, Ceramic, 10 µF, 25 V, 10%, X7R, 1206
C8 1 Capacitor, Ceramic, 0.04 7µF, 25 V, 10%, X7R, 0603
C11 1 Capacitor, Ceramic, 100 pF, 25 V, 10%, X7R, 0603
Csys 1 Capacitor, Electrolytic, 220 µF, 25 V
D1, D2 2 Diode, Schottky, 30 V, 200 mA, SOT-23, Fairchild, BAT54
Q1 1 Dual N-channel MOSFET, 30 V, SON3.3X3.3, TI, CSD87312Q3E
Q2 1 P-channel MOSFET, -20 V, SON3.3X3.3, TI, CSD25401Q3
Q3, Q4 2 N-channel MOSFET, 30 V, SON3.3X3.3, TI, CSD17308Q3
L1 1 Inductor, SMT, 9.2 A, 16.5mohm, Vishay, IHLP3232DZER3R3M01
R1 1 Resistor, Chip, 43 0 kΩ, 1/10W, 1%, 0603
R2 1 Resistor, Chip, 66.5 kΩ, 1/10W, 1%, 0603
R3, R4 2 Resistor, Chip, 4.02 kΩ, 1/10W, 1%, 0603
R5 1 Resistor, Chip, 15 Ω, 1/4W, 5%, 0603
R6 1 Resistor, Chip, 10 Ω, 1/4W, 1%, 1206
R7, R8, R9 3 Resistor, Chip, 10.0 kΩ, 1/10W, 1%, 0603
RAC, Rsns 2 Resistor, Chip, 0.01 Ω, 1/2W, 1%, 1206
U1 1 Charger controller, 20-pin VQFN, TI, bq24715RGR
9.2.1 Design Requirements

For this example, use the following as the input parameters.
Table 9. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input Voltage 17.7 V < Adapter Voltage < 24 V
Input Current Limit 3.2 A for 65-W adapter
Battery Charge Voltage 8400 mV for 2s battery
Battery Charge Current 4096 mA for 3s battery
Minimum System Voltage 6144 mA for 2s battery
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection

The bq24715 has three selectable fixed switching frequency. Higher switching frequency allows the use of
smaller inductor and capacitor values. Inductor saturation current should be higher than the charging current
(ICHG) plus half the ripple current (IRIPPLE):
ISAT ³ ICHG + (1/2) IRIPPLE (3)
The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fS) and
inductance (L):
V ´ D ´ (1 - D)
IRIPPLE = IN
fS ´ L (4)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging
voltage range is from 9V to 12.6V for 3-cell battery pack. For 20 V adapter voltage, 10 V battery voltage gives
the maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12 V to
16.8 V, and 12 V battery voltage gives the maximum inductor ripple current.

bq24715
Usually inductor ripple is designed in the range of (20-40%) maximum charging current as a trade-off between
inductor size and efficiency for a practical design.
9.2.2.2 Input Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case
RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at
50% duty cycle, then the worst case capacitor RMS current occurs where the duty cycle is closest to 50% and
can be estimated by Equation 5:
ICIN = ICHG ´ D × (1 - D) (5)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage
rating of the capacitor must be higher than normal input voltage level. 25-V rating or higher capacitor is preferred
for 19-20 V input voltage. 10-20 μF capacitance is suggested for typical of 3-4 A charging current.
applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a significant
capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's data
9.2.2.3 Output Capacitor

Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The
output capacitor RMS current is given:
I
ICOUT = RIPPLE » 0.29 ´ IRIPPLE
2 ´ 3 (6)
The preferred ceramic capacitor is 25V X7R or X5R for output capacitor. Capacitance of 47μF ~ 350μF is
suggested for the output capacitor. Place the capacitors after charging current sensing resistor to get the best
charge current regulation accuracy.
applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant
capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data
9.2.2.4 Power MOSFETs Selection

Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are
internally integrated into the IC with 6V of gate drive voltage. 30V or higher voltage rating MOSFETs are
preferred for 19-20 V input voltage.
Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction
loss and switching loss. For the top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance,
RDS(ON), and the gate-to-drain charge, QGD. For the bottom side MOSFET, FOM is defined as the product of the
MOSFET's on-resistance, RDS(ON), and the total gate charge, QG.
FOMtop = RDS(on) x QGD; FOMbottom = RDS(on) x QG (7)
The lower the FOM value, the lower the total power loss. Usually lower RDS(ON) has higher cost with the same
package size.
The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle
(D=VOUT/VIN), charging current (ICHG), MOSFET's on-resistance (RDS(ON)), input voltage (VIN), switching frequency
(fS), turn on time (ton) and turn off time (toff):
1
Ptop = D ´ ICHG2 ´ RDS(on) + ´ VIN ´ ICHG ´ (t on + t off ) ´ f s
2 (8)

bq24715
The first item represents the conduction loss. Usually MOSFET RDS(ON) increases by 50% with 100°C junction
temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn-off times are
given by:
Q Q
t on = SW , t off = SW
Ion Ioff (9)
where Qsw is the switching charge, Ion is the turn-on gate driving current and Ioff is the turn-off gate driving
current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge
(QGD) and gate-to-source charge (QGS):
1
QSW = QGD + ´ QGS
2 (10)
Gate driving current can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total turn-on
gate resistance (Ron) and turn-off gate resistance (Roff) of the gate driver:
VREGN - Vplt Vplt
Ion = , Ioff =
Ron Roff (11)
The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in
synchronous continuous conduction mode:
Pbottom = (1 - D) x ICHG 2 x RDS(on) (12)
When charger operates in non-synchronous mode, the bottom-side MOSFET is off. As a result all the
freewheeling current goes through the body-diode of the bottom-side MOSFET. The body diode power loss
depends on its forward voltage drop (VF), non-synchronous mode charging current (INONSYNC), and duty cycle (D).
PD = VF x INONSYNC x (1 - D) (13)
The maximum charging current in non-synchronous mode can be up to 0.25 A for a 10mΩ charging current
sensing resistor or 0.5A if battery voltage is below 2.5 V. The minimum duty cycle happens at lowest battery
voltage. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the
maximum non-synchronous mode charging current.
9.2.2.5 Input Filter Design

During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second
order system. The voltage spike at VCC pin maybe beyond IC maximum voltage rating and damage IC. The
input filter must be carefully designed and tested to prevent over voltage event on VCC pin.
There are several methods to damping or limit the over voltage spike during adapter hot plug-in. An electrolytic
capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin
voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level.
However these two solutions may not have low cost or small size.
A cost effective and small size solution is shown in Figure 9. The R1 and C1 are composed of a damping RC
network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is used
for reverse voltage protection for VCC pin. C2 is VCC pin decoupling capacitor and it should be place to VCC pin
as close as possible. C2 value should be less than C1 value so R1 can dominant the equivalent ESR value to
get enough damping effect. R2 is used to limit inrush current of D1 to prevent D1 getting damage when adapter
hot plug-in. R2 and C2 should have 10us time constant to limit the dv/dt on VCC pin to reduce inrush current
when adapter hot plug in. R1 has high inrush current. R1 package must be sized enough to handle inrush current
power loss according to resistor manufacturer’s datasheet. The filter components value always need to be
verified with real application and minor adjustments may need to fit in the real application circuit.

bq24715
D1
R2(1206)
R1(2010) 10-20 Ω
Adapter 2Ω
connector VCC pin
C1
2.2μF C2
0.47-1μF
Figure 9. Input Filter
9.2.3 Application Curves
Table 10. Table of Graphs

FIGURES
VCC, ACDET, REGN and ACOK Power Up Figure 10
System Power Up Figure 11
Charge Startup and Shutdown Figure 12
PFM Mode Switching Waveforms Figure 13
PwM Mode Switching Waveforms Figure 14
CELL-GND in Learn Mode Figure 15
0~3A System Load Transient (IDPM disable and Charge disable) Figure 16
2~6A System Load Transient (IDPM disable and Charge disable) Figure 17
0~3A System Load Transient (IDPM enable and Charge enable) Figure 18
2~6A System Load Transient (IDPM enable and Charge enable) Figure 19
CH1: VCC/VIN, 10V/div, CH2: ACDET, 5V/div, CH3: ACOK, 5V/div, CH1: CELL, 2V/div; CH2: SRN, 10V/div; CH3: PHASE, 20V/div;
CH4: REGN, 5V/div, 1ms/div CH4: VCC, 10/div, 10ms/div
Figure 10. VCC, ACDET, REGN and ACOK Power Up Figure 11. System Power Up

bq24715
CH1: BATDRV, 5V/div; CH2: SRN, 5V/div; CH3: Inductor current, CH2: system voltage (AC), 200mA/div, CH3: PHASE, 20V/div, CH4:
5A/div; CH4: Charge current, 5A/div, 200ms/div inductor current, 2A/div, 10µs/div
Figure 12. Charge Startup and Shutdown Figure 13. PFM Mode Switching Waveforms
CH1: Input current, 1A/div; CH2: system voltage AC), 200mV/div, CH1: CELL, 2V/div, CH2: system voltage, CH3: input current,
CH3: PHASE, 20V/div, CH4: (inductor current, 2A/div, 1µs/div 2A/div, 5V/div, CH4: inductor current, 2A/div, 200µs/div
Figure 14. PWM Mode Switching Waveforms Figure 15. CELL-GND in Learn Mode
CH1: Input current, 2A/div; CH2: system voltage(AC), 200mv/div; CH1: Input current, 2A/div; CH2: system voltage(AC), 200mv/div;
CH3: IOUT, 1V/div; CH4: inductor current, 2A/div, 1ms/div CH3: IOUT, 1V/div; CH4: inductor current, 2A/div, 200µs/div
Figure 16. 0~3A System Load Transient (IDPM Disable and Figure 17. 2~6A System Load Transient (IDPM Disable and
Charge Disable) Charge Disable)

bq24715
CH2: system voltage (AC), 200mV/div; CH3: system load current, CH1: input current, 1A/div; CH2: system voltage (AC), 5V/div; CH3:
5A/div; CH4: battery charge current, 2A/div, 400us/div system load, 5A/div; CH4: battery charge current, 5A/div, 1ms/div
Figure 18. 0~3A System Load Transient (IDPM Enable and Figure 19. 2 to 6 A System Load Transient (IDPM Enable
Charge Enable) and Charge Enable)
10 Power Supply Recommendations

When adapter is attached, and ACOK goes HIGH, the system is connected to adapter through ACFET/RBFET.
An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The adapter detect
threshold should typically be programmed to a value greater than the maximum battery voltage, but lower than
the IC maximum allowed input voltage (ACOVP) and system maximum allowed voltage.
When adapter is removed, the system is connected to battery through BATFET. Typically the battery depletion
threshold should be greater than the minimum system voltage so that the battery capacity can be fully utilized for
maximum battery life.

bq24715
11 Layout
11.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 20) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout PCB according to this specific order is essential.
1. Place input capacitor as close as possible to switching MOSFET’s supply and ground connections and use
shortest copper trace connection. These parts should be placed on the same layer of PCB instead of on
different layers and using vias to make this connection.
2. The IC should be placed close to the switching MOSFET’s gate terminals and keep the gate drive signal
traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching
MOSFETs.
3. Place inductor input terminal to switching MOSFET’s output terminal as close as possible. Minimize the
copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop
area) and do not route the sense leads through a high-current path (see Figure 21 for Kelvin connection for
best current accuracy). Place decoupling capacitor on these traces next to the IC.
5. Place output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC
use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
8. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using power pad as the single ground
connection point. Or using a 0Ω resistor to tie analog ground to power ground (power pad should tie to
analog ground in this case if possible).
9. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
10. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
11. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the QFN
information, see SCBA017 and SLUA271.

bq24715
11.2 Layout Example
Figure 20. High Frequency Current Path
Figure 21. Sensing Resistor PCB Layout

bq24715
12 Device and Documentation Support
12.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
BQ24715RGRR ACTIVE VQFN RGR 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR BQ715
BQ24715RGRT ACTIVE VQFN RGR 20 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR BQ715
HPA02277RGRR ACTIVE VQFN RGR 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR BQ715
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Sep-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ24715RGRR VQFN RGR 20 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q2
BQ24715RGRT VQFN RGR 20 250 180.0 12.4 3.75 3.75 1.15 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Sep-2018
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ24715RGRR VQFN RGR 20 3000 367.0 367.0 35.0
BQ24715RGRT VQFN RGR 20 250 210.0 185.0 35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGR 20 VQFN - 1 mm max height
3.5 x 3.5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4228482/A
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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bq24715 2-3 Cell NVDC-1 Battery Charger Controller

4 Simplified Application Diagram

Copyright © 2016, Texas Instruments Incorporated

Changes from Revision A (February 2014) to Revision B Page

• Added Full Production Data specifications to data sheet ...................................................................................................... 4

Changes from Original (March 2013) to Revision A Page

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6 Pin Configuration and Function

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Pin Descriptions (continued)

7.2 ESD Ratings

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7.3 Recommended Operating Conditions

7.4 Thermal Information

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7.5 Electrical Characteristics

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Electrical Characteristics (continued)

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Electrical Characteristics (continued)

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Electrical Characteristics (continued)

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Electrical Characteristics (continued)

7.6 Timing Requirements

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7.7 SMBus Timing Characteristics

Figure 1. SMBus Communication Timing Waveforms

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Figure 2. SMBus Writing Timing

tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:DAT tSU:STO tBUF

Figure 3. SMBus Read Timing

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7.8 Typical Characteristics

60% VSYS = 13.5 V

20% VSYS = 8.4 V 90%

System Load Current (A) 0 2 4 6 8 10

VIN = 19.5 V System Load Current (A)

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8.2 Functional Block Diagram

WD_TIMEOUT WATCHDOG EN_CHRG

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8.3 Feature Description

8.3.2 High Accuracy Current Sense Amplifiers

8.3.3 Charger Timeout

8.3.4 Input Over-Current Protection (ACOC)

8.3.5 Converter Over-Current Protection

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