2023-2024

Sessional Test I–March, 2023

Set-A

Roll No: ……………… [Total No. of Pages: 3]

General Instructions:

● Follow the instructions given in each section.

● Do not write anything on the question paper, except your roll no.

● Make sure that you attempt the questions in order.

Section - A
(Q 1 to 5: Each question carries 1 mark)

Q1 Four addressing modes are given below. Specify the mode in which the operand value is directly specified.
a) Immediate b) Direct
c) Indirect d) Relative
Ans: a
Q2 The sequence of register transfers are given below. Which of the following correspond to instruction fetch?
a) AR←PC, IR←M[AR], PC←PC+1
b) IR←PC, AR←M[IR], PC←PC+1
c) PC←IR, AR←IR, PC←PC+1
d) AR←IR, IR←M[PC], PC←PC+1
Ans: a
Q3 A MOD-60 counter is to be designed. How many flip-flops are required to implement this operation?

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a) 4 b) 5
c) 6 d) 7
Ans: c
Q4 Refer to the NAND and NOR latches shown in the figure below. The inputs (P1, P2) for both latches are first
made (0, 1) and then, after a few seconds, made (1, 1). The corresponding stable outputs (Q1, Q2) are:

a) NAND: first (0, 1) then (0, 1) NOR: first (1, 0) then (0, 0)
b) NAND : first (1, 0) then (1, 0) NOR : first (0, 1) then (0, 0)
c) NAND : first (1, 0) then (1, 0) NOR : first (1, 0) then (0, 0)
d) NAND : first (1, 0) then (1, 1) NOR : first (0, 1) then (0, 1)
Ans: b

Q5 The boolean function Y = AB + CD is to be realized using only 2-input NAND gates. The minimum number of
gates required are:
a) 2 b) 3
c) 4 d) 5
Ans: b

Section - B
(Q 6 to 10: Each question carries 3 marks)

Q6 Explain what is meant by Race Around condition in relation to the JK flip flop. Suggest a method of avoiding
it.
Ans:
Race Around Condition In JK Flip-flop – For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q
output will toggle as long as CLK is high, which makes the output of the flip-flop unstable or uncertain. This prob -
lem is called race around condition in J-K flip-flop. This problem (Race Around Condition) can be avoided by en -
suring that the clock input is at logic “1” only for a very short time. This introduced the concept of Master Slave

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JK flip flop. The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together in a
series configuration.

Q7 A 4-bit serial-in-parallel-out shift register is initially set to 1111. The data 1010 is applied to the input. List the
sequence of states after each shift for 3 clock cycles. Illustrate the same using a timing diagram.
Ans:

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Timing Diagram

Q8 A logic circuit shown in the figure below, represents a logic gate. Derive the Boolean expression. Justify the
same with a truth table.

Ans:

Q=(AB)’

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 So, the Boolean of the given circuit is Q=(AB)’

Q9 A computer uses a memory unit with 65536 words of 32 bits each. A binary instruction code is stored in one
word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to spe-
cify one of 1024 registers and an address part.
a) How many bits are there in the operation code, the register part, indirect bit and the address part?
b) Draw an instruction word format and indicate the number of bits in each part.

Ans:
a) Memory unit with word size 65536, So number of address bits = 16
Resister 1024, Register code 10 bits.
Indirect bit 1 bit.
So, operation code = (32-10-16-1)=5 bits
b)
1 5 10 16
I Opcode Register Address
Total 32 bits.

Q10 To determine the type of instruction, make a flow chart depicting the complete instruction cycle.
Ans:

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 Section – C
(Q 11 to 12: Each question carries 5 marks)

Q11 A 4-bit shift register circuit configured for right-shift operation is shown in the figure below. Given that the
present state of the shift register is 1010, then how many clock cycles are required to again reach the state
1010. List the sequence of states of the four flip-flops after each shift. Illustrate the same with a timing diagram.

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Ans:
The present output of the shift register is ‘1010’. After 1 st clock pulse (CLK) output will be ‘1101’, after 2 nd clock
pulse output will be ‘0110’ and so on. After 7 th clock pulse output will be ‘1010’ as shown in the table and timing
diagram below.
Output Sequences
CLK D3 D2 D1 D0
0 1 0 1 0
1 1 1 0 1
2 0 1 1 0
3 0 0 1 1
4 0 0 0 1
5 1 0 0 0
6 0 1 0 0
7 1 0 1 0

Timing diagram

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Q12 Explain why each of the following micro-operations cannot be executed during a single clock pulse in the
system. Illustrate the same using a common bus system. For each transfer, specify: (1) The binary value that
must be applied to bus select inputs (S2, S1, S0); (2) The register whose load control input must be active (if
any); (3) A memory read or write operation (if needed)
a) IR←M[PC]
b) AC←AC+TR
IR: Instruction Register; PC: Program Counter; AC: Accumulator; TR: Temporary Register.

Ans:

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 Common Bus System

S0S1S2 Load Memory

010 (PC selected) AR, IR Read

110 (TR) DR, AC ---

Section – D
(Q 13: Question carries 10 marks)

Q13 a) An instruction at address 021 in the basic computer has an address part equal to 083 (all numbers are in
hexadecimal). The memory word at address 083 contains the operand B8F2 and the content of AC (Accumu -
lator) is A937. Determine the contents of the registers at the end of the execute phase: PC (Program Counter),

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 AR (Address Register), AC and IR (Instruction Register). Implement the problem using following operation codes
(Hexadecimal code):
i) AND (0083)
ii) CMA (7200)

b) Illustrate the basic computer instruction formats for the memory 4096 x 16. (6+4 = 10)
Ans:
a)

PC AR AC IR
Initial 021 083 A937 0083
AND 022 083 A832 0083
CMA 022 200 56C8 7200

b) Basic Instruction Formats:

 The basic computer has three instruction code formats each having 16 bits:
○ Memory reference instructions

○ Register reference instructions

○ I/O instructions

 The opcode part of the instruction contains three bits and the meaning of the remaining 13 bits depends on the
operation code encountered.

 Memory Reference Instructions:

Bits 0-11 for specifying address.

Bits 12-14 for specifying address.

15th bit specifies addressing modes. (0 for direct and 1 for indirect)

Opcode = 000 through 110

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 I=0 or 1

Eg:

○ AND - 0xxx(direct) or 8xxx(indirect)

Register Reference Instructions:

 Recognized by the operation code 111 with a 0 in the 15th bit of the instruction.
 Specifies an operation on or a test of the AC register.

 An operand from memory is not needed.

 Therefore the 12 bits are used to specify the operation to be executed.

Eg:

○ CLA - 7800 : Clear AC

Input-Output Instructions:

○ These instructions are needed for transferring information to and from AC register.
○ Recognized by the opcode 111 and a 1 in the 15th bit.

○ Bits 0-11 specify the type of I/O Operation performed.

Eg:

○ INP - F800 : Input characters to AC

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