Interrupts Part 1

INTERRUPTS
Interrupt and its Need:

The microprocessors allow normal program execution to be interrupted in order to carry out a
specific task/work.
The process of interrupting the normal program execution to carry out a specific task/work is
referred to as interrupt.
The processor can be interrupted in the following ways
Hardware interrupt
By an external signal generated by a peripheral, eg: keyboard interrupt
Software interrupt
An internal signal generated by a special instruction in the program,
eg: interrupt due to INT instruction in program
by an internal signal generated due to an exceptional condition which occurs while executing an
instruction.
Eg: division by zero interrupt ,overflow interrupt
.
 When a microprocessor receives an interrupt signal and if it is ready to accept the

request then stops executing current normal program, save the status (or content)
of various registers IP, CS and flag registers in stack
 The processor executes a subroutine/procedure in order to perform the specific
task/work requested by the interrupt.
 The subroutine/procedure that is executed in response to an interrupt is also called
Interrupt Service Subroutine (ISR).
 At the end of ISR, the stored status of registers in stack is restored to respective
registers, and the processor resumes the normal program execution from the point
where it was interrupted.
.
 Whenever a number of devices interrupt a CPU at a time and if

the processor is able to handle them properly ,it is called
multiple interrupt processing capability .
 In 8086 there are 2 interrupt pins NMI ad INTR .
 NMI is a nonmaskable interrupt input pin which means that any
interrupt request at NMI input cannot be masked or disabled by
any means .
 The INTR interrupt may be masked using the status of interrupt
flag .
 INTR is of 256 types and type numbered from 0 to 255 or
(00 H to FFH) .
 If more than one type of INTR interrupt occurs at a time , then
an external chip called programmable interrupt controller is
required to handle them .
INTERRUPT CYCLE OF 8086
Types of interrupts : external interrupts internal interrupts
External devices interrupts 8086 at the Interrupt pin NMI or INTR
 NMI is a nonmaskable interrupt input pin which means that any interrupt request at NMI
input cannot be masked or disabled by any means . Like division by zero interrupt ,NMI ,
TRAP
 The INTR interrupt may be masked using the status of interrupt flag .
 CPU acknowledges the interrupt request using INTA’ pin
 Note that response to the NMI ,TRAP ,and Division by Zero interrupt requests are independent
of the IF flags.
 Every external and internal interrupt is assigned with a type (N) ie either implicit in case of
NMI ,TRAP and Division by zero or specified in the instruction INT N in case of internal
interrupts .
 in case of external interrupts the type is passed to the processor by an external hardware called
programmable interrupt controller .
.
8086 support total of 256 types of interrupts

Address information relating to these 256 interrupts are available from a special memory
space known as Interrupt Vector Table
Interrupt Vector Table
 In the zeroth segment of physical address space ,ie CS=0000H , Intel has reserved 1024
locations for storing the interrupt vector table .
 Address of 256 interrupts are ranging from 00 to FF H .
 Each interrupt requires 4 bytes ie ,2 bytes for IP and CS of its ISR . Total 1024 bytes
 Hence interrupt vector table starts from 0000:0000 to 0000:03FFH
 in case of external interrupts the type is passed to the processor by an external hardware
called programmable interrupt controller .
 Incase of INT N type instruction , type N is multiplied by 4 and the hexadecimal
multiplication obtained gives the offset address in the zeroth code segment at which the IP
and CS addresses of the interrupt service routine are stored .
.
.
INTERRUPT TYPES
TYPE 0 Division by zero

TYPE 1 Single step interrupt :system will execute one instruction and
wait for further direction from user –useful for debugging
TYPE2 Non maskable interrupt
TYPE3 Break point interrupt : used for debugging faulty software
TYPE4 INTO : overflow interrupt
.
Whenever processor accept an interrupt request then :
• The value of flag register is pushed into the stack.
It means that first the value of SP (Stack Pointer) is decremented by 2 then the value of flag
register is pushed to the memory address of stack segment.
• The value of starting memory address of CS (Code Segment) is pushed into the stack after
decrementing stack pointer by 2.
• The value of IP (Instruction Pointer) is pushed into the stack after decrementing SP by 2 .
• Pass the control to interrupt vector table ( CS:0000H and OFFSET : TYPE x 4 in Hex)
• IP is loaded from word location (Interrupt type) * 04.
• CS is loaded from the next word location.
• Interrupt and Trap flag are reset to 0.
• Start ISR execution and at the end there execute IRET instruction then control transfer from
ISR
• POP from stack the stored IP,CS and PSW and place back in respective register and resume in
terrupted program execution from the point of interrupt .
.
INTERRUPT
.
PROGRAMMING
While programming for any type of interrupt , the programmer must either externally
or through the program set the interrupt vector table for that type suitably with the CS and IP addresses of the
interrupt service routine .
Execution Sequence Of Software Interrupt
Nested interrupts
QN :
ALP
.
to create a file RESULT and store in it 500 H bytes from the memory
block starting at 1000:1000 , if either an interrupt appears at INTR pin with Type 0AH
or an instruction equivalent to the available interrupt is executed
1000:1000
Main program
FILE :RESULT 500 BYTES
.
.
.
.
INT 0A H
.
.
.
ASSUME CS : CODE ,DS:DATA
DATA SEGMENT
FILENAME DB “RESULT” ,”$”
FURTHER : INT 0AH
MSG DB “FILE WASNN’T CREATED “,”$” STOP : MOV AH,4CH If the file is created successfully
DATA ENDS INT 21H Write into it and return to DOS
CODE SEGMENT prompt .
START : MOV AX,CODE ISROA PROC NEAR
MOV BX,AX
MOV DS,AX // SET DS AT CODE FOR SETTING IVT
MOV CX,500H
MOV DX,OFFSET ISR0A //SET DX AT THE OFFSET OF ISR0A MOV DX,1000H
MOV AX,250AH // SET IVT USING FUNCTION VALUE 250AH IN AX MOV AX,1000H
INT 21H MOV DS,AX
MOV DX,OFFSET FILENAME MOV AH ,40H
INT 21H Write in the file
MOV AX,DATA
IRET
MOV DS,AX ISROA ENDP
MOV CX,00H
MOV AH,3CH CODE ENDS
INT 21H END START
JNC FURTHER
MOV DX,OFFSET MSG
MOV AH,09H
INT 21 H
JMP STOP WW

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INTERRUPTS

Interrupt and its Need:

 When a microprocessor receives an interrupt signal and if it is ready to accept the

 Whenever a number of devices interrupt a CPU at a time and if

8086 support total of 256 types of interrupts

TYPE 0 Division by zero

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