CO-3rd module important questions with answers

1. Explain different methods of designing Control Unit

There are primarily two different approaches for designing a control unit:

A. Hardwired control unit

B. Microprogrammed control unit

A. In hardwired control unit, the control units use fixed logic circuits to
interpret instructions and generate control signals from them. A controller
that uses this approach can operate at high speed; however, it has little
flexibility, and the complexity of the instruction set it can implement is
limited. The hardwired approach has become less popular as computers have
evolved.

Figure 5 below shows a detailed block diagram of a hardwired control unit:

Here,
the
fixed

combinational circuits namely the encoder and decoder generate the necessary control
signals as shown above.

1.The decoder decodes the instructions that are loaded in the IR (Instruction
Register).Accordingly the number of output lines of the decoder depends on the size
of the IR. For example if the IR is 10 bit then the number of output lines of the
decoder will have 210 or 1024 lines one for each possible instruction.

2.According to the code in the IR only one of the possible 1024 lines will be set to 1,
all the others will be 0 only.
 3.The counter is used to keep track of the control steps. Each state or count of this
counter corresponds to one control step. The step decoder provides a separate signal
line for each step, or time slot in a control sequence.

4.The encoder takes inputs from instruction decoder, step decoder, external inputs
and condition codes as shown in the diagram. The required control signals are thus
determined by the following:

a. Contents of the control step counter

b. Contents of the instruction register

c. Contents of the condition code flags

5.External input signals can be from an external interrupting source or a device

requesting access to an external bus. Conditions codes are as per condition and
status flags set in earlier instructions.

6.The input signals to the encoder block in Figure are combined to generate the
individual control signals Y in, PC OUT Add, End, and so on. The output of the control
unit is responsible for indicating the function that needs to be performed (like
addition), selection of the storage units and for selection of data path/data route.

7.If the logic function below is responsible for the generation of the END control
signal End = T7. Add + T6.BR + (T5.N + T4. N¯). BRN + ...
The logic circuit for the above function is shown in Figure 6.

This circuit alone can be used for implementing the End control signal in a hardwired
control unit.

. Terminologies used in Microprogrammed Control Unit Design

What is a microprogram? •

A sequence of micro instructions is a microprogram.which is stored in a ROM or RAM

called a Control Memory (CM).

Control Word:A control word is a word whose individual bits represent various
control signals.

Micro-instruction:Individual control words in this micro-routine are referred to as

microinstructions.

Control Store:the micro-routines for all instructions in the instruction set of a

computer are stored in a special memory called the Control Store.

B. Micro-programmed Control Unit

As the name suggests, these control units are designed with the help of a micro-program. This
micro-program is a collections of micro-instructions stored in the control memory. This
control unit uses CISC (Complex Instruction Set Computer) microprocessors.

A control unit whose binary control variables are stored in memory is known as a
microprogrammed control unit.
In Microprogrammed Control, the control information is stored in the control memory and is
programmed to initiate the required sequence of micro-operations.
By creating a definite collection of signals at each system clock beat, a controller generates the
instructions to be executed. Each of these output signals causes a single micro-operation, such
as register transfer. As a result, defined micro-operations that can be preserved in memory are
formed from the sets of control signals.
Each bit in the microinstruction is connected to a single control signal. The control signal is
active when its bit is set. The control signal becomes inactive when it is cleared. The internal
control memory can store a sequence of these microinstructions. A microprogram-controlled
computer's control unit is a computer within a computer.

Example of micro-instruction:
MAR←R3

In the above instruction, we are fetching the operand.

The control signal for the above example:
MARᵢₙ, R3ₒᵤₜ
A micro-instruction consist of one or more micro-operations to be executed and the address of
the next micro-instruction.

2. Compare Hardwired CU and Microprogrammed CU

Hardwired control unit generates the control Microprogrammed control unit generates
signals needed for the processor using logic the control signals with the help of micro
circuits instructions stored in control memory

Hardwired control unit is faster when compared This is slower than the other as micro
to microprogrammed control unit as the instructions are used for generating
required control signals are generated with the signals here
help of hardwares
Difficult to modify as the control signals that Easy to modify as the modification need
need to be generated are hard wired to be done only at the instruction level
Less costlier than hardwired control as
More costlier as everything has to be realized in
only micro instructions are used for
terms of logic gates
generating control signals
It cannot handle complex instructions as the
It can handle complex instructions
circuit design for it becomes complex
Only limited number of instructions are used Control signals for many instructions can
due to the hardware implementation be generated
Used in computer that makes use of
Used in computer that makes use of Reduced
Complex Instruction Set
Instruction Set Computers(RISC)
Computers(CISC)

3. Explain pipelining concept

A pipeline is the mechanism a RISC processor uses to execute instructions. Using a pipeline
speeds up execution by fetching the next instruction while other instructions are being
decoded and executed.

Figure 1. shows a three-stage pipeline:

Fig 1

Fetch loads an instruction from memory.

▪

Decode identifies the instruction to be executed.

▪

Execute processes the instruction and writes the result back to a register.
Figure 2. illustrates the pipeline using a simple example. It shows a sequence of three
instructions being fetched, decoded, and executed by the processor. Each instruction takes a
single cycle to complete after the pipeline is filled.

Fig 2

The three instructions are placed into the pipeline sequentially. In the first cycle the core fetches the
ADD instruction from memory. In the second cycle the core fetches the SUB instruction and
decodes the ADD instruction. In the third cycle, both the SUB and ADD instructions are moved
along the pipeline. The ADD instruction is executed, the SUB instruction is decoded, and the CMP
instruction is fetched. This procedure is called filling the pipeline. The pipeline allows the core to
execute an instruction every cycle.

As the pipeline length increases, the amount of work done at each stage is
reduced, which allows the processor to attain a higher operating frequency. This
in turn increases the performance.

Module II

1. I/O Module

I/O Operation
I/O operation are accomplished through a wide assortment of external devices that provide a means
of exchanging the data between the external environment and the computer. Inputs are the signals or
data received by the system and outputs are the signals or data sent from it. The term can also be
used as part of an action; to "perform I/O" is to perform an input or output operation. I/O devices
are used by a human (or other system) to communicate with a computer. For instance, a keyboard or
mouse is an input device for a computer, while monitors and printers are output devices. In
computer architecture, the combination of the CPU and main memory, to which the CPU can read
or write directly using individual instructions, is considered the brain of a computer. Any transfer of
information to or from the CPU/memory combo, for example by reading data from a disk drive, is
considered I/O. An I/O interface is required whenever the I/O device is driven by the processor. The
interface must have necessary logic to interpret the device address generated by the processor. An
external device attaches to the computer by a link to an I/O module as shown in the Figure 1.

The link is used to exchange control, status, and data between the I/O module and the external
device. As shown in the figure with an I/O module. The module actually consists of a few function,
which are:
 Control and timing
 Processor communication
 Device Communication
 Data buffering
 Error detection

Since I/O operation deals with the exchanges of data between the memory and the external devices
either in the direction to the memory (READ) or in the direction from the memory (WRITE). But
the problem arise on how the processor will manage the flow of data to and from the external
devices in term of transfer speed, processor idle time, complexity and etc.

2. Different I/O Techniques

There are three technique for I/O operation , which are:

 Programmed I/O
 Interrupt driven I/O
 Direct Memory Access

1. Programmed I/O

With programmed I/O, data are exchanged between the processor and the I/O module. The
processor executes a program that gives it direct control of the I/O operation, including
sensing device status, sending a read or write command, and transferring the data. When the
processor issues a command to the I/O module, it must wait until the I/O operation is
complete.

The overall operation of the programmed I/O can be summaries as follow:

1.The processor is executing a program and encounters an instruction relating to I/O

operation.
2.The processor then executes that instruction by issuing a command to the appropriate I/O
module.
3.The I/O module will perform the requested action based on the I/O command issued by the
processor (READ/WRITE) and set the appropriate bits in the I/O status register.
4.The processor will periodically check the status of the I/O module until it find that the
operation is complete.

2. Interrupt Driven I/O

In interrupt program controlled approach, when a peripheral is ready to transfer data, it

sends an interrupt signal to the microprocessor. This indicates that the Input Output Transfer
Techniques is initiated by the external I/O device. When interrupted, the microprocessor stops
the execution of the program and transfers the program control to an interrupt service
routine. This interrupt service routine performs the data transfer. After the data transfer, it
returns control to the main program at the point it was interrupted.

3. Direct Memory Access(DMA)

Direct Memory Access is a technique for transferring data within main memory and external
device without passing it through the CPU. DMA is a way to improve processor activity and
I/O transfer rate by taking-over the job of transferring data from processor, and letting the
processor to do other tasks. This technique overcomes the drawbacks of other two I/O
techniques which are the time consuming process when issuing command for data transfer
and tie-up the processor in data transfer while the data processing is neglected. It is more
efficient to use DMA method when large volume of data has to be transferred. For DMA to be
implemented, processor has to share its’ system bus with the DMA module. Therefore, the
DMA module must use the bus only when the processor does not need it, or it must force the
processor to suspend operation temporarily

Basic Operation of DMA

When the processor wishes read or send a block of data, it issues a command to the DMA
module by sending some information to DMA module. The information includes:
- read or write command, sending through read and write control lines.

- number of words to be read or written, communicated on the data lines and stored in the
data count register.
- starting location in memory to read from or write to, communicated on data lines and stored
in the address register.
- address of the I/O device involved, communicated on the data lines.

4. Features of standard I/O interfaces

Refer Notes given in class

a. General Features of PCI Interface

b. USB bus interface

c. SCSI bus interface

Module IV: Notes already given

1. Evolution of microprocessors

2. Registers of 8086 PROCESSORS