f = number of cycles completed in a second.

F = 2.7 *109 Hz = > 2.7 GHz

Time period = 1/f seconds

F = 2 *109 F = 3 *109

T = 1/2 * 109 T = 1/3*109

In any specific architecture, every operation is completed in defined clock cycles.

Operation Clock Cycles 2 GHz 4 GHz

Add 200 Exe T = 200 /2*109 Exe T = 200/4*109

Sub 250

Multiplication 400

Division 450

Load/Store 150

1000 x 40 bit words of either number or instruction

 Signed magnitude binary number

 1 sign bit
 39 bits for magnitude -> (0 - 239-1)
 O for positive& 1 for negative. [( Signed Number ->( 00001111) -> (15)
 O for positive& 1 for negative. [( Signed Number ->( 10001111) -> (-15)
 In signed numbers Magnitude will be based of 7 bits out of total 8 bits and highest
value could be 27 = 128-1 because most significant value will be used for sign instead
of value/ magnitude.

 O for positive& 1 for negative. [( UnSigned Number ->( 00001111) -> (15)
 O for positive& 1 for negative. [( UnSigned Number ->( 10001111) ->
(128+0+0+0+8+4+2+1 = 143)

 In unsigned numbers Magnitude will be based of 8 bits out of total 8 bits and highest
value could be 28 = 256-1 because most significant value will be used for magnitude
instead of sign.

 2 x 20 bit instructions

 Left and right instructions (left executed first)

 8-bit opcode -> 28 = 256 Operations ( Maximum Limit )

 12 bit address -> 212 = 4096 Locations at Max ( 0 – 4095 )

If we increase the frequency of our processor, it will reduce the execution time of a process.

Keeping all other parameters constant if we double the frequency of our system, the execution time
of a processor will be half.

Number length = 8 bits -> Magnitude 28 = 256 ( 00000000 – 11111111)

00000001 = 20 = 1

00000011 = 21 + 20 = 3

00010011 = 24 +0 +0 +21 + 20 = 16+0+0+2+1 = 19

10010011 = 27 +0 +0 +24 +0 +0 +21 + 20 = 128+0+0+16+0+0+2+1 =147

11111111 = 27 +26 +25 +24 +23+22 +21 + 20 = 128+64+32+16+8+4+2+1 =255 (28-1 = 256-1 = 255)

256 => 0-255 239

I have two options available, a system with 4 GHz single core and a system with 2 GHz dual core.

Which one is better and why?

 Consider the execution of a program which results in the execution of 2 million instructions
on a 400-MHz processor. The program consists of four major types of instructions. The
instruction mix and the CPI for each instruction type are given below based on the result of a
program trace experiment:

 Calculate its CPI, Total time required for the execution of below given program and its MIPS
rate?

Time period = 1 /400 * 106 => 0.0025 * 10-6

T = Ic * CPI * Timeperiod = 2000000 * 2.24 * 0.0025 *10-6 => 11200 *10-6 => 0.0112 sec

MIPS Rate ( Millions of Instruction per second) = 178571428.57/1000000 = 178.5

MIPS Rate ( Millions of Instruction per second) = 400 * 106 / 2.24 * 106 => 400/2.24 => 178.57
MIPS Rate = Ic / T * 106 => Ic / Ic * CPI * t * 106 => 1/CPI * t * 106 => f / CPI *106

Memory Storage Types on basis of their storage phenomena:

Electrical

Magnetic

Optical

Electrical

a. Registers
b. Cache
c. RAM
i. Static & its types
ii. Dynamic & Its types
d. ROM and its Types
e. USB
f. SSD ( Solid State Drive )

Magnetic

1) Floppy Drive/Disk
2) Magnetic Disk (SATA / with different RPMS)
3) Magnetic Tape

Optical

1) CD
2) DVD
3) Rewriteable CD / DVD
4) Blu-Ray Disk

Discuss memory hierarchy with reasoning & you guys are supposed to discuss the following concepts
regarding each memory type:

1) Storage Phenomena ( How does it store 0/1)

2) Write Phenomena
3) Read Phenomena
 4) Delete Phenomena
5) Search Phenomena

Mapping functions:
Direct Mapping Fully Associative Mapping

1. Set Associative Mapping

Number of locations =16

Number of address bits
Number of bits required to address 16 locations = 2 = 16 =>24 = 16
Number of address bits = 4 ( Address length = 4 bits )
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

0
000 1
0
001 1
0
010 1
0
011 1
0
100 1
0
101 1
0
110 1
0
111 1
 00
00 01
10
11
00
01 01
10
11
00
10 01
10
11
00
11 01
10
11

000
0 001
010
011
100
101
110
111
000
1 001
010
011
100
101
110
111
Direct Mapping

Ram Blocks:

0 to 31 ( 32 Blocks -> Each block consist of 16 locations )

Cache Blocks / Lines: 0 to 7 (8 blocks / Lines)

Line Table: => Line Number = Block number of RAM % Total number of lines in Cache

Cache: RAM

0 0, 8, 16, 24

1 1, 9, 17, 25

2 2, 10, 18, 26

3 3, 11, 19, 27

4 4, 12, 20, 28

5 5, 13, 21, 29

6 6, 14, 22, 30

7 7, 15, 23, 31

Set Associative:

Generate sets of cache lines.

Set size = 2 lines in a set

No of sets in cache = 8/2 = 4 sets

Set Table:

Cache: RAM

0 0, 4, 8, 12, 16, 20, 24, 28

1 1, 5, 9, 13, 17, 21, 25, 29

2 2, 6, 10, 14, 18, 22, 26, 30

3 3, 7, 11, 15, 19, 23, 27, 31

Questions: 1
 Consider we have RAM of 2048 words and Cache consists of 256 Words. Calculate
Tag bits and Line Table when Line Size/block size in cache is 16 Words. Word size is 4 bytes
and Memory is Word addressable. When direct mapping function is implemented.
RAM Cache

Address Length = Number of bits required to address certain memory is called address length.

A.L => 2A.L = 2048 => 211 = 2048 A.L => 2A.L = 256 => 28 = 256

A.L = 11 bits A.L = 8 bits

A.L = XXXXXXXXXXX A.L = XXXXXXXX

Block Size = 16 Words Line / Block Size = 16 Words

Number of Blocks = 2048 / 16 Number of Blocks = 256 / 16

Number of Blocks = 128 Blocks Number of Lines/Blocks = 16 Lines/Blocks

A.L = XXXXXXXXXXX A.L = XXXXXXXX

S=7 bits W=4 bits r=4bits W=4 bits

Direct Mapping:

A.L = S+W A.L = r+w

Number of Blocks of RAM allocated in a Single Line/Block of Cache = Total No of Blocks in RAM/
Total number of lines in cache

Number of Blocks of RAM allocation in a Single Line/Block of Cache = 128/16 = 8 Blocks in single line

Line Table:

Cache RAM Blocks

000 001 010 011 100 101 110 111

0 0 16 32 48 64 80 96 112
(0010000) (0100000
)
1 1 17 33 49 65 81 97 113
(0100001 (0110001
) )
2 2 18 34 50 66
3 3 19 35 51 67
4 4 20 36 52 68
5 5 21 37 53 69
6 6 22 38 54 70
7 7 23 39 55 103
8 8 24 40 56 104
9 9 25 41 57 105
10 10 26 42 58 106
11 11 27 43 59 107
12 12 28 44 60 108
13 13 29 45 61 77 93 109 125
14 14 30 46 62 78 94 110 126
(1111110)
15 15 31 47 63 79 95 111 127
(1111111)
S=7bits W=4 bits

Tag Bits: => A.L = XXXXXXXXXXX s-r bitsr bitsW bits Tag bits = S-r = 7-4 = 3 bits

1-> 11001110000 - Cache MIss 11001110001 - Cache Hit 11001111111 - Cache Hit

00001111111 - Cache Miss 00100001100 - Cache Miss 00000011100 - Cache Miss

11001110000 - Cache Miss 01100001100 - Cache Miss 00100001100 - Cache Miss

Hit Rate = 2/9 = 0.2223 Miss Rate = 7/9 = 0.8887

Line No Tag bits Block Placement ( Each Block Contains 16 Locations )

0000 001 0010000 (16 Block Numb)
0001 000 0000001 (Block Numb = 1)
0010
0011
0100
0101
0110
0111 110, 000 1100111 (Block Number = 103), 0000111 (Block NO: 7)
1000
1001
1010
1011
1100
1101
1110
1111

Fully Associative:

Tag Bits: => In fully associative there will be no line table because we can place any block of RAM
in any LINE/Block of cache. So “S” bits will be saved as Tag bits.

A.L = XXXXXXXXXXXXXX Tag bits = S bits = 7 bits

11001110000 - Cache Miss 11001110001 - Cache Hit 11001111111 - Cache Hit

00001111111 - Cache Miss 00100001100 - Cache Miss 00000011100 - Cache Miss

11001110000 - Cache Hit 01100001100 - Cache Miss 00100001100 - Cache HiT

Hit Rate = 4/9 = 0.44443 Miss Rate = 5/9 = 0.5555

Line No Tag bits Block Placement ( Each Block Contains 16 Locations )

0000 1100111 1100111 (Block Numb = 103)
0001 0000111 0000111 (Block Numb = 7)
0010 0010000 0010000 (Block Numb = 16)
0011 0000001 0000001 (Block Numb = 1)
0100 0110000 0110000 (Block Numb = 48)
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Set Associative:

1-Way set Associative = set Size is equal to 1 Lines of Cache  Direct Mapping

2-Way set Associative = set Size is equal to 2 Lines of Cache

4-Way set Associative = set Size is equal to 4 Lines of Cache

8-Way set Associative = set Size is equal to 8 Lines of Cache

16-Way set Associative = set Size is equal to 16 Lines of Cache Fully Associative Mapping

Draw set table and calculate Tag bits when set size is equal to 4 lines. ( 4 Way set Associative)
Total number of sets = Total number of lines or blocks in cache / Set size

Total number of sets = 16 / 4 = 4 set

Set Table will give you the allocation of each line in a specific set.

Number of Blocks allocated in a single set = Total Blocks in RAM / Total sets in Cache -> 128/4 = 32

Blocks (25 = 32) Tag bits should be 5 bits.

d bits will be used to identify set number => 2d = 4 set => 22 = 4 set =>
d=2bits
Set number = Block Number % Total Number of Sets

Set Table:

0: 0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124

1: 1,5,9,13,17,21,25,29,33,37,41,45,49,53,57,61,65,69,73,77,81,85,89,93,97,101,105,109,113,117,121,125
2: 2,6,*******************************************************************************126

3: 3,7,11,15**************************************************************************127

S=7bits W=4 bits

Tag Bits: => A.L = XXXXXXXXXXX s-d bits d bits W bits Tag bits = S-d = 7-2 = 5 bits

11001110000 - Cache Miss 11001110001 - Cache Hit 11001111111 - Cache Hit

00001111111 - Cache Miss 00100001100 - Cache Miss 00000011100 - Cache Miss

11001110000 - Cache Hit 01100001100 - Cache Miss 00100001100 - Cache Hit

Hit Rate = 4/9 = 0.4444 Miss Rate = 5/9 = 0.5556

Set No Tag bits Block Placement ( Each Block Contains 16 Locations )

00100 0010000 (Block Number = 16)

00 01100 0110000 (Block Number = 48)

00000 0000001 (Block Number = 1)

01
10
11001 1100111 (Block Number = 103)

11 00001 0000111 (Block Number = 7)

Questions: 2

Consider we have RAM of 2048 words and Cache consists of 256 Words. Calculate
Tag bits and Line Table when Line Size in cache is 16 Words. Word size is 4 bytes and
Memory is Word addressable. When direct mapping function is implemented.
RAM Cache

Address Length = Number of bits required to address certain memory is called address length.

A.L => 2A.L = 2048 => 211 = 2048 A.L => 2A.L = 256 => 28 = 256

A.L = 11 bits A.L = 8 bits

A.L = XXXXXXXXXXX A.L = XXXXXXXX

Block Size = 16 Words Line / Block Size = 16 Words

Number of Blocks = 2048 / 16 Number of Blocks = 256 / 16

Number of Blocks = 128 Blocks Number of Lines/Blocks = 16 Lines/Blocks

A.L = XXXXXXXXXXX A.L = XXXXXXXX

S=7 bits W=4 bits r=4bits W=4 bits

Direct Mapping:

A.L = S+W A.L = r+w

Number of Blocks of RAM allocation in a Single Line/Block of Cache = Total No of Blocks in RAM/
Total number of lines in cache

Number of Blocks of RAM allocation in a Single Line/Block of Cache = 128/16 = 8 Blocks in single line

Line Table:

Cache RAM Blocks

000 001 010 011 100 101 110 111

0 0 16 32 48 64 80 96 112
1 1 17 33 49 65 81 97 113
2 2 18 34 50 66
3 3 19 35 51 67
4 4 20 36 52 68
5 5 21 37 53 69
6 6 22 38 54 70
7 7 23 39 55 103
8 8 24 40 56 104
9 9 25 41 57 105
10 10 26 42 58 106
11 11 27 43 59 107
12 12 28 44 60 108
13 13 29 45 61 77 93 109 125
14 14 30 46 62 78 94 110 126
15 15 31 47 63 79 95 111 127

S=7bits W=4 bits

Tag Bits: => A.L = XXXXXXXXXXX

s-r bitsr bitsW bits Tag bits = S-r = 7-4 = 3 bits

11001110000 - Cache Miss 11001110001 - Cache Hit 11001111111 - Cache Hit

00001111111 - Cache Miss 00100001100 - Cache Miss 00000011100 - Cache Miss

Hit Rate = 2/6 = 0.333 Miss Rate = 4/6 = 0.6667

Line No Tag bits Block Placement

0000 001 0010000 (16)
0001 000 0000001 (1)
0010
0011
0100
0101
0110
0111 000 0000111 (7) -> 16 Locations
1000
1001
1010
1011
1100
1101
1110
1111

Fully Associative Mappning:

In fully associative cache mapping technique there will be no Line table because in fully associative mapping
function, we can place any block of RAM in any block/line of cache and S bits will be saved as Tag bits.

Question: 3

RAM has the address length of 14 bits and Cache consists of 1024 Words. Calculate
Tag bits and Line Table when Line Size in cache is 32 Words. Word size is 4 bytes and
Memory is Word addressable.
I. When direct Mapping function is implemented.
II. When Fully Associative Mapping function is implemented.
III. When 4-way set associative mapping function is implemented.

RAM Cache
A.L = 14 bits A.L => 2A.L = 1024 Words
Memory Size = 214 = 16384 Words A.L = 10 bits
A.L = XXXXXXXXXXXXXX A.L = XXXXXXXXXX
Block Size = 32 Words Block/Line Size = 32 Words
Number of Blocks = 16384 / 32 Number of lines = 1024/32
Number of Blocks = 512 Blocks Number of lines = 32
Lines/Blocks
2W = 32W = 5 bits 2W = 32W = 5 bits
2S= 512 S = 9 bits 2r= 32 r = 5 bits
Direct Mappning:
Blocks allocated in a Single line = Total num of blocks in RAM / Total number of blocks in cache

Blocks allocated in a Single line = 512 / 32 = 16 Blocks

 Line Table :
Cache RAM
Line Num Block Number
0 0 32 64 96 128 160 192 ………… 480

1 1 33 65 97 129 161 193 ………… 481

2 2 34 66 98 130 162 194 ………… 482

3 3 35 67 99 131 163 195 ………… 483

4 4 36 68 100 132 164 196 ………… 484

. . . . . . . . …………

. . . . . . . . …………

. . . . . . . . …………

. . . . . . . . …………

29 29 61 93 125 157 189 221 ………… 509

30 30 62 94 126 158 190 222 ………… 510

31 31 63 95 127 159 191 223 ………… 511

Tag bits are used to differentiate among the blocks which are nominated in a same line of cache.

S=9 W=5

XXXXXXXXXXXXXX In Direct Mapping S-r bits will be used as tag bits

S-r = 4 r = 5 W=5

Fully Associative Mappning:

In fully associative cache mapping technique there will be no Line table because in fully associative
mapping function, we can place any block of RAM in any block/line of cache and S bits will be saved as Tag bits.

Question: 4

RAM has the address length of 4096 Words and Cache consists of 512 Words.
Calculate Tag bits and Line Table when Line Size in cache is 32 Words. Word size is 4 bytes
and Memory is Word addressable.

I. When direct Mapping function is implemented.

 II. When Fully Associative Mapping function is implemented.
III. When 4-way set associative mapping function is implemented.

RAM Cache
A.L = 12 bits A.L => 2A.L = 512 Words
Memory Size = 212 = 4096 Words A.L = 9 bits
A.L = XXXXXXXXXXXX A.L = XXXXXXXXX
Block Size = 32 Words Block/Line Size = 32 Words
Number of Blocks = 4096 / 32 Number of lines = 512/32
Number of Blocks = 128 Blocks Number of lines = 16
Lines/Blocks
2W = 32W = 5 bits 2W = 32W = 5 bits
2S= 128 S = 7 bits 2r= 32 r = 4 bits
Direct Mappning:
Blocks allocated in a Single line = Total num of blocks in RAM / Total number of blocks in cache

Blocks allocated in a Single line = 128 / 16 = 8 Blocks

Line Table :
Cache RAM
Line Num Block Number

000 001 010 011 100 101 110 111

0 0 16 32 48 64 80 96 112
1 1 17 33 49 65 81 97 113
2 2 18 34 50 66 82 98 114
3 3 19 35 51 67 83 99 115
4 4 20 36 52 68 84 100 116
5 5 21 37 53 69 85 101 117
6 6 22 38 54 70 86 102 118
7 7 23 39 55 71 87 103 119
8 8 24 40 56 72 88 104 120
9 9 25 41 57 73 89 105 121
10 10 26 42 58 74 90 106 122
11 11 27 43 59 75 91 107 123
12 12 28 44 60 76 92 108 124
13 13 29 45 61 77 93 109 125
14 14 30 46 62 78 94 110 126
15 15 31 47 63 79 95 111 127

Tag bits are used to differentiate among the blocks which are nominated in a same line of cache.

S=7 W=5

XXXXXXXXXXXX In Direct Mapping S-r bits will be used as tag bits

S-r= 3r = 4W=5

Fully Associative Mappning:

In fully associative cache mapping technique there will be no Line table because in fully associative
mapping function, we can place any block of RAM in any block/line of cache and S bits will be saved as Tag bits.

Hit & Miss Rate when direct Mapping is implemented:

General Discussion:

100011000000 – Miss

100011000001 – Hit

100011001100 – Hit

000011000000 – Miss

000011001111 - Hit

100011000000 – Miss

100000000000 – Miss 100000000001 - Hit

Hit Rate = 4 / = 0.5 Miss Rate = 4 / 8 = 0.5

Line No Tag bits Block Placement

0000 100 1000000(64)
0001
0010
0011
0100
0101
0110 100 1000110 (70)
0111
1000
1001
1010
1011
1100
1101
1110
1111
 4-way set associative mapping function is implemented.
Total number of sets = total number lines / set size => 16/4 = 4 Sets

d = 2 bits

Number of blocks allocated in a single set = 128 / 4 = 32 Blocks in a single set

S=7 W=5

XXXXXXXXXXXX In 4-way set associative Mapping S-d bits will be used as tag bits

S-d=5 d=2W=5

Set Table:

S
e
t

N
o
0 0 4 8 1 1 2 2 2 3 3 4 4 4 5 5 6 6 6 7 7 8 8 8 9 9 1 1 1 1 1 1 1
2 6 0 4 8 2 6 0 4 8 2 6 0 4 8 2 6 0 4 8 2 6 0 0 0 1 1 2 2
0 4 8 2 6 0 4
1 1 5 1
2
5
2 2 6 1
2
6
3 3 7 1
2
7
Hit & Miss Rate when 4-Way Set Associative Mapping is implemented:

General Discussion:

100011000000 – Miss 100011000001 – Hit 000011001100 – Miss 000011000000 – Hit

000111001111 – Miss 100011000000 – Hit 110001000000 – Miss 001111000001 – Miss

001110100001 - Miss

Hit Rate = 3 /9 = Miss Rate = 6 / 9 =

Set No Tag bits Block Placement

00

01 00111 0011101 (29)

10 10001, 1000110 (70), 0011110
00111
00001 0000110 (6)
00011 0001110 (14)
11000 1100010 (98),
11

Question No: 5

Calculate the hit ratio and miss ratio for the following 20 requests of Block Numbers.
Update the Tag bits and requested block in respective lines when your system has 128
Blocks and 16 Lines in Total. Use (i) direct mapping (ii) Fully Associative (iii) 4-way
Set associative (iv) 2-way set associative mythology for Placement and FIFO for
replacement.

Requested Blocks: 0, 8, 12, 0, 9, 45, 84, 24, 127, 9, 15, 114, 12, 125, 84, 127, 9, 8, 45,
12

Hit : Total blocks will be 128. S bits = 7 r bits = 4

Line TAG Bits Block Number Hit / Miss

No:

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Solution:
a) Direct Mapping

Requested Blocks: 0(00000000), 8(0001000), 12(0001100), 0(0000000), 9(0001001), 45(0101101),

84(1010100), 24(0011000), 127(1111111), 9(0001001), 15(0001111), 114(1110010),
12(0001100), 125(1111101), 84(1010100), 127(1111111), 9(0001001), 8(0001000), 45(0101101),
12(0001100)

Hit : Total blocks will be 128. S bits = 7 r bits = 4

Total Requests = 20 Num of Hits = 6 Num of Miss = 14

Hit Rate = 6/20 Miss Rate = 14/20

Line No: TAG Bits Block Number Hit / Miss

0(0000) 000 0000000, M,H

1(0001)
2(0010) 111 1110010 M
3(0011)
4(0100) 101 1010100 M,H
5(0101)
6(0110)
7(0111)
8(1000) 000, 001, 0001000, M,M,M
000 0011000, 0001000
9(1001) 000 0001001, M,H,H
10(1010
)
11(1011
)
12(1100 000 0001100, M,H,H
)
13(1101 010 , 111, 0101101, M,M,M
) 010 1111101, 0101101
14(1110
)
15(1111 111, 000, 1111111, M,M,M
) 111 0001111, 1111111
b) Fully Associative Mapping

Requested Blocks: 0, 8, 12, 0, 9, 45, 84, 24, 127, 9, 15, 114, 12, 125, 84, 127, 9, 8, 45, 12

Hit : Total blocks will be 128. S bits = 7 r bits = 4

Total Requests = 20 Num of Hits = 9 Num of Miss = 11

Hit Rate = 9/20 Miss Rate = 11/20

Line TAG Bits Block Number Hit / Miss

No:
All S bits will bwe saved as Tag bits
0 ( s=7 bits) = > 0000000 0 M, H
1 0001000 8 M,H
2 0001100 12 M,H,H
3 9 M,H,H
4 45 M,H
5 84 M,H
6 24 M
7 127 M,H
8 15 M
9 114 M
10 125 M
11
12
13
14
15

Addressing Mode:

Calculate the total addressable memory when an instruction field of an instruction is 11 bits long.

a) Memory is one byte organized.

b) Memory Is two bytes organized.

c) Memory is four bytes organized.

Perform the calculations for the following addressing modes:

1) Immediate: In immediate addressing mode we place operand in an instruction, so from given

statement we really can’t judge about memory size.

2) Direct Addressing Mode:

a) 211 = 2048 Locations / bytes

b) 211 = 2048 Locations * 2 = 4096 Bytes

C) 211 = 2048 Locations * 4 = 8192 Bytes

3) Indirect Addressing Mode with Single Reference

a)
2048 (Will store next reference only) + 256*2048 = 526336 Locations/bytes

2048 + 256*2048 = 526336 Locations/bytes

Total memory in bytes when memory is one byte organized & single referenced.

2048 locations for 1st reference & 256*2048 = 524288 bytes for operand storage.

b) When memory is 2 bytes orgarnized:

2048 + 65536*2048 = 134219776 Locations * 2 = bytes Total memory in bytes when memory is
two byte organized & single referenced.

C) When Memory is 4 bytes Organized:

4) Indirect Addressing Mode with Double memory reference

a) (2048 + 256*2048 + 2048 * 256 * 256) = Total memory in bytes when memory is one byte
organized & Double referenced.

b) (2048 + 65536*2048 + 2048 * 65536 * 65536)*2 = Total memory in bytes when memory is two
byte organized & Double referenced.

1. Draw & Calculate the size of the memory for 1st reference, 2nd reference and operands if
address the address length is 8 bits long and affective address will be obtained in 2nd
reference. Assume that memory is two bytes organized. Do calculate the total size of the
memory in bytes as well.
(10)

If Address length is 8 bits long then 2 = 256 Locations

8

1 st
Reference will be utilized in 256 Locations only but each memory location contain 2
bytes (16 bits ) because the memory is two by organized.

In 1st reference on 1st 256 locations will be accessed.

In 2nd reference (256 *65536) Locations will be accessed in which affective address will
be obtained.

In 3rd access the oprand will be accessed and the total memory locations will be
(256*65536*65536) Locations (Operands Memory )

(256 + 256 * 65536 + 256 * 65536 * 65536) Locations

(256 + 256 * 65536 + 256 * 65536 * 65536) * 2 = Bytes

Total memory in bytes when memory is two byte organized & Double referenced.