Passive and Active Circuits by Example - 2023 - Springer

Erkan Yuce
Shahram Minaei
Passive
and Active
Circuits
by Example
Passive and Active Circuits by Example
Erkan Yuce • Shahram Minaei
Passive and Active Circuits

by Example
Erkan Yuce Shahram Minaei
Department of Electrical Department of Electrical
and Electronics Engineering and Electronics Engineering
Pamukkale University Dogus University
Denizli, Türkiye Istanbul, Türkiye
ISBN 978-3-031-44965-9 ISBN 978-3-031-44966-6 (eBook)

https://doi.org/10.1007/978-3-031-44966-6
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Preface
In the past three decades, research and development of active building blocks have
been rapidly increased. While operational amplifier-based circuits still find nice
applications, new active elements derived from concept of current conveyors have
emerged as alternatives for designing active filters, simulated inductors, etc.
This book deals with analysis and design of different types of active filters,
simulated inductors, etc. through giving more than 200 examples.
The text comprises nine chapters that are chosen to provide a complete source for
the researchers, undergraduate students, and graduate students who are working on
the applications and designs of active filters, simulated inductors, oscillators, recti-
fiers, etc. with new active elements.
Chapter 1 introduces basic concepts such as symbols, units, and prefixes. Several
fundamental functions such as constant, sine wave, full-wave rectified, positive half-
wave rectified, square wave, triangular wave, sawtooth wave, exponential, delta, unit
step, and unit ramp functions versus time are given, where 1 MHz frequency is taken
for all the periodical signals. Sensitivity analysis with three examples are treated in
which an arbitrary function, an RLC circuit, and two bipolar junction transistor
(BJT)-based structures are used.
Chapter 2 treats analog signals and systems. The concepts involving linearity,
non-linearity, time-invariant, time-variant, linear time-invariant, and causality are
briefly explained. Total harmonic distortion is defined, which is explained with an
NMOS transistor-based simple amplifier. Definitions of Laplace and Fourier trans-
forms are given. Ideal, second-order ideal, and first-order ideal transfer functions are
discussed in detail.
Chapter 3 investigates the basic passive elements, resistor, capacitor, and induc-
tor. Current and voltage relations of these passive elements in the time domain,
s domain, and frequency domain are also given. Phase and magnitude of any
impedance are explained by means of many practices. Fundamental RC and RL
circuits and their operating frequency ranges are given. Parallel and/or series RLC
circuits are analyzed with some examples. Time domain, s domain, and frequency
domain analyses for the series and parallel RC, RL, and RLC circuits are given with
v
vi Preface
some examples. Quality factors of the series and parallel RC, RL, and RLC circuits
are explained. Numerous SPICE simulation results are also included to explain the
given circuits in which ideal elements are used.
Chapter 4 describes passive component-based voltage, current, transimpedance
and transadmittance-mode first-order, second-order, and high-order filter transfer
functions in detail. In the filter realizations, resistors, capacitors, and inductors are
used. Combinations of resistors, capacitors, and inductors implement all the filter
transfer functions.
Chapter 5 deals with operational amplifiers and their applications. Some funda-
mental circuits based on ideal operational amplifiers are given. Several restrictions of
the operational amplifier-based circuits are exhibited. Many circuits such as simu-
lated grounded inductors, rectifiers, oscillators, and filters employing operational
amplifier(s) are given. Slew rate limitations with numerous examples are given. Full-
power bandwidth is defined.
Chapter 6 introduces unity gain cells, i.e., current followers and voltage fol-
lowers. Current and voltage follower-based many analog circuits, for example,
amplifier/attenuator, integrator, differentiator, voltage-mode filters, adder, all-pass
filters, instrumentation amplifiers, etc., are given.
Chapter 7 describes unity gain inverting amplifiers and negative impedance
converters. A number of circuits for realizing different transfer functions, first-
order voltage-mode all-pass filters, and one first-order current-mode universal filter
based on a single unity gain amplifier are given. Afterward, many circuits based on
negative impedance converter(s) are investigated.
Chapter 8 deals with current-mode active devices, current conveyors (CCs).
These CCs are called first-generation CC (CCI), second-generation CC (CCII),
and third-generation CC, and subtractor-connected CCI, current-controlled CCII
(CCCII), inverting CCII, differential CC, dual X CCII, differential voltage CC,
differential difference CC, fully differential CCII, current differencing CC, and
extra X CCCII. A number of circuits for instance simulated inductors, oscillators,
rectifiers, filters, etc. are investigated.
Chapter 9 introduces other important active components, namely current feed-
back operational amplifier, operational transresistance amplifier, four-terminal float-
ing nullor, operational transconductance amplifier, voltage differencing inverting
buffered amplifier, voltage differencing buffer amplifier, current differencing buff-
ered amplifier, current amplifier, current follower transconductance amplifier, cur-
rent differencing transconductance amplifier, differential voltage current conveyor
transconductance amplifier, and current operational amplifier. Simulated inductors
are generally given as application examples for these active devices.
Denizli, Türkiye Erkan Yuce

Istanbul, Türkiye Shahram Minaei
August 2023
Acknowledgments
The authors would like to thank Prof. Dr. Aydin Kizilkaya, Prof. Dr. Sezai Tokat,
Associate Prof. Dr. Firat Yucel, Assistant Prof. Dr. Tolga Yucehan, and Assistant
Mehmet Dogan for their helpful suggestions. The author Erkan Yuce would like to
dedicate the book to his wife Yildiz Yuce, his daughters Rana Nur Yuce, Gulsu Nur
Yuce and his parents. The author Shahram Minaei would like to dedicate the book to
his wife Elham Minayi, his daughter Aylin Minayi and his parents.
vii
Contents
1 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Symbols, Units, and Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Some Fundamental Functions . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Signals, Systems, and Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Fundamentals of the Signals and Systems . . . . . . . . . . . . . . . . . . 11
2.2 Laplace and Fourier Transforms . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 Ideal Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4 Ideal Second-Order Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5 Ideal First-Order Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3 Passive Circuit Elements and Their Analysis . . . . . . . . . . . . . . . . . . . 35
3.1 Passive Circuit Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2 Passive Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3 RC and RL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4 RLC Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4 Main Transfer Functions of the Circuits . . . . . . . . . . . . . . . . . . . . . . 73
4.1 Definition of the Filter Transfer Function . . . . . . . . . . . . . . . . . . 73
4.1.1 VM FTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.1.2 CM FTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.1.3 TIM FTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.1.4 TAM FTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.2 First-Order VM FTFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.2.1 VM LPF TFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.2.2 VM HPF TFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2.3 VM APF TFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ix
x Contents
4.3 First-Order CM FTFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.4 Second-Order VM FTFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.5 Second-Order CM FTFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.6 High-Order VM BPF TF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5 Operational Amplifiers and Their Applications . . . . . . . . . . . . . . . . . 89
5.1 Practical Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . 89
5.2 Ideal OAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3 OA-Based Basic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.4 Some More Examples Based on the OA . . . . . . . . . . . . . . . . . . . 106
5.5 Finite Open Loop Gain of the OA . . . . . . . . . . . . . . . . . . . . . . . 108
5.6 Practical Open Loop Gain OA . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.7 Expression of the Open Loop Gain in the Frequency Domain . . . 116
5.8 Gain Bandwidth Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.9 DC Supply Voltage Restrictions . . . . . . . . . . . . . . . . . . . . . . . . 121
5.10 Simulated Grounded Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.10.1 Lossy SGIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.10.2 Lossless SGIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.11 Rectifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.12 Wien Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.13 Analog Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.14 Large Signal Operation in the OA . . . . . . . . . . . . . . . . . . . . . . . 144
5.15 SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.16 Full-Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6 Unity Gain Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.1 Unity Gain Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.2 CFs and Their Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.3 VFs and Their Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.4 CF and VF-Based Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
7 Unity Gain Inverting Amplifiers and Negative
Impedance Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.2 UGIAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.3 NICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
8 Current Conveyors and Their Applications . . . . . . . . . . . . . . . . . . . 189
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
8.2 CCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
8.3 CCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Contents xi
8.3.1 Realizations of the Other Active Devices

Based on the CCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
8.3.2 Realizations of the Instrumentation Amplifier
Based on the CCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
8.3.3 Realizations of the Simulated Inductors Based
on the CCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
8.3.4 Realizations of the QOs Based on the CCII . . . . . . . . . . 199
8.3.5 Realizations of the CCII- Based on the CCII+s . . . . . . . 200
8.4 CCIII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
8.5 CCCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
8.6 ICCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
8.7 DCCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
8.8 DXCCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
8.9 DVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
8.10 DDCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
8.11 FDCCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
8.12 CDCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8.13 EX-CCCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
9 Other Active Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
9.2 CFOA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
9.3 OTRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
9.4 FTFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
9.5 OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
9.6 VDIBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
9.7 VDBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
9.8 CDBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
9.9 CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
9.10 CFTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
9.11 CDTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
9.12 DVCCTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
9.13 COA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
About the Authors
Erkan Yuce was born in 1969 in Nigde, Turkey. He

received the B.Sc. degree from Middle East Technical
University, the M.Sc. degree from Pamukkale Univer-
sity, and the Ph.D. degree from Bogazici University, all
in Electrical and Electronics Engineering in 1994, 1998,
and 2006, respectively. He is currently a Professor at the
Electrical and Electronics Engineering Department of
Pamukkale University. His current research interests
include analog circuits, active filters, synthetic induc-
tors, and MOS transistor-based circuits. He is the author
or co-author of about 190 papers published in scientific
journals or conference proceedings. He is an assistant
editor-in-chief of the International Journal of Electron-
ics and Communications (AEU).
Shahram Minaei received the B.Sc. degree in Electrical

and Electronics Engineering from Iran University of Sci-
ence and Technology, Tehran, Iran, in 1993, and the M.
Sc. and Ph.D. degrees in Electronics and Communication
Engineering from Istanbul Technical University, Istanbul,
Turkey, in 1997 and 2001, respectively. He is currently a
Professor at the Department of Electrical and Electronics
Engineering, Dogus University, Istanbul, Turkey. He has
more than 190 publications in scientific journals or con-
ference proceedings. His current field of research con-
cerns current-mode circuits and analog signal
processing. Dr. Minaei is editor of the Journal of Circuits,
Systems and Computers (JCSC), International Journal of
Circuit Theory and Applications (IJCTA), Elektronika ir
Elektrotechnika, and editor-in-chief of the AEU – Inter-
national Journal of Electronics and Communications.
xiii
Chapter 1
Basic Concepts
1.1 Symbols, Units, and Prefixes
Symbols, units, and prefixes are very important issues especially in electrical and
electronics engineering (EEE). The international system of units (SI) is exhibited in
Table 1.1. Numerous units derived from the SI are demonstrated in Table 1.2.
Furthermore, unit prefixes are given in Table 1.3 [1].
Example 1.1 Find value of 5 F/m2 in terms of fF/(μm)2
Solution 1.1 5 F/m2 = 5 × 1015 fF/(106 μm)2 = 5 × 1015 fF/1012 (μm)2 = 5 × 103 fF/
(μm)2
1.2 Some Fundamental Functions
It is a well-known fact that functions are very essential issue for science and
engineering notably in EEE. Some of the fundamental functions, namely, constant,
sine wave, full-wave rectified, positive half-wave rectified, square wave, triangular
wave, sawtooth wave, exponential, delta, unit step, and unit ramp functions are
introduced in this chapter.
A constant function, namely, x1(t), is depicted in Fig. 1.1, where A is a real
number and t is time variable. Therefore, the function has a constant value of A for all
the times.
A sine wave function is called as x2(t) = Bsin(2πft + ψ), where f > 0 is the
frequency, |B| is the peak value, and -180° ≤ ψ ≤ 180° is the phase angle.
Furthermore, f and B are real numbers, while ω = 2πf is angular frequency,
and T = 1/f is the period. The function x2(t) is depicted in Fig. 1.2 in which
B = 500 mV, f = 1 MHz, and ψ = 60° are chosen as a practice. A full-wave
rectified function at 1 MHz is depicted in Fig. 1.3, while a positive half-wave
© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 1

E. Yuce, S. Minaei, Passive and Active Circuits by Example,
https://doi.org/10.1007/978-3-031-44966-6_1
2 1 Basic Concepts
Table 1.1 International sys- Fundamental physical quantity SI SI symbol

tem of units (SI)
Length Meter m
Mass Kilogram kg
Time Second s
Electric current Ampere A
Thermodynamic temperature Kelvin K
Amount of substance Mole mol
Luminous intensity Candela cd
Table 1.2 A number of units derived from the SI

SI Expressed in Expressed in other
Unit(s) SI symbol SI-based unit SI unit
Force, weight Newton N kgms-2 –
Frequency Hertz Hz s-1 –
Energy, work, heat Joule J kg.m2.s-2 Nm
Electric charge Coulomb C A.s –
Electric potential (voltage) Volt V kg.m2.s-3.A-1 J/C
Magnetic flux Weber Wb kg.m2.s-2.A-1 Vs
Inductance Henry H kg.m2.s-2.A-2 Wb/A
Capacitance Farad F kg-1.m-2.s4.A2 C/V
Resistance, impedance, Ohm Ω kg.m2.s-3.A-2 V/A
reactance
Electrical conductance Siemens S kg-1.m-2.s3.A2 A/V
Magnetic flux density Tesla T kg.s-2.A-1 Wb/m2
Power, radiant flux Watt W kg.m2.s-3 J/s
Angle Radian rad m.m-1 –
rectified function at 1 MHz is depicted in Fig. 1.4. In Figs. 1.3 and 1.4, sinusoidal
signals with peak 500 mV at 500 kHz and 1 MHz are applied, respectively. In
addition, a full-wave rectifier output is obtained from any function by taking absolute
value of this function. A square wave function at 1 MHz is demonstrated in Fig. 1.5,
while a triangular wave function at 1 MHz is shown in Fig. 1.6. A sawtooth wave
function is plotted in Fig. 1.7 at 1 MHz, while an exponential one is given in
Fig. 1.8. Further, this exponential function is defined as x3(t) = 0.5exp(-t/10-6)
for t ≥ 0.
δΔ(t) function is shown in Fig. 1.9 [2]. Delta function, namely, δ(t), is defined as
δðt Þ = lim δΔ ðt Þ ð1:1Þ

Δ→0
uΔ(t) function is exhibited in Fig. 1.10. Unit step function, namely, u(t), is given
below.
1.2 Some Fundamental Functions 3
Table 1.3 Unit prefixes Name Symbol Prefix multiplier

Yocto y ×10-24
Zepto z ×10-21
Atto a ×10-18
Femto f ×10-15
Pico p ×10-12
Angstrom Ao ×10-10
Nano n ×10-9
Micro μ ×10-6
Mili m ×10-3
Santi c ×10-2
Desi d ×10-1
Kilo k ×103
Mega M ×106
Giga G ×109
Tera T ×1012
Peta P ×1015
Exa E ×1018
Zetta Z ×1021
Yotta Y ×1024
Fig. 1.1 A constant x1(t)

function
A
uðt Þ = lim uΔ ðt Þ ð1:2Þ

Δ→0
u(t) function is depicted in Fig. 1.11, and unit ramp function demonstrated in
Fig. 1.12 is computed as follows:
r ðt Þ = uðτÞdτ = tuðt Þ ð1:3Þ

-1
Some relations among δ(t), u(t), and r(t) functions are given below.
dr ðt Þ
uð t Þ = ð1:4aÞ
dt
4 1 Basic Concepts
Fig. 1.2 A sine wave function at 1 MHz
Fig. 1.3 A full-wave rectifier function at 1 MHz
duðt Þ d2 rðt Þ
δðt Þ = = ð1:4bÞ
dt dt 2
1.2 Some Fundamental Functions 5
Fig. 1.4 A half-wave rectifier function at 1 MHz
Fig. 1.5 A square wave function at 1 MHz
uð t Þ = δðτÞdτ ð1:4cÞ
-1
6 1 Basic Concepts
Fig. 1.6 A triangular wave function at 1 MHz
Fig. 1.7 A sawtooth wave function at 1 MHz
1.3 Sensitivity
The sensitivity, namely, the robustness of the outcomes of any models, deals with the
effect of independent parameters on the dependent ones. Sensitivity of any function
y(x, z, w) to x is defined in Eq. (1.5).
1.3 Sensitivity 7
Fig. 1.8 An exponential function
Fig. 1.9 Representation of G'(t)

δΔ(t) function
1/'
t
-'/2 '/2
Fig. 1.10 Representation of u'(t)

uΔ(t) function
1
1/2
t
-' '
Fig. 1.11 Representation of u(t)

u(t) function
1
t
8 1 Basic Concepts
Fig. 1.12 Representation of r(t)

r(t) function
x ∂yðx, z, wÞ
Syxðx,z,wÞ = ð1:5Þ
yðx, z, wÞ ∂x
Note It is desired that sensitivities of any functions should be small in magnitude

[3–8].
Example 1.2 Find the sensitivity of function F(x) to x shown below in which B is a
real number.
x
F ðxÞ = ð1:6Þ
x-B
Solution 1.2 The sensitivity of the function F(x) given above with respect to x is
evaluated as in the following:
x d x B
SFx ðxÞ = = ð1:7Þ
x
x-B dx x - B B-x
Note It is observed from Eq. (1.7) that if x approaches to B, sensitivity goes to

infinity in magnitude. As a result, the function given in (1.6) is an undesired function
due to sensitivity point of view.
Example 1.3 A parallel/series RLC circuit has the angular resonance frequency (ω0)
as given in Eq. (1.8). Thus, find the sensitivities of ω0 to both passive elements.
1
ω0 = p ð1:8Þ
LC
Solution 1.3 The sensitivities of ω0 to both passive elements are found as
L dω0 1
SωL 0 = =- ð1:9aÞ
ω0 dL 2
C dω0 1
SωC0 = =- ð1:9bÞ
ω0 dC 2
1.3 Sensitivity 9
Fig. 1.13 A simple VCC

BJT-based circuit
IC1
RB
VBB
Fig. 1.14 A BJT-based VCC

circuit with a resistor in
emitter IC2
RB
VBB
RE
In order to express sensitivity more, bipolar junction transistor (BJT)-based

simple circuits operated in the forward active region are given in Figs. 1.13 and
1.14 as examples. It is assumed that both BJTs are identical. Thus, collector currents
of the topologies given in Figs. 1.13 and 1.14 are, respectively, computed as [9]
βF ðV BB - V BE Þ
I C1 = ð1:10aÞ
RB
βF ðV BB - V BE Þ
I C2 = ð1:10bÞ
RB þ ðβF þ 1ÞRE
Sensitivities of the collector currents demonstrated in Figs. 1.13 and 1.14 to the
current gain (βF = IC/IB) can be, respectively, given below.
βF dI C1
SIβC1 = =1 ð1:11aÞ
F I C1 dβF
βF dI C2 RB þ RE
SIβC2 = = ð1:11bÞ
F I C2 dβF RB þ ðβF þ 1ÞRE
One observes from the equations denoted in (1.11a) and (1.11b) that the circuit in
Fig. 1.14 is less sensitive than one exhibited in Fig. 1.13 due to the resistor RE. In
Eqs. (1.11a) and (1.11b), dIC1/dβF and dIC2/dβF are, respectively, evaluated by
dI C1 V BB - V BE
= ð1:12aÞ
dβF RB
10 1 Basic Concepts
dI C2 ðV BB - V BE ÞðRB þ ðβF þ 1ÞRE Þ - βF ðV BB - V BE ÞRE

=
dβF ðRB þ ðβF þ 1ÞRE Þ2
ð1:12bÞ
ðV BB - V BE ÞðRB þ RE Þ
=
ðRB þ ðβF þ 1ÞRE Þ2
It is understood from above that sensitivity gives a measure for performances of the
circuit with respect to their elements or parameters. In other words, it provides
selection of the adequate element tolerances [10].
References
1. J.W. Nilsson, S.A. Riedel, Electric Circuits, 10th edn. (Pearson, 2015)
2. A.V. Oppenheim, A.S. Willsky, S.H. Nawab, Signals and Systems, Pearson New International
Edition (Pearson Education Limited, Harlow, 2013)
3. A.B. Williams, Analog Filter and Circuit Design Handbook (McGraw Hill Professional, 2013)
4. R. Schaumann, M.E.V. Valkenburg, Design of Analog Filters (Oxford University Press, 2001)
5. A.F. Anday, Aktif devre sentezi (Istanbul Technical University, 1992)
6. A. Anand, M. Agrawal, N. Bhatt, M. Ram, Advances in System Reliability Engineering
(Elsevier, Academic, 2019), pp. 267–279
7. E.A. Ustinov, Sensitivity Analysis in Remote Sensing (Springer Briefs in Earth Sciences, 2015)
8. https://www.embedded.com/analyzing-circuit-sensitivity-for-analog-circuit-design/
9. A.S. Sedra, K.C. Smith, T.C. Carusone, V. Gaudet, Microelectronic Circuits, 8th edn. (Oxford
University Press, New York, 2020)
10. N.B. Hamida, B. Kaminska, Multiple fault analog circuit testing by selectivity analysis. Analog
Integr. Circ. Sig. Process 4(3), 231–243 (1993)
Chapter 2
Signals, Systems, and Filters
2.1 Fundamentals of the Signals and Systems
Signals can be mainly divided into two subcategories, voltage and current ones.
Furthermore, they can be separated into two subgroups, analog and digital ones
[1]. In this book, we concentrate on the analog voltage and current signals.
Linearity and time-invariance are other important issues. However, full-wave recti-
fier configurations are nonlinear, while rheostat is a variable resistor. It is assumed
that active and passive circuits given in Figs. 2.1 and 2.2 are linear time-invariant
(LTI). The circuits exhibited in Figs. 2.1 and 2.2 are examples for the circuit analysis
and circuit synthesis, respectively. In Fig. 2.1, vin(t) and the circuit are known, where
the output is required. Additionally, in Fig. 2.2, vin(t) and vout(t) are known in which
the circuit is required. In Fig. 2.1, the circuit has only a single output voltage, while
the topology in Fig. 2.2 can be implemented in several methods [2].
If the circuit in Fig. 2.1 is an active structure, its output voltage with respect to the
input voltage can be defined as follows [3]:
1
vout ðt Þ = f ðvin ðt ÞÞ = ak ðt Þvink ðt Þ
k=0
ð2:1Þ
= a0 ðt Þ þ a1 ðt Þvin ðt Þ þ a2 ðt Þv2in ðt Þ þ ...
where v0in(t) = 1, ak(t) (k = 0, 1, 2, . . .) is a complex number and k of vkin(t)

represents kth exponent. The circuit is nonlinear and time-varying for a0(t) ≠ 0, even
if it is as in the following form:

https://doi.org/10.1007/978-3-031-44966-6_2
12 2 Signals, Systems, and Filters
Fig. 2.1 A circuit used in

the analysis + Given +
vin(t) circuit Calculated output
_ _
Fig. 2.2 A circuit utilized

in the synthesis + Required +
vin(t) circuit vout(t)
_ _
1
vout ðt Þ = ak ðt Þvkin ðt Þ = a0 ðt Þ þ a1 ðt Þvin ðt Þ ð2:2Þ
k=0
The circuit in Fig. 2.1 is linear if its output voltage is as in the following:
vout ðt Þ = a1 ðt Þvin ðt Þ ð2:3Þ
However, equation in (2.3) is time-varying. Apart from this, if the circuit in

Fig. 2.1 is time-invariant, it has generally the following equation:
1
vout ðt Þ = ak vkin ðt Þ ð2:4Þ
k=0
If the configuration in Fig. 2.1 is LTI, it can be defined below.
vout ðt Þ = a1 vin ðt Þ ð2:5Þ
An LTI circuit can be generally shown as
n m
dk vout ðt Þ di vin ðt Þ
bk = ai ð2:6Þ
k=0 dt k i=0 dt i
where a0(d0v(t)/dt0) = a0v(t), bk (k = 0, 1, 2, . . . , n), and ai (i = 0, 1, 2, . . ., m) are

time-invariant complex numbers. Also, n ≥ m is required for causality [3]. Input
voltage signal and corresponding output voltage signal can be, respectively, dem-
onstrated by
vin ðt Þ = A sinðωt Þ ð2:7aÞ

2.1 Fundamentals of the Signals and Systems 13
Fig. 2.3 An NMOS VDD

transistor-based simple
amplifier circuit [4] iD(t)
RD
vout(t)
vin(t) M
VA
1
vout ðtÞ = Bk cosðkωtÞ ð2:7bÞ
k=0
From Eq. (2.7b), the total harmonic distortion (THD) is defined as
1 2
Bk
THD = 100 × ð2:8Þ
k=2
B1
One observes from equation given in (2.8) that DC term of the output signal is not
utilized in calculation of the THD. Furthermore, the first nine harmonics including
fundamental harmonic are taken in the SPICE simulation program.
Example 2.1 Find the THD value of the NMOS transistor-based simple amplifier in
Fig. 2.3.
Solution 2.1 It is assumed that the transistor operates in the saturation region. If the
channel-length modulation effect is ignored, drain current of the circuit in Fig. 2.3 is
computed as
iD ðt Þ = I D þ id ðt Þ þ io ðt Þ
1
= k n ðvin ðt Þ - V A - V TN Þ2 ð2:9Þ
2
1 1
= k n ð - V A - V TN Þ2 þ kn ð - V A - V TN Þvin ðt Þ þ kn v2in ðt Þ
2 2
Here, VTN is the threshold voltage of the NMOS transistor, while kn is

transconductance parameter. In addition, VA is sufficiently less than -VTN. Thus,
constant current (ID), desired current (id(t)), and other current (io(t)) signals are,
respectively, calculated as
1
ID = k ð- V A - V TN Þ2 ð2:10aÞ
2 n
id ðt Þ = kn ð- V A - V TN Þvin ðt Þ ð2:10bÞ
1 2
io ðt Þ = k v ðt Þ ð2:10cÞ
2 n in
Note cos(2ω0t) = 2cos2(ω0t) - 1. If vin(t) = Acos(ω0t) is chosen, id(t) and io(t) are,
respectively, computed by
id ðt Þ = k n ð- V A - V TN ÞA cosðω0 t Þ ð2:11aÞ
1 1 1 þ cos ð2ω0 t Þ
io ðt Þ = kn ðA cos ðω0 t ÞÞ2 = kn A2
2 2 2
1 2 1 2 ð2:11bÞ
= kn A þ kn A cos ð2ω0 t Þ
4 4
= I DC þ iu ðt Þ
From (2.11b), IDC and undesired current (iu(t)) are, respectively, written as
1
I DC = k A2 ð2:12aÞ
4 n
1
i u ðt Þ = k A2 cosð2ω0 t Þ ð2:12bÞ
4 n
vout(t) of the circuit exhibited in Fig. 2.3 is found as in the following:
vout ðt Þ = V DD - RD × iD ðt Þ
= V DD - RD × ðI D þ id ðt Þ þ io ðt ÞÞ ð2:13Þ
= V DD - RD × ðI D þ I DC þ id ðt Þ þ iu ðt ÞÞ
If constant currents in vout(t) of equation in (2.13) are ignored, AC part of the output
voltage (vout/(t)) is obtained as
=
vout ðt Þ = RD × ðid ðt Þ þ iu ðt ÞÞ
1
= RD × k n ð - V A - V TN ÞA cos ðω0 t Þ þ k n A2 cos ð2ω0 t Þ ð2:14Þ
4
= B1 cos ðω0 t Þ þ B2 cos ð2ω0 t Þ
Here, B1 = RD × kn(-VA-VTN)A and B2 = RD × knA2/4. Finally, THD of the circuit

in Fig. 2.3 is evaluated as
2.2 Laplace and Fourier Transforms 15
1 2 2 2
Bk Bk
THD = 100 × = 100 ×
k=2
B1 k=2
B1
1 ð2:15Þ
RD × kn A2 A
= 100 × 4 = 25 ×
RD × k n ð - V A - V TN ÞA - V A - V TN
2.2 Laplace and Fourier Transforms
By taking all the initial conditions zero, Laplace transforms of vin(t) and vout(t) in
Fig. 2.2 are, respectively, found as follows:
1
V in ðsÞ = vin ðtÞe - st dt ð2:16aÞ
-1
1
V out ðsÞ = vout ðt Þe - st dt ð2:16bÞ

-1
By using equations given in (2.6), (2.16a), and (2.16b), a transfer function

(TF) can be defined as
m
ai si
V ðsÞ i=0
H ðsÞ = out = ð2:17Þ
V in ðsÞ n
bj sj
j=0
In Eq. (2.17), real parts of all the poles must be negative for the stability. The
following condition, m ≤ n (m ≥ 0 and n ≥ 1) is required for the causality. If m ≥ 1
and n ≥ 1, the equation in (2.17) can be expressed as follows:
m
s þ zj
j=1
H ðsÞ = K n ð2:18Þ
ð s þ pi Þ
i=1
Here, K = am/bn. Also, -pi (i = 1, 2, 3,. . ., n) and -zj ( j = 1, 2, 3,. . ., m) are poles
and zeroes, respectively. pi given in Eq. (2.18) can be written as
pi = σ i þ jωi ð2:19Þ
If real part of pi = σ i > 0, it is stable. If σ i = 0 and ωi ≠ ωk (k = 1, 2, 3, . . ., n and

i ≠ k), it is marginally stable. Otherwise, it is unstable. By taking all the initial
conditions zero, Fourier transform of vin(t) in Fig. 2.2 is found as Vin(ω). Likewise,
Fourier transform of vout(t) is computed as Vout(ω). Vin(ω) and Vout(ω) are, respec-
tively, given by
V in ðωÞ = vin ðt Þe - jωt dt ð2:20aÞ

-1
1
V out ðωÞ = vout ðt Þe - jωt dt ð2:20bÞ

-1
By using equations in (2.20a) and (2.20b), TF of the circuit can be defined as
V out ðωÞ
H ð ωÞ = ð2:21Þ
V in ðωÞ
Equation given in (2.21) can be expressed by
HðωÞ = jHðωÞjej∠HðωÞ ð2:22Þ
where ∠H(ω) is phase and |H(ω)| is gain. Thus, the relationship between input and
output of the circuit in the time domain and frequency domain are, respectively,
given as
vout ðt Þ = hðt Þ vin ðt Þ ð2:23aÞ

V out ðωÞ = H ðωÞV in ðωÞ ð2:23bÞ
Here, h(t) is impulse response of the LTI topology, while H(ω) is its Fourier
transform. In addition, * is the convolution operator.
Note Gain of the passive circuit is between zero and one, while gain of the active
configuration can be any positive or negative real numbers. In other words, gain of
the active circuit can be more or less than unity in magnitude [1].
2.3 Ideal Filters 17
2.3 Ideal Filters
Ideal low-pass filter (LPF), band-pass filter (BPF), notch filter (NF), and high-pass
filter (HPF) have noncausal TFs, but they can be tried to realize with some approx-
imations such as Butterworth, Chebyshev, etc. TFs of the LPF, BPF, NF and HPF
are, respectively, demonstrated in Figs. 2.4, 2.5, 2.6, and 2.7, while ideal all-pass
filter (APF) TF that is causal is exhibited in Fig. 2.8. ωC in Figs. 2.4 and 2.7 is
angular cutoff frequency. Additionally, ω1 and ω2 in Figs. 2.5 and 2.6 are angular
cutoff frequencies. LPF has a bandwidth (BW) of ωC, while HPF and APF possess
Fig. 2.4 Characteristics of H LP ( )

the ideal LPF
0
C
Fig. 2.5 Characteristics of H BP ( )

the ideal BPF
0
1 2
Fig. 2.6 Characteristics of H NF ( )

the ideal NF
0
1 2
Fig. 2.7 Characteristics of H HP ( )

the ideal HPF
0
C
Fig. 2.8 Characteristics of H AP ( )

the ideal APF
infinity BW. BPF and NF have the following equations for ωC, BW, and quality
factor (Q) [5, 6]:
ω2C = ω1 × ω2 ð2:24aÞ
BW = ω2 - ω1 ð2:24bÞ
ω
Q= C ð2:24cÞ
BW
ωC of BPF and NF in Figs. 2.5 and 2.6 is angular resonance frequency or center
frequency. Ideal filters demonstrated in Figs. 2.4, 2.5, 2.6, 2.7, and 2.8 can be,
respectively, expressed as
1 ω ≤ ωC
jH LP ðωÞj = ð2:25aÞ
0 ω > ωC
1 ω 1 ≤ ω ≤ ω2
jH BP ðωÞj = ð2:25bÞ
0 ω < ω1 and ω > ω2
1 ω ≤ ω1 and ω ≥ ω2
jH NF ðωÞj = ð2:25cÞ
0 ω1 < ω < ω 2
2.4 Ideal Second-Order Filters 19
1 ω ≥ ωC
jH HP ðωÞj = ð2:25dÞ
0 ω < ωC
jH AP ðωÞj = 1 ω ≥ 0 ð2:25eÞ
Note For the characteristics given in Figs. 2.4, 2.5, 2.6, 2.7, and 2.8, the negative
frequency responses are ignored.
2.4 Ideal Second-Order Filters
A second-order universal filter can realize all the LPF, BPF, NF, HPF, and APF
responses [7]. Non-inverting second-order unity gain LPF, BPF, NF, HPF, and APF
phase and gain responses for different Q values are, respectively, depicted
in Figs. 2.9, 2.10, 2.11, 2.12, and 2.13, which are obtained by using one resistor,
one capacitor, and one inductor. Resonance frequency of these filter circuits is taken
as f0 ffi 1.59 MHz. Non-inverting second-order unity gain LPF, BPF, NF, HPF, and
APF in Figs. 2.9, 2.10, 2.11, 2.12, and 2.13 are, respectively, given below.
ω20
H LP ðsÞ = ð2:26aÞ
DðsÞ
Fig. 2.9 Non-inverting second-order unity gain LPF phase and gain responses for different quality
factors against frequency
Fig. 2.10 Non-inverting second-order unity gain BPF phase and gain responses for different
quality factors versus frequency
Fig. 2.11 Non-inverting second-order unity gain NF phase and gain responses for different quality
factors with respect to frequency
ω0
Q s
H BP ðsÞ = ð2:26bÞ
DðsÞ
Fig. 2.12 Non-inverting second-order unity gain HPF phase and gain responses for different
quality factors versus frequency
Fig. 2.13 Non-inverting second-order unity gain APF phase and gain responses for different
quality factors against frequency
s2 þ ω20
H NF ðsÞ = ð2:26cÞ
D ðs Þ
s2
H HP ðsÞ = ð2:26dÞ
DðsÞ
ω0
s2 - Q s þ ω20
H AP ðsÞ = ð2:26eÞ
DðsÞ
The denominator, D(s), in Eq. (2.26) is in the form of
ω0
DðsÞ = s2 þ s þ ω20 ð2:27Þ
Q
Here, ω0 is angular resonance frequency, while Q is quality factor. Apart from this,
bandwidth (BW) is evaluated by
ω0
BW = ð2:28Þ
Q
An ideal non-inverting second-order unity gain LPF in the frequency domain has,
respectively, the following phase and gain responses:
ω0 ω
Q
∠H LP ðωÞ = - Arctan ð2:29aÞ
ω20 - ω2
ω20
jH LP ðωÞj = ð2:29bÞ
2
2 ω0 ω
ω20 - ω2 þ Q
It is seen from Fig. 2.9 and equation indicated in (2.29a) that phase responses of the
non-inverting second-order LPF will vary from 0° to -180° if the frequency changes
from 0° to infinity. Phase of the LPF is equal to -90° at the resonance frequency. In
addition, if f >> f0, gain of the LPF decreases with -40 dB/decade. On the other
hand, an ideal non-inverting second-order unity gain BPF in frequency domain has,
ω0 ω
Q
∠H BP ðωÞ = 90 ° - Arctan ð2:30aÞ
ω20 - ω2
ω0 ω
Q
jH BP ðωÞj = ð2:30bÞ
2
2 ω0 ω
ω20 - ω2 þ Q
An ideal non-inverting second-order unity gain NF in the frequency domain has,

ω0 ω
Q
- Arctan if ω < ω0
ω20 - ω2
∠H NF ðωÞ = 0 if ω = ω0 ð2:31aÞ
ω0 ω
Q
180 ° - Arctan if ω > ω0
ω0 - ω2
2
ω20 - ω2
jH NF ðωÞj = ð2:31bÞ
2
2 ω0 ω
ω20 - ω2 þ Q
Likewise, an ideal non-inverting second-order unity gain HPF in the frequency

domain has, respectively, the following phase and gain responses:
ω0 ω
Q
∠H HP ðωÞ = 180 ° - Arctan ð2:32aÞ
ω20 - ω2
ω2
jH HP ðωÞj = ð2:32bÞ
2
2 ω0 ω
ω20 - ω2 þ Q
Phase of the HPF is equal to 90° at the resonance frequency. In addition, if f << f0,
gain of the HPF increases with 40 dB/decade. Finally, an ideal non-inverting second-
order unity gain APF in the frequency domain has, respectively, the following phase
and gain responses:
ω0 ω
Q
∠H AP ðωÞ = - 2Arctan ð2:33aÞ
ω20 - ω2
jH AP ðωÞj = 1 ð2:33bÞ
One observes from Eq. (2.33a) that phase response varies from 0° to -360° as the
frequency goes from zero to infinity.
Inverting second-order unity gain LPF, BPF, NF, HPF, and APF phase and gain
responses with respect to frequency are, respectively, given in Figs. 2.14, 2.15, 2.16,
2.17, and 2.18, which are obtained by using one resistor, one capacitor, and one
inductor. Resonance frequency of these figures is chosen as f0 ffi 1.59 MHz. TFs of
the filters given in Figs. 2.14, 2.15, 2.16, 2.17, and 2.18 are, respectively, found as
Fig. 2.14 Inverting second-order unity gain LPF phase and gain responses for different quality
Fig. 2.15 Inverting second-order unity gain BPF phase and gain responses for different quality
factors versus frequency
ω20
H LP ðsÞ = - ð2:34aÞ
DðsÞ
Fig. 2.16 Inverting second-order unity gain NF phase and gain responses for different quality
factors with respect to frequency
Fig. 2.17 Inverting second-order unity gain HPF phase and gain responses for different quality
ω0
Q s
H BP ðsÞ = - ð2:34bÞ
DðsÞ
Fig. 2.18 Inverting second-order unity gain APF phase and gain responses for different quality
factors versus frequency
s2 þ ω20
H NF ðsÞ = - ð2:34cÞ
DðsÞ
s2
H HP ðsÞ = - ð2:34dÞ
D ðs Þ
ω0
s2 - Q s þ ω20
H AP ðsÞ = - ð2:34eÞ
DðsÞ
The denominator, D(s) denoted in Eqs. (2.34a), (2.34b), (2.34c), (2.34d), and
(2.34e), was defined before in Eq. (2.27). The inverting second-order unity gain
LPF, BPF, NF, HPF, and APF possess the same gain responses of the non-inverting
second-order unity gain LPF, BPF, NF, HPF, and APF, respectively. An ideal
inverting second-order unity gain LPF in the frequency domain has the following
phase responses:
ω0 ω
Q
∠H LP ðωÞ = 180 ° - Arctan ð2:35Þ
ω20 - ω2
An ideal inverting second-order unity gain BPF in the frequency domain has the
following phase responses:
ω0 ω
Q
∠H BP ðωÞ = - 90 ° - Arctan ð2:36Þ
ω20 - ω2
An ideal inverting second-order unity gain NF in the frequency domain has the
following phase response:
ω0 ω
Q
180 ° - Arctan if ω < ω0
ω20 - ω2
∠H NF ðωÞ = 180 ° if ω = ω0 ð2:37Þ

ω0 ω
Q
360 ° - Arctan if ω > ω0
ω20 - ω2
Likewise, an ideal inverting second-order unity gain HPF in the frequency domain
has the following phase response:
ω0 ω
Q
∠H HP ðωÞ = - Arctan ð2:38Þ
ω20 - ω2
Finally, an ideal inverting second-order unity gain APF in the frequency domain has
the following phase response:
ω0 ω
Q
∠H AP ðωÞ = 180 ° - 2Arctan ð2:39Þ
ω 0 - ω2
2
One observes from Eq. (2.39) that phase response varies from 180° to -180° as the
frequency goes from zero to infinity.
Note For the non-inverting and inverting second-order universal filter responses,
magnitudes of the gains can be more or less than unity if active devices are used in
the implementation of the filter structures.
Example 2.2 Find the frequency of the second-order LPF for Q > 1/√2, where the
gain is maximum.
Solution 2.2 Derivative of the gain of the second-order LPF defined in Eq. (2.29b)
is taken as
d jH LP ðωÞj 2 × ω × ω0 ω0 1 - - ω2
2 2 1
2Q2
= 3 ð2:40Þ
dω 2 2
2 ω0 ω
ω20 - ω2 þ Q
If equation given in (2.40) is taken as zero, maximum frequency value is found.

Therefore, the following more simpler equation is obtained as:
1 1
ω2 - ω20 1 - = 0 ) ω2 = ω20 1 - ð2:41Þ
2Q2 2Q2
Therefore, ωmax is evaluated as
1
ωmax = ± ω0 1- ð2:42Þ
2Q2
However, ωmax > 0; thus, it is found by
1
ωmax = ω0 1- ð2:43Þ
2Q2
Note ωmax = 0 for Q ≤ 1/√2.

Example 2.3 Find the ωC of the second-order LPF with respect to ω0 and Q.
Solution 2.3 Firstly, |HLP(ω)| = 1/√2 is taken. Afterward, the following equation is
obtained:
ω20 1
=p ð2:44Þ
2 ω0 ω
2 2
ω20 - ω2 þ Q
ω = ωC
From equation given in (2.44), the following equation is obtained:
2
ω40 1 2 ω 0 ωC
2
= ) ω20 - ω2C þ = 2ω40 ð2:45Þ
2 ω0 ωC 2 Q
ω20 - ω2C þ Q
If the equation given in (2.45) is expanded, the following equation is obtained:
Q2 ω4C þ ω20 ω2C - 2Q2 ω20 ω2C - Q2 ω40 = 0 ð2:46Þ
The above equation simplifies as

2.5 Ideal First-Order Filters 29
1
ω4C - ω2C 2 - ω2 - ω40 = 0 ð2:47Þ
Q2 0
Solution of the equation exhibited in (2.47), the following ωC is found:
ω0
ωC = ± p 2Q2 - 1 þ 8Q4 - 4Q2 þ 1 ð2:48Þ
Q 2
Nevertheless, ωC must be greater than zero. The equation in (2.48) turns into
ω0
ωC = p 2Q2 - 1 þ 8Q4 - 4Q2 þ 1 ð2:49Þ
Q 2
If Q = 1/√2 is taken, ωC = ω0 is obtained.

Example 2.4 Find gains of the ideal second-order LPF, BPF, and HPF.
Solution 2.4 Gains of the ideal second-order LPF, BPF, and HPF are, respectively,
found as follows:
GLP = lim jH LP ðωÞj ð2:50aÞ

ω→0
GBP = jH BP ðωÞjω = ω0 ð2:50bÞ

GHP = ωlim j H ð ωÞ j
→ 1 HP
ð2:50cÞ
2.5 Ideal First-Order Filters
It is a well-known fact that a first-order universal filter can realize all the LPF, HPF,
and APF responses. Non-inverting and inverting first-order unity gain LPF, HPF,
and APF phase and gain responses are, respectively, exhibited in Figs. 2.19, 2.20,
and 2.21, which are obtained by using resistors and capacitors. Pole frequency of the
filter circuits in these figures is chosen as f0 ffi 1.59 MHz. Non-inverting and
inverting first-order unity gain LPF, HPF, and APF shown in Figs. 2.19, 2.20, and
2.21 are, respectively, given as follows:
ω0
H LP ðsÞ = ± ð2:51aÞ
DðsÞ
Fig. 2.19 Non-inverting and inverting first-order unity gain LPF phase and gain responses against
frequency
Fig. 2.20 Non-inverting and inverting first-order unity gain HPF phase and gain responses versus
frequency
Fig. 2.21 Non-inverting and inverting first-order unity gain APF phase and gain responses with
respect to frequency
s
H HP ðsÞ = ± ð2:51bÞ
DðsÞ
ω0 - s
H AP ðsÞ = ± ð2:51cÞ
DðsÞ
Here, + sign corresponds to the non-inverting filters, while - sign is related to the
inverting filters. Further, the denominator, D(s) is given as
DðsÞ = s þ ω0 ð2:52Þ
where ω0 is the angular pole frequency. TFs of Eq. (2.51) in the frequency domain
convert to
ω0
H LP ðωÞ = ± ð2:53aÞ
DðωÞ
jω
H HP ðωÞ = ± ð2:53bÞ
DðωÞ
ω0 - jω
H AP ðωÞ = ± ð2:53cÞ
DðωÞ
Here, the denominator, D(ω) is given by

DðωÞ = ω0 þ jω ð2:54Þ
If the TFs in Eq. (2.53) are non-inverting, they have, respectively, the following
phase responses:
ω
∠H LP ðωÞ = - Arctan ð2:55aÞ
ω0
ω
∠H HP ðωÞ = 90 ° - Arctan ð2:55bÞ
ω0
ω
∠H AP ðωÞ = - 2Arctan ð2:55cÞ
ω0
One observes from equation in (2.55c) that phase response varies from 0° to -180°
as the frequency goes from zero to infinity. Apart from this, if the TFs in Eq. (2.53)
are inverting, they have, respectively, the following phase responses:
ω
∠H LP ðωÞ = 180 ° - Arctan ð2:56aÞ
ω0
ω
∠H HP ðωÞ = - 90 ° - Arctan ð2:56bÞ
ω0
ω
∠H AP ðωÞ = 180 ° - 2Arctan ð2:56cÞ
ω0
One sees from equation in (2.56c) that phase response varies from 180° to 0° as the
frequency goes from zero to infinity. On the other hand, gains of the TFs of equations
in (2.53) can be given below.
ω0
jH LP ðωÞj = ð2:57aÞ
ω20 þ ω2
ω
ω20þ ω2
ω20 þ ð- ωÞ2
jH AP ðωÞj = =1 ð2:57cÞ
ω20 þ ω2
It is observed from equations in (2.57a) and (2.57b) that gain of the first-order LPF
decreases -20 dB/decade if ω >> ω0, while gain of the first-order HPF increases
20 dB/decade if ω << ω0.
Fig. 2.22 Phase and gain responses of the video filter against frequency
Example 2.5 Investigate the TF of a video filter given as below [8].
ω202 s2 þ ω201
H ðsÞ = ð2:58Þ
s2 þ ωQ011 s þ ω201 s2 þ ωQ022 s þ ω202
where f01 = 4 MHz, f02 = 3 MHz, Q1 = 4, and Q2 = 1 are chosen.

Solution 2.5 Phase and gain responses for the video filter with respect to frequency
are shown in Fig. 2.22.
Example 2.6 Investigate the TF of the fourth-order Butterworth LPF shown by
ω40
H ðsÞ = ð2:59Þ
s2 þ Qω01 s þ ω20 s2 þ Qω02 s þ ω20
Here, f0 ffi 3.18 MHz, Q1 ffi 0.541, and Q2 ffi 1.306 are taken.

Solution 2.6 Phase and gain responses for the fourth-order Butterworth LPF against
frequency are depicted in Fig. 2.23.
One observes from Fig. 2.23 that for f >> f0, gain of the fourth-order Butterworth
LPF decreases as -80 dB/decade.
Fig. 2.23 Phase and gain responses of the fourth-order Butterworth LPF versus frequency
References
2. A.F. Anday, Devre ve sistem analizi çözümlü problemler (Birsen, 2004)
Edition. (Pearson Education Limited, Harlow, 2013)
4. B. Razavi, Fundamentals of Microelectronics: With Robotics and Bioengineering Applications,
3rd edn. (Wiley, 2021)
7. E. Yuce, A single-input multiple-output voltage-mode second-order universal filter using only
grounded passive components. Indian J. Eng. Mater. Sci. 24(2), 97–106 (2017)
8. E. Yuce, S. Minaei, H. Alpaslan, Single voltage controlled CMOS grounded resistors and their
application to video filter. Indian J. Eng. Mater. Sci. 21(5), 501–509 (2014)
Chapter 3
Passive Circuit Elements and Their Analysis
3.1 Passive Circuit Elements
Electrical symbols of the fundamental passive elements, resistor, capacitor, and

inductor are depicted in Fig. 3.1. Capacitor and inductor are called as energy storage
elements and possess memory. However, resistor is memoryless and dissipates
power. As state variables, the capacitor has a voltage across its terminals, while
the inductor has a current in it. These voltage and current are stated as initial
conditions for the capacitor and inductor, respectively. In addition, their current
and voltage relationships in the time domain, s domain (complex frequency domain),
and frequency domain are given in Table 3.1. It is seen from Table 3.1 that the
voltage across the capacitor terminals and the current passing through the inductor
are continuous.
3.2 Passive Circuits
Passive elements can be divided into two subcategories: grounded and floating
passive elements. Two identical grounded passive circuits are demonstrated in
Figs. 3.2 and 3.3. A voltage source is applied to the topology given in Fig. 3.2,
while a current source is applied to the same configuration in Fig. 3.3 [1, 2]. Input
impedance and admittance of the circuit given in Fig. 3.2 are, respectively, computed
as follows:
V test
Z= ð3:1aÞ
I circuit

https://doi.org/10.1007/978-3-031-44966-6_3
36 3 Passive Circuit Elements and Their Analysis
Fig. 3.1 Fundamental

passive circuit components + IR + IC + IL
(a) resistor, (b) capacitor,
and (c) inductor VR R VC C VL L
_ _ _
(a) (b) (c)
Table 3.1 Current and voltage relationships of the fundamental passive circuit components
Domain
Passive elements Time s Frequency
Resistor vR(t) = RiR(t) VR(s) = RIR(s) VR(ω) = RIR(ω)
Capacitor C ðt Þ
iC ðt Þ = C dvdt IC(s) = sCVC(s) IC(ω) = jωCVC(ω)
Inductor L ðt Þ
vL ðt Þ = L didt VL(s) = sLIL(s) VL(ω) = jωLIL(ω)
Fig. 3.2 A voltage source Icircuit

applied to the grounded
passive circuit Passive circuit
Vtest +
_
Fig. 3.3 A current source

applied to the grounded + Passive circuit
passive circuit
Itest Vcircuit
_
I circuit
Y= ð3:1bÞ
V test
Input impedance and admittance of the circuit shown in Fig. 3.3 are, respectively,
calculated below.
V circuit
Z= ð3:2aÞ
I test
I test
Y= ð3:2bÞ
V circuit
The circuit of Fig. 3.3 has the same input impedance and admittance as the
topology in Fig. 3.2 possesses.
Example 3.1 Find phase and magnitude of the input impedance of the ideal resistor
shown in Fig. 3.4.
3.2 Passive Circuits 37
Fig. 3.4 An ideal grounded Vin

resistor Iin
ZR

capacitor Iin
ZC
Solution 3.1 The input impedance of the resistor in the frequency domain is
evaluated as
V in ðωÞ
Z R ð ωÞ = =R ð3:3Þ
I in ðωÞ
Input impedance of the resistor given in Eq. (3.3) can be expressed as
Z R ðωÞ = jZ R ðωÞjej∠Z R ðωÞ ð3:4Þ
Here, ∠ZR(ω) is defined as phase, and |ZR(ω)| is defined as magnitude of the input
impedance of the resistor. In addition, they are, respectively, computed as
∠Z R ðωÞ = 0o ð3:5aÞ
j Z R ð ωÞ j = R ð3:5bÞ
Example 3.2 Find phase and magnitude of the input impedance of the ideal
capacitor depicted in Fig. 3.5.
Solution 3.2 The input impedance of the capacitor in the frequency domain is
calculated as
V in ðωÞ 1 1
Z C ðωÞ = = = -j ð3:6Þ
I in ðωÞ jωC ωC
Input impedance of the capacitor given in Eq. (3.6) can be expressed as


inductor Iin
ZL
Z C ðωÞ = jZ C ðωÞjej∠Z C ðωÞ ð3:7Þ
where ∠ZC(ω) is defined as phase and |ZC(ω)| is defined as magnitude of the input
impedance of the capacitor. Further, they are, respectively, computed as
∠Z C ðωÞ = - 90o ð3:8aÞ

1
j Z C ð ωÞ j = ð3:8bÞ
ωC
Example 3.3 Find phase and magnitude of the input impedance of the ideal
inductor exhibited in Fig. 3.6.
Solution 3.3 The input impedance of the inductor in the frequency domain is found
as
V in ðωÞ
Z L ð ωÞ = = jωL ð3:9Þ
I in ðωÞ
Similarly, input impedance of the inductor given in Eq. (3.9) can be expressed as
Z L ðωÞ = jZ L ðωÞjej∠Z L ðωÞ ð3:10Þ
where ∠ZL(ω) is defined as phase and |ZL(ω)| is defined as magnitude of the input
impedance of the inductor. Moreover, they are, respectively, evaluated below.
∠Z L ðωÞ = 90o ð3:11aÞ

jZ L ðωÞj = ωL ð3:11bÞ
Phases and magnitudes of impedances of the ideal grounded resistor in Fig. 3.4,
the ideal grounded capacitor in Fig. 3.5, and the ideal grounded inductor in Fig. 3.6
are simulated through the SPICE program. In all the simulations, R = 1 kΩ,
C = 10 pF, and L = 100 μH are chosen. Additionally, the frequency in all the AC
simulations is taken from 1 kHz to 1 GHz. Their AC simulation results are,
respectively, shown in Figs. 3.7, 3.8, and 3.9 for the ideal grounded resistor in
Fig. 3.4, the ideal grounded capacitor in Fig. 3.5, and the ideal grounded inductor in
Fig. 3.7 Phase and magnitude of the impedance of the resistor exhibited in Fig. 3.4
Fig. 3.8 Phase and magnitude of the impedance of the capacitor depicted in Fig. 3.5
Fig. 3.6, respectively. Time domain simulation results are, respectively, given in
Figs. 3.10, 3.11, and 3.12 in which a sinusoidal peak input current signal with peak
50 μA at 1 MHz is separately applied to each of the ideal grounded resistor in
Fig. 3.4, the ideal grounded capacitor in Fig. 3.5, and the ideal grounded inductor in
Fig. 3.6.
Fig. 3.9 Phase and magnitude of the impedance of the inductor shown in Fig. 3.6
Fig. 3.10 Input current of the resistor in Fig. 3.4 and the corresponding output voltage
The ideal floating resistor, the ideal floating capacitor, and the ideal floating
inductor are demonstrated in Figs. 3.13, 3.14, and 3.15, respectively. The ideal
floating resistor, the ideal floating capacitor, and the ideal floating inductor in
s domain are, respectively, expressed with the following matrix equations:
Fig. 3.11 Input current of the capacitor in Fig. 3.5 and the corresponding output voltage
Fig. 3.12 Input current of the inductor in Fig. 3.6 and the corresponding output voltage
Fig. 3.13 An ideal floating I1 R I2

resistor + +
V_ 1 V_ 2
Fig. 3.14 An ideal floating C I2

I1
capacitor
+ +
V_1 V_ 2
Fig. 3.15 An ideal floating I1 L I2

inductor + +
V1 V_ 2
_
I1 1 1 -1 V1
= ð3:12aÞ
I2 R -1 1 V2
I1 1 -1 V1
= sC ð3:12bÞ
I2 -1 1 V2
I1 1 1 -1 V1
= ð3:12cÞ
I2 sL -1 1 V2
Example 3.4 Find equivalent impedance (Zeq) of n impedances all in series.

Solution 3.4 Zeq can be evaluated as
n
Z eq = Zi ð3:13Þ
i=1
Example 3.5 Find Zeq of m impedances all in parallel.

Solution 3.5 Zeq can be computed by
m
1 1 1
= ) Z eq = m ð3:14Þ
Z eq i=1
Zi 1
Zi
i=1
Example 3.6 Find equivalent admittance (Yeq) of k admittances all in parallel.

Solution 3.6 Yeq can be calculated as
k
Y eq = Yi ð3:15Þ
i=1
Example 3.7 Find Yeq of n admittances all in series.

Solution 3.7 Yeq can be calculated below.
n
1 1 1
= ) Y eq = n ð3:16Þ
Y eq i=1
Yi 1
Yi
i=1
In general, any impedances in the frequency domain can be defined as in the

following:
m
ak ðjωÞk
V ðωÞ k=0 AR ðωÞ þ jAI ðωÞ
ZðωÞ = in = =
I in ðωÞ n BR ðωÞ þ jBI ðωÞ ð3:17Þ
bi ðjωÞi
i=0
= jZðωÞjej∠ZðωÞ
Here, AR(ω), AI(ω), BR(ω), and BI(ω) are function of real numbers. -
180° ≤ ∠Z(ω) ≤ 180° is phase and |Z(ω)| is magnitude. They are, respectively,
evaluated below.
A I ð ωÞ B ð ωÞ
∠Z ðωÞ = tan - 1 - tan - 1 I ð3:18aÞ
AR ðωÞ B R ð ωÞ
A2R ðωÞ þ A2I ðωÞ

jZ ðωÞj = ð3:18bÞ
B2R ðωÞ þ B2I ðωÞ
From equation given in (3.17), the corresponding admittance can be expressed as
I in ðωÞ 1
Y ðω Þ = = ð3:19Þ
V in ðωÞ Z ðωÞ
Impedance and admittance selection suitable for integrated circuit

(IC) fabrications is given in Table 3.2 in which only resistor and capacitor are
considered.
Table 3.2 Impedance and Z Y Condition

admittance selection suitable
R 1/R Resistor
for IC processes
1/(sC) sC Capacitor
R/(1 + sCR) sC + 1/R Parallel resistor and capacitor
1/(sC) + R sC/(1 + sCR) Series resistor and capacitor
1 0 Open circuit
0 1 Short circuit
Any impedances and the corresponding admittances in s domain can be generally

expressed below.
m m
ai s i ðs - zi Þ
V ðsÞ i=0 a i=1
Z ðsÞ = in = = m ð3:20aÞ
I in ðsÞ n bn n
bj s j s - pj
j=0 j=1
n n
=
bj sj s - zj
1 I ðsÞ j=0 b j=1
Y ðsÞ = = in = = n ð3:20bÞ
Z ðsÞ V in ðsÞ m am m
=
ai si s - pi
i=0 i=1
where ai (i = 1, 2, . . ., m) and bj ( j = 1, 2, . . ., n) are real numbers. zi and z/j refer to

zeroes, and pj and p/i are poles. Also, they have the following relations:
=
zj = pj ðj = 1, 2, 3, . . . , nÞ ð3:21aÞ
=
pi = zi ði = 1, 2, 3, . . . , mÞ ð3:21bÞ
Note Real parts of all the poles and zeroes in Eq. (3.20) must be in the left half
s plane for the stability [3].
Example 3.8 Find phase and magnitude of the impedance given below, where a, b,
c, and d are all real numbers.
V in ðωÞ a þ jb
Z in ðωÞ = = ð3:22Þ
I in ðωÞ c þ jd
Solution 3.8 Phase and magnitude of the impedance given in Eq. (3.22) are,
respectively, found as follows:
b d
∠Z in ðωÞ = Arc tan - Arc tan ð3:23aÞ
a c
V in ðωÞ a2 þ b 2
jZ in ðωÞj = = ð3:23bÞ
I in ðωÞ c2 þ d 2
Example 3.9 Find phase and magnitude of the impedance of the RLC circuit in the
frequency domain, which is demonstrated in Fig. 3.16.
Solution 3.9 Impedance of the structure in Fig. 3.16 in the frequency domain can be
computed as
Fig. 3.16 An RLC circuit Vin

Iin
Zin
R C
1
Z in ðωÞ = jωL þ R==
jωC
R
= jωL þ
1 þ jωCR
Rð1 - jωCRÞ ð3:24Þ
= jωL þ
1 þ ω2 C 2 R2
R CR2
= þ jωðL - Þ
1 þ ω2 C 2 R2 1 þ ω2 C2 R2
= jZ in ðωÞjej∠Z in ðωÞ
From equation given in (3.24), ∠Zin(ω) and |Zin(ω)| are, respectively, calculated
below.
CR2
ω L- 1þω2 C 2 R2
∠Z in ðωÞ = Arctan R ð3:25aÞ
1þω2 C 2 R2
2 2
R CR2
jZ in ðωÞj = þ ω2 L - ð3:25bÞ
1 þ ω2 C2 R2 1 þ ω2 C 2 R2
Example 3.10 Find the input impedance of the circuit in s domain, which is
depicted in Fig. 3.17.
Solution 3.10 Input impedance of the structure exhibited in Fig. 3.17 is evaluated
below.
1 1
Z in ðsÞ = R1 þ þ sL1 þ 1 ð3:26Þ
sC 1 R2 þ sC 2 þ sL2
1
Fig. 3.17 A passive Vin

configuration Iin
R1
C1
Zin
L1
R2 C2 L2
3.3 RC and RL Circuits
RC circuit consisting of only one capacitor, resistor(s), and independent source

(s) with no inductor is called as first-order topology. Also, RL circuit composed of
only one inductor, resistor(s), and independent source(s) with no capacitor is called
as first-order structure. As state variables, the capacitors possess voltages across their
terminals, while the inductors have currents in them. These voltages and currents are
considered as initial conditions for the capacitors and inductors, respectively. On the
other hand, voltages/currents of the resistors can change abruptly. First-order RC and
RL circuits for t ≥ 0 can be defined by
df ðt Þ
τ þ f ðt Þ = K × input ð3:27Þ
dt
where K and the input are constants. f(t) can be capacitor current/voltage, inductor
current/voltage, and resistor current/voltage. Also, τ is time constant and can be,
respectively, defined for the capacitor and inductor as RC and L/R. From equation
denoted in (3.27), f(t) is found as
f ðt Þ = A þ Be - τ
t
ð3:28Þ
where A and B are real numbers. From equation given in (3.28), A and B are,
respectively, computed as follows:
f ð 0Þ = A þ B ) B = f ð 0Þ - A ð3:29aÞ
f ð 1Þ = A ð3:29bÞ
Hence, from equations in (3.28) and (3.29), f(t) for t ≥ 0 can be rewritten as given
below.
3.3 RC and RL Circuits 47
Fig. 3.18 A simple circuit

+ vR(t) - iC(t)
containing one capacitor,
one resistor, and one R +
independent voltage source Viu(t) +- C vC(t)
-
Fig. 3.19 Calculation of R

Req
Req=R
f ðt Þ = f ð1Þ þ ðf ð0Þ - f ð1ÞÞe - τ

t
ð3:30Þ
Example 3.11 Find vC(t), vR(t), and iC(t) in the simple topology of Fig. 3.18, where
Vi is constant positive voltage value and vC(0-) = 0 V.
Solution 3.11 For the structure in Fig. 3.18, at time t = 0+, the capacitor is short
circuit and the current passing through the capacitor is Vi/R. At time t = 1, the
capacitor is open circuit and vC(1) = Vi. vC(t), vR(t), and iC(t) for t ≥ 0 are,
respectively, evaluated below.
vC ðt Þ = vC ð1Þ þ ðvC ð0Þ - vC ð1ÞÞe - τ = V i 1 - e - τ

t t
ð3:31aÞ
vR ð t Þ = V i - vC ð t Þ = V i - V i 1 - e - τ = V i e - τ
t t
ð3:31bÞ
dvC ðt Þ V
= i e-τ
t
i C ðt Þ = C ð3:31cÞ
dt Req
Here, τ = ReqC. Req is calculated as follows: Independent voltage source is short-

circuited. Capacitor is taken, and it is looked at from the taken capacitor as seen from
Fig. 3.19. The seen resistor is Req. In Example 3.11, Req = R. In Fig. 3.20, time
domain simulation results for the circuit in Fig. 3.18 is demonstrated in which
R = 1 kΩ, C = 50 pF, and Vi = 1 V are chosen. Also, τ is found as 50 ns.
Example 3.12 For the topology of Fig. 3.21, find the current passing through the
capacitor, iC(t) in which vC(0-) = 0 V, Vi is constant voltage value, and Ii is constant
current value.
Solution 3.12 Req is found such that the independent input voltage source is short-
circuited, while the independent input current source is open-circuited. Capacitor is
taken, and it is looked at from the taken capacitor as seen from Fig. 3.22. Therefore,
Fig. 3.20 Time domain capacitor current, capacitor voltage, and applied input voltage
Fig. 3.21 A structure R1

including one capacitor, two
resistors, one independent iC(t)
Viu(t) +- R2 Iiu(t) C
voltage source, and one
independent current source
Fig. 3.22 Evaluation of Req R1
R2
Req=R1//R2
the seen resistor is Req = R1//R2. In the circuit of Fig. 3.21, iC(0) = Ii + Vi/R1 and
iC(1) = 0. Therefore, iC(t) is computed as
iC ðt Þ = iC ð1Þ þ ðiC ð0Þ - iC ð1ÞÞe - τ

t
V ð3:32Þ
= Ii þ i e - τ
t
R1
Fig. 3.23 Time domain capacitor current, applied input current, and applied input voltage of the
circuit given in Fig. 3.21
Fig. 3.24 A circuit using

R1 + vC(t) -
one voltage source, two
resistors, and one capacitor +
vin(t) +- C R2 vo(t)
-
Here, τ = ReqC. In Fig. 3.23, the time domain simulation results for the circuit in
Fig. 3.21 are given, where R1 = 2 kΩ, R2 = 3 kΩ, C = 10 pF, Vi = 2 V, and
Ii = 100 μA are taken. Therefore, Req = 1.2 kΩ and τ = 12 ns are found.
Example 3.13 Find vC(t) and vo(t) of the circuit in Fig. 3.24 in which C = 50 pF,
R1 = 1 kΩ, and R2 = 2 kΩ are chosen. Also, vC(0-) = 2 V is taken and applied piece-
wise constant input voltage, and vin(t) is exhibited in Fig. 3.25.
Solution 3.13 For the circuit in Fig. 3.24, Req = R1 + R2 = 3 kΩ yielding
τ = ReqC = 150 ns. There are two conditions for the circuit in Fig. 3.24.
(i) The first condition, 0 ≤ t < 300 ns resulting in vC(0) = 2 V and vC(1) = 5 V.
Hence, vC(t) is found below.
Fig. 3.25 Applied piece- vin(t), V

wise input voltage
5
t, ns
300
-5
vC ðt Þ = vC ð1Þ þ ðvC ð0Þ - vC ð1ÞÞe - τ

t
ð3:33Þ
= 5 - 3e - τ
t
From equation given in (3.33), vC(300- ns) is evaluated as
vC ð300 - nsÞ = 5 - 3e - 2 ffi 4:594 V ð3:34Þ
(ii) The second condition, t ≥ 300 ns resulting in vC(300 ns) ffi 4.954 V and
vC(1) = -5 V. Thus, vC(t) is evaluated as follows:
t - 300 ns
vC ðt Þ = vC ð1Þ þ ðvC ð300 nsÞ - vC ð1ÞÞe - τ
t - 300 ns
ð3:35Þ
ffi - 5 þ 9:954e - 150 ns
(i) The first condition, 0 ≤ t < 300 ns yielding vo(0) = (5 - 2) × 2/3 = 2 V and
vo(1) = 0 V. In this case, vo(t) is calculated as in the following:
vo ðt Þ = vo ð1Þ þ ðvo ð0Þ - vo ð1ÞÞe - τ

t
ð3:36Þ
= 2e - 150 ns
t
Here, vo(300- ns) is computed as 0.27 V. However, vo(300+ ns) is independent from
one in (3.36) and computed as
2
vo ð300þ nsÞ = ð- 5 - 4:594Þ × ffi - 6:396 V ð3:37Þ
3
(ii) The second condition, t ≥ 300 ns yielding vo(300+ ns) ffi -6.396 V and
vo(1) = 0 V. As a result, vo(t) can be evaluated by
t - 300 ns
vo ðt Þ = vo ð1Þ þ ðvo ð300 nsÞ - vo ð1ÞÞe - τ
t - 300 ns
ð3:38Þ
= - 6:396e - 150 ns
In Fig. 3.26, the time domain analysis results for the circuit of Fig. 3.24 are
shown.
Fig. 3.26 Time domain simulation results for the topology of Fig. 3.24
Fig. 3.27 A circuit R1

employing one voltage
source, two resistors, one R2 +
capacitor, and one switch +
Viu(t) - t=t0 C vC(t)
-
Example 3.14 Find the capacitor voltage, vC(t) given in Fig. 3.27, where t0 = 40 ns,
C = 10 pF, R1 = 2 kΩ, R2 = 3 kΩ, vC(0-) = 1 V, and Vi = 2.5 V are selected.
Solution 3.14 There are two cases for the circuit in Fig. 3.27.
(i) The first case, for 0 ≤ t < 40 ns, vC(0) = 1 V, vC(1) = 2.5 V, and Req = R1 = 2 kΩ.
Consequently, τ1 = ReqC = 20 ns, and vC(t) is found below.
vC ðt Þ = vC ð1Þ þ ðvC ð0Þ - vC ð1ÞÞe - τ

t
ð3:39Þ
= 2:5 - 1:5e - 20 ns
t
From equation given in (3.39), vC(40- ns) is found as follows:

Fig. 3.28 Time domain simulation results for the circuit in Fig. 3.27
vC ð40 - nsÞ = vC ð1Þ þ ðvC ð0Þ - vC ð1ÞÞe - τ

t
ð3:40Þ
= 2:5 - 1:5e - 2 ffi 2:297 V
(ii) The second case, for t ≥ 40 ns, vC(40+ ns) = vC(40- ns) ffi 2.297 V,
vC(1) = 1.5 V, and Req = R1//R2 = 1.2 kΩ. Therefore, τ2 = ReqC = 12 ns is
obtained, and vC(t) is calculated by
t - 40 ns
vC ðt Þ = vC ð1Þ þ ðvC ð40þ nsÞ - vC ð1ÞÞe - 12 ns
t - 40 ns
= 1:5 þ ð2:297 - 1:5Þe - 12 ns ð3:41Þ
- t -1240nsns
= 1:5 þ 0:797e
The time domain simulation results for the circuit of Fig. 3.27 are depicted in
Fig. 3.28.
Example 3.15 Find the voltage across the capacitor, vC(t) in terms of the applied
input current, iin(t) for the circuit of Fig. 3.29.
Solution 3.15 vC(t) via iin(t) is found as
t
dv ðt Þ 1
iC ðt Þ = iin ðt Þ = C C ) vC ðt Þ = iin ðτÞdτ ð3:42Þ
dt C
-1
Equation (3.42) for t > 0 can be expressed by

Fig. 3.29 A circuit +

composed of one current iin(t) C vC(t)
source and one capacitor
-
Fig. 3.30 The time domain simulation results for the topology in Fig. 3.29
t
1
vC ðt Þ = vC ð0Þ þ iin ðτÞdτ ð3:43Þ
C
0
The time domain simulation results for the topology in Fig. 3.29 are exhibited in
Fig. 3.30 in which C = 25 pF and iin(t) = 100(μA)u(t) are taken.
Note In the time domain simulation results for the topology in Fig. 3.29, a very
large-valued parallel resistor is connected to the capacitor in the SPICE simulation.
Example 3.16 A capacitor has a constant DC voltage across its two terminals, Vi. If
its two terminals are short-circuited at t = 0, find its current.
Solution 3.16 The voltage across the two terminals of the capacitor is given by
vC ðt Þ = V i uð- t Þ ð3:44Þ
Therefore, the current is evaluated as

Fig. 3.31 A topology made iL(t)

up of an input current
source, one resistor, and one iR(t)
inductor Iiu(t) R L
Fig. 3.32 Computation of

Req for the structure of R
Fig. 3.31
Req=R
dvC ðt Þ duð- t Þ
i C ðt Þ = C = CV i
dt dt ð3:45Þ
= - CV i δð - t Þ = - CV i δðt Þ
Example 3.17 Find the currents, iL(t) and iR(t) in Fig. 3.31, where Ii is a constant
DC current and iL(0-) = 0 A.
Solution 3.17 At time t = 0+, inductor behaves like an open circuit, i.e.,
iL(0+) = iL(0-) = 0 A. At time t = 1, inductor behaves like a short circuit; thus,
iL(1) = Ii is obtained. In RL circuits, it is known that τ = L/Req. Req is evaluated as
follows: Inductor is taken, the independent voltage source is short-circuited, and the
independent current source is open-circuited. It is looked at from the taken inductor
such that equivalent resistor is Req. For the circuit in Fig. 3.31, evaluation of Req is
depicted in Fig. 3.32. iL(t) and iR(t) for t ≥ 0 are, respectively, found as
iL ðt Þ = iL ð1Þ þ ðiL ð0Þ - iL ð1ÞÞe - τ

t
ð3:46aÞ
= Ii 1 - e - τ
t
i R ðt Þ = I i - i L ðt Þ
ð3:46bÞ
= Iie - τ
t
The topology given in Fig. 3.31 is simulated through the SPICE program in which
Ii = 100 μA, R = 1 kΩ, and L = 100 μH are selected. As a result, τ = 100 ns is found,
and the time domain simulation results for the topology in Fig. 3.31 are demon-
strated in Fig. 3.33.
Fig. 3.33 The time domain simulation results for the topology in Fig. 3.31
Fig. 3.34 A circuit with iL(t)

one voltage source and one
inductor
vin(t) +- L
Example 3.18 Find the inductor current, iL(t) in terms of vin(t) in Fig. 3.34.
Solution 3.18 The inductor current, iL(t) in terms of vin(t) can be computed as
t
di ðt Þ 1
vL ðt Þ = vin ðt Þ = L L ) iL ðt Þ = vin ðτÞdτ ð3:47Þ
dt L
-1
From equation given in (3.47), iL(t) for t > 0 can be expressed by
t
1
iL ðt Þ = iL ð0Þ þ vin ðτÞdτ ð3:48Þ
L
0
Fig. 3.35 Time domain simulation results for the circuit given in Fig. 3.34
The simulation results for the topology in Fig. 3.34 are given in Fig. 3.35, where
L = 50 μH and vin(t) = u(t) are taken.
Note In the time domain simulation results for the topology in Fig. 3.34, a very
small-valued series resistor is connected to the inductor in the SPICE simulation.
Any RL or RC circuit in general form can be defined as [4, 5]
Z = R þ jX ð3:49Þ
Here, R is real part of the impedance, while X is imaginary part of the impedance.
Also, R and X are real numbers. Therefore, quality factor (Q) of this first-order circuit
can be expressed as follows:
X
Q= ð3:50Þ
R
Example 3.19 Find impedance, phase, Q, and operating frequency of the series RL
circuit depicted in Fig. 3.36.
Solution 3.19 The impedance of this series RL topology in s domain is given below.
Z s = r s þ sLs ð3:51Þ
From equation denoted in (3.51), the impedance of the series RL circuit in the
frequency domain is expressed by
Fig. 3.36 A series RL

topology
Ls
rs
Zs
Fig. 3.37 A parallel RL

topology
Lp Rp
Zp
Z s ðωÞ = r s þ jωLs ð3:52Þ
where R = rs and X = ωLs. Then, Qs is evaluated below.
ωLs ωLs
Qs = = ð3:53Þ
rs rs
If Qs ≥ 10 is chosen, the effect of rs can be ignored. Further, the circuit in Fig. 3.36
behaves like a lossless inductor at sufficiently high frequencies. In this case, oper-
ating frequency range can be found as in the following:
ωLs 2πfLs 10 r s
Qs = ≥ 10 ) ≥ 10 ) f ≥ × ð3:54Þ
rs rs 2π Ls
Phase and magnitude of the structure in Fig. 3.36 are, respectively, evaluated as
ωLs
∠Z s ðωÞ = Arctan ð3:55aÞ
rs
j Z s ð ωÞ j = r 2s þ ω2 L2s ð3:55bÞ
Example 3.20 Find impedance, phase, Q, and operating frequency of the parallel
RL circuit given in Fig. 3.37.
Solution 3.20 The impedance of this parallel RL circuit in s domain can be
computed by
Z p = Rp == sLp
sLp Rp ð3:56Þ
=
sLp þ Rp
Equation of (3.56) in the frequency domain can be expressed as follows:
jωLp Rp
Z p ð ωÞ =
jωLp þ Rp
ð3:57Þ
ω2 L2p Rp þ jωLp R2p
=
ω2 L2p þ R2p
From equation given in (3.57), R and X are, respectively, found as
ω2 L2p Rp
R= ð3:58aÞ
ω2 L2p þ R2p
ωLp R2p
X= ð3:58bÞ
ω2 L2p þ R2p
Hence, Qp is calculated below.
ωLp R2p
X ω2 L2p þR2p Rp
Qp = = = ð3:59Þ
R ω2 L2p Rp ωLp
ω2 L2p þR2p
If Qp ≥ 10 is taken, the effect of Rp can be ignored. Hence, the parallel RL circuit of

Fig. 3.37 can operate like a lossless inductor at sufficiently low frequencies. In this
situation, the operating frequency range is calculated as
Rp Rp 1 Rp
Qp = ≥ 10 ) ≥ 10 ) f ≤ 0:1 × × ð3:60Þ
ωLp 2πfLp 2π Lp
Phase and magnitude of the impedance of the circuit in Fig. 3.37 are, respectively,
found by
Rp
∠Z p ðωÞ = Arctan ð3:61aÞ
ωLp
2 2
ω2 L2p Rp þ ωLp R2p
Z p ð ωÞ = ð3:61bÞ
ω2 L2p þ R2p
Fig. 3.38 A series RC

circuit
Cs
rs
Zs
Example 3.21 Find the impedance, phase, Q, and operating frequency of the series
RC circuit exhibited in Fig. 3.38.
Solution 3.21 The impedance of this circuit in s domain is computed as
1
Zs = þ rs ð3:62Þ
sC s
Equation of (3.62) in the frequency domain can be expressed as
1 j
Z s ð ωÞ = þ rs = - þ rs ð3:63Þ
jωC s ωC s
where R = rs and X = -1/(ωCs). In this case, Qs is found below.
- ωC1
1
Qs = s
= ð3:64Þ
rs ωC s r s
If Qs ≥ 10 is selected, the effect of rs can be ignored. Thus, this series RC topology

works like a lossless capacitor at sufficiently low frequencies. In this situation,
operating frequency range of this topology is found below.
1 1 1 1
Qs = ≥ 10 ) ≥ 10 ) f ≤ 0:1 × × ð3:65Þ
ωCs r s 2πfC s r s 2π Cs r s
Phase and magnitude of the series RC structure in Fig. 3.38 are, respectively,
computed as
- ωC1
1
∠Z s ðωÞ = Arctan s
= - Arctan ð3:66aÞ
rs ωCs r s
1
jZ s ðωÞj = þ r 2s ð3:66bÞ
ω2 C 2s
Example 3.22 Find impedance, phase, Q, and operating frequency of the parallel
RC circuit given in Fig. 3.39.
Solution 3.22 The impedance of this circuit in s domain is found as
1 Rp
Zp = ==Rp = ð3:67Þ
sCp sC p Rp þ 1
The equation of (3.67) in the frequency domain can be expressed as in the

following:
Rp
Z p ð ωÞ =
jωC p Rp þ 1
Rp - jωC p R2p ð3:68Þ
=
ω2 C 2p R2p þ 1
From equation given in (3.68), R and X are, respectively, found as
Rp
R= ð3:69aÞ
ω2 C 2p R2p þ 1
- ωC p R2p
X= ð3:69bÞ
ω2 C 2p R2p þ 1
Thus, Qp is evaluated by
ωC R2
X - ω2 C2 pR2 pþ1
Qp = = Rp
p p
= ωC p Rp ð3:70Þ
R 2 2 2 ω C p Rp þ1
If Qp ≥ 10 is taken, the effect of Rp can be ignored. As a result, the parallel topology

in Fig. 3.39 behaves like a lossless capacitor at sufficiently high frequencies. In this
case, operating frequency range is computed below.
10 1
Qp = ωCp Rp ≥ 10 ) 2πfC p Rp ≥ 10 ) f ≥ × ð3:71Þ
2π Cp Rp
Fig. 3.39 A parallel RC

circuit
Cp Rp
Zp
3.4 RLC Circuits 61
Phase and magnitude of the parallel RC structure in Fig. 3.39 can be, respectively,
found by
- ωCp R2p
ω2 C 2p R2p þ1
∠Z p ðωÞ = Arctan Rp = - Arctan ωC p Rp ð3:72aÞ
ω2 C 2p R2p þ1
2
R2p þ ωC p R2p
Rp
Z p ð ωÞ = = ð3:72bÞ
ω2 C 2p R2p þ1 1 þ ω2 C 2p R2p
3.4 RLC Circuits
RLC circuits have at least one resistor and two energy storage elements, i.e., one
capacitor and one inductor. If this circuit has no resistor, it is called as lossless.
Example 3.23 Analyze the parallel RLC circuit in Fig. 3.40.
Solution 3.23 Applying KCL, the following equation for the parallel RLC topology
depicted in Fig. 3.40 is obtained:
iin ðt Þ = iC ðt Þ þ iL ðt Þ þ iR ðt Þ ð3:73Þ
Here, iin(t), iC(t), iL(t), and iR(t) are applied input current, capacitor current, inductor
current, and resistor current, respectively. Also, v(t) in Fig. 3.40 is a capacitor
voltage. On the other hand, inductor voltage of the circuit of Fig. 3.40 can be
expressed as
diL ðt Þ
vð t Þ = L ð3:74Þ
dt
The capacitor current and resistor current in terms of v(t) can be found below.
Fig. 3.40 A parallel RLC v(t)

circuit
iin(t) C L R
iL(t)
dvðt Þ d 2 i ðt Þ
i C ðt Þ = C = CL L2 ð3:75aÞ
dt dt
vðt Þ L diL ðt Þ
iR ðt Þ = = ð3:75bÞ
R R dt
If equations denoted in (3.75) are replaced into Equation (3.73), the following
second-order differential equation is obtained:
L diL ðt Þ d 2 i ðt Þ
iin ðt Þ = iL ðt Þ þ þ CL L2 ð3:76Þ
R dt dt
Rearranging the equation in (3.76), the following equation is obtained:
1 d2 iL ðtÞ 1 diL ðtÞ 1

iin ðtÞ = þ þ i ðtÞ ð3:77Þ
CL dt 2 CR dt CL L
The equation of (3.77) simplifies as
d2 iL ðt Þ ω0 diL ðt Þ
ω20 iin ðt Þ = þ þ ω20 iL ðt Þ ð3:78Þ
dt 2 Q dt
where ω0 and Q are, respectively, found by
1
ω0 = ð3:79aÞ
LC
C
Q=R ð3:79bÞ
L
The characteristic expression of the differential equation given in (3.78) can be

evaluated as below.
ω0
m2 þ m þ ω20 = 0 ð3:80Þ
Q
Thus, homogeneous solution of the second-order differential equation indicated in

(3.78) can be calculated by using the roots.
ω0 ω20
m1,2 = - ± - ω20 ð3:81Þ
2Q 4Q2
One observes from equation in (3.81) that there are three cases that are explained as
follows:
3.4 RLC Circuits 63
(i) m1 and m2 are real and distinct.
ω0 ω20
m1 = - - - ω20 ð3:82aÞ
2Q 4Q2
ω0 ω20
m2 = - þ - ω20 ð3:82bÞ
2Q 4Q2
In this case, the overdamped condition is met as given below.
ω20 1
2
- ω20 > 0 ) Q < ð3:83Þ
4Q 2
(ii) m1 and m2 are real and equal.
ω0
m1 = m2 = - ð3:84Þ
2Q
In this case, the critically damped condition is met as follows:
ω20 1
2
- ω20 = 0 ) Q = ð3:85Þ
4Q 2
(iii) m1 and m2 are complex conjugate.
ω0 ω2
m1 = - - j ω20 - 02 ð3:86aÞ
2Q 4Q
ω0 ω2
m2 = - þ j ω20 - 02 ð3:86bÞ
2Q 4Q
In this case, the underdamped condition is met as in the following:
ω20 1
- ω20 < 0 ) Q > ð3:87Þ
4Q2 2
On the other hand, a particular solution depends on the form of the applied input,
iin(t). After specifying form of iin(t) such as δ(t), u(t), r(t), exponential function,
sinusoidal function, etc., the particular solution can be obtained. Then, a complete
response for the parallel RLC circuit in Fig. 3.40 can be found by adding homoge-
neous and particular solutions.
Fig. 3.41 A series RLC i(t)

circuit R L
_
+ vR(t) _ + vL(t)
+
+
vin(t) - C v_C(t)
Note Initial conditions of the capacitor and inductor are considered in the complete
response.
Example 3.24 Analyze the series RLC circuit in Fig. 3.41.
Solution 3.24 Applying KVL, the following equation for the series RLC structure
depicted in Fig. 3.41 is obtained:
vin ðt Þ = vR ðt Þ þ vL ðt Þ þ vC ðt Þ ð3:88Þ
where vin(t), vR(t), vL(t), and vC(t) exhibit applied input voltage, resistor voltage,
inductor voltage, and capacitor voltage, respectively. Further, i(t) in Fig. 3.41 is a
capacitor current. Apart from these, the capacitor current of the circuit of Fig. 3.41
can be given by
dvC ðt Þ
i ðt Þ = C ð3:89Þ
dt
The inductor voltage and resistor voltage in terms of i(t) can be found below.
diðt Þ d 2 vC ð t Þ
vL ð t Þ = L = CL ð3:90aÞ
dt dt 2
dvC ðt Þ
vR ðt Þ = Riðt Þ = CR ð3:90bÞ
dt
If equations in (3.90) are replaced into Eq. (3.88), the following second-order
differential equation is obtained:
dvC ðt Þ d 2 vC ð t Þ
vin ðt Þ = CR þ CL þ vC ð t Þ ð3:91Þ
dt dt 2
Rearranging the equation in (3.91), the following equation is obtained:
1 d 2 vC ðt Þ R dvC ðt Þ 1
vin ðt Þ = 2
þ þ vC ð t Þ ð3:92Þ
CL dt L dt CL
The equation given in (3.92) simplifies as

3.4 RLC Circuits 65
Fig. 3.42 A series LC

circuit
Ls
Cs
Zs
d2 vC ðt Þ ω0 dvC ðt Þ
ω20 vin ðt Þ = þ þ ω20 vC ðt Þ ð3:93Þ
dt 2 Q dt
where ω0 and Q are, respectively, found as
1
ω0 = ð3:94aÞ
LC
1 L
Q= ð3:94bÞ
R C
The similar calculations can be performed for the series RLC circuit, which is
made for the parallel RLC topology. On the other hand, any second-order series RLC
circuit can be defined as given below.
s2 þ s ωQ0 þ ω20
Z= ð3:95Þ
að s Þ
From equation given in (3.95), BW based on ω0 and Q is evaluated as follows:
ω0
BW = ð3:96Þ
Q
Example 3.25 Find phase and impedance of the series LC circuit in Fig. 3.42.
Solution 3.25 The series LC circuit demonstrated in Fig. 3.42 has the following
impedance:
1 s × sLs þ sC1 s
Z s = sLs þ = ð3:97Þ
sC s s×1
From equation given in (3.97), Zs simplifies as given below.

s2 Ls þ C1s ÷ Ls s2 þ Ls1Cs
Zs = = ð3:98Þ
s ÷ Ls s
Ls
From equation in (3.98), ω0 and Q are, respectively, found as
1
ω0 = ð3:99aÞ
Ls C s
Q=1 ð3:99bÞ
Impedance of the series LC circuit demonstrated in Fig. 3.42 in the frequency

domain can be found as follows:
1
Ls C s - ω2
Z s ðωÞ = jω ð3:100Þ
Ls
Phase and magnitude of the impedance of the topology in Fig. 3.42 for
1/(√(LsCs)) ≥ ω > 0 are, respectively, evaluated as
∠Z s ðωÞ = - 90 ° ð3:101aÞ
1
Ls C s - ω2
jZ s ðωÞj = ω ð3:101bÞ
Ls
Phase and magnitude of the impedance of the circuit in Fig. 3.42 for ω > 1/
(√(LsCs)) are, respectively, computed by
∠Z s ðωÞ = 90 ° ð3:102aÞ
ω2 - 1
Ls C s
Ls
Phase and magnitude of the impedance of the circuit given in Fig. 3.42 are
exhibited in Fig. 3.43, where Ls = 100 μH and Cs = 100 pF yielding f0 ffi 1.59 MHz
are taken. Additionally, simulations are performed through the SPICE program.
One observes from Fig. 3.43 that the phase response varies from -90° to 90° as
the frequency changes from zero to infinity.
Example 3.26 Find phase and impedance of the parallel LC circuit in Fig. 3.44.
Solution 3.26 Impedance of the parallel LC circuit demonstrated in Fig. 3.44 is
evaluated below.
3.4 RLC Circuits 67
Fig. 3.43 Phase and magnitude of the impedance of the circuit given in Fig. 3.42
Fig. 3.44 A parallel LC

topology
Cp Lp
Zp
1 sLp × sC1 p s × sLp × sC1 p

Z p = sLp == = = ð3:103Þ
sCp sLp þ sC1 s × sLp þ sC1 p
p
The equation in (3.103) simplifies as
sLp
Cp ÷ Lp s
Cp
Zp = = ð3:104Þ
s2 Lp þ C1p ÷ Lp s2 þ Lp1Cp
Similarly, from equation in (3.104), ω0 and Q are, respectively, found as
1
ω0 = ð3:105aÞ
Lp C p
Q=1 ð3:105bÞ
A parallel LC circuit in Fig. 3.44 in the frequency domain has the following
impedance:
jω
Cp
Z p ðωÞ = ð3:106Þ
1
Lp C p - ω2
Phase and magnitude of the parallel LC circuit in Fig. 3.44 for 1/(√(LpCp)) ≥ ω > 0,
are respectively, computed as
∠Z p ðωÞ = 90 ° ð3:107aÞ
ω
Cp
Z p ðωÞ = ð3:107bÞ
1
Lp C p - ω2
Phase and magnitude of the parallel LC circuit in Fig. 3.44 for ω > 1/(√(LpCp)) are,
respectively, calculated by
∠Z p ðωÞ = - 90 ° ð3:108aÞ
ω
Cp
Z p ðωÞ = ð3:108bÞ
ω2 - 1
Lp C p
Phase and magnitude of the impedance of the circuit in Fig. 3.44 are exhibited in
Fig. 3.45 in which L = 100 μH and C = 100 pF yielding f0 ffi 1.59 MHz are chosen.
Moreover, simulations are performed via the SPICE program.
Fig. 3.45 Phase and magnitude of the impedance of the topology in Fig. 3.44
3.4 RLC Circuits 69
Fig. 3.46 A series RLC

circuit
Ls
rs
Cs
Zs
It is observed from Fig. 3.45 that the phase response varies from 90° to -90° as
the frequency changes from zero to infinity.
Example 3.27 Find impedance of the series RLC circuit in Fig. 3.46.
Solution 3.27 Impedance of the series RLC circuit in Fig. 3.46 is found as follows:
1
s × sLs þ þ rs
1 sC s
Z s = sLs þ þ rs =
sC s s×1
1 ð3:109Þ
s2 Ls þ sr s þ ÷ Ls s 2 þ s r s þ 1
Cs Ls Ls C s
= = s
s ÷ Ls
Ls
From equation indicated in (3.109), ω0 and ω0/Q are, respectively, computed by
1
ω0 = ð3:110aÞ
Ls C s
ω0 r
= s ð3:110bÞ
Q Ls
From equations in (3.110), Q is evaluated as
ω0 Ls 1 Ls
Q= = ð3:111Þ
rs rs Cs
Impedance of the series RLC circuit in Fig. 3.46 in the frequency domain is given
by
jω Lrss þ Ls1Cs - ω2
Z s ð ωÞ = jω ð3:112Þ
Ls
Phase and magnitude of the impedance of the series RLC circuit in Fig. 3.46 in the
frequency domain are, respectively, calculated below.
Fig. 3.47 Phase and magnitude of the impedance of the circuit shown in Fig. 3.46
ω Lrss
∠Z s ðωÞ = - 90o þ Arctan ð3:113aÞ
1
Ls C s - ω2
2 2
1
Ls C s - ω2 þ ω Lrss
Ls
Phase and magnitude of the impedance of the circuit in Fig. 3.46 are demonstrated in
Fig. 3.47 in which rs = 1 kΩ, Ls = 100 μH, and Cs = 100 pF resulting in
f0 ffi 1.59 MHz and Q = 1 are selected. Also, simulations are made via the SPICE
program.
One sees from Fig. 3.46 that the phase response varies from -90° to 90°as the
frequency changes from zero to infinity.
Example 3.28 Find impedance of the parallel RLC circuit depicted in Fig. 3.48.
Solution 3.28 Impedance of the parallel RLC circuit depicted in Fig. 3.48 can be
found as given below.
1
Z p = sLp == ==Rp ð3:114Þ
sC p
The impedance given in Eq. (3.114) can be easily evaluated as

3.4 RLC Circuits 71
Fig. 3.48 A parallel RLC

structure.
Cp Rp Lp
Zp
1 1 1× s
Cp
Zp = = = ð3:115Þ
Yp 1
sLp þ R1p þ sC p 1
þ R1p þ sC p × s
sLp Cp
The impedance in Eq. (3.115) simplifies as

s
Cp
Zp = ð3:116Þ
s2 þ s Rp1Cp þ Lp1Cp
From the equation in (3.116), ω0 and ω0/Q are, respectively, evaluated as
1
ω0 = ð3:117aÞ
Lp C p
ω0 1
= ð3:117bÞ
Q Rp C p
Similarly, from the equations given in (3.117), Q is found below.
Cp
Q = ω0 Rp C p = Rp ð3:118Þ
Lp
Substituting s = jω into (3.116), the following impedance in the frequency

domain can be obtained as
jω
Cp
Z p ð ωÞ = ð3:119Þ
jω Rp1Cp þ Lp1Cp - ω2
Phase and magnitude of the impedance of the circuit depicted in Fig. 3.48 are,
respectively, evaluated as in the following:
Fig. 3.49 Phase and magnitude of the impedance of the circuit shown in Fig. 3.48
ω
Rp C p
∠Z p ðωÞ = 90 ° - Arctan ð3:120aÞ
1
Lp C p - ω2
ω
Cp
Z p ð ωÞ = ð3:120bÞ
2 2
ω
1
Lp C p - ω2 þ Rp C p
Phase and magnitude of the impedance of the circuit in Fig. 3.48 are demonstrated in
Fig. 3.49, where Rp = 1 kΩ, Lp = 100 μH, and Cp = 100 pF yielding f0 ffi 1.59 MHz
and Q = 1 are taken. Further, simulations are made through the SPICE program.
It is seen from Fig. 3.49 that the phase response varies from 90° to -90° as the
References
1. J.A. Svoboda, R.C. Dorf, Dorf’s Introduction to Electric Circuits, Global edition. (Wiley, 2018)
2. J.W. Nilsson, S. Riedel, Electric Circuits, Global edition, 11th ed. (Pearson, 2018)
3. L.O. Chua, C.A. Desoer, E.S. Kuh, Linear and Nonlinear Circuits (McGraw-Hill, 1987)
4. R.J. Cameron, C.M. Kudsia, Microwave Filters for Communication Systems, 2nd edn. (Wiley,
2018)
5. D.M. Pozar, Microwave Engineering, 3rd edn. (Wiley, 2005)
Chapter 4
Main Transfer Functions of the Circuits
4.1 Definition of the Filter Transfer Function
If the input is x(t) and the corresponding output is y(t) in a LTI system, the filter
transfer function (FTF) of this system is defined as [1]
m
ai s i
Y ðsÞ i=0
H ðsÞ = = ð4:1Þ
X ð sÞ n
bj sj
j=0
Here, ai (i = 0, 1, 2, . . ., m) and bj ( j = 0, 1, 2, . . ., n) are real numbers. Moreover,

X(s) and Y(s) represent Laplace transform of x(t) and y(t), respectively. In this
section, FTFs can be divided into four categories depending on the applied input
and the corresponding output whether they are current and/or voltage. These FTFs
called as voltage-mode (VM), current-mode (CM), transimpedance-mode (TIM),
and transadmittance-mode (TAM) are, respectively, depicted in Figs. 4.1, 4.2, 4.3,
and 4.4. Apart from these, these FTFs are obtained from the various combinations of
R, L, and C.
4.1.1 VM FTF
A VM FTF has ideally infinite input impedance and zero output impedance. The VM
FTF in Fig. 4.1 is found as [2, 3]
V out ðsÞ
H V ðsÞ = ð4:2Þ
V in ðsÞ

https://doi.org/10.1007/978-3-031-44966-6_4
74 4 Main Transfer Functions of the Circuits
Fig. 4.1 Block diagram of a

VM filter + HV +
V_in Vout
_
Fig. 4.2 Block diagram of a Iout

CM filter
HI
Iin
Fig. 4.3 Block diagram of a

TIM filter HZ +
Vout
Iin _
Fig. 4.4 Block diagram of a Iout

TAM filter
+ HY
Vin
_
4.1.2 CM FTF
A CM FTF has ideally zero input impedance and infinite output impedance. The CM
FTF in Fig. 4.2 is given by
I out ðsÞ
H I ðsÞ = ð4:3Þ
I in ðsÞ
4.1.3 TIM FTF
A TIM FTF possesses ideally zero input and output impedances. The TIM FTF in
Fig. 4.3 is expressed as follows:
V out ðsÞ
H Z ðsÞ = = Rm ð4:4Þ
I in ðsÞ
4.2 First-Order VM FTFs 75
4.1.4 TAM FTF
A TAM FTF possesses ideally infinite input and output impedances. The TAM FTF
in Fig. 4.4 is expressed below.
I out ðsÞ
H Y ðsÞ = = Gm ð4:5Þ
V in ðsÞ
4.2 First-Order VM FTFs
Transfer functions (TFs) of the first-order VM filters can be divided into three
categories, low-pass filter (LPF), high-pass filter (HPF), and all-pass filter
(APF) TFs.
4.2.1 VM LPF TFs
In this subsection, VM LPF TFs based on the various combinations of R, L, and C

are investigated.
Example 4.1 Draw the circuit, and find the TF of a first-order VM LPF based
on RC.
Solution 4.1 The first-order VM LPF based on RC is demonstrated in Fig. 4.5 and
has the following TF:
1
V out ðsÞ sC
H LP ðsÞ = =
V in ðsÞ 1
þR
sC ð4:6Þ
1
1 RC ω0
= = =
sCR þ 1 1 s þ ω0
sþ
RC
Fig. 4.5 A first-order VM R

LPF based on RC
+ +
Vin Vout
_ C _
where ω0 = 1/(RC) is called as angular pole frequency. Further, equation of (4.6) in

the frequency domain can be written as
ω0
H LP ðωÞ =
jω þ ω0 ð4:7Þ
= jH LP ðωÞjej∠H LP ðωÞ
Phase and gain of the TF in Eq. (4.7) are, respectively, evaluated as
ω
∠H LP ðωÞ = - tan - 1 ð4:8aÞ
ω0
ω0
jH LP ðωÞj = ð4:8bÞ
ω2 þ ω20
Gain of the TF in Eq. (4.8b) can be written in dB as follows:
ω0
20 logjH LP ðωÞj = 20 log
ω2 þ ω20
ð4:9Þ
= 20 logðω0 Þ - 20 log ω2 þ ω20
= 20 logðω0 Þ - 10 log ω2 þ ω20
One observes from Eq. (4.9) that if ω << ω0 is taken, the gain is 0 dB. If ω = ω0 is
chosen, the gain is approximately -3 dB. Also, if ω >> ω0 is selected, the gain of
the LPF decreases with slope of -20 dB/decade.
Example 4.2 Draw the circuit, and find the TF of a first-order VM LPF based
on RL.
Solution 4.2 The first-order VM LPF based on RL is exhibited in Fig. 4.6 and has
the following TF:
V out ðsÞ R
H LP ðsÞ = =
V in ðsÞ sL þ R
R ð4:10Þ
ω0
= L =
R s þ ω0
sþ
L
Here, ω0 = R/L is called as angular pole frequency.
Fig. 4.6 A first-order VM L

LPF based on RL + +
V_in Vout
_
R
4.2 First-Order VM FTFs 77
Fig. 4.7 A first-order VM C

HPF based on RC
+ +
V_in V_out
R
4.2.2 VM HPF TFs
In this subsection, VM HPFs based on various combinations of R, C, and L are

investigated.
Example 4.3 Draw the circuit, and find the TF of a first-order VM HPF based
on RC.
Solution 4.3 The first-order VM HPF based on RC is shown in Fig. 4.7 and has the
following TF:
V out ðsÞ R
H HP ðsÞ = =
V in ðsÞ 1
þR
sC ð4:11Þ
sCR s s
= = =
sCR þ 1 1 s þ ω0
sþ
RC
Similarly, ω0 = 1/(RC) is found. TF given in Eq. (4.11) in the frequency domain can
be expressed as
jω
H HP ðωÞ =
jω þ ω0 ð4:12Þ
= jH HP ðωÞjej∠H HP ðωÞ
Phase and gain of the HPF TF are, respectively, calculated as given below.
ω
∠H HP ðωÞ = 90o - tan - 1 ð4:13aÞ
ω0
ω
ω2 þ ω20
Gain of the TF in Eq. (4.13b) can be written in dB as follows:
ω
20 logjH HP ðωÞj = 20 log
ω2 þ ω20
ð4:14Þ
= 20 logðωÞ - 20 log ω2 þ ω20
= 20 logðωÞ - 10 log ω2 þ ω20

Fig. 4.8 A first-order VM R

HPF based on RL + +
V_in V_out
L
It is seen from equation given in (4.14) that for ω << ω0, the gain increases
20 dB/decade, while for ω = ω0, the gain is about -3 dB. Moreover, for ω >> ω0,
the gain is 0 dB.
Example 4.4 Draw the circuit, and find the TF of a first-order VM HPF based
on RL.
Solution 4.4 The first-order VM HPF based on RL is given in Fig. 4.8 and has the
following TF:
V out ðsÞ sL
H LP ðsÞ = =
V in ðsÞ sL þ R
s s ð4:15Þ
= =
R s þ ω0
sþ
L
Likewise, ω0 = R/L.
4.2.3 VM APF TFs
VM APFs have different realizations. In the following, a floating output realization

of the first-order APF is given.
Example 4.5 Find the TF of the first-order VM APF given in Fig. 4.9.
Solution 4.5 First-order VM APF in Fig. 4.9 for R2 = R1 can provide the
following TF:
V out ðsÞ 1 1
H AP ðsÞ = = -
V in ðsÞ 2 1 þ sCR
s ð4:16Þ
1-
1 1 - sCR 1 ω0
=- × =- ×
2 1 þ sCR 2 1þ s
ω0
Here, ω0 = 1/(RC). From Eq. (4.16), TF in the frequency domain can be written as
4.3 First-Order CM FTFs 79
Fig. 4.9 First-order VM +

APF based on RC V_in
R1 R
_
+ Vout
R2 C
H AP ðωÞ = jH AP ðωÞjej∠H AP ðωÞ ð4:17Þ
where ∠HAP(ω) and |HAP(ω)| are, respectively, calculated as
ω
∠H AP ðωÞ = 180o - 2 tan - 1 ð4:18aÞ
ω0
2
ω
12 þ -
1 1 - ω0
jω
1 ω0 1
jH AP ðωÞj = - = × = ð4:18bÞ
2 1 þ jω 2 2 2
ω0 ω
1 þ
2
ω0
The circuit in Fig. 4.9 has inverting APF responses. On the other hand, one can
change the polarity of the output in Fig. 4.9 to obtain a non-inverting first-order VM
all-pass filter. Thus, gain does not change, while the phase becomes below.
ω
∠H AP ðωÞ = - 2 tan - 1 ð4:19Þ
ω0
4.3 First-Order CM FTFs
Similarly, first-order CM FTFs can be obtained from various combinations of R, L,

and C.
Example 4.6 Find the TFs of the RC-based first-order CM filter demonstrated in
Fig. 4.10.
Solution 4.6 In order to analyze this RC circuit, an arbitrary auxiliary node called as
Vtest is used. By applying KCL, the following equation is obtained:
Fig. 4.10 A first-order CM Vtest

filter based on RC
Iin R C
ILP IHP
1
I in ðsÞ = V test þ sC ð4:20Þ
R
Thus, Vtest can be easily evaluated as follows:
R
V test = I ð4:21Þ
sCR þ 1 in
From equation in (4.21), a first-order TIM LPF TF is found as
V test R
H ðsÞ = = ð4:22Þ
I in sCR þ 1
By using Eq. (4.21), low-pass current (ILP) and high-pass one (IHP) are, respectively,
evaluated as
V test 1
I LP = = I ð4:23aÞ
R sCR þ 1 in
sCR
I HP = sCV test = I ð4:23bÞ
sCR þ 1 in
From equations given in (4.23), the following LPF and HPF TFs are, respectively,
computed by
I LP 1
= ð4:24aÞ
I in sCR þ 1
I HP sCR
= ð4:24bÞ
I in sCR þ 1
The angular pole frequency of this filter is calculated as 1/(CR).

Example 4.7 Find the output currents of the RL-based first-order CM filter shown
in Fig. 4.11.
Solution 4.7 In order to analyze this RL circuit, Vtest is used. By applying KCL, the
following equation is obtained:
1 1
I in = V test þ ð4:25Þ
R sL
Therefore, Vtest can be easily evaluated by

4.4 Second-Order VM FTFs 81
Fig. 4.11 A first-order CM Vtest

filter based on RL
Iin L R
ILP IHP
sR
V test = I in ð4:26Þ
s þ RL
From equation indicated in (4.26), a first-order TIM HPF TF is found as
V test ðsÞ sR
H ðsÞ = = ð4:27Þ
I in ðsÞ s þ RL
By using Eq. (4.26), ILP and IHP are, respectively, calculated as
R
V test
I LP = = L R I in ð4:28aÞ
sL sþL
V test s
I HP = = I in ð4:28bÞ
R s þ RL
The angular pole frequency of the filter is calculated as R/L.
4.4 Second-Order VM FTFs
Example 4.8 Find the output voltage of the second-order three-input single-output
universal filter based on RLC depicted in Fig. 4.12.
Solution 4.8 This filter is analyzed by using KCL as below.
V 1 - V out V - V2
= out þ ðV out - V 3 ÞsC ð4:29Þ
sL R
Organization of the equation in (4.29), output voltage, Vout depending on the applied
input voltages is evaluated as
s2 V 3 þ s RC
1
V 2 þ LC
1
V1
V out = ð4:30Þ
s þ s RC þ LC
2 1 1
From equation given in (4.30), ω0 and Q are, respectively, computed by

Fig. 4.12 A second-order

three-input single-output
universal filter based on V1
L
RCL
V2 Vout
R
V3
C
1
ω0 = p ð4:31aÞ
LC
C
Q=R = ω0 RC ð4:31bÞ
L
In Eq. (4.30), Vout is obtained as follows:

1. If V2 = V3 = 0 and V1 = Vin are chosen, an LPF response is obtained.
2. If V1 = V3 = 0 and V2 = Vin are chosen, a BPF response is obtained.
3. If V1 = V2 = 0 and V3 = Vin are chosen, an HPF response is obtained.
4. If V1 = V3 = Vin and V2 = -Vin are chosen, an APF response is obtained. The
voltage, -Vin can be easily obtained by using a unity gain inverting amplifier.
5. If V1 = V3 = Vin and V2 = 0 are chosen, an NF response is obtained.
Note Gains of the LPF, BPF, HPF, APF, and NF in Fig. 4.12 are unity.
Example 4.9 Find the output voltages Vout1 and Vout2 of the circuit shown in
Fig. 4.13. Which filter responses are realized?
Solution 4.9 Responses of the second-order single-input two-output filter depicted
in Fig. 4.13 can be, respectively, evaluated by
1
þ sL 1 þ s2 LC
V out1 = sC V in = V
1 s2 LC þ sCR þ 1 in
sL þ R þ
sC ð4:32aÞ
1
s2 þ
= LC V in
sR 1
s2 þ þ
L LC
4.4 Second-Order VM FTFs 83
Fig. 4.13 A second-order R C

single-input two-output
filter + +
+
Vin Vout2
Vout1 L _
_ _
Fig. 4.14 A second-order C L

single-input single-output
filter + +
Vin R Vout
_ _
sL s2 LC
V out2 = V in = V
1 s2 LC þ sCR þ 1 in
sL þ R þ
sC ð4:32bÞ
s2
= V
sR 1 in
s2 þ þ
L LC
So, NF and HPF responses are obtained from Vout1 and Vout2, respectively. From
equations denoted in (4.32), ω0 and Q are, respectively, calculated as
1
ω0 = p ð4:33aÞ
LC
1 L
Q= ð4:33bÞ
R C
Example 4.10 Find the output voltage Vout of the circuit shown in Fig. 4.14. Which
filter response is realized?
Solution 4.10 Response of the second-order single-input single-output BPF shown
in Fig. 4.14 can be computed as
sR
R
V out = V in = 2 sRL V in ð4:34Þ
sL þ R þ sC
1
s þ L þ LC
1
From equation given in (4.34), TF of the circuit is calculated as in the following:
V out ðsÞ sR
H ðsÞ = = 2 sRL ð4:35Þ
V in ðsÞ s þ L þ LC
1
So, a BPF response is obtained from the output, Vout.

Fig. 4.15 A second-order R L

single-input single-output
+ +
filter
Vin Vout
C _
_
Example 4.11 Find the output voltage, Vout of the circuit shown in Fig. 4.15. Which
filter response is realized?
Solution 4.11 Response of the second-order single-input single-output filter shown
in Fig. 4.15 can be computed as
1 1
V out = sC V in = C V in
1 1
sL þ R þ s2 L þ sR þ
sC C ð4:36Þ
1
= LC V
sR 1 in
s2 þ þ
L LC
From equation given in (4.36), TF of the filter is calculated as follows:
V out ðsÞ 1
H ðsÞ = = 2 LC ð4:37Þ
V in ðsÞ s þ sR
L þ LC
1
So, an LPF response is obtained from the output Vout.
4.5 Second-Order CM FTFs
Example 4.12 Find the output currents of the second-order CM universal filter
based on RLC demonstrated in Fig. 4.16.
Solution 4.12 Vtest can be easily evaluated by using the following equation:
1 1
I in = V test þ þ sC ð4:38Þ
sL R
From equation given in (4.38), Vtest is found by
s C1
V test = I
1 in
ð4:39Þ
s2 þ s RC
1
þ LC
4.5 Second-Order CM FTFs 85
Fig. 4.16 A second-order Vtest

single-input three-output
CM universal filter
Iin L R C
ILP IBP IHP
Fig. 4.17 A second-order Vtest

single-input single-output R
CM LPF
Iin C L
Iout
LPF, BPF, and HPF currents by using Vtest are, respectively, calculated as follows:
1
V test
I LP = = LC I in ð4:40aÞ
sL DðsÞ
V test s 1
I BP = = RC I in ð4:40bÞ
R DðsÞ
s2
I HP = V test sC = I ð4:40cÞ
DðsÞ in
Here, D(s) is given as
1 1
DðsÞ = s2 þ s þ ð4:41Þ
RC LC
By using LPF, BPF, and HPF currents, NF and APF currents can be, respectively,
obtained as
I NF = I LP þ I HP ð4:42aÞ
I AP = I LP - I BP þ I HP ð4:42bÞ
Example 4.13 Find the output current of the second-order CM LPF based on RLC
exhibited in Fig. 4.17.
Solution 4.13 Vtest can be easily evaluated by using the following equation:
1 I in I ðsL þ RÞ
I in = V test sC þ ) V test = = 2 in ð4:43Þ
sL þ R sC þ sLþR s CL þ sCR þ 1
1
From equation in (4.43), TF of the LPF is computed below.
1
I out V test
H ðsÞ = = = LC
ð4:44Þ
I in I in ðsL þ RÞ s2 þ sR
L þ LC
1
4.6 High-Order VM BPF TF
A fourth-order single-input single-output VM BPF is demonstrated in Fig. 4.18

[4]. In this filter, Q1 = ω01R1C1, Q2 = ω02R2C2, ω01 = 1/√((L1+L3)C1), and ω02 = 1/
√((L2+L3)C2). If the passive elements are taken as C1 = C2 = 100 pF,
L1 = 10.83 μH, L2 = 23.14 μH, L3 = 5 μH, R1 = 2 kΩ, and R2 = 2 kΩ then
f01 ffi 4 MHz, f02 ffi 3 MHz, Q1 ffi 5.03, and Q2 ffi 3.77 are found. Simulation results
for this filter are plotted in Fig. 4.19.
One observes from Fig. 4.19 that phase response varies from 90° to -270° as the
R1 L1 L2
+ +
Vin Vout
_ C1 L3 R2 C2 _
Fig. 4.18 A fourth-order single-input single-output VM BPF
Fig. 4.19 Phase and gain of the fourth-order single-input single-output VM BPF in Fig. 4.18
References 87
References
Edition. (Pearson Education Limited, Harlow, 2013)
4. M. Dogan, E. Yuce, S. Minaei, M. Sagbas, Synthetic transformer design using commercially
available active components. Circuits Syst. Sign. Process. 39(8), 3770–3786 (2020)
Chapter 5
Operational Amplifiers and Their
Applications
5.1 Practical Operational Amplifiers
Electrical symbol of the operational amplifier (OA) is depicted in Fig. 5.1. OA has
three terminals, non-inverting (+ terminal), inverting (- terminal), and output ones.
In addition, it has two symmetrical DC supply voltages, VEE and VCC, where
VEE = -VCC [1–4].
Output voltage, Vout, of the OA is evaluated as
V out = AðV þ - V - Þ ð5:1Þ
Here, A is open loop gain of the OA. Furthermore, A is frequency-dependent and can
be modeled by using a single pole model as follows:
A0
A= ð5:2Þ
1 þ fjf
b
where A0 is DC open loop gain, while fb is -3 dB frequency. A0 takes values

between 104 and 106 practically. Due to high values of A0, OA-based circuits are
designed by using feedback. Rated voltages are maximum/minimum voltages at the
output of the OA. These voltages are always lower than supply voltages of the OA in
magnitude. For example, if VCC = -VEE = 12 V are taken, rated voltages are about
Vr+ = 9 V and Vr- = -9 V. In other words, Vr+ < VCC and Vr- > VEE. Moreover,
Vout and output current Iout are, respectively, expressed as
V r - ≤ V out ≤ V rþ ð5:3aÞ
jI out j ≤ I out, max ð5:3bÞ

https://doi.org/10.1007/978-3-031-44966-6_5
90 5 Operational Amplifiers and Their Applications
Fig. 5.1 Representation of VCC

the practical OA
I+
V+ +
OA Vout
Iout
V- -
I-
VEE
Fig. 5.2 V+ - V- versus Vout

Vout characteristics
Vr+
A0
Vr-/A0
V+-V-
Vr+/A0
Vr-
where Iout,max is the maximum current that can be supplied by the OA. In Fig. 5.2,
V+ - V- against Vout characteristics is given in which A0 is the slope.
Example 5.1 If A = 104, Vr+ = 9 V, Vr- = -9 V, V+ = 5 V, and V- = -2 V are
taken, find the value of Vout.
Solution 5.1 From Eq. (5.1), Vout = A(V+ – V-), Vout = 104 × (5-(-2)) = 7 × 104 V
is found. Vout cannot exceed 9 V; thus, Vout = 9 V.
Example 5.2 If A = 104 Vr+ = 9 V, Vr- = -9 V, V+ = 0 V, and V- = 4 V are
chosen, find the value of Vout.
Solution 5.2 From Eq. (5.1), Vout = A(V+ - V-), Vout = 104 × (0 - 4) = -4 × 104 V
is found. Vout cannot be less than -9 V; therefore, Vout = -9 V.
5.2 Ideal OAs
Two models for the OA can be given. These models are, respectively, given in
Figs. 5.3 and 5.4. Vi and Vout in Fig. 5.3 are, respectively, calculated by
Vi = Vþ - V - ð5:4aÞ
5.2 Ideal OAs 91
Fig. 5.3 The first model for I+ Rout Iout

the OA V+ Vout
+ +
AVi
Rin Vi -
-
V-
I-
V+ Vout
GmV+
+
PVd
+ -
GmV- R Vd
V- -
Fig. 5.4 The second model for the OA
V out = AV i þ I out Rout ð5:4bÞ
Vout in Fig. 5.4 is found as
V out = μV d = μGm RðV þ - V - Þ ð5:5Þ
Here, Vd = GmR(V+ - V-).

An ideal OA-based model in Fig. 5.3 has the following properties:
1. I+ = I- = 0.
2. Rin = 1.
3. A = 1.
4. Rout = 0.
5. Infinity bandwidth.
6. No offset current.
7. No offset voltage.
8. Infinity slew rate (SR).
9. Zero THD.
10. Zero noise.
11. Infinity dynamic range.
12. Infinity common-mode rejection ratio.
13. No parasitic resistors and capacitors.
14. -1 ≤ Iout ≤ 1
15. -1 ≤ V+ ≤ 1, -1 ≤ V- ≤ 1, and -1 ≤ Vout ≤ 1
16. No restricted DC supply voltages.

17. Infinity power supply rejection ratio.
18. Infinity signal to noise ratio.
19. No stability problem.
5.3 OA-Based Basic Circuits
In this section, OAs are considered as ideal (A → 1).

Example 5.3 Find Vout/Vin of the inverting amplifier in Fig. 5.5.
Solution 5.3 Due to infinite gain of the OA, V- = V+ = 0. Analysis of the circuit in
Fig. 5.5 is performed as follows:
V in - V - V - V out V R
= - ) out = - 2 ð5:6Þ
R1 R2 V in R1
Thus, this amplifier has 180° phase difference between Vout and input voltage, Vin.
Input resistance of the inverting amplifier Rin = R1 in which A → 1. Also,
equivalent circuit of Fig. 5.5 is demonstrated in Fig. 5.6. Mechanical analogy of
the inverting amplifier is depicted in Fig. 5.7 [5], while Vin - Vout characteristics of
the inverting amplifier are depicted in Fig. 5.8. AC and transient responses of the
inverting amplifier are, respectively, given in Figs. 5.9 and 5.10, where LM318/NS
OA model is utilized. DC supply voltages of the OA are taken as ±12 V, while
R1 = 1 kΩ and R2 = 5 kΩ are chosen. As it is seen from Fig. 5.9, -3 dB frequency
(cutoff frequency) of the inverting amplifier is approximately 6.42 MHz. A
R2
R1
Vin -
OA Vout
+ Ao f
Fig. 5.5 An inverting amplifier
Fig. 5.6 Equivalent circuit Vin Vout

of the inverting amplifier
+
R1 - -R2Vin /R1
5.3 OA-Based Basic Circuits 93
Fig. 5.7 Mechanical

analogy of the inverting Vin R1
amplifier
R2 Vout
Vout
R2
–
R1
Vin
Fig. 5.8 Vin - Vout characteristics of the inverting amplifier
Fig. 5.9 AC analysis result of the inverting amplifier
sinusoidal input voltage with peak 1 V at 100 kHz is applied. Thus, the results are
shown in Fig. 5.10.
Note As shown in Fig. 5.5, feedback is fed to – terminal of the OA. Otherwise, the
inverting amplifier becomes unstable.
Fig. 5.10 Transient analysis results of the inverting amplifier
Fig. 5.11 A non-inverting Vin +

amplifier
OA Vout
- Ao∞
R2
R1
Example 5.4 Find Vout/Vin of the non-inverting amplifier in Fig. 5.11.

Solution 5.4 Analysis of the non-inverting amplifier given in Fig. 5.11 is achieved
as in the following:
V out - V in V in V R
= ) out = 1 þ 2 ð5:7Þ
R2 R1 V in R1
Input resistance of the non-inverting amplifier Rin → 1. In addition, equivalent

circuit of Fig. 5.11 is demonstrated in Fig. 5.12. Mechanical analogy of the
non-inverting amplifier is depicted in Fig. 5.13 [5], while Vin - Vout characteristics
of the non-inverting amplifier are plotted in Fig. 5.14.
Fig. 5.12 Equivalent Vin Vout

representation of the
non-inverting amplifier +
- (1+R2 /R1)Vin
Fig. 5.13 Mechanical

analogy of the non-inverting R2
amplifier Vout
R1
Vin
Vout
R2
1+
R1
Vin
Fig. 5.14 Vin - Vout characteristics of the non-inverting amplifier
Fig. 5.15 Topology of R2=100 k:

Example 5.5
R1=20 k:
Vin -
R3=20 k: OA Vout
+ A→f
R5=1 k:
R4=20 k:
Example 5.5 Find Vout/Vin and input resistance of the circuit depicted in Fig. 5.15.
Solution 5.5 I+ = 0 A; thus, V+ = 0 V (R4 and R5 have no effect). V- = V+;
accordingly, R3 has no effect. Therefore, Vout/Vin and Rin are, respectively, found as
Fig. 5.16 Circuit of

Example 5.6 R3
R2
-
Iin OA Vout
R1
+
A→f
Fig. 5.17 Simplified circuit

of Example 5.6 R3
R1+R2
-
R1Iin
_ OA Vout
+
+ A→f
V out R 100kΩ
=- 2=- = -5 ð5:8aÞ
V in R1 20kΩ
Rin = R1 = 20kΩ ð5:8bÞ
Example 5.6 Find Vout/Iin in the structure of Fig. 5.16.

Solution 5.6 The circuit of Fig. 5.16 simplifies as given in Fig. 5.17 in which a
source transformation technique is used. Hence, Vout/Iin is evaluated as
V out R3 V R1 R3
= ) out = ð5:9Þ
R1 I in R1 þ R2 I in R1 þ R2
Example 5.7 If gain of the nominal value of the inverting amplifier is 10 and both
resistors have 5% tolerance, find the range of Vout/Vin.
Solution 5.7 The range of Vout/Vin is found below.
0:95 V out 1:05 V

- 10 × ≥ ≥ - 10 × ) - 9:05 ≥ out ≥ - 11:05 ð5:10Þ
1:05 V in 0:95 V in
Fig. 5.18 An integrator C

topology
R
Vin(s) -
OA Vout(s)
+ A→f
Fig. 5.19 A differentiator R

circuit
C
Vin(s) -
OA Vout(s)
+ A→f
Example 5.8 Analyze the integrator circuit depicted in Fig. 5.18.

Solution 5.8 Transfer function (TF) of this structure in s domain is evaluated by
V in ðsÞ 1
= - sCV out ðsÞ ) V out ðsÞ = - V ðsÞ
R sCR in
V ðsÞ 1
) H ðsÞ = out =- ð5:11Þ
V in ðsÞ sCR
Output voltage of the integrator in the time domain is calculated as
t
1
vout ðt Þ = - vin ðτÞdτ ð5:12Þ
CR
-1
Example 5.9 Analyze the differentiator circuit demonstrated in Fig. 5.19.

Solution 5.9 TF of this structure in s domain is calculated as follows:
V out ðsÞ
V in ðsÞsC = - ) V out ðsÞ = - sCRV in ðsÞ
R
V ðsÞ
) H ðsÞ = out = - sCR ð5:13Þ
V in ðsÞ
Output voltage of the differentiator in the time domain is found as

Fig. 5.20 An R
antilogarithmic amplifier
circuit based on a physical
D
diode
Vin -
OA Vout
+ A→f
Fig. 5.21 An R
antilogarithmic amplifier
circuit based on a pnp-type
BJT
BJT
Vin -
OA Vout
+ A→f
Fig. 5.22 A logarithmic D

amplifier circuit based on a
physical diode
R
Vin -
OA Vout
+ A→f
dvin ðt Þ
vout ðt Þ = - CR ð5:14Þ
dt
Example 5.10 Analyze the antilogarithmic amplifier topologies given in Figs. 5.20
and 5.21. A physical diode is used in Fig. 5.20, while a pnp-type BJT is utilized in
Fig. 5.21.
Solution 5.10 Analysis of these structures is performed as given below.
V in - V -
V - - V out V in
I Se VT
= ) V out = - RI S e V T ð5:15Þ
R
where IS is the saturation current and VT is the thermal voltage. Also, VT = kT/
q ffi 25 mV at room temperature that is 27 °C = 300 K. For Vin ≥ 5 VT, the circuits
given in Figs. 5.20 and 5.21 operate properly.
Example 5.11 Analyze the logarithmic amplifier circuits are depicted in Figs. 5.22
and 5.23. A physical diode is used in Fig. 5.22, while an npn type BJT is utilized in
Fig. 5.23.
Fig. 5.23 A logarithmic BJT

amplifier topology based on
an npn type BJT
R
Vin -
OA Vout
+ A→f
Fig. 5.24 A squarer based R

on a PMOS transistor, one
resistor, and one OA
PMOS
Vin -
OA Vout
– VTP + A→f
Fig. 5.25 A square rooter NMOS

based on an NMOS
transistor, one resistor, and
one OA R
Vin - VTN
OA Vout
+ A→f
Solution 5.11 Analysis of these circuits is performed as given below.
V - - V out V in - V - V
ISe VT
= ) V out = - V T ln in ð5:16Þ
R I SR
For Vout ≤ -5 VT, the circuits given in Figs. 5.22 and 5.23 operate properly.
Example 5.12 Analyze the squarer circuit based on a PMOS transistor, one resistor,
and one OA shown in Fig. 5.24. It is assumed that PMOS transistor works in the
saturation region.
Solution 5.12 Analysis of this structure is performed as given below.
kp V - V out kp
ðV - ð - jV TP jÞ - jV TP jÞ2 = - ) V out = - R V 2in ð5:17Þ
2 in R 2
Example 5.13 Analyze the square rooter circuit based on an NMOS transistor, one
resistor, and one OA shown in Fig. 5.25. It is assumed that NMOS transistor works
in the saturation region.
Fig. 5.26 An analog adder

structure R3
R1
V1 -
V2 OA Vout
R2
+ A→f
R2
R1
V1 - R5
R3
OA -
Vo
(1) OA Vout
+ A→f
(2)
+ A→f
V2
R4
Fig. 5.27 A circuit for providing Vout = 3 V1 – 4 V2
Solution 5.13 Analysis of this topology is performed as
kN V -V- 2V in
ðV TN - V out - V TN Þ2 = in ) V out = ± ð5:18Þ
2 R kN R
where VGS > VTN must be satisfied; therefore, Vout is evaluated as in the following:
2V in
V out = - ð5:19Þ
kN R
For the circuits in Figs. 5.24 and 5.25, Vin > 0 must be satisfied.
Example 5.14 Analyze the analog adder circuit depicted in Fig. 5.26.
Solution 5.14 Analysis of this circuit is performed by
V1 - V - V2 - V - V - V out V V
þ = - ) V out = - R3 1 þ 2 ð5:20Þ
R1 R2 R3 R1 R2
Example 5.15 Design a circuit for realizing Vout = 3 V1 – 4 V2.

Solution 5.15 The structure for providing Vout = 3 V1 – 4 V2 is given in Fig. 5.27.
Vout of the topology in Fig. 5.27 is found below.
R3
R1
V1 - R7
R4
V2 OA -
R2 Vo
(1) OA Vout
+ A→f
(2)
+ A→f
V3
R5
V4
R6
Fig. 5.28 A circuit for providing Vout = 5 V1 + 4 V2 - 2.5 V3 – 2 V4
R2 R R R R R
Vo = - V ) V out = - 5 V o - 5 V 2 ) V out = 2 5 V 1 - 5 V 2 ð5:21Þ
R1 1 R3 R4 R1 R3 R4
It is observed from equation in (5.21) that if R1 = R4 = 1 kΩ, R2 = 3 kΩ, and

R3 = R5 = 4 kΩ are chosen, Vout = 3 V1 – 4 V2 is easily obtained.
Example 5.16 Design a circuit for realizing Vout = 5 V1 + 4 V2 – 2.5 V3 – 2 V4.
Solution 5.16 The structure for providing Vout = 5 V1 + 4 V2 - 2.5 V3 – 2 V4 is
given in Fig. 5.28. Vout of the circuit in Fig. 5.28 is evaluated as
R3 R R R R
Vo = - V - 3 V ) V out = - 7 V o - 7 V 3 - 7 V 4 ð5:22Þ
R1 1 R2 2 R4 R5 R6
From Eq. (5.22), Vout of the circuit in Fig. 5.28 is recomputed as follows:
R3 R7 R R R R
V out = V þ 3 7V - 7V - 7V ð5:23Þ
R1 R4 1 R2 R4 2 R5 3 R6 4
It is seen from equation given in (5.23) that if R1 = R3 = R4 = 1 kΩ, R2 = 1.25 kΩ,

R5 = 2 kΩ, R6 = 2.5 kΩ, and R7 = 5 kΩ are taken, Vout = 5 V1 + 4 V2 - 2.5 V3 – 2 V4
is easily obtained.
Example 5.17 Analyze the first-order low-pass filter (LPF) depicted in Fig. 5.29.
Solution 5.17 Analysis of this topology is performed as follows:
V in 1 R2 1
= - V out sC þ ) V out = - V ð5:24Þ
R1 R2 R1 1 þ sCR2 in
Example 5.18 Analyze the first-order high-pass filter (HPF) demonstrated in

Fig. 5.30.
Fig. 5.29 A first-order LPF C
R2
R1
Vin -
OA Vout
+ A→f
Fig. 5.30 A first-order HPF R2

R1 C
Vin(s) -
OA Vout(s)
+ A→f
C1
C2
R2
R1
Vin(s) - R4
R3
OA (1) -
OA (2) Vout(s)
+ A→f
+ A→f
Fig. 5.31 A topology for realizing TF given in (5.26)
Solution 5.18 Analysis of this topology is performed as
V in - V out R sCR1 R s
= ) V out = - 2 V =- 2 V ð5:25Þ
R1 þ sC1 R2 R1 1 þ sCR1 in R1 s þ CR1 in
1
Example 5.19 Design a circuit for realizing the following TF:
100
H ðsÞ = 2
ð5:26Þ
1 þ 10s 7
Solution 5.19 The circuit for providing TF in (5.26) is given in Fig. 5.31. This
circuit can be easily obtained by cascading two first-order LPFs given in Fig. 5.29.
Hence, TF of (5.26) becomes below.
R2
R1 C1
Vin(s) - C2 R4
R3
OA (1) -
+ A→f OA (2) Vout(s)
+ A→f
Fig. 5.32 A topology for providing TF given in (5.30)
100 - 10 - 10
H ðsÞ = = × ð5:27Þ
2 1 þ 10s 7 1 þ 10s 7
1 þ 10s 7
From Eq. (5.27), H(s) simplifies as
- 10 - 10 - RR21 - RR43
H ðsÞ = × = × ð5:28Þ
1 þ 10s 7 1 þ 10s 7 1 þ sC1 R2 1 þ sC2 R4
From Eq. (5.28), the following equations are obtained:
R2 R4
= = 10 ð5:29aÞ
R1 R3
C1 R2 = C2 R4 = 10 - 7 ð5:29bÞ
If C1 = C2 = 100 pF are chosen, R2 = R4 = 1 kΩ and R1 = R3 = 100 Ω are found.

Example 5.20 Design a topology for realizing the following TF:
100s2
H ðsÞ = 2
ð5:30Þ
s þ 107
Solution 5.20 The circuit for providing TF of (5.30) is plotted in Fig. 5.32. This
topology can be easily obtained by cascading two first-order HPFs given in
Fig. 5.30. Therefore, TF of (5.30) becomes as
100s2 - 10s - 10s - RR21 s - RR43 s

H ðsÞ = = × = × ð5:31Þ
s þ 107
2
s þ 107 s þ 107 s þ C11R1 s þ C21R3
From Eq. (5.31), the following equations are obtained:

R2
R1 R6
- R4
Vo1
Vin
C1 OA (1) -
+ A→f OA (2) Vout
+ A→f
C2
R3
- R5
Vo2
OA (3)
+ A→f
Fig. 5.33 A topology for providing a PID controller
R2 R4
= = 10 ð5:32aÞ
R1 R3
C1 R1 = C2 R3 = 10 - 7 ð5:32bÞ
If C1 = C2 = 100 pF are taken, R1 = R3 = 1 kΩ and R2 = R4 = 10 kΩ are found.

Example 5.21 Design a circuit for realizing the proportional integral derivative
(PID) controller. Further, TF of the PID controller is defined as
1
H ðsÞ = K p þ þ sT d ð5:33Þ
sT i
Here, Kp, Ti, and Td are, respectively, called as proportional, integral, and derivative
constants.
Solution 5.21 The OA-based PID controller is demonstrated in Fig. 5.33. Analysis
of this PID controller is achieved as follows: Firstly, Vo1 and Vo2 in Fig. 5.33 are,
respectively, evaluated as
1 V R
sC 1 þ V = - o1 ) V o1 = - 2 V in - sC 1 R2 V in ð5:34aÞ
R1 in R2 R1
V in V in
= - sC 2 V o2 ) V o2 = - ð5:34bÞ
R3 sC 2 R3
From equations in (5.34), Vout through Vo1 and Vo2 is computed as

R6 R
V out = - V - 6V ð5:35Þ
R4 o1 R5 o2
By replacing Vo1 and Vo2 into Eq. (5.35), Vout is calculated below.
R6 R2 R6 1 R
V out = þ þ sC 1 R2 6 V in
R4 R1 R5 sC 2 R3 R4
ð5:36Þ
1
= Kp þ þ sT d V in
sT i
The parameters, Kp, Ti, and Td are, respectively, found as follows:
R6 R2
Kp = ð5:37aÞ
R4 R1
C 2 R3 R5
Ti = ð5:37bÞ
R6
R6
T d = C 1 R2 ð5:37cÞ
R4
Fig. 5.34 A voltage divider Vout

circuit RS=100 k:
+_ Vs=10V RL=10 k:
Iout
+
RS=100 k:
OA Vout
+
_ Vs=10V
- A→f
Iout RL=10 k:
Fig. 5.35 An example for the use of the voltage follower

5.4 Some More Examples Based on the OA
Example 5.22 Find Iout and Vout of the topologies depicted in Figs. 5.34 and 5.35.
Solution 5.22 Iout and Vout of the circuit in Fig. 5.34 are, respectively, found as
10
I out = ffi 0:0909mA ð5:38aÞ
110k
10
V out = × 10 ffi 0:909V ð5:38bÞ
110
Iout and Vout of the circuit given in Fig. 5.35 are, respectively, evaluated below.
10
I out = = 1mA ð5:39aÞ
10k
V out = 10V ð5:39bÞ
Example 5.23 Design a circuit to obtain a current from the voltage.

Solution 5.23 This circuit is shown in Fig. 5.36. Analysis of this circuit, the
following current is obtained.
V in
I out = ð5:40Þ
R
Example 5.24 Design a circuit to obtain a voltage from the current.

Solution 5.24 This topology is depicted in Fig. 5.37. Analysis of this circuit, the
following voltage is obtained:
V out = - RI in ð5:41Þ
Fig. 5.36 The circuit of Vin +

Example 5.23
OA
- A→f
Iout R
5.4 Some More Examples Based on the OA 107
Fig. 5.37 The circuit of

Example 5.24 R
Iin -
OA Vout
+ A→f
Fig. 5.38 The circuit of

Example 5.25 R2
-
Iin OA Vout
R1
+
A→f RL
Fig. 5.39 The obtained

circuit by performing R2
source transformation
to Example 5.25
-
R1
R1Iin + OA Vout
_
+ A→f
RL
Example 5.25 Find output voltage of the circuit in Fig. 5.38 in terms of the applied
input current.
Solution 5.25 No current is passing through resistor R1 resulting in IR2 = Iin.
Therefore, output voltage is computed as
V out = - R2 I in ð5:42Þ
The second approach for solution of Example 5.25 is source transformation tech-
nique. Therefore, the structure in Fig. 5.38 is obtained as in Fig. 5.39, and the
following output voltage is found:
I in R1 V
= - out ) V out = - R2 I in ð5:43Þ
R1 R2
Example 5.26 Find output voltage of the circuit in Fig. 5.40 in terms of the applied
input current.
Fig. 5.40 The circuit of -

Example 5.26
Iin OA Vout
R1 +
A→f
Vtest
R3
I //
R2 I /
Solution 5.26 Vtest is firstly calculated as
0 - V test
I in = ) V test = - R1 I in ð5:44Þ
R1
The currents I/ and I// are, respectively, computed as follows:
0 - V test R
I= = = 1 I in ð5:45aÞ
R2 R2
R1
I == = I = þ I in = 1 þ I ð5:45bÞ
R2 in
From equations in (5.45), Vout is evaluated as
R1
V out = V test - I == R3 = - R1 I in - 1 þ I R
R2 in 3
ð5:46Þ
R R
= - R1 þ R3 þ 1 3 I in
R2
5.5 Finite Open Loop Gain of the OA
In practice, open loop gain A < 1. In other words, A takes values between
104 ≤ A ≤ 106 where value of A is taken as DC. Actually, A is frequency dependent
and decreases as the frequency rises. In this subsection, effect of the finite open loop
gain of the OA on the output of the inverting amplifier, non-inverting amplifier, and
voltage follower (VF) is investigated.
5.5 Finite Open Loop Gain of the OA 109
Fig. 5.41 An inverting

amplifier with a finite R2
R1
gain OA
Vin -
V-
OA Vout
+ A<f
Fig. 5.42 A non-inverting Vin +

amplifier with a finite
gain OA OA Vout
- A<f
V-
R2
R1
(a) An inverting amplifier with a finite gain OA is shown in Fig. 5.41. Analysis of
this amplifier is performed by the following two equations:
V in - V - V - V out
= - ð5:47aÞ
R1 R2
V out
ð0 - V - ÞA = V out ) V - = - ð5:47bÞ
A
If V- in Eq. (5.47b) is replaced into Eq. (5.47a), Vout is found as
R2 1
V out = - R V in ð5:48Þ
R1 1þR2
1þ A
1
(b) A non-inverting amplifier with a finite gain OA is shown in Fig. 5.42. Analysis
of this amplifier is accomplished by the following two equations:
V out - V - V
= - ð5:49aÞ
R2 R1
V out
V out = ðV in - V - ÞA ) V - = V in - ð5:49bÞ
A
If V- in Eq. (5.49b) is replaced into Eq. (5.49a), Vout is found as

Fig. 5.43 A VF with a Vin +

finite gain OA
OA Vout
- A<f
1 þ RR21
V out = R V in ð5:50Þ
1þR2
1þ A
1
(c) A VF with a finite gain OA is depicted in Fig. 5.43.

If the VF with a finite gain is analyzed, Vout is found below.
A
V out = ðV in - V out ÞA ) V out = V ð5:51Þ
1 þ A in
5.6 Practical Open Loop Gain OA
The finite open loop gain OA with a single pole model in s domain can be modeled by
A0
AðsÞ = ð5:52Þ
1 þ ωsb
Here, A0 is DC open loop gain, while ωb is -3 dB angular pole frequency. Also,

ωb = 2πfb, where fb is -3 dB pole frequency. The finite open loop gain with a single
pole model in the frequency domain can be modeled as follows:
A0
AðωÞ = ð5:53Þ
1 þ ωjωb
Example 5.27 Plot A( f ) versus frequency in which fb = 1 Hz and A0 = 106

Solution 5.27 A( f ) against frequency is drawn in Fig. 5.44 in which 20log
(A0) = 120 dB and 20log(A( f = fb = 1 Hz)) = 117 dB. At f = fb = 1 Hz, magnitude
of the open loop gain is -3 dB below.
Example 5.28 Analyze the inverting amplifier with a finite gain by replacing a
single pole model for A.
5.6 Practical Open Loop Gain OA 111
Fig. 5.44 Variation of the open loop gain with respect to frequency
Solution 5.28 Analysis of the inverting amplifier with a finite gain by replacing a
single pole model for A is performed below.
R2 1 R2 1
V out = - R V in = - V in ð5:54Þ
R1 1þR2 R1 R
1þ 1 1þR2 1þωs
1þ
A0 1 b
1þωs A0
b
From equation in (5.54), Vout is computed as
R2 1 R2 1
V out = - V in ffi - V ð5:55Þ
R1 1þR2
R
R1 1 þ A0sωb in
1þ A0
1
þ A0 ωb
s
R
1þ 2
R R1
1þ 2
R1
where (1 + R2/R1)/A0 << 1. Hence, it is ignored. Equation in (5.55) can be rewritten

as follows:
R2 1
V out ffi - s V in ð5:56Þ
R1 1 þ ω3dB
Here, ω3dB is closed loop gain angular pole frequency. Moreover, it is expressed by
A0 ωb
ω3dB = ð5:57Þ
1 þ RR21
Fig. 5.45 An inverting R2=1 MΩ

amplifier with a finite open
loop gain OA
R1=10 kΩ
Vin -
OA Vout
+ A0=105
Example 5.29 Analyze the non-inverting amplifier with a finite gain by replacing a
single pole model for A.
Solution 5.29 Analysis of the non-inverting amplifier with a finite gain by replacing
a single pole model for A is performed as
1 þ RR21 1 þ RR21
V out = V in ffi s V in ð5:58Þ
R
1þR2 1 þ ω3dB
1þ A0
1
1þωs
b
Example 5.30 Analyze of the VF with a finite gain by replacing a single pole model
for A.
Solution 5.30 Analysis of the VF with a finite gain by replacing a single pole model
for A is performed as
A0
1þωs A0 A0 1
V out = b
V in = V = V in
1 þ 1þA0 s 1 þ A0 þ ωsb in 1 þ A0 1 þ ωb ð1þA
s
0Þ
ωb
A0 1
= s V in ð5:59Þ
1 þ A0 1 þ ω3dB
In Eq. (5.59), ω3dB = (1 + A0)ωb.

Example 5.31 Find Vout/Vin for the circuit in Fig. 5.45, where A0 = 105 V/V.
Solution 5.31 Vout/Vin for the topology in Fig. 5.45 is approximately found below.
V out R 1 100 V
=- 2 =- ffi - 99:99 ð5:60Þ
1 þ 100000
R 101
V in R1 1þR2 V
1þ A0
1
Example 5.32 Find the value of R1 in the circuit of Fig. 5.46 in which R2 = 100 kΩ,
A0 = 105 V/V, and Vout/Vin = -100 V/V.
Solution 5.32 The value of R1 for the structure in Fig. 5.46 is evaluated by the
following equation:
Fig. 5.46 An inverting R2=100kΩ

loop gain OA
R1=?
Vin -
OA Vout
+ A0=105
Fig. 5.47 An inverting R2

loop gain
R1
- -
Vin
Vi OA Vout
+
+ A0=105
V out R 1 100k 1 V
=- 2 R =- 1þ100k
= - 100 ð5:61Þ
V in R1 1þR2 R1 V
1þ A
1 1þ R1
100000
From equation in (5.61), R1 is approximately calculated as
1000
1 þ100k
= 1 ) R1 ffi 998:99Ω ð5:62Þ
R1 þ R100000
Example 5.33 Find the range of Vi in Fig. 5.47, where A0 = 105 V/V and -
9 V ≤ Vout ≤ 9 V.
Solution 5.33 The range of Vi exhibited in Fig. 5.47 is found below.
- 9 ≤ V out ≤ 9 ) - 9 ≤ 105 × V i ≤ 9 ) - 90μV ≤ V i ≤ 90μV ð5:63Þ
Here, Vout = 105 Vi.

Example 5.34 Find input resistance of the inverting amplifier that has a finite open
loop gain.
Solution 5.34 In order to find input resistance of the inverting amplifier that has a
finite open loop gain, the OA model shown in Fig. 5.48 is given. Therefore, input
resistance is evaluated by
Rin = R1 þ Rp ð5:64Þ
where Rp is found below.

Iin R1 R2
Vin
Vout
+
Vi +
- Rp
-
-A0Vi
Rin
Fig. 5.48 Model of the inverting amplifier with a finite open loop gain
V i - ð- A0 V i Þ ð1 þ A0 ÞV i V R2
I in = = ) Rp = i = ð5:65Þ
R2 R2 I in 1 þ A0
From equations in (5.64) and (5.65), Rin is calculated as
R2
Rin = R1 þ ð5:66Þ
1 þ A0
Example 5.35 Find Rin in Fig. 5.48 if R1 = 1 kΩ, R2 = 100 kΩ, and A = 105 are
taken.
Solution 5.35 Rin in Fig. 5.48 is computed as follows:
R2
Rin = R1 þ
1 þ A0
ð5:67Þ
100kΩ
= 1kΩ þ ffi 1001Ω
1 þ 105
Example 5.36 Find output resistance of the non-inverting and inverting amplifiers
that have a finite open loop gain.
Solution 5.36 In order to find output resistance of the non-inverting and inverting
amplifiers that have a finite open loop gain, the OA model in Fig. 5.49 is given in
which the identical model is used. In other words, input is taken as zero for both
non-inverting and inverting amplifiers. Thus, output resistance is found below.
Rout = Ramp ==ðR1 þ R2 Þ ð5:68Þ
Here, Ramp is calculated as in the following:
V out
Ramp = ð5:69Þ
I amp
In Eq. (5.69), Vout is an auxiliary voltage, while Vin = -V/. Iamp and V/ are,
respectively, evaluated as
Ro Iamp Iout
Vout
+ +
Vin Rin→f -
A0Vin
- Ramp
R2 Rout
I=0A
/
V
R1
Fig. 5.49 Model for the non-inverting and inverting amplifiers with a finite open loop gain to find
output resistance
V out - A0 V in
I amp = ð5:70aÞ
Ro
R1
V= = V ð5:70bÞ
R1 þ R2 out
From equation in (5.70b), Vin is found as
R1
V in = - V ð5:71Þ
R1 þ R2 out
If Vin in Eq. (5.71) is replaced into equation in (5.70a), Iamp is calculated as
V out þ A0 R1RþR
1
V out
I amp = 2
ð5:72Þ
Ro
From equation in (5.72), Ramp is computed below.
V out Ro
Ramp = = ð5:73Þ
I amp 1 þ A0 R1RþR
1
2
Finally, Rout is found as follows:
Ro
Rout = ==ðR1 þ R2 Þ ð5:74Þ
1 þ A0 R1RþR
1
2
5.7 Expression of the Open Loop Gain in the Frequency

Domain
The open loop gain in the frequency domain can be expressed as
A0
AðωÞ = = jAðωÞjej∠AðωÞ ð5:75Þ
1 þ ωjωb
Here, phase and magnitude of the open loop gain are, respectively, defined by
ω
∠AðωÞ = - tan - 1 ð5:76aÞ
ωb
A0
jAðωÞj = ð5:76bÞ
1 þ ωω2
2
|A(ω)| in Eq. (5.75) can be expressed in three cases as given below.
ifω << ωb , AðωÞ = A0 ð5:77aÞ

A0 ωb
if ω >> ωb , AðωÞ = ð5:77bÞ
jω
A0
otherwise AðωÞ = ð5:77cÞ
1 þ ωjωb
If |A(ω)| is equal to unity or 0 dB, the angular frequency, ω = ωt = 2πft is found and
evaluated as follows:
A0 A0 A0 ωb
A ð ωÞ = jω ffi jω ) jAðω = ωt Þj ffi = 1 ) ωt = A0 ωb ð5:78Þ
1 þ ωb ωb ωt
ω = ωt
If a single pole model for A is used, TF of the inverting amplifier is found below.
V out R 1 R2 1 R 1
=- 2 ffi - =- 2 =
V in R1 R
1þR2 R1 1 þ ωbsA0 R1 1 þ s
ωt
1þ A0
1
R
1þ 2
R
1þ 2
R1
1þωs R1
b
R2 1
- ð5:79Þ
R1 1 þ ω3dB
s
where (1 + R2/R1)/A0 = 0. In Eq. (5.79), closed loop -3 dB angular pole frequency,

ω3dB, can be expressed as follows:
5.7 Expression of the Open Loop Gain in the Frequency Domain 117
ωt
ω3dB = ð5:80Þ
1 þ RR21
Note ω3dB is the same for the non-inverting amplifier as given for the inverting
amplifier in Eq. (5.80).
Example 5.37 Find the value of f3dB for the non-inverting and inverting amplifiers
if A0 = 5 × 105 R2/R1 = 20, and ft = 10 MHz.
Solution 5.37 f3dB is found as
ft 107
f 3dB = R2 = 1 þ 20 ffi 476:2kHz ð5:81Þ
1 þ R1
Example 5.38 Find the value of |Vout/Vin| for the non-inverting and inverting
amplifiers if A0 = 5 × 105 R2/R1 = 20, ft = 10 MHz, and f = 0.1 × f3dB = 47.62 kHz.
Solution 5.38 |Vout/Vin| for the non-inverting and inverting amplifiers is computed as
V out R 1 20 V out V
=- 2 =- ) ffi 19:9 ð5:82Þ
V in R1 1 þ jf
1þ jf V in V
ft
R
476:2 × 103
1þ 2
R1
Example 5.39 Find the value of |Vout / Vin| for the non-inverting and inverting
amplifiers if A0 = 5 × 105 R2/R1 = 20, ft = 10 MHz, and f = 10f3dB = 4762 kHz.
Solution 5.39 |Vout/Vin| for the non-inverting and inverting amplifiers is calculated by
V out R 1 20 V V
=- 2 =- ) out ffi 1:99 ð5:83Þ
V in R1 1 þ jf
ft 1 þ 476:2jf× 103 V in V
R
1þ 2
R1
Example 5.40 Find the value of |Vout/Vin| for the non-inverting and inverting
amplifiers if A0 = 5 × 105 R2/R1 = 20, ft = 10 MHz, and f = f3dB = 476.2 kHz.
Solution 5.40 |Vout/Vin| for the non-inverting and inverting amplifiers is evaluated
as follows:
V out R 1 20 V 20 V
=- 2 =- ) out ffi p ð5:84Þ
V in R1 1 þ jf
ft 1 þ 476:2jf× 103 V in 2 V
R
1þ 2
R1
Example 5.41 Find the value of fb for the non-inverting and inverting amplifiers if
A0 = 5 × 105, R2/R1 = 20, and ft = 10 MHz.
Solution 5.41 fb for the non-inverting and inverting amplifiers is found below.
ft 107
f t = A0 × f b ) f b = = = 20Hz ð5:85Þ
A0 5 × 105
Example 5.42 Find the value of A0 for the non-inverting and inverting amplifiers if
f3dB = 100 kHz, R2/R1 = 100, and fb = 10 Hz.
Solution 5.42 ft for the non-inverting and inverting amplifiers is found by
ft f
f 3dB = = 100kHz = t ) f t = 10MHz ð5:86Þ
1 þ RR21 100
Afterward, A0 is evaluated as follows:
ft f 107 V
fb = = 10Hz ) A0 = t = = 106 ð5:87Þ
A0 fb 10 V
Example 5.43 Find the value of |A( f = 1 kHz)|, fb, and ft for the non-inverting and
inverting amplifiers if A0 = 106 and |A( f = 10 kHz)| = 60 dB.
Solution 5.43 |A( f = 100 kHz)| = 40 dB, |A( f = 1 MHz)| = 20 dB, |A-
( f = ft = 10 MHz)| = 0 dB, |A( f = 1 kHz)| = 80 dB. Further, fb is computed as
ft 107
fb = = 6 = 10 Hz ð5:88Þ
A0 10
Note If f >> fb, A( f ) decreases -20 dB/decade as the frequency rises.
5.8 Gain Bandwidth Product
Gain bandwidth product (GBP) is defined as A0 × fb.

Example 5.44 Find fb, |A( f = fb)|, |A( f = 1 MHz)|, and GBP for the non-inverting
and inverting amplifiers if A0 = 120 dB and ft = 10 MHz.
Solution 5.44 fb is found below.
120 ft 107
A0 = 10 20 = 106 ) f b = = 6 = 10 Hz ð5:89Þ
A 10
5.8 Gain Bandwidth Product 119
(1) (2)
Vin amplifier amplifier Vout
Cutoff frequency =f3dB Cutoff frequency =f3dB
Fig. 5.50 Two cascaded identical amplifiers
|A( f = fb)| is computed by |A( f = fb)| = 120 - 3 = 117 dB. |A( f = 1 MHz)| is
calculated as
A0 f b 106 × 10
jAðf Þj ffi = = 10 = 20 dB ð5:90Þ
f 106
GBP is evaluated below.
GBP = A0 × f b = 106 × 10 = 107 ð5:91Þ
Example 5.45 Find f3dB,new for the non-inverting and inverting amplifiers if two
identical amplifiers are cascaded as depicted in Fig. 5.50. Each of these amplifiers
has a cutoff frequency of f3dB and a gain of K.
Solution 5.45 f3dB,new is found as
K2 K2 f 2 p p
2
= p ) 3dB,new
2
þ 1 = 2 ) f 3dB,new = f 3dB × 2-1
1 þ f jf 2 f 3dB
3dB f = f 3dB,new
ð5:92Þ
Example 5.46 Find f3dB,new for the non-inverting and inverting amplifiers if
n (n = 3, 4, 5, . . .) similar amplifiers are cascaded. Each of these amplifiers has a
cutoff frequency of f3dB and a gain of K.
Solution 5.46 f3dB,new is calculated by
n
Kn Kn f 23dB,new 2
p 1
n =p ) þ1 = 2 ) f 3dB,new = f 3dB × 2n - 1
1þf jf 2 f 23dB
3dB f = f 3dB,new
ð5:93Þ
Example 5.47 Find f3dB for the non-inverting and inverting amplifiers if 1 + R2/
R1 = 40 dB = 100 and ft = 10 MHz.
Solution 5.47 f3dB is evaluated as in the following:
ft 107
f 3dB = R2 = 100 = 100 kHz ð5:94Þ
1 þ R1
Example 5.48 Find f3dB,new for two identical cascaded non-inverting and inverting
amplifiers if each of these amplifiers has 1 + R2/R1 = 20 dB = 10 and ft = 10 MHz.
Solution 5.48 f3dB for each of the amplifiers is found below.
ft 107
f 3dB = R2 = 10 = 1 MHz ð5:95Þ
1 þ R1
By using equation in (5.93), f3dB,new is evaluated as
p
f 3dB,new = f 3dB 2 - 1 ffi 644 kHz ð5:96Þ
Note Contrary to a single OA-based cutoff frequency in (5.94) of the amplifier,

more than six times cutoff frequency is obtained, while gain is fixed. However, two
OAs and four resistors are employed. GBP is computed by
GBP = K × f 3dB ð5:97Þ
Here, K is gain, while f3dB is cutoff frequency.

Example 5.49 Find GBP for the non-inverting and inverting amplifiers.
Solution 5.49 GBP for the non-inverting and inverting amplifiers are, respectively,
calculated as follows:
ft
GBP = f 3dB × K = ×K =ft ð5:98aÞ
1 þ RR21
ft ft ×K
GBP = f 3dB × K = R2 × K = 1 þ K ð5:98bÞ
1 þ R1
Example 5.50 Find GBP for two identical cascaded non-inverting and inverting
amplifiers if each of these amplifiers has 1 + R2/R1 = 20 dB = 10 and ft = 10 MHz.
Solution 5.50 From results obtained in Example 5.45, GBP for two identical
cascaded non-inverting and inverting amplifiers are, respectively, computed as
GBP = f t = 10MHz ð5:99aÞ

5.9 DC Supply Voltage Restrictions 121
ft ×K 10MHz × 10
GBP = = ffi 9:09MHz ð5:99bÞ
1þK 1 þ 10
5.9 DC Supply Voltage Restrictions
In this subsection, Vr = ±9 V is taken for the OA. In other words, -9 V ≤ Vout ≤ 9 V.

Example 5.51 Find the range of Vin for the topology in Fig. 5.51.
Solution 5.51 V+ = V- is found below.
10
Vþ = V - = 5 × = 2:5 V ð5:100Þ
20
For the circuit in Fig. 5.51, the following equation is written
V in - 2:5 2:5 - V out

= ð5:101Þ
5 25
Vout in terms of Vin is evaluated as
V out
V in = 3 - ) V out = 15 - 5V in ð5:102Þ
5
From equation in (5.102), the range of Vin for the structure in Fig. 5.51 is computed by
- 9 ≤ V out ≤ 9 ) - 9 ≤ 15 - 5V in ≤ 9 ) 4:8 ≥ V in ≥ 1:2 ð5:103Þ
Fig. 5.51 An example for

the supply voltage R2=25 kΩ
R1=5 kΩ
restrictions Vin -
OA Vout
5V + A→∞
R3=10 kΩ
R4=10 kΩ
Fig. 5.52 Another example R2

for the supply voltage
restrictions
R1=2 k:
-
OA Vout
R3=15 k:
+ A→f
_
Vin=5 V R4=10 k:
+
It is seen from Eq. (5.103) that in this range of Vin, the OA operates in the linear
region. In other words, for Vin < 1.2 V (Vout = 9 V) or Vin > 4.8 V (Vout = -9 V), the
OA saturates.
Example 5.52 Find the range of R2 for the circuit in Fig. 5.52 such that OA operates
in linear region in which Vr = ±9 V.
Solution 5.52 V+ = V- is calculated by
10
Vþ = V - = - 5 × = - 2V ð5:104Þ
25
The range of Vout is computed as
- 9 V ≤ V out ≤ 9 V ð5:105Þ
From KVL, the following equation is obtained:
-5-V- V - V out -5 þ 2 - 2 - V out

= - ) = ð5:106Þ
R1 R2 2k R2
From Eq. (5.106), Vout is calculated as
3
V out = - 2 þ R ð5:107Þ
2k 2
From Eq. (5.107), the range of R2 is evaluated as follows:
3 22
-9≤ -2 þ R ≤ 9 ) R2 ≤ kΩ ð5:108Þ
2k 2 3
5.10 Simulated Grounded Inductors 123
5.10 Simulated Grounded Inductors
Simulated inductors (SIs), namely, synthetic inductors, can be mainly categorized

into two subgroups, grounded and floating ones. In addition, SIs can be divided into
two subsections, lossy and lossless ones. In this subsection, simulated grounded
inductors (SGIs) are investigated. SGIs behave like an inductor in a certain fre-
quency range.
5.10.1 Lossy SGIs
Example 5.53 Find the input impedance of the parallel lossy SGI depicted in
Fig. 5.53 [6].
Solution 5.53 Analysis of this circuit is accomplished below.
V in - V test V in
I in = þ ð5:109aÞ
R1 R2
V in V
= - sCV test ) V test = - in ð5:109bÞ
R2 sCR2
If Vtest in Eq. (5.109b) is replaced into Eq. (5.109a), Iin in terms of Vin is computed as
V in V in V in
I in = þ þ ð5:110Þ
R2 R1 sCR1 R2
From equation in (5.110), Zin = Vin/Iin is evaluated by
Fig. 5.53 A parallel

lossy SGI R1
C
Vtest
Iin
Vin -
R2
OA
+ A→f
Zin
Fig. 5.54 An equivalent Iin

circuit for the parallel lossy Vin
SGI in Fig. 5.53
Req Leq
Zin
R1
C
Vtest
Vin +
Iin
OA (1) -
R2
- OA (2)
A→f
Zin + A→f
Fig. 5.55 Another parallel lossy SGI
V in 1
Z in = = = sLeq ==Req ð5:111Þ
I in 1
R1 þ R12 þ sCR11 R2
Here, Leq = CR1R2 and Req = R1//R2. Equivalent circuit for the parallel lossy SGI is
given in Fig. 5.54.
Example 5.54 Find the input impedance of another parallel lossy SGI shown in
Fig. 5.55 [7].
Solution 5.54 Analysis of this circuit is achieved below.
V in - V test
I in = ð5:112aÞ
R1
V in V
= - V test sC ) V test = - in ð5:112bÞ
R2 sCR2
If Vtest in Eq. (5.112b) is replaced into Eq. (5.112a), Iin in terms of Vin is calculated by
V in V in
I in = þ ð5:113Þ
R1 sCR1 R2
From above equation, Zin = Vin/Iin is found as

Fig. 5.56 A series lossy

SGI
-
OA
Vin + A→f
Iin
C
R1
Vtest
Zin
R2
V in 1
Z in = = = sLeq ==Req ð5:114Þ
I in 1
R1 þ sCR11 R2
where Leq = CR1R2 and Req = R1.

Example 5.55 Find the input impedance of the series lossy SGI demonstrated in
Fig. 5.56 [8].
Solution 5.55 Analysis of this structure is accomplished as follows:
V in - V test
I in = ð5:115aÞ
R1
V in - V test V
þ ðV in - V test ÞsC = test ð5:115bÞ
R1 R2
Expansion of equation in (5.115b), the following equation is obtained:
V in V V
þ sCV in = test þ test þ sCV test ð5:116Þ
R1 R1 R2
From equation given in (5.116), Vtest is evaluated as
1
R1 þ sC
V test = V in ð5:117Þ
1
R1 þ R12 þ sC
If Vtest in Eq. (5.117) is replaced in Eq. (5.115a), Iin is found below.

Fig. 5.57 An equivalent Iin

circuit for the series lossy Vin
SGI
Req
Leq
R1 þsC R1 þR2 þsC - R1 - sC

1 1 1
V in - V in V in þ 1
V in
R1 R2 þsC
þ R1 R2 þsC
þ R1 þR2 þsC
1 1 1 1 1 1
I in = = ð5:118Þ
R1 R1
Simplification of equation in (5.118), the following equation is found:

1
R2
V in
R1 þR2 þsC
1 1
I in = ð5:119Þ
R1
Further simplification of equation in (5.119), the following equation is obtained:

1
× R2
R2
V in × 1
R1
R1 þR2 þsC × R2
1 1
I in = ð5:120Þ
R1 × 1
R1
From equation in (5.120), Zin is evaluated as follows:
V in
Z in = = R1 þ R2 þ sCR1 R2 = Req þ sLeq ð5:121Þ
I in
Here, Leq = CR1R2 and Req = R1 + R2. Further, an equivalent circuit for the series
lossy SGI is depicted in Fig. 5.57.
Example 5.56 Find the input impedance of another series lossy SGI shown in
Fig. 5.58 [7].
Solution 5.56 Analysis of this topology is carried out as in the following two
equations:
V in - V test
I in = ð5:122aÞ
R1
V test
ðV in - V test ÞsC = ð5:122bÞ
R2
Expansion of equation in (5.122b), the following equation is obtained:

-
OA (2)
Vin + A→f
Iin
C
R1
+ Vtest
Zin
OA (1)
- R2
A→f
Fig. 5.58 Another series lossy SGI
V test
sCV in = þ sCV test ð5:123Þ
R2
From above equation, Vtest is calculated as
sC
V test = V in ð5:124Þ
1
R2 þ sC
If Vtest in Eq. (5.124) is replaced into Eq. (5.122a), the following equation is found:
R2 þsC
1
- sC
V in - sC
V in V in þ V in
R2 þsC R2 þsC R2 þsC
1 1 1
I in = = ð5:125Þ
R1 R1
From equation given in (5.125), Iin is computed as

1
R2
V in
R2 þsC
1
I in = ð5:126Þ
R1
Simplifying equation in (5.126), Iin is obtained below.

1
× R2
R2
V in × 1
R1
R2 þsC × R2
1
I in = ð5:127Þ
R1 × 1
R1
From equation in (5.127), Zin is evaluated as

V in
Z in = = R1 þ sCR1 R2 = Req þ sLeq ð5:128Þ
I in
where Leq = CR1R2 and Req = R1.
5.10.2 Lossless SGIs
In this subsection, negative/positive lossless SGIs by example are treated.

Example 5.57 Find the input impedance of the negative lossless SGI depicted in
Fig. 5.59.
Solution 5.57 Analysis of this structure is achieved by the following two equations:
V in - V test
I in = ð5:129aÞ
R1
V in
ðV test - V in ÞsC = ð5:129bÞ
R2
Expansion of equation in (5.129b), the following equation is found:
V in
V in - V test = - ð5:130Þ
sCR2
If equation in (5.130) is replaced into equation in (5.129a), the following input

impedance is evaluated:
Fig. 5.59 A negative R1

lossless SGI
Vin +
Iin
OA Vtest
- A→f
Zin
C
R2
A→f
(1)
OA
-
+
Iin R1 R4 R2 V2 C
Vin
V1
R3
-
+
OA
Zin (2)
A→f
Fig. 5.60 A positive lossless SGI
V in
Z in = = - sCR1 R2 = - sLeq ð5:131Þ
I in
Here, Leq = CR1R2.

Example 5.58 Find the input impedance of the positive lossless SGI given in
Fig. 5.60 [9].
Solution 5.58 Analysis of this circuit is achieved by the following three equations:
V in - V 1
I in = ð5:132aÞ
R1
V 1 - V in V in - V 2
= ð5:132bÞ
R4 R2
V in
ðV 2 - V in ÞsC = ð5:132cÞ
R3
From equations in (5.132), Zin is calculated by
V in sCR1 R2 R3
Z in = = = sLeq ð5:133Þ
I in R4
Here, Leq = CR1R2R3/R4.

Example 5.59 Find the input impedance of another positive lossless SGI demon-
strated in Fig. 5.61 [10].
R1
V2
C1
R2
Vin +
-
V1
Iin OA (2)
OA (1)
V1
+ A→f
- A→f
C2
R3
Zin
Fig. 5.61 Another positive lossless SGI
Solution 5.59 This structure is analyzed by the following three equations:
V in - V 2
I in = ð5:134aÞ
R1
V in - V 1
= ðV 1 - V 2 ÞsC 1 ð5:134bÞ
R2
V1
ðV in - V 1 ÞsC 2 = ð5:134cÞ
R3
From equations given in (5.134), Zin is computed as follows:
V in sC 1 R1 R2 ð1 þ sC2 R3 Þ
Z in = = ð5:135Þ
I in 1 þ sC 1 R2
If the following matching condition is met:
C 2 R3 = C 1 R2 ð5:136Þ
Input impedance of this SGI becomes as
V in
Z in = = sC 1 R1 R2 = sLeq ð5:137Þ
I in
In above equation, Leq = C1R1R2.

Example 5.60 Find the input impedance of the single OA-based positive lossless
SGI shown in Fig. 5.62 [11].
Fig. 5.62 A single

OA-based positive R6
lossless SGI.
V2
V3
R5
C
R4
R3
Vin -
Iin V1
OA
R1 V1
+ A→f
Zin R2
Solution 5.60 This circuit is analyzed by the following four equations:
V in - V 1 V in - V 1 V in - V 3
I in = þ þ ð5:138aÞ
R3 R1 R6
V in - V 1
= ðV 1 - V 2 ÞsC ð5:138bÞ
R3
V2 - V3 V2
ðV 1 - V 2 ÞsC = þ ð5:138cÞ
R5 R4
V in - V 1 V 1
= ð5:138dÞ
R1 R2
From equations indicated in (5.138), Zin is found below.
V in
Z in =
I in
sC ðR1 þ R2 ÞR3 R4 R6
=
R1 ðR4 þ R5 Þ þ sC ðR1 R3 R4 þ R1 R4 R5 þ R1 R4 R6 þ R3 R4 R6 - R2 R3 R5 Þ
ð5:139Þ
In above equation, if the following matching constraint is met,
R1 R3 R4 þ R1 R4 R5 þ R1 R4 R6 þ R3 R4 R6 = R2 R3 R5 ð5:140Þ
Zin simplifies as
V in sC ðR1 þ R2 ÞR3 R4 R6
Z in = = = sLeq ð5:141Þ
I in R1 ðR4 þ R5 Þ
Note Mathematical programs should be used in calculation of the input impedances

of the SGIs in Figs. 5.60, 5.61, and 5.62.
5.11 Rectifiers
Rectifiers can be divided into two subgroups, half-wave rectifiers (HWRs) and full-
wave rectifiers (FWRs).
Example 5.61 Find the output voltage of the simple single OA-based HWR given
in Fig. 5.63 [4].
Solution 5.61 This HWR is analyzed as follows:
If vin ðt Þ ≥ 0 is taken, diode is ON ) vout ðt Þ = vin ðt Þ ð5:142aÞ

If vin ðt Þ < 0 is taken, diode is OFF ) vout ðt Þ = 0 ð5:142bÞ
A drawback of this circuit is that the OA is in saturation when vin(t) < 0 and OA can
be destroyed if the magnitude of the input voltage is larger than a few volts. Vin-Vout
characteristics of the HWR of Fig. 5.63 are depicted in Fig. 5.64.
Example 5.62 Find the output voltage of another single OA-based HWR shown in
Fig. 5.65.
Fig. 5.63 A single vin(t) +

OA-based HWR D
OA vout(t)
- A→f
RL
Fig. 5.64 Vin-Vout Vout

characteristics of the HWR
in Fig. 5.63
1
Vin
5.11 Rectifiers 133
Fig. 5.65 Another single R1 R2

OA-based HWR vin(t) vout(t)
D2
D1
-
OA
+ A→f
Fig. 5.66 Vin-Vout

characteristics of the HWR Vout
in Fig. 5.65
R2
–
R1
Vin
Solution 5.62 This HWR is analyzed below.
If vin ðt Þ ≥ 0 is taken, D1 is ON and D2 is OFF ) vout ðt Þ = 0 ð5:143aÞ

R2
If vin ðt Þ < 0 is taken, D1 is OFF and D2 is ON ) vout ðt Þ = - v ðt Þ ð5:143bÞ
R1 in
Vin-Vout characteristics of the HWR in Fig. 5.65 are demonstrated in Fig. 5.66.
Example 5.63 Find the output voltage of the OA-based FWR shown in
Fig. 5.67 [4].
Solution 5.63 This circuit for R2 = R1 is analyzed as in the following:
If vin ðt Þ ≥ 0 is chosen D1 is ON and D2 is OFF ) vout ðt Þ = vin ðt Þ ð5:144aÞ

If vin ðt Þ < 0 is chosen D1 is OFF and D2 is ON ) vout ðt Þ = - vin ðt Þ ð5:144bÞ
From equations denoted in (5.144), vout(t) is evaluated as
vout ðt Þ = jvin ðt Þj ð5:145Þ
Vin-Vout characteristics of the FWR in Fig. 5.67 are shown in Fig. 5.68.
Example 5.64 Find the output voltage of another OA-based FWR depicted in
Fig. 5.69 [12].
-
OA (1)
D1
vin(t) + A→f
vout(t)
R1 R2
-
OA (2)
D2
+ A→f
Fig. 5.67 An OA-based FWR
Fig. 5.68 Vin-Vout

Vout
characteristics of the FWR
in Fig. 5.67
1
-1
Vin
R R Vo R/2 aR
vin(t)
D2
-
D1
- OA (2) vout(t)
OA (1)
+ A→f
+ A→f
Fig. 5.69 Another OA-based FWR

5.12 Wien Oscillators 135
Fig. 5.70 Vin-Vout Vout

characteristics of the FWR
in Fig. 5.69 a
-a
Vin
Fig. 5.71 A Wien oscillator R4
-
OA Vout
R1
+ A→f
C1
R3
R2 C2
Solution 5.64 This structure with four resistive matching condition is analyzed as
If vin ðtÞ ≥ 0 is taken, D1 is OFF and D2 is ON

ð5:146aÞ
) vout ðtÞ = - ðaR=RÞðvin ðtÞÞ - aRðR=2Þð - vin ðtÞÞ = avin ðtÞ
If vin ðtÞ < 0 is taken, D1 is ON and D2 is OFF
ð5:146bÞ
) vout ðt Þ = - ðaR=RÞðvin ðt ÞÞ - 0 = - avin ðt Þ
Therefore, vout(t) is calculated as
vout ðt Þ = ajvin ðt Þj ð5:147Þ
Vin-Vout characteristics of the FWR in Fig. 5.69 are depicted in Fig. 5.70.
5.12 Wien Oscillators
Wien oscillators provide only one sinusoidal output.

Example 5.65 Find the characteristic eq. (D(s)), oscillation condition (OC), and
oscillation frequency (OF) of the Wien oscillator demonstrated in Fig. 5.71 [13].
Solution 5.65 Its analysis is carried out by the following three equations:
V - = Vþ ð5:148aÞ
V out - V - V-
= ð5:148bÞ
R4 R1 þ sC1 1
V out - V þ 1
= V þ sC 2 þ ð5:148cÞ
R3 R2
By using equations in (5.148a) and (5.148b), Vout in terms of V+ is found as
R4 R4 þ R1 þ sC1 1
V out = V þ þ V þ = Vþ ð5:149Þ
R1 þ sC1 1 R1 þ sC1 1
If both numerator and denominator are multiplied by sC1, Vout becomes as
R1 þ R4 sC 1 þ 1
V out = Vþ ð5:150Þ
sC 1 R1 þ 1
If equation in (5.148c) is rearranged, Vout by means of V+ is found as follows:
R3
V out = V þ sC 2 R3 þ þ1 ð5:151Þ
R2
Equation given in (5.150) equal to equation in (5.151); thus, the following equation
is obtained:
R3 R þ R4 sC 1 þ 1
V out = V þ sC 2 R3 þ þ 1 = Vþ 1 ð5:152Þ
R2 sC 1 R1 þ 1
From equation in (5.152), the following equation is obtained:
R
sC 2 R3 þ R32 þ 1 R þ R4 sC 1 þ 1
= 1 ð5:153Þ
1 sC1 R1 þ 1
Similarly, from equation in (5.153), the following equation is obtained:
R3
sC 2 R3 þ þ1 sC1 R1 þ 1 = R1 þ R4 sC 1 þ 1 ð5:154Þ
R2
Expansion of equation in (5.154), the following equation is found:

5.12 Wien Oscillators 137
Fig. 5.72 Another Wien R1

oscillator
-
OA Vout
R2
+ A→f
R3 C1
R4 C2
R3 R3
s2 C 1 C 2 R 1 R 3 þ s C 1 R 1 þ C2 R3 - C1 R4 þ =0 ð5:155Þ
R2 R2
If both sides of equation in (5.155) are multiplied by R2/R3, the following D(s) is
obtained:
R2 R4
DðsÞ = s2 C1 C2 R1 R2 þ s C 1 R1 þ C 2 R2 - C 1 þ 1=0 ð5:156Þ
R3
From equation given in (5.156), the following OC and OF are, respectively, obtained
as
R2 R4
C1 ≥ C1 R1 þ C 2 R2 ð5:157aÞ
R3
1 1
f0 = ð5:157bÞ
2π C 1 C 2 R1 R2
Example 5.66 Find D(s), OC, and OF of another Wien oscillator shown in
Fig. 5.72 [4].
Solution 5.66 Analysis of this topology is achieved by the following two equations:
R2
V - = Vþ = V ð5:158aÞ
R1 þ R2 out
V out - R2
R1 þR2 V out R2 1
= V sC 2 þ ð5:158bÞ
R3 þ sC1 1 R1 þ R2 out R4
From equation in (5.158b), D(s) is evaluated as

C 1 R1 R4
DðsÞ = s2 C1 C2 R3 R4 þ s C 1 R3 þ C 2 R4 - þ 1=0 ð5:159Þ
R2
From equations given in (5.159), OC and OF are, respectively, computed below.
C 1 R1 R4
≥ C 1 R3 þ C2 R4 ð5:160aÞ
R2
1 1
f0 = ð5:160bÞ
2π C 1 C 2 R3 R4
5.13 Analog Filters
Analog filters can be mainly divided into three subcategories, first-order filters,
second-order filters, and high-order filters. In this subsection, it is dealt with first-
order and second-order ones.
Example 5.67 Find the first-order all-pass filter (APF) depicted in Fig. 5.73 [14].
Solution 5.67 This filter is analyzed as follows:
1
V - = Vþ = V ð5:161aÞ
1 þ sCR in
V in - 1
1þsCR V in
1
1þsCR V in - V out
= ð5:161bÞ
R1 R2
From above equations, TF is computed by
Fig. 5.73 A first-order APF R2
R1
-
Vin OA Vout
+ A→f
R
C
5.13 Analog Filters 139
C1
R1
Vin +
Vtest R2
OA (1) +
OA (2) Vout
- A→f
C2
- A→f
Fig. 5.74 A second-order LPF
V out 1 - sCR RR21

H ðsÞ = = ð5:162Þ
V in 1 þ sCR
If R2 = R1 is taken for equation in (5.162), TF of this filter becomes below.
V out 1 - sCR
H ðsÞ = = ð5:163Þ
V in 1 þ sCR
Example 5.68 Find the TF of the second-order LPF exhibited in Fig. 5.74 [15].
Solution 5.68 Analysis of this circuit is achieved by the following two equations:
V in - V test
= ðV test - V out ÞsC1 ð5:164aÞ
R1
V test - V out
= V out sC 2 ) V test = V out ð1 þ sC 2 R2 Þ ð5:164bÞ
R2
From above equations, TF is evaluated as
1
V out C 1 C 2 R1 R2 ω20
H ðsÞ = = 2 = 2 ð5:165Þ
V in s þ s C1 R1 þ C1 C2 R1 R2 s þ s ωQ0 þ ω20
1 1
where angular resonance frequency (ω0) and quality factor (Q) are, respectively,
found as
1 1
ω20 = ) ω0 = ð5:166aÞ
C 1 C 2 R1 R2 C 1 C 2 R1 R2
ω0 1 C1 R1
= ) Q= ð5:166bÞ
Q C 1 R1 C2 R2
Example 5.69 Find the TF of the multiple feedback second-order LPF demon-
strated in Fig. 5.75.
R2 C1
R1 R3
Vin
Vtest
-
OA Vout
C2
+ A→f
Fig. 5.75 A multiple feedback second-order LPF
Solution 5.69 Analysis of this circuit is achieved by the following two equations:
V in - V test V - V out V test

= test þ þ V test sC 2 ð5:167aÞ
R1 R2 R3
V test
= - V out sC 1 ) V test = - V out sC 1 R3 ð5:167bÞ
R3
From equations in (5.167), the following TF is computed:
V out R 1
H ðsÞ = =- 2 ð5:168Þ
V in R1 s2 C C R R þ sC R þ R þ R2 R3 þ 1
1 2 2 3 1 2 3 R1
Here, ω0 and Q are, respectively, evaluated as
1 1
ω20 = ) ω0 = ð5:169aÞ
C 1 C 2 R2 R3 C 1 C 2 R2 R3
ω0 R2 þ R3 þ R1
R2 R3
1 C 2 R2 R3
= ) Q= ð5:169bÞ
Q C 2 R2 R3 R2 þ R3 þ RR2 R1 3 C1
Example 5.70 Find the TF of the second-order LPF demonstrated in Fig. 5.76 [16].
Solution 5.70 This LPF is analyzed by the following two equations:
V in - V test V - V out
= ðV test - V out ÞsC 1 þ test ð5:170aÞ
R1 R2
V test - V out
= V out sC 2 ) V test = V out ð1 þ sC2 R2 Þ ð5:170bÞ
R2
From above equations, the following TF is obtained:

C1
R1 R2
Vin +
Vtest
OA Vout
C2
- A→f
Fig. 5.76 A second-order LPF
R2
R1 C1
Vin +
Vtest
OA Vout
C2 R3
- A→f
Fig. 5.77 A Sallen-Key second-order BPF
V out 1
H ðsÞ = = 2 ð5:171Þ
V in s C 1 C 2 R1 R2 þ sC 2 ðR1 þ R2 Þ þ 1
where ω0 and Q are, respectively, found as follows:
1 1
ω20 = ) ω0 = ð5:172aÞ
C 1 C 2 R1 R2 C 1 C 2 R1 R2
ω0 R1 þ R2 1 C 1 R1 R2
= ) Q= ð5:172bÞ
Q C 1 R1 R2 R1 þ R2 C2
Note If RC-CR transformations are performed for the LPFs in Figs. 5.74, 5.75, and
5.76, HPFs are obtained.
Example 5.71 Find the TF of the Sallen-Key second-order band-pass filter (BPF)
shown in Fig. 5.77.
C1 R2
R1 C2
Vin -
Vtest
OA Vout
R3 + A→f
Fig. 5.78 A multiple feedback second-order BPF
Solution 5.71 Analysis of this topology is carried by the following two equations:
V in - V test V - V out
= test þ ðV test - V out ÞsC 1 þ V test sC 2 ð5:173aÞ
R1 R2
V out 1
ðV test - V out ÞsC1 = ) V test = V out 1 þ ð5:173bÞ
R3 sC1 R3
From above equations, the following TF is calculated:
V out sC 1 R2 R3
H ðsÞ = = 2
V in s C1 C2 R1 R2 R3 þ sðC 1 R1 R2 þ C2 R1 R2 þ C 1 R2 R3 Þ þ R1 þ R2
ð5:174Þ
From equation in (5.174), ω0 and Q are, respectively, computed as
R1 þ R2 R1 þ R2
ω20 = ) ω0 = ð5:175aÞ
C 1 C 2 R1 R2 R3 C 1 C 2 R1 R2 R3
ω0 C1 R1 R2 þ C 2 R1 R2 þ C1 R2 R3 ðR1 þ R2 ÞC1 C 2 R1 R2 R3
= ) Q= ð5:175bÞ
Q C1 C2 R1 R2 R3 C1 R1 R2 þ C 2 R1 R2 þ C1 R2 R3
Example 5.72 Find the TF of the multiple feedback second-order BPF depicted in
Fig. 5.78.
Solution 5.72 Analysis of this circuit is accomplished by the following two
equations:
V in - V test V
= ðV test - V out ÞsC 1 þ V test sC 2 þ test ð5:176aÞ
R1 R3
C1 R2
R1 C2
Vin -
Vtest
OA Vout
+ A→f
Fig. 5.79 Deliyannis second-order BPF
V out V
V test sC 2 = - ) V test = - out ð5:176bÞ
R2 sC 2 R2
From above equations, the following TF is found:
V out sC2 R2 R3
H ðsÞ = =- 2 ð5:177Þ
V in s C 1 C 2 R1 R2 R3 þ sðC1 þ C2 ÞR1 R3 þ R1 þ R3
Here, ω0 and Q are, respectively, found below.
R1 þ R3 R1 þ R3
ω20 = ) ω0 = ð5:178aÞ
C 1 C 2 R1 R2 R3 C 1 C 2 R1 R2 R3
ω0 C 1 þ C 2 1 ðR1 þ R3 ÞC 1 C 2 R2
= ) Q= ð5:178bÞ
Q C1 C2 R2 C1 þ C2 R1 R3
Example 5.73 Find the TF of the Deliyannis second-order BPF demonstrated in

Fig. 5.79.
Solution 5.73 Analysis of this structure is achieved by the following two equations:
V in - V test
= ðV test - V out ÞsC1 þ V test sC 2 ð5:179aÞ
R1
V out V
V test sC 2 = - ) V test = - out ð5:179bÞ
R2 sC 2 R2
From above equations, the following TF is evaluated:
V out sC 2 R2
H ðsÞ = =- 2 ð5:180Þ
V in s C 1 C 2 R1 R2 þ sðC 1 þ C 2 ÞR1 þ 1
where ω0 and Q are, respectively, found by

1 1
ω20 = ) ω0 = ð5:181aÞ
C 1 C 2 R1 R2 C 1 C 2 R1 R2
ω0 C 1 þ C 2 1 C 1 C 2 R2
= ) Q= ð5:181bÞ
Q C 1 C 2 R2 C1 þ C2 R1
5.14 Large Signal Operation in the OA
If LM318/NS type OA is supplied with ±12 V, output voltage (Vout) of this OA is

generally less than 9 V and greater than -9 V. In other words, Vout is restricted with
±9 V. These restricted voltages are called as rated voltages that are defined below.
V rþ ffi 9 V < V CC ð5:182aÞ
V r - ffi - 9 V > V EE ð5:182bÞ
Output current (Iout) of any OA cannot exceed Iout,max. For example, LM318/NS
type OA has Iout,max ffi 21 mA. Iout, for LM318/NS OA is found as
jI out j ≤ I out, max ffi 21 mA ð5:183Þ
Example 5.74 Find vout(t) and iout(t) in Fig. 5.80 if Vr ffi ±9 V and vin(t) = (1 V)sin
(ωt) are taken.
Fig. 5.80 A non-inverting VCC

amplifier with a load
vin(t) +
iout(t)
OA vout(t)
-
VEE
R2=10 k:
R1=2 k: RL=0.5 k:
5.15 SR 145
Solution 5.74 vout(t) and iout(t) are, respectively, computed as
10
vout ðt Þ = 1 þ sinðωt Þ = 6 sinðωt Þ ð5:184aÞ
2
6 6
iout ðtÞ = þ sin ðωtÞ = 12:5ðmAÞsinðωtÞ ð5:184bÞ
12k 0:5k
Example 5.75 Find vout(t) in Fig. 5.80 if Vr ffi ±9 V and vin(t) = (2 V)sin(ωt) are
chosen.
Solution 5.75 vout(t) is calculated by
10
vout ðtÞ = 1 þ × 2sin ðωtÞ = 12sin ðωtÞ ð5:185Þ
2
However, in Eq. (5.185), vout(t) is limited at about ±9 V as shown in Fig. 5.81. iout(t)
of Example 5.75 is drawn in Fig. 5.81. In addition, f = 10 kHz is taken, where
LM318/NS OA model is used.
5.15 SR
SR is a nonlinear distortion [4]. SR occurs at high frequencies and is defined as

follows:
dvout ðtÞ
SR = ð5:186Þ
dt max
Unit of the SR is V/μs. In order to express SR, an input voltage depicted in Fig. 5.82
(a pulse) is applied to the VF in Fig. 5.83, where VI is sufficiently high. SR is found
from slope of vout(t) in Fig. 5.82.
Example 5.76 Find vout(t), if vin(t) = VIu(t) is applied to the input of the VF shown
in Fig. 5.83 and VI is sufficiently small (ωtVI ≤ SR).
Solution 5.76 vout(t) is evaluated as follows [3, 4]: From equation given in (5.59),
output voltage, vout(t) of the VF of Fig. 5.83 in s domain is found as
A0 1 1
V out ðsÞ = V in ðsÞ ffi s V in ðsÞ ð5:187Þ
1 þ A0 1 þ ωb ð1þA
s
0 Þ 1 þ ωt
Input voltage, vin(t) in s domain is calculated by

Fig. 5.81 vin(t), vout(t), and iout(t) of Example 5.75
VI
V in ðsÞ = ð5:188Þ
s
From equations denoted in (5.187) and (5.188), vout(t) of the VF of Fig. 5.83 in
s domain is found as follows:
5.15 SR 147
Fig. 5.82 Input and output vin(t) vout(t)

voltages of the VF
VI
-SR
SR
Fig. 5.83 A VF given to vin (t) +

test SR
OA vout (t)
1 V V VI
V out ðsÞ = × I = I - ð5:189Þ
1 þ ωst s s s þ ωt
From above equation, vout(t) of the VF of Fig. 5.83 is computed as
vout ðt Þ = V I ð1 - e - tωt Þ ð5:190Þ
Here, ωt = 2πft is calculated in Eq. (5.78). tr, namely, rise time, is defined as the time
of vout(t) to reach from 10% to 90%. Furthermore, tr is computed by
1
tr = lnð9Þ ð5:191Þ
ωt
Above equation is obtained as follows:
1 1
0:1 × V I = V I ð1 - e - t1 ωt Þ ) t 1 = ln ð5:192aÞ
ωt 0:9
1
0:9 × V I = V I ð1 - e - t2 ωt Þ ) t 2 = lnð10Þ ð5:192bÞ
ωt
1 1
tr = t2 - t1 = lnð10 × 0:9Þ = lnð9Þ ð5:192cÞ
ωt ωt
Otherwise, for ωtVI > SR, tr is calculated as below.
VI V
tr = × ð0:9 - 0:1Þ = I × 0:8 ð5:193Þ
SR SR
In Fig. 5.84, input and output voltages of the VF at various frequencies are given in
which input voltage is taken as 5 V peak, and the LM318/NS OA model is utilized.
Fig. 5.84 Input and output voltages of the VF at various frequencies
Example 5.77 Find tr if the VF has SR = 107 V/s, ft = 10 MHz, and Vin(t) = 100
(mV)u(t).
Solution 5.77 Firstly, the following condition is checked.
ωt V I = 2π × 107 × 0:1 ffi 6:28 × 106 ≤ SR = 107 ð5:194Þ
From equation in (5.192c), tr is found by
1 1
tr = lnð9Þ = lnð9Þ ffi 35 ns ð5:195Þ
ωt 2π × 107
Example 5.78 Find tr if the VF has SR = 107 V/s, ft = 10 MHz, and VI = Vin(t) = 1
(V)u(t).
Solution 5.78 Firstly, the following condition is checked.
ωt V I = 2π × 107 × 1 ffi 6:28 × 107 > SR = 107 ð5:196Þ
From equation given in (5.193), tr is found as given below.
VI 1
tr = × 0:8 = 7 × 0:8 = 80 ns ð5:197Þ
SR 10
5.16 Full-Power Bandwidth 149
5.16 Full-Power Bandwidth
Full-power bandwidth ( fM) is defined as the maximum frequency, where the OA

provides an undesired AC output with the largest amplitude. Hence, fM for the VF
can be expressed as in the following [3, 4]:
1 SR
fM = ð5:198Þ
2π V out, max
where Vout,max = min{Vr+, |Vr-|}. Operating frequency of any OA is given as [3, 4].
V out, max
f ≤fM ð5:199Þ
V out
where Vout ≤ Vout,max.

Example 5.79 Find fM if the VF has SR = 107 V/s and Vout,max = 9 V, i.e., Vr+ = -
Vr- = 9 V.
Solution 5.79 fM is calculated below.
1 SR 107
fM = = ffi 176:84 kHz ð5:200Þ
2π V out, max 2π × 9
Example 5.80 Find the operating frequency if the VF has SR = 107 V/s, Vout,
max = 9 V, Vout = 2 V, and fM ffi 176.84 kHz, i.e., Vr+ = -Vr- = 9 V.
Solution 5.80 The operating frequency of the VF is evaluated as
V out, max 9
f ≤fM ffi 176:84 kHz ) f ≤ 795:77 kHz ð5:201Þ
V out 2
Example 5.81 Find SR and fM if the VF has Vout,max = 9 V, Vout = 5 V, and

f ffi 1 MHz. In other words, Vr+ = -Vr- = 9 V.
Solution 5.81 SR and fM are, respectively, found by
SR = 2πf M V out, max = 2πfV out ) SR = 2π × 106 × 5 ffi 3:14 × 107 V=s ð5:202aÞ
SR π × 107
fM = = ffi 555:56 kHz ð5:202bÞ
2πV out, max 2π × 9
Example 5.82 Find f3dB and fM if the non-inverting amplifier has Vout,max = 9 V,
SR = 107 V/s, ft = 10 MHz, and 1 + R2/R1 = 100, i.e., Vr+ = -Vr- = 9 V.
Solution 5.82 f3dB and fM are, respectively, evaluated below.
ft 10 MHz
f 3dB = = = 100 kHz ð5:203aÞ
1 þ RR21 100
SR 107
fM = = ffi 176:84 kHz ð5:203bÞ
2πV out, max 2π × 9
It is understood from above that if f ≤ fM is taken, Vout ≤ Vout,max. Also, Vin,

max = 9 V/100 = 90 mV.
References
1. J.A. Svoboda, R.C. Dorf, Dorf’s Introduction to Electric Circuits, Global edition. (Wiley,
2018)
2. J.W. Nilsson, S. Riedel, Electric Circuits: Global Edition, 11th ed. (Pearson, 2018)
3. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, 3rd ed.
5. K. Ogata, Modern Control Engineering, 5th edn. (Prentice Hall, Boston [etc.], 2010) ISBN-13:
9780136156734
6. R. Ford, F.E.J. Girling, Active filters and oscillators using simulated inductance. Electron. Lett.
2(2), 52 (1966)
7. K.R. Rao, S. Venkateswaran, Synthesis of inductors and gyrators with voltage-controlled
voltage sources. Electron. Lett. 6(2), 29–30 (1970)
8. A.J. Prescott, Loss-compensated active gyrator using differential-input operational amplifiers.
Electron. Lett. 7(2), 283–284 (1966)
9. http://www.chuacircuits.com/PDFs/AntoniouInductance-Simulation Circuit.pdf
10. B. Maundy, S.J. Gift, Active grounded inductor circuit. Int. J. Electron. 98(5), 555–567 (2011)
11. H.J. Orchard, A.N. Willson, New active-gyrator circuit. Electron. Lett. 13(10), 261–262 (1974)
12. P. Horowitz, W. Hill, The Art of Electronics, 2nd edn. (Cambridge University Press, Cam-
bridge, 1989) ISBN 0-521-37095-7
13. N. Boutin, Two new single op-amp RC bridge-T oscillator circuits. IEE Proc. G (Electron.
Circuit Syst.) 130(5), 222–224 (1983)
14. R. Genin, Realization of an all-pass transfer function using operational amplifiers. Proc. IEEE
56, 1746–1747 (1968)
15. R.E. Bach, Selecting RC values for active filters. Electronics 33, 82–85 (1960)
16. R.P. Sallen, E.L. Key, A practical method of designing RC active filters. IRE Trans. Circuit
Theory 2(1), 74–85 (1955)
Chapter 6
Unity Gain Cells
6.1 Unity Gain Cells
Unity gain cells (UGCs), namely, current followers (CFs) and voltage followers
(VFs), are main analog devices. They have been found wide application areas in the
open literature [1–12].
6.2 CFs and Their Practices
CFs can be divided into four categories, plus-type single output CF (CF+), minus-
type single output current follower (CF-), dual output CF (DO-CF), and multiple
output CF (MO-CF). CF+ and CF- have two terminals, while DO-CF has three
terminals. Also, DO-CF has both Z+ and Z- terminals. MO-CF has at least four
terminals. Ideal model of the CF+ is given in Fig. 6.1, while the symbols of the CF+
are depicted in Fig. 6.2. The CF+ can be expressed with the following matrix
equation:
I Zþ α
= ½I X ð6:1Þ
VX 0
Here, α is frequency-dependent nonideal gain and ideally equal to unity. Input and
output impedances of the CF+ are ideally equal to zero and infinity, respectively.
Therefore, the CF+ is suitable for current-mode (CM) circuits.
Similarly, ideal model of the CF- is shown in Fig. 6.3, while the symbols of the
CF- are demonstrated in Fig. 6.4. The CF- can be defined by the following matrix
equation:
https://doi.org/10.1007/978-3-031-44966-6_6
152 6 Unity Gain Cells
Fig. 6.1 Ideal model of the

CF+
VX CF+ VZ+
IX α IX IZ+
Fig. 6.2 The symbols of the

CF+ VX X CF Z+ VZ+
IX IZ+
(a)
VX X CF+ Z VZ+
IX IZ+
(b)

CF- VX CF- VZ-
IX γI X IZ-
Fig. 6.4 The symbols of the

CF- VX X CF Z- VZ-
IX IZ-
(a)
VX X CF- Z VZ-
IX IZ-
(b)
I Zþ -γ
= ½I X ð6:2Þ
VX 0
where γ is frequency-dependent nonideal gain and ideally equal to unity.

Note CF- has all the properties of the CF+ except current direction of the
Z terminal.
6.2 CFs and Their Practices 153
Fig. 6.5 A simple VM

circuit based on the CF+ Vin X CF+ Z Vout
Z1
Z2
Fig. 6.6 A simple VM

topology based on the CF- Vin X CF- Z Vout
Z1
Z2
Example 6.1 Analyze the simple voltage-mode (VM) circuits in Figs. 6.5 and 6.6.
Solution 6.1 The simple structures based on CF+ and CF- are, respectively,
exhibited in Figs. 6.5 and 6.6. Analysis of the simple topology based on CF+ is
carried out as follows:
I Zþ = αI X ð6:3aÞ
V in
= IX ð6:3bÞ
Z1
V out
= - I Zþ ð6:3cÞ
Z2
From above equations, the following transfer function (TF) is easily obtained:
V in V V Z
α = - out ) H v = out = - α 2 ð6:4Þ
Z1 Z2 V in Z1
Ideally, TF in Eq. (6.4) turns to
V out Z
Hv = =- 2 ð6:5Þ
V in Z1
Likewise, analysis of the simple topology based on CF- is achieved as
I Z - = - γI X ð6:6aÞ
Fig. 6.7 An inverting VM

amplifier/attenuator Vin X CF+ Z Vout
R1
R2
Fig. 6.8 A non-inverting

VM amplifier/attenuator Vin X CF- Z Vout
R1
R2
V in
= IX ð6:6bÞ
Z1
V out
= - IZ - ð6:6cÞ
Z2
From above equations, the following TF is easily obtained:
V in V out V Z
γ = ) H v = out = γ 2 ð6:7Þ
Z1 Z2 V in Z1
From above equation, TF ideally converts to
V out Z
Hv = = 2 ð6:8Þ
V in Z1
By appropriate choice of the impedances, Z1 and Z2 given in Figs. 6.5 and 6.6, the
following topologies are obtained.
(a) In Fig. 6.7, an inverting VM amplifier/attenuator can be easily obtained by taking
Z1 = R1 and Z2 = R2 of the circuit in Fig. 6.5. Thus, TF is evaluated as
V out R
Hv = =- 2 ð6:9Þ
V in R1
(b) In Fig. 6.8, a non-inverting VM amplifier/attenuator can be easily obtained by

taking Z1 = R1 and Z2 = R2 of the circuit in Fig. 6.6. Therefore, TF is evaluated by

integrator Vin X CF+ Z Vout
R

VM integrator Vin X CF- Z Vout
R

differentiator structure Vin X CF+ Z Vout
C
R
V out R
Hv = = 2 ð6:10Þ
V in R1
(c) In Fig. 6.9, an inverting VM integrator can be easily obtained by taking Z1 = R1

and Z2 = 1/(sC) of the structure in Fig. 6.5. Hence, TF is calculated as
V out 1
Hv = =- ð6:11Þ
V in sCR
(d) In Fig. 6.10, a non-inverting VM integrator circuit can be easily obtained by

taking Z1 = R1 and Z2 = 1/(sC) of the structure in Fig. 6.6. As a result, TF is
calculated by
V out 1
Hv = = ð6:12Þ
V in sCR
(e) In Fig. 6.11, an inverting VM differentiator circuit can be easily obtained by

taking Z1 = 1/(sC) and Z2 = R of the structure in Fig. 6.5. Hence, TF is computed
below.

VM differentiator Vin X CF- Z Vout
C
R
Vin X CF+ Z Vout

R1
C R2
Fig. 6.13 An inverting first-order VM LPF

first-order VM LPF Vin X CF- Z Vout
R1
C R2
V out
Hv = = - sCR ð6:13Þ
V in
(f) In Fig. 6.12, a non-inverting VM differentiator topology can be easily obtained

by taking Z1 = 1/(sC) and Z2 = R of the circuit in Fig. 6.6. Consequently, TF is
computed by
V out
Hv = = sCR ð6:14Þ
V in
(g) In Fig. 6.13, an inverting first-order VM low-pass filter (LPF) can be easily
obtained by taking Z1 = R1 and Z2 = R2//(1/(sC)) of the structure in Fig. 6.5.
Thus, TF is found below.
V out R 1
Hv = =- 2 ð6:15Þ
V in R1 sCR2 þ 1
(h) In Fig. 6.14, a non-inverting first-order VM LPF can be easily obtained by

Fig. 6.15 An inverting

first-order VM HPF Vin X CF+ Z Vout
R1
C
R2

first-order VM HPF Vin X CF- Z Vout
R1
C
R2
choosing Z1 = R1 and Z2 = R2//(1/(sC)) of the circuit of Fig. 6.6. Hence, TF is

found as
V out R 1
Hv = = 2 ð6:16Þ
V in R1 sCR2 þ 1
(i) In Fig. 6.15, an inverting first-order VM high-pass filter (HPF) can be easily
obtained by taking Z1 = R1 + 1/(sC) and Z2 = R2 of the structure in Fig. 6.5. As a
result, TF is computed below.
V out R sCR1
Hv = =- 2 ð6:17Þ
V in R1 sCR1 þ 1
(j) In Fig. 6.16, a non-inverting first-order VM HPF can be easily obtained by

choosing the impedances Z1 = R1 + 1/(sC) and Z2 = R2 of the structure of
Fig. 6.6. Thus, TF is calculated as
V out R sCR1
Hv = = 2 ð6:18Þ
V in R1 sCR1 þ 1
Example 6.2 Design a VM analog adder circuits based on a single output CF.
Solution 6.2 CF+ and CF- based VM analog adders are, respectively, depicted in
Figs. 6.17 and 6.18. Outputs of these circuits are, respectively, indicated below.

analog adder based on the V1 X CF+ Z Vout
CF+ R1
V2
R2 RT
Vn
Rn

VM analog adder based on V1 X CF- Z Vout
the CF- R1
V2
R2 RT
Vn
Rn
Fig. 6.19 An inverting C

first-order CM APF based
on the CF+
Vtest X CF Z+
R
Iin Iout
n
RT
V out = - V ð6:19aÞ
i=1
Ri i
n
RT
V out = V ð6:19bÞ
i=1
Ri i
Example 6.3 Find TF of the inverting first-order current-mode (CM) all-pass filter
(APF) shown in Fig. 6.19 [1].
Solution 6.3 Analysis of the inverting first-order CM APF based on the CF+ in
Fig. 6.19 is performed as follows:
Fig. 6.20 A non-inverting R

first-order CM APF based
on the CF+
X CF Z+
C
Iin Iout

first-order VM APF based
on the CF+
R1
Vin X CF Z+ Vout
R2
1 1
I in = V test sC þ and I out = V test sC -
R R
1 1
I out V test sC - R × sC -
Hi = = R = R
1 1 ð6:20Þ
I in
V test sC þ R × sC þ
R R
ðsCR - 1Þ × ð- 1Þ × ð- 1Þ 1 - sCR
= =-
1 þ sCR 1 þ sCR
Example 6.4 Find TF of the non-inverting first-order CM APF depicted in

Fig. 6.20, which is obtained from one given in [1] by RC-CR transformation.
Solution 6.4 Analysis of the inverting first-order CM APF based on the CF+ in
Fig. 6.20 is found below.
I out 1 - sCR
H i ðsÞ = = ð6:21Þ
I in 1 þ sCR
Example 6.5 Find TF of the inverting first-order VM APF demonstrated in

Fig. 6.21 [2].
Solution 6.5 TF of this topology is given below.
V out
R1
R2 - 1 - sCR1
Hv = =- ð6:22Þ
V in 1 þ sCR1

first-order APF based on the
CF+
Vin X CF Z+ Vout
R1
R2
If R1 = 2R2 is taken, the circuit in Fig. 6.21 behaves like a CF+ based inverting first-
order VM APF. Analysis of the structure in Fig. 6.21 is achieved by using the
following steps:
V in 1
= ðV in - V out Þ sC þ ð6:23aÞ
R2 R1
R1 V in
= ðV in - V out ÞðsCR1 þ 1Þ ð6:23bÞ
R2
R1 V in
ðsCR1 þ 1ÞV out = V in ðsCR1 þ 1Þ - ð6:23cÞ
R2
R1
ðsCR1 þ 1ÞV out = V in sCR1 þ 1 - × ð- 1Þ × ð- 1Þ ð6:23dÞ
R2
R1
ðsCR1 þ 1ÞV out = - V in - 1 - sCR1 ð6:23eÞ
R2
V out
R1
R2 - 1 - sCR1
=- ð6:23fÞ
V in 1 þ sCR1
Example 6.6 Find TF of the inverting first-order VM APF shown in Fig. 6.22 [2].
Solution 6.6 TF of this circuit is evaluated as
V out 1 - sCR1
Hv = = - R1 ð6:24Þ
R2 þ sCR1
V in
If R1 = R2 is chosen, the topology in Fig. 6.22 behaves like a CF+ based inverting
first-order VM APF. Analysis of the structure in Fig. 6.22 is accomplished by using
the following steps:

first-order VM APF based
on the CF+
R2
Vin X CF Z+ Vout
R1
V in V out
ðV in - V out ÞsC - = ð6:25aÞ
R1 R2
V in V out
sCV in - = þ sCV out ð6:25bÞ
R1 R2
V in V out
sCV in - × R1 = þ sCV out × R1 ð6:25cÞ
R1 R2
R1
V in ðsCR1 - 1Þ = V out þ sCR1 ð6:25dÞ
R2
R1
V out þ sCR1 = V in ðsCR1 - 1Þ × ð- 1Þ × ð- 1Þ ð6:25eÞ
R2
R1 V 1 - sCR1
V out þ sCR1 = - V in ð1 - sCR1 Þ ) out = - R1 ð6:25fÞ
R2 þ sCR1
R2 V in
Example 6.7 Find TF of the inverting first-order APF depicted in Fig. 6.23 [2].
Solution 6.7 TF of this circuit is computed as follows:
V out 1 - sCR1
Hv = = - 2R1 ð6:26Þ
R2 þ sCR1
V in
If R1 = 2R2 is taken, the circuit in Fig. 6.23 behaves like a CF+ based inverting first-
order VM APF. Analysis of the structure in Fig. 6.23 is carried out by using the
following steps:
V in V out V
þ = ðV in - V out ÞsC - out ð6:27aÞ
R1 R2 R2
V in 2V out
þ = ðV in - V out ÞsC ð6:27bÞ
R1 R2
2V out V
þ V out sC = sCV in - in ð6:27cÞ
R2 R1
R1
Vin X CF Z+ Vout
R2
C
Fig. 6.24 A non-inverting first-order VM APF based on the CF+
2 1
R1 × þ sC V out = R1 × sC - V ð6:27dÞ
R2 R1 in
2R1
þ sCR1 V out = ðsCR1 - 1ÞV in ð6:27eÞ
R2
2R1
þ sCR1 V out = ð- 1Þ × ð- 1Þ × ðsCR1 - 1ÞV in ð6:27fÞ
R2
2R1 V 1 - sCR1
þ sCR1 V out = - ð1 - sCR1 ÞV in ) out = - 2R1 ð6:27gÞ
R2 þ sCR1
R2 V in
Example 6.8 Find TF of the non-inverting first-order APF depicted in Fig. 6.24 [3].
Solution 6.8 TF of this structure is evaluated below.
V out 1 - sC ðR1 - R2 Þ
Hv = = ð6:28Þ
V in 1 þ sCR2
If R1 = 2R2 is taken, the topology in Fig. 6.24 behaves like a CF+ based
non-inverting first-order VM APF. Analysis of the structure in Fig. 6.24 is accom-
plished by using the following steps:
V in V - V out
= in ð6:29aÞ
R2 þ sC1 R1
V in × sC V in sC V - V out
= = in ð6:29bÞ
R2 þ sC1
× sC sCR2 þ 1 R1
V in sC V - V out
× R1 = in × R1 ð6:29cÞ
sCR2 þ 1 R1
V in sCR1
= V in - V out ð6:29dÞ
sCR2 þ 1
V in sCR1
V out = V in - ð6:29eÞ
sCR2 þ 1
V2 X CF Z+ X CF Z+ Vout
R1 (1) (2)
R3
V1
R2
Fig. 6.25 An IA implementation based on the two CF+s
(1) (2)
VX X CF Z+ X CF Z+ VZ-
IX IZ-
Fig. 6.26 Realization of the CF- by using two CF+s
Fig. 6.27 Symbol of the IZ+

DO-CF Z+ VZ+
VX X CF
IX Z- VZ-
IZ-
Fig. 6.28 Ideal model of

the DO-CF CF IZ+
VZ+
VX VZ-
IX α IX γ IX IZ-
sCR2 þ 1 sCR1 1 þ sCR2 - sCR1

V out = V - V ) V out = V in ð6:29fÞ
sCR2 þ 1 in sCR2 þ 1 in sCR2 þ 1
Example 6.9 Realize an instrumentation amplifier (IA) based on two CF+s.

Solution 6.9 Realization of the IA is depicted in Fig. 6.25 [4], where R2 = R1 is
taken. Therefore, output voltage of this IA is calculated by
R3
V out = ðV - V 1 Þ ð6:30Þ
R1 2
Example 6.10 Implement a CF- by using CF+s.

Solution 6.10 Implementation of the CF- by using two CF+s is shown in Fig. 6.26.
The electrical symbol of the DO-CF is demonstrated in Fig. 6.27, while ideal model
Fig. 6.29 Realization of the Iout

floating current source based Z+ a
on the DO-CF
Vin X CF
R Z- b
Iout
Fig. 6.30 The symbol of a

the floating current source
Iout
Z1
(1) Iout
X CF+ (2)
Z1
Vtest
Z2 X CF+
Iin R
Z2
C
Fig. 6.31 Non-inverting first-order CM APF
of the DO-CF is given in Fig. 6.28. This DO-CF can be defined by the following
matrix equation:
I Zþ α
IZ - = - γ ½I X ð6:31Þ
VX 0
Example 6.11 Design a floating current source based on the DO-CF.

Solution 6.11 The floating current source can be implemented by using a voltage
source, a resistor, and a DO-CF as depicted in Fig. 6.29. The symbol of this floating
current source is shown in Fig. 6.30.
The current, Iout, in Figs. 6.29 and 6.30 is evaluated as follows:
V in
I out = ð6:32Þ
R
Vin Z- Z- Z-
Iin (1) (2)
CF CF
Vtest
X Z+ X
R1 R2
Zin
C
Fig. 6.32 A positive lossless SGI
Example 6.12 Find the TF of the CM topology in Fig. 6.31 [5].

Solution 6.12 The circuit of Fig. 6.31 is analyzed as
1 - I in R
V test sC þ = - I in ) V test = ð6:33Þ
R sCR þ 1
From equation indicated in (6.33), output current, Iout is found by
2V test 1 - sCR
I out = - I in - = I ð6:34Þ
R 1 þ sCR in
Hence, the TF is calculated below.
I out 1 - sCR
H ðsÞ = = ð6:35Þ
I in 1 þ sCR
Example 6.13 Find the input impedance of the positive lossless simulated
grounded inductor (SGI) in Fig. 6.32 [6].
Solution 6.13 The circuit given in Fig. 6.32 is analyzed with the two equations as
given below.
It is considered that the current flowing into the X terminal of the CF is equal to
the current extracted from the Z- terminal of the same CF.
- V test
I in = ð6:36aÞ
R2
V in V
= - V test sC ) V test = - in ð6:36bÞ
R1 sCR1
If Vtest in Eq. (6.36b) is replaced instead of equation denoted in (6.36a), the following
input impedance is obtained:
V in V
I in = ) Z in = in = sCR1 R2 ð6:37Þ
sCR1 R2 I in
6.3 VFs and Their Applications
The symbol of the voltage follower (VF) is given in Fig. 6.33, while ideal model of
the VF is depicted in Fig. 6.34. The VF can be defined by the following matrix
equation:
IY 0 0 VY
= ð6:38Þ
VX β 0 IX
where β is frequency dependent nonideal voltage gain, which is ideally equal to

unity.
Note In Fig. 6.34, Rin is ideally equal to infinity.
Example 6.14 Find the current TF of the VF-based simple circuit in Fig. 6.35.
Solution 6.14 The analysis of the circuit in Fig. 6.35 is performed by using the
following three equations:
VX = VY ð6:39aÞ
Fig. 6.33 The symbol of

the VF
VY Y VF X VX
IY IX
Fig. 6.34 Ideal model of

the VF VF
VY VX
IY Rin + V IX
_ Y
6.3 VFs and Their Applications 167
Fig. 6.35 A simple CM

topology based on the VF
Y VF X
Iin Z1 Z2
Iout
Fig. 6.36 The VF-based

second-order VM Y VF X Vo1
multifunction filter (1)
R1 C2
C1
X VF Y
(2)
R2
Vi1 Vo2
Vi2
VY
I in = ð6:39bÞ
Z1
VX
I out = ð6:39cÞ
Z2
From above equations, the following TF is obtained:
I out Z
I in Z 1 = I out Z 2 ) H i = = 1 ð6:40Þ
I in Z2
So, various first-order current TFs based on the selection of Z1 and Z2 are obtained.
Example 6.15 Find the voltage responses of the VF-based second-order
multifunction filter in Fig. 6.36 [7].
Solution 6.15 The analysis of the circuit in Fig. 6.36 is performed by using the
following two equations:
V o1 - V o2
ðV i1 - V o1 ÞsC1 = ð6:41aÞ
R1
V o2 - V i2
ðV o1 - V o2 ÞsC 2 = ð6:41bÞ
R2
From equations denoted in (6.41), if Vi1 = 0 is chosen, the following LPF TF is

found as follows:
V o1 1
= ð6:42Þ
V i2 C 1 C 2 R1 R2 s2 þ C1 R1 s þ 1
Similarly, if Vi2 = 0 is taken, the following HPF TF is evaluated by
V o2 C1 C2 R1 R2 s2
= ð6:43Þ
V i1 C 1 C 2 R1 R2 s2 þ C1 R1 s þ 1
6.4 CF and VF-Based Circuits
In this section, CF and VF-based structures are treated with several examples.
Example 6.16 Find the phase and magnitude of the impedance of the parallel lossy
SGI in Fig. 6.37 [8]. Also, find the useful operating frequency range of this SGI.
Solution 6.16 The analysis of the topology in Fig. 6.37 is achieved by using the
V in - V test V in
I in = þ ð6:44aÞ
R1 R2
V in
= - sCV test ð6:44bÞ
R2
From equation indicated in (6.44b), Vtest is computed below.
V in
V test = - ð6:45Þ
sCR2
If Vtest is replaced in Eq. (6.44a), Iin is calculated as
R1
Iin Vtest
Vin X CF Z+ Y VF X
R2 (1) (2)
Zin
Fig. 6.37 The UGC-based parallel lossy SGI
6.4 CF and VF-Based Circuits 169
V in þ sCR
V in
V 1 1 1
I in = 2
þ in = V in þ þ ð6:46Þ
R1 R2 R1 R2 sCR1 R2
From equation given in (6.46), the admittance of the structure in Fig. 6.37 is found as
in the following:
I in 1 1 1
Y in = = þ þ
V in R1 R2 sCR1 R2
ð6:47Þ
1 1
= þ
Req sLeq
Here, Leq = CR1R2 and Req = R1//R2 = R1R2/(R1 + R2). In other words, the
impedance in s domain is evaluated as
Z in ðsÞ = ðsCR1 R2 Þ==R1 ==R2 ð6:48Þ
On the other hand, the impedance of the circuit of Fig. 6.37 in the frequency domain
is found as
Z in ðωÞ = ðjωCR1 R2 Þ==R1 ==R2 ð6:49Þ
The phase and magnitude of the impedance of the parallel lossy SGI in Fig. 6.37 are,
respectively, computed by
π
∠Z in ðωÞ = - tan - 1 ðωCðR1 þ R2 ÞÞ ð6:50aÞ
2
ωCR1 R2 ðR1 ==R2 Þ
jZ in ðωÞj = ð6:50bÞ
ðωCR1 R2 Þ2 þ ðR1 ==R2 Þ2
It is seen from above equations that if the following condition is met, the circuit in
Fig. 6.37 operates as a lossless inductor.
R1 R2 1
> > ωCR1 R2 ) ≥ 10ωC ð6:51Þ
R1 þ R2 R1 þ R2
From equation in (6.51), the operating frequency range is found below.
0:1 1
f≤ × ð6:52Þ
2π C ðR1 þ R2 Þ
Example 6.17 Find the phase and magnitude of the impedance of parallel lossy SGI
in Fig. 6.38 [9]. Also, find the useful operating frequency range of this SGI.
R1
Iin Vtest
Vin Y VF X X CF Z+ Y VF X
R2 (2)
(1) (3)
Zin
Fig. 6.38 The UGC-based another parallel lossy SGI
Solution 6.17 The analysis of the topology in Fig. 6.38 is carried out by using the
V in - V test
I in = ð6:53aÞ
R1
V in
R2
From equation indicated in (6.53b), Vtest is computed below.
V in
V test = - ð6:54Þ
sCR2
If Vtest is replaced in Eq. (6.53a), Iin is computed by
V in þ sCR
V in
1 1
I in = 2
= V in þ ð6:55Þ
R1 R1 sCR1 R2
From equation given in (6.55), the admittance of the topology of Fig. 6.38 is found
as
I in 1 1
Y in = = þ
V in R1 sCR1 R2
ð6:56Þ
1 1
= þ
Req sLeq
where Leq = CR1R2 and Req = R1. In other words, the impedance in s domain is
computed below.
Z in ðsÞ = ðsCR1 R2 Þ==R1 ð6:57Þ
On the other hand, the impedance of the circuit of Fig. 6.38 in the frequency domain
is found as follows:
Z- CF X
(1)
R1
Iin Vtest
Vin Y VF X X CF Z+ Y VF X
R2 (3)
(2) (4)
Zin
Fig. 6.39 The UGC-based positive lossless SGI
Z in ðωÞ = ðjωCR1 R2 Þ==R1 ð6:58Þ
The phase and magnitude of the impedance of the another parallel lossy SGI in
Fig. 6.38 are, respectively, calculated as
π
∠Z in ðωÞ = - tan - 1 ðωCR2 Þ ð6:59aÞ
2
ωCR21 R2
jZ in ðωÞj = ð6:59bÞ
ðωCR1 R2 Þ2 þ R21
It is observed from above equations that if the following condition is met, the circuit
in Fig. 6.38 operates as a lossless inductor.
1 1
R1 > > ωCR1 R2 ) > > ωC ) ≥ 10ωC ð6:60Þ
R2 R2
From equation in (6.60), the operating frequency range is found as follows:
0:1 1
f≤ × ð6:61Þ
2π CR2
Example 6.18 Find the impedance of the positive SGI in Fig. 6.39 [10].
Solution 6.18 The analysis of the topology in Fig. 6.39 is accomplished by using
the following two equations:
V test
I in = - ð6:62aÞ
R1
V in
R2
From equation indicated in (6.62b), Vtest is evaluated as

Z1
Iin Vtest
Vin X CF Z- Y VF X
Z2 (1) (2)
Z3
Zin
Fig. 6.40 The UGC-based negative lossless SGI
V in
V test = - ð6:63Þ
sCR2
If Vtest is replaced in Eq. (6.62a), Iin is computed as in the following:
V in
sCR2 1
I in = = V in ð6:64Þ
R1 sCR1 R2
From equation in (6.64), the impedance of the topology of Fig. 6.39 is calculated as
V in
Z in = = sCR1 R2 = sLeq ð6:65Þ
I in
where Leq = CR1R2.

Example 6.19 Find the impedance of the negative lossless SGI in Fig. 6.40 [11].
Solution 6.19 The analysis of the topology in Fig. 6.40 is carried out by using the
V in - V test
I in = ð6:66aÞ
Z1
V in V - V test
= - in ð6:66bÞ
Z2 Z3
From equation indicated in (6.66b), Vin - Vtest is found below.
Z3
V in - V test = - V in ð6:67Þ
Z2
If Vin - Vtest in Eq. (6.67) is replaced in (6.66a), Iin is evaluated as
- V in ZZ 32 Z
I in = = - V in 3 ð6:68Þ
Z1 Z1Z2
From above equation, the impedance is computed as follows:

Z1
Iin (2) (3)

Vin Vtest VF
X CF Z+ Y X
Z2
(1)
Y VF X
Zin
Z3
Fig. 6.41 The UGC-based positive lossless SGI
V in Z1Z2
Z in = =- ð6:69Þ
I in Z3
Here, if Z1 = R1, Z2 = R2, and Z3 = 1/(sC) are chosen, a negative lossless SGI is
obtained.
Example 6.20 Find the impedance of the positive lossless SGI in Fig. 6.41 [12].
Solution 6.20 The analysis of the topology in Fig. 6.41 is performed by using the
V in - V test
I in = ð6:70aÞ
Z1
V in V in - V test
= ð6:70bÞ
Z2 Z3
From equation indicated in (6.70b), Vin - Vtest is found as follows:
Z3
V in - V test = V in ð6:71Þ
Z2
If Vin - Vtest in Eq. (6.71) is replaced in (6.70a), Iin is calculated by
V in ZZ 32 Z
I in = = V in 3 ð6:72Þ
Z1 Z1Z2
From above equation, the impedance is computed below.
V in Z 1 Z 2
Z in = = ð6:73Þ
I in Z3
where if Z1 = R1, Z2 = R2, and Z3 = 1/(sC) are taken, a positive lossless SGI is
obtained.
References
1. S. Maheshwari, A new current-mode current-controlled all-pass section. J. Circuit. Syst.

Comput. 16(2), 181–189 (2007)
2. A. Toker, S. Ozcan, H. Kuntman, O. Cicekoglu, Supplementary all-pass sections with reduced
number of passive elements using a single current conveyor. Int. J. Electron. 88(9), 969–976
(2001)
3. O. Cicekoglu, H. Kuntman, S. Berk, All-pass filters using a single current conveyor.
Int. J. Electron. 86(8), 947–955 (1999)
4. L. Safari, G. Ferri, S. Minaei, V. Stornelli, Current-Mode Instrumentation Amplifiers (Springer,
2019)
5. L. Safari, S. Minaei, E. Yuce, CMOS first-order current-mode all-pass filter with electronic
tuning capability and its applications. J. Circuit. Syst. Comput. (JCSC) 22(3), 17 (2013)
6. E. S. Erdoğan, Active Filter Design with Unity Gain Current Cells (MSc thesis, Bogazici
University, 2004)
7. F. Yucel, E. Yuce, A new voltage mode multifunctional filter using only two voltage followers
and a minimum number of passive elements. J. Circuit. Syst. Comput. (JCSC) 24(6), 16 (2015)
8. A. Fabre, O. Saaid, F. Wiest, C. Boucheron, Low power current-mode second-order bandpass
IF filter. IEEE Trans. Circuit. Syst. II Analog Digital Sign. Process. 44(6), 436–446 (1997)
9. H. Alpaslan, E. Yuce, Current-mode biquadratic universal filter design with two terminal unity
gain cells. Radioengineering 21(1), 304–311 (2012)
10. H. Alzaher, N. Tasadduq, CMOS digitally programmable inductance. In 2006 International
conference on microelectronics (IEEE, 2006), pp. 138–141
11. A.U. Keskin, A. Toker, A NIC with impedance scaling properties using unity gain cells. Analog
Integr. Circ. Sig. Process 41(1), 85–87 (2004)
12. H. Alpaslan, E. Yuce, New grounded inductor simulator using unity gain cells. Indian J. Pure
Appl. Phys. 51(09), 651–656 (2013)
Chapter 7
Unity Gain Inverting Amplifiers
and Negative Impedance Converters
7.1 Introduction
Unity gain inverting amplifiers (UGIAs) and negative impedance converters (NICs)
are main analog devices. They have been found wide application realms in the
related open literature [1–9].
7.2 UGIAs
The electrical symbol of the UGIA is depicted in Fig. 7.1, while ideal model of the
UGIA is demonstrated in Fig. 7.2. The UGIA with nonideal voltage gain is
expressed as follows:
IY 0 0 VY
= ð7:1Þ
VX -β 0 IX
Here, IX is an arbitrary current depending on the load connected the X terminal of the
UGIA. β is frequency dependent nonideal voltage gain, ideally equal to unity. Also,
Rin in Fig. 7.2 is ideally equal to infinity.
Example 7.1 Design a simple current-mode (CM) circuit for realizing different
transfer functions (TFs) based on the UGIA.
Solution 7.1 The simple circuit based on the UGIA is shown in Fig. 7.3. Analysis of
the simple topology is carried out as below.
V X = - βV Y ð7:2aÞ
https://doi.org/10.1007/978-3-031-44966-6_7
176 7 Unity Gain Inverting Amplifiers and Negative Impedance Converters
Fig. 7.1 The electrical

symbol of the UGIA
VY
IY
Y -1 X
IX
VX

UGIA
VY _ VX
IY Rin VY IX
+
Fig. 7.3 The CM simple

circuit based on the UGIA
Y -1 X
Iin Z1 Z2
Iout
VY
I in = ð7:2bÞ
Z1
VX
I out = ð7:2cÞ
Z2
From above equations, the following CM TF is obtained:
- I out Z 2 I βZ
I in Z 1 = ) H i = out = - 1 ð7:3Þ
β I in Z2
By selecting different elements for Z1 and Z2, various types of TFs can be obtained.
Example 7.2 Design a VF by using the UGIAs.
Solution 7.2 The VF realization by using two UGIAs is demonstrated in Fig. 7.4.
Example 7.3 Find the TF of the first-order voltage-mode (VM) APF based on a
single UGIA [1], which is given in Fig. 7.5.
7.2 UGIAs 177
VY
IY
Y -1 X Y -1 X
IX
VX
(1) (2)
Fig. 7.4 The VF implementation with two UGIAs
Fig. 7.5 The first-order VM

APF using a single UGIA R
Vin Y -1 X Vout
Fig. 7.6 Another first-order Vout

VM circuit employing a
single UGIA R1 R2
R Vtest
Vin Y -1 X
Solution 7.3 By applying the KVL for the circuit in Fig. 7.5, the following equation
is obtained:
- V in - V out
= ðV out - V in ÞsC ð7:4Þ
R
Rearranging the equation denoted in (7.4), the equation given below is obtained.
- V in - V out = ðV out - V in ÞsCR ) - V in þ V in sCR = V out þ V out sCR ð7:5Þ
From above equation, TF of the VM APF is found as
V out - 1 þ sCR 1 - sCR

V in ð- 1 þ sCRÞ = V out ð1 þ sCRÞ ) = =- ð7:6Þ
V in 1 þ sCR 1 þ sCR
Example 7.4 Find the TF of another first-order VM topology based on a single

UGIA [2], which is depicted in Fig. 7.6.
Solution 7.4 By applying the KVL for the circuit in Fig. 7.6, the following equation
is obtained:
V in - V out V þ V test
= out ð7:7Þ
R1 R2
Here, Vtest is evaluated as
1
V test = V ð7:8Þ
1 þ sCR in
If R1 = 2R2 is taken for the equations indicated in (7.7), the following equation is
obtained:
V in - V out V þ V test V - V out

= out ) in = V out þ V test ð7:9Þ
2R2 R2 2
Rearrangement of the equation in (7.9), the equation given below is obtained.
V in - V out V in V V in V
= V out þ ) in - = out þ V out ð7:10Þ
2 1 þ sCR 2 1 þ sCR 2
Further arranging the equation in (7.10), the following equation is obtained as
1
2 V in þ 12 sCRV in - V in 1 1 - sCR 1 3
=- V = V out þ 1 = V out ð7:11Þ
1 þ sCR 2 1 þ sCR in 2 2
Finally, the following first-order VM APF TF is found.
V out 1 1 - sCR
=- ð7:12Þ
V in 3 1 þ sCR
Example 7.5 Find the TFs of the first-order CM topology based on a single UGIA
[3], which is shown in Fig. 7.7. Also, R1 = R2 = R and C1 = C2 = C are chosen.
Solution 7.5 Analysis of the first-order CM filter is accomplished by the following
five equations:
1 I in RI in
I in = V test sC þ ) V test = = ð7:13aÞ
R sC þ R1 sCR þ 1
V test
I LP1 = ð7:13bÞ
R
I HP1 = V test sC ð7:13cÞ
7.3 NICs 179
Vtest
Y -1 X
C1 R2
R1 C2
Iin IHP1 ILP2
ILP1 IHP2
IAP1
IAP2
Fig. 7.7 The first-order CM structure consisting of a single UGIA
V test
I LP2 = - ð7:13dÞ
R
I HP2 = - sCV test ð7:13eÞ
From above equations, the following output currents are obtained:
1
I LP1 = I ð7:14aÞ
1 þ sCR in
sCR
I HP1 = I ð7:14bÞ
1 þ sCR in
1
I LP2 = - I ð7:14cÞ
1 þ sCR in
sCR
I HP2 = - I ð7:14dÞ
1 þ sCR in
1 - sCR
I AP1 = I HP1 þ I LP2 = - I ð7:14eÞ
1 þ sCR in
1 - sCR
I AP2 = I LP1 þ I HP2 = I ð7:14fÞ
1 þ sCR in
7.3 NICs
The symbol of the NIC is given in Fig. 7.8 [4]. NIC can be divided into two
subcategories, current NIC (INIC) and voltage NIC (VNIC). The symbols of the
INIC and VNIC are, respectively, shown in Figs. 7.9 and 7.10.
Fig. 7.8 The symbol of the

NIC
V1 1 NIC 2 V2
I1 I2

the INIC
V1 1 INIC 2 V2
I1 I2

the VNIC
V1 1 VNIC 2 V2
I1 I2
Fig. 7.11 The first-order C

VM circuit based on
the INIC
Vin 1 INIC 2 Vout

R1
R2
INIC and VNIC are, respectively, expressed by the following matrix equations:
I2 1 0 I1
= ð7:15aÞ
V1 0 1 V2
I2 -1 0 I1
= ð7:15bÞ
V1 0 -1 V2
Example 7.6 Find the TF of the first-order VM topology based on a single INIC [5],
which is shown in Fig. 7.11.
Solution 7.6 The topology of Fig. 7.11 is analyzed as in the following:
V in - V out V
ðV in - V out ÞsC - = out ð7:16aÞ
R1 R2
V in V out V
V in sC - = - out þ V out sC ð7:16bÞ
R1 R2 R1
7.3 NICs 181
Fig. 7.12 The negative

grounded impedance based Vin 1 INIC 2 Vin
on a single INIC Iin Iin
Z(s)
Zin
1 1 1
R1 × V in sC - = R1 × V out - þ sC ð7:16cÞ
R1 R2 R1
R1
V in ðsCR1 - 1Þ = V out - 1 þ sCR1 ð7:16dÞ
R2
R1
ð- 1Þ × ð- 1Þ × V in ðsCR1 - 1Þ = V out - 1 þ sCR1 =
R2
- V in ð1 - sCR1 Þ ð7:16eÞ
Thus, output voltage is found as
1 - sCR1
V out = - V in ð7:17Þ
R1
R2 - 1 þ sCR1
If R1 = 2R2 is taken, TF of the structure in Fig. 7.11 is computed as follows:
1 - sCR1 V 1 - sCR1
V out = - V ) out = - ð7:18Þ
1 þ sCR1 in V in 1 þ sCR1
Example 7.7 Find the input impedance of the circuit depicted in Fig. 7.12.
Solution 7.7 After analysis of the topology of Fig. 7.12, the following input
impedance is found as
V in - I in Z ðsÞ
Z in = = = - Z ðs Þ ð7:19Þ
I in I in
Example 7.8 Find the input impedance of the structure in Fig. 7.13.
Solution 7.8 After analysis of the circuit in Fig. 7.13, the following input imped-
ance is found by
Vin 1 INIC 2
Iin Z1
Z2
Zin
Fig. 7.13 A topology based on a single INIC
Fig. 7.14 The positive

parallel lossy SGI based on a Vin 1 INIC 2
single INIC Iin R
C R
Zin
Vin 1 INIC 2
Iin
R
R
Zin
Fig. 7.15 The negative parallel lossy SGI based on a single INIC
Z in = Z 1 - Z 2 ð7:20Þ
If Z1 = R and Z2 = R//(1/(sC)) in Fig. 7.13 are taken, a positive parallel lossy

simulated grounded inductor (SGI) in Fig. 7.14 is obtained. This parallel lossy SGI is
expressed as [6]
Z in = R== sCR2 ð7:21Þ
If Z1 = R//(1/(sC)) and Z2 = R in Fig. 7.13 are selected, a negative parallel lossy SGI
in Fig. 7.15 is obtained. This negative parallel lossy SGI is expressed by [6]
7.3 NICs 183
Fig. 7.16 Another circuit

based on a single INIC Vin 1 INIC 2
Iin
Z1 Z2
Zin
Fig. 7.17 The positive

series lossy SGI based on a Vin 1 INIC 2
single INIC Iin
R
R
C
Zin
Fig. 7.18 The negative

series lossy SGI based on a Vin 1 INIC 2
single INIC Iin
R
R
C
Zin
Z in = - R== - sCR2 ð7:22Þ
Example 7.9 Find the input impedance of the structure given in Fig. 7.16.
ance is found as given below.
Z in = Z 1 ==ð- Z 2 Þ ð7:23Þ
If Z1 = R and Z2 = R + 1/(sC) in Fig. 7.16 are chosen, a positive series lossy SGI in
Fig. 7.17 is obtained. This series lossy SGI is expressed below [6].
Z in = sCR2 þ R ð7:24Þ
If Z1 = R + 1/(sC) and Z2 = R in Fig. 7.16 are taken, a negative series lossy SGI in
Fig. 7.18 is obtained. This series lossy SGI is expressed as [6]
Vin 1 INIC 2 1 INIC 2

Iin (1) (2)
R
R R
Zin
Fig. 7.19 The positive lossless SGI based on two INICs
Vin 1 INIC 2 1 INIC 2

Iin (1) R (2)
R
R
C
Zin
Fig. 7.20 Another positive lossless SGI based on two INICs
Z in = - sCR2 - R ð7:25Þ
Example 7.10 Find the input impedance of the structure given in Figs. 7.19 and
7.20 [6].
Solution 7.10 Using the results given in the above examples, after analysis of the
circuits in Figs. 7.19 and 7.20, the input impedance for both circuits is found below.
Z in = sCR2 = sLeq ð7:26Þ
where Leq = CR2.

Example 7.11 Find the input impedance of the circuit given in Fig. 7.21 [7].
ance is found by
sCR1 R2 þ R1 - R2
Z in ðsÞ = ð7:27Þ
sC ðR2 - R1 Þ þ 4
If R1 = R2 = R is taken, the input impedance of the topology turns to
sCR2
Z in ðsÞ = = sLeq ð7:28Þ
4
Here, Leq = CR2/4.

7.3 NICs 185
Fig. 7.21 A positive Iin

lossless SGI based on one Vin 2 INIC 1
INIC and one VNIC
R1 R2
Zin
1 VNIC 2
Vtest Vtest
I1
V1 1 INIC 2
I1 Z1 (1)
Z2
V2 1 INIC 2
I2 (2) I2
V2
Fig. 7.22 The floating circuit based on two INICs
Example 7.12 Find the admittance matrix equation for the circuit exhibited in
Fig. 7.22.
Solution 7.12 The following equations can be written for the circuit in Fig. 7.22 to
obtain the admittance matrix equation:
V 1 - V test
I1 = ð7:29aÞ
Z1
V 2 - V test
I1 = ð7:29bÞ
Z2
I2 = - I1 ð7:29cÞ
From above equations, the following admittance matrix equation is found as
I1 1 1 -1 V1
= ð7:30Þ
I2 Z1 - Z2 -1 1 V2
Fig. 7.23 Another floating V1

circuit based on two INICs Ia
V1 1 INIC 2
I1 (1) Ia
Ib
Z1 Z2
V2 1 INIC 2
I2 Ia (2)
V2
Fig. 7.24 A Wien oscillator

based on one INIC 1 INIC 2 Vout
R1
C2 R2
C1
Example 7.13 Find the admittance matrix equation for another topology in
Fig. 7.23.
Solution 7.13 The following equations can be written for the structure in Fig. 7.23
to obtain the admittance matrix equation:
I1 = Ia þ Ib ð7:31aÞ
I 2 = - ðI a þ I b Þ ð7:31bÞ
V2 - V1
Ia = ð7:31cÞ
Z2
V1 - V2
Ib = ð7:31dÞ
Z1
From above equations, the following admittance matrix equation is evaluated as
I1 1 1 -1 V1
= ð7:32Þ
I2 Z 1 ==ð- Z 2 Þ -1 1 V2
7.3 NICs 187
Fig. 7.25 A second-order

VM universal filter based on C1
one INIC and one VF V1 Y VF X Vout
(2)
V2
R1
R2
C2
2
INIC
1 (1)
Vtest
R3
V3
Example 7.14 Find the characteristic equation (D(s)), osillation condition (OC),
and osillation frequency (OF) of the Wien oscillator in Fig. 7.24 [8].
Solution 7.14 Analysis of the circuit in Fig. 7.24 is achieved as
V out 1
= V out sC 2 þ ð7:33Þ
R1 þ sC1 1 R2
From above equation, D(s) is calculated by
DðsÞ = s2 C 1 C 2 R1 R2 þ sðC 1 R1 þ C2 R2 - C 1 R2 Þ þ 1 = 0 ð7:34Þ
Therefore, OC and OF are, respectively, found as follows:
C1 R2 ≥ C 1 R1 þ C2 R2 ð7:35aÞ
1 1
f0 = ð7:35bÞ
2π C1 C2 R1 R2
Note VNIC is sometimes used instead of INIC or vice versa, because INIC changes
the direction of current, while VNIC changes the polarity of the voltage.
Example 7.15 Find the output voltage (Vout), resonance frequency ( f0), and quality
factor (Q) of the universal filter in Fig. 7.25 [9].
Solution 7.15 Analysis of the circuit in Fig. 7.25 is carried out as in the following:
V 2 - V out V - V test
ðV 1 - V out ÞsC 1 þ = out ð7:36aÞ
R1 R2
V test - V out V - V3
ðV out - V test ÞsC2 þ = test ð7:36bÞ
R2 R3
From above two equations, if R2 = R3 = R are taken, output response, f0, and Q of
the universal filter are, respectively, computed as
s2 C1 C2 R1 R2 V 1 þ sC 2 R2 V 2 þ R1 V 3
V out = ð7:37aÞ
s2 C 1 C 2 R1 R2 þ sC 2 R2 þ R1
1 1
f0 = × p ð7:37bÞ
2π R C 1 C 2
R1 C1
Q= × ð7:37cÞ
R C2
One sees from equations given in (7.37) that all the second-order VM filter responses
can be easily obtained with appropriate choice of input voltage(s). Furthermore, Q of
this filter can be changed by varying R1 without disturbing the resonance frequency f0.
References
1. A. Toker, S. Ozoguz, Tunable all pass filter for low voltage operation. Electron. Lett. 39(2),
175–176 (2003)
2. E. Yuce, S. Minaei, A novel phase shifter using two NMOS transistors and passive elements.
Analog Integr. Circuit. Signal Process. (ALOG) 62, 77–81 (2010)
3. E. Yuce, S. Minaei, N. Herencsar, J. Koton, Realization of first-order current-mode filters with
low number of MOS transistors. J. Circuit. Syst. Comput. (JCSC) 22(1), 14 (2013)
4. A.S. Sedra, K.C. Smith, A second-generation current conveyor and its applications. IEEE Trans.
Circuit Theory 17(1), 132–134 (1970)
5. O. Cicekoglu, H. Kuntman, S. Berk, All-pass filters using a single current conveyor.
Int. J. Electron. 86(8), 947–955 (1999)
6. T.S. Rathore, B.M. Singhi, A family of inductance simulation. JIE PT ET-2 61, 58–59 (1980)
7. E. Yuce, H. Alpaslan, S. Minaei, U.E. Ayten, A new simulated grounded inductor based on two
NICs, two resistors and a grounded capacitor. Circuit. Syst. Signal Process. (CSSP) 40(12),
5847–5863 (2021)
8. S. Celma, P.A. Martinez, A. Carlosena, Approach to the synthesis of canonic RC-active
oscillators using CCII. IEEE Proc. Circuits Devices Syst. 141(6), 493–497 (1994)
9. E. Yuce, S. Tez, A novel voltage-mode universal filter composed of two terminal active devices.
Int. J. Electron. Commun. (AEU) 86, 202–209 (2018)
Chapter 8
Current Conveyors and Their Applications
8.1 Introduction
Current conveyors (CCs) have the property of higher linearity, wider bandwidth,
larger dynamic range, etc. when compared to operational amplifiers [1–5]. Three
generation CCs are available in the literature, first-generation CC (CCI) [6], second-
generation CC (CCII) [7], and third-generation CC (CCIII) [8]. Other types of CCs
such as subtractor connected CCI (S-CCI), current controlled CCII (CCCII),
inverting CCII (ICCII), differential CC (DCCII), dual X CCII (DX-CCII), differen-
tial voltage CC (DVCC), differential difference CC (DDCC), fully differential CCII
(FDCCII), current differencing CC (CDCC), extra X CCCII (EX-CCCII), etc. are
also available in the literature.
8.2 CCI
Symbol of the dual-output CCI (DO-CCI) is shown in Fig. 8.1. If one of the Z- or Z
+ terminal of this DO-CCI is removed, plus-type CCI (CCI+) and minus-type CCI
(CCI-) are, respectively, obtained. This DO-CCI is expressed in the matrix equation
(8.1).
VX 1 0
IY 0 1 VY
= ð8:1Þ
I Zþ 0 1 IX
IZ - 0 -1
https://doi.org/10.1007/978-3-031-44966-6_8
190 8 Current Conveyors and Their Applications
Fig. 8.1 Symbol of the VY VZ+

Y Z+
DO-CCI IY IZ+
DO-CCI
VX X Z- VZ-
IX IZ-
R/2
I1
Y
C Vtest
CCI Z+
I1
Vin X
Iin R Vtest I1
Zin
Fig. 8.2 CCI+ based SGI
One of the most important applications of the CCs is found in realization of the
simulated inductors (SIs) that can be lossy or lossless. SIs can be divided into two
groups, simulated grounded inductor (SGI) and simulated floating inductor (SFI).
Example 8.1 Find the input impedance of the SGI in Fig. 8.2 [9].
Solution 8.1 Its analysis is carried out by using the following four equations:
V in - V test
I in = þ ðV in - V test ÞsC þ I 1 ð8:2aÞ
R
V in - V test V
= test þ I 1 ð8:2bÞ
R R
2V test
ðV in - V test ÞsC = þ I1 ð8:2cÞ
R
V
Z in = in ð8:2dÞ
I in
From equations indicated in (8.2), input impedance of the SGI in Fig. 8.2 is
evaluated as
V in 1
Z in = = sCR2 ð8:3Þ
I in 3
8.2 CCI 191
I1
Vin Y Vtest
Iin
CCI Z- Y VF X
(1) I1
X (2)
I1
C
Zin R
Fig. 8.3 CCI- and VF-based SGI
Example 8.2 Find the input impedance of the SGI in Fig. 8.3 [10]. This SGI
consists of one CCI and one voltage follower (VF).
Solution 8.2 Its analysis is accomplished by using the following four equations:
V in - V test
I in = þ I1 ð8:4aÞ
R
V
I 1 = - in ð8:4bÞ
R
I 1 = V test sC ð8:4cÞ
V in
Z in = ð8:4dÞ
I in
evaluated as
V in
I in
Example 8.3 Find the input impedance of the SGI in Fig. 8.4 [10]. This SGI uses
one CCI and one unity gain-inverting amplifier (UGIA).
Solution 8.3 Its analysis is accomplished by using the following four equations:
V in - ð- V test Þ
I in = þ I1 ð8:6aÞ
R
V
I 1 = - in ð8:6bÞ
R
I1
Vin Y Vtest
Iin
CCI Z+ Y -1 X
(1) I1
X (2)
I1
C
Zin R
Fig. 8.4 CCI+ and UGIA-based SGI
R1
I1
Vo1 Y Vo2
CCI Z- Y VF X Vo2
(1)
I1
X (2)
C1 I1
C2
R2
Fig. 8.5 CCI- and VF-based QO
I 1 = - V test sC ð8:6cÞ
V in
Z in = ð8:6dÞ
I in
calculated as
V in
I in
Example 8.4 Find the characteristic equation (D(s)), oscillation condition (OC),
and oscillation frequency (OF) of the quadrature oscillator (QO) demonstrated in
Fig. 8.5 [10].
8.3 CCII 193
R1
I1
Vo1 Y -Vo2
CCI Z+ Y -1 X Vo2
(1) I1
X (2)
C1 I1
C2
R2
Fig. 8.6 CCI+ and UGIA-based QO
Solution 8.4 Its analysis is carried out by using the following three equations:
V o2 - V o1
= V o1 sC 1 þ I 1 ð8:8aÞ
R1
V o1
I1 = - ð8:8bÞ
R2
I 1 = V o2 sC 2 ð8:8cÞ
From equations indicated in (8.8), D(s) of the QO in Fig. 8.5 is calculated as
DðsÞ = s2 C 1 C 2 R1 R2 þ sC 2 ðR2 - R1 Þ þ 1 = 0 ð8:9Þ
From equation denoted in (8.9), OC and OF are, respectively, found as follows:
R1 ≥ R2 ð8:10aÞ
1 1
f0 = ×p ð8:10bÞ
2π C1 C2 R1 R2
If the analysis of the QO in Fig. 8.6 is achieved [10], the same D(s) value evaluated
for the circuit in Fig. 8.5 is found.
8.3 CCII
Symbol of the dual-output CCII (DO-CCII) is exhibited in Fig. 8.7. If one of the Z-
or Z+ terminal of this DO-CCII is removed, plus-type CCII (CCII+) and minus-type
CCII (CCII-) are, respectively, obtained. This DO-CCII is defined in the matrix
equation (8.11).
Fig. 8.7 Symbol of the VY Y Z+ VZ+

DO-CCII IY IZ+
DO-CCII
VX X Z- VZ-
IX IZ-
Fig. 8.8 INIC design based

Z+
on the CCII
V1 X CCII V2
I1 I2
Y
Fig. 8.9 VF design based

on the CCII
VY Y CCII X VX
IY IX
Z+ Z-
Fig. 8.10 CF design based VZ+

Z+
on the CCII IZ+
VX X CCII
IX
Y Z- VZ-
IZ-
VX 1 0
IY 0 0 VY
= ð8:11Þ
I Zþ 0 1 IX
IZ - 0 -1
8.3.1 Realizations of the Other Active Devices Based

on the CCII
Example 8.5 Implement the current negative impedance converter (INIC), VF, and
current follower (CF) by utilizing the CCII.
Solution 8.5 The INIC, VF, and CF implementations based on the CCII are,
respectively, demonstrated in Figs. 8.8, 8.9, and 8.10.
8.3 CCII 195
8.3.2 Realizations of the Instrumentation Amplifier Based

on the CCII
Example 8.6 Find the output voltage of the instrumentation amplifier (IA) in
Fig. 8.11 [11].
Solution 8.6 Analysis of the IA in Fig. 8.11 is carried out by
R2
V out = ðV - V 1 Þ = A v ðV 2 - V 1 Þ ð8:12Þ
R1 2
Here, Av = R2/R1.
8.3.3 Realizations of the Simulated Inductors Based

on the CCII
Example 8.7 Find the input impedance of the SGI designs in Figs. 8.12 [12] and
8.13 [13].
Solution 8.7 Analysis of the SGIs in Fig. 8.12 and 8.13 is achieved by the following
two equations:
V test
I in = ð8:13aÞ
R1
V in V
= V test sC ) V test = in ð8:13bÞ
R2 sCR2
If Vtest in Eq. (8.13b) is replaced into Eq. (8.13a), the following input current is
obtained as
Fig. 8.11 IA realization V2 Y (1)

based on the CCII
CCII Z+ Vout
X
R2
R1
V1 Y X
CCII Z+
(2)
Fig. 8.12 The SGI X

realization based on the R1
CCII Z- CCII
(1) Y
Vin Vtest
Iin C
Z+
Y CCII
Zin (2) X
R2
Fig. 8.13 Another SGI Vin X (1)

implementation based on the Iin
CCII CCII
Z- Y
Zin
Vtest Y (2) Z+
CCII
X
R1 R2
V in
V test V in
I in = = sCR2 = ð8:14Þ
R1 R1 sCR1 R2
From above equation, input impedance of the SGIs in Figs. 8.12 and 8.13 is found as
V in
I in
where Leq = CR1R2.

Example 8.8 Find the admittance matrix equation of the SFI shown in
Fig. 8.14 [14].
Solution 8.8 Analysis of the SFI in Fig. 8.14 is accomplished by the following three
equations:
8.3 CCII 197
X X
R1
V1 Z+ CCII CCII Z+ V2
I1 I2
(1) Y Y (2)
Z+ Z+
Y CCII Vtest C CCII Y

(3) X X (4)
R2
Fig. 8.14 The SFI implementation based on the CCII
I2 = - I1 ð8:16aÞ
V test
I1 = ð8:16bÞ
R1
V1 - V2 V - V2
V test sC = ) V test = 1 ð8:16cÞ
R2 sCR2
If Vtest in Eq. (8.16c) is replaced into equation denoted in (8.16b), the currents I1 and
I2 are, respectively, obtained as follows:
V1 - V2
I1 = ð8:17aÞ
sCR1 R2
V1 - V2
I2 = - ð8:17bÞ
sCR1 R2
Hence, the SFI of Fig. 8.14 is expressed by the following matrix equation:
I1 1 1 -1 V1 1 1 -1 V1
= = ð8:18Þ
I2 s C R1 R2 -1 1 V2 s Leq -1 1 V2
Here, Leq = CR1R2.

Example 8.9 Find the admittance matrix equation of the SFI in Fig. 8.15 [15].
Solution 8.9 Analysis of the SFI in Fig. 8.15 is accomplished by the following three
equations:
I2 = - I1 ð8:19aÞ
V test
I1 = - ð8:19bÞ
R2
R2
V1 X Z- X Z+
I1 R1 Vtest
CCII CCII
Y (1) Z+ Y (2) Z-
V2
I2
Fig. 8.15 The SFI based on the CCII
R1
X (2) Z+
Io1
CCII
Vo2
Z+ (1) Z- Y Z-
Io2
CCII C2
Vo1 Y X
C1
R2
Fig. 8.16 The QO based on the CCII
V1 - V2 V - V2
V test sC = - ) V test = - 1 ð8:19cÞ
R1 sCR1
If Vtest in Eq. (8.19c) is replaced into equation denoted in (8.19b), the same currents
I1 and I2 are obtained as given for the SFI in Fig. 8.14.
8.3 CCII 199
8.3.4 Realizations of the QOs Based on the CCII
Example 8.10 Find D(s), OC, and OF of the QO in Fig. 8.16 [16].
Solution 8.10 Analysis of the QO in Fig. 8.16 is accomplished by the following two
equations:
V o1
= - V o2 sC 2 ) V o1 = - V o2 sC 2 R2 ð8:20aÞ
R2
V o2 - V o1 V V R
= V o1 sC 1 - o1 ) V o2 - V o1 = V o1 sC 1 R1 - o1 1 ð8:20bÞ
R1 R2 R2
If Vo1 in Eq. (8.20a) is replaced into equation denoted in (8.20b), the following
equation is obtained by
V o2 þ V o2 sC 2 R2 = - V o2 s2 C 1 C 2 R1 R2 þ V o2 sC 2 R1 ð8:21Þ
Rearrangement of equation given in (8.21), the following equation is obtained as
V o2 s2 C1 C2 R1 R2 þ sC 2 R2 - sC 2 R1 þ 1 = 0 ð8:22Þ
From above equation, D(s), OC, and OF are, respectively, found as
DðsÞ = s2 C 1 C 2 R1 R2 þ sC 2 ðR2 - R1 Þ þ 1 = 0 ð8:23aÞ

R1 ≥ R2 ð8:23bÞ
1 1
f0 = ×p ð8:23cÞ
2π C1 C2 R1 R2
The output voltage, Vo1, is expressed in terms of Vo2 as
V o1 = - jωC2 R2 V o2 ð8:24Þ
The currents of the QO, Io1 and Io2, are also defined as
V o2 - V o1
I o1 = - I o2 = ð8:25Þ
R1
Example 8.11 Find the D(s), OC, and OF of the QO in Fig. 8.17 [17].
Solution 8.11 Analysis of the QO in Fig. 8.17 is achieved by the following two
equations:
Fig. 8.17 The QO based on

the CCII
C1 R1 R2 C2 R3
Vo1 Y X Z+ Y X
CCII Vo2 CCII
(1) (2)
Z+
R4
Y X
CCII
(3)
Z+
V o1
= V o2 sC 2 ð8:26aÞ
R2
V o1 V o2 V
- = V o1 sC 1 þ o1 ð8:26bÞ
R4 R3 R1
From above equations, D(s), OC, and OF are, respectively, found as follows:
1 1
DðsÞ = s2 C1 C2 R2 R3 þ sC 2 R2 R3 - þ 1=0 ð8:27aÞ
R1 R4
R1 ≥ R4 ð8:27bÞ
1 1
f0 = ×p ð8:27cÞ
2π C1 C2 R2 R3
8.3.5 Realizations of the CCII- Based on the CCII+s
Example 8.12 Implement the CCII- by using the CCII+s.

Solution 8.12 Implementation of the CCII- by using two CCII+s is depicted in
Fig. 8.18.
8.4 CCIII 201
VX X (1) (2)
IX
CCII Z+ X CCII Z+ VZ-
VY Y
IZ-
Y
IY
Fig. 8.18 Realization of the CCII- by utilizing two CCII+s
Fig. 8.19 Symbol of the VZ+

VY Y Z+
DO-CCIII IY IZ+
CCIII
VX X Z- VZ-
IX IZ-
Fig. 8.20 Series RL circuit C

based on the CCIII+
I1
Vin Y Vtest
Iin
CCIII Z+
I1
X
I1
Zin
R2
R1
8.4 CCIII
Symbol of the dual-output CCIII (DO-CCIII) is demonstrated in Fig. 8.19. If one of

the Z- or Z+ terminal of this DO-CCIII is removed, plus-type CCIII (CCIII+) and
minus-type CCIII (CCIII-) are, respectively, obtained. This DO-CCIII is defined in
the matrix equation (8.28).
VX 1 0
IY 0 -1 VY
= ð8:28Þ
I Zþ 0 1 IX
IZ - 0 -1
Example 8.13 Find the input impedance of the series lossy inductor in
Fig. 8.20 [18].
Fig. 8.21 Parallel RL C

circuit based on the CCIII+
I1
Vin X Vtest
Iin
CCIII Z+
I1
Y
I1
Zin
R2
R1
Solution 8.13 The input impedance of the series lossy inductor in Fig. 8.20 is
computed with the following four equations:
V in
Z in = ð8:29aÞ
I in
I in = - I 1 þ ðV in - V test ÞsC ð8:29bÞ
V in V test - V in
I1 = - þ ð8:29cÞ
R1 R2
V in - V test
I 1 = ðV in - V test ÞsC þ ð8:29dÞ
R2
From above equations, the input impedance of the series lossy inductor in Fig. 8.20
is evaluated as
V in
Z in = = sCR1 R2 þ 2R1 = sLeq þ Req ð8:30Þ
I in
Here, Leq = CR1R2 and Req = 2R1.

Example 8.14 Find the input admittance of the parallel lossy inductor in
Fig. 8.21 [18].
Solution 8.14 The input admittance of the parallel lossy inductor in Fig. 8.20 is
calculated with the following four equations:
I in
Y in = ð8:31aÞ
V in
I in = I 1 þ ðV in - V test ÞsC ð8:31bÞ
8.5 CCCII 203
V in V in - V test
I1 = þ ð8:31cÞ
R1 R2
V in - V test
I 1 = ðV in - V test ÞsC þ ð8:31dÞ
R2
From above equations, the input admittance of the parallel lossy inductor in Fig. 8.21
is found below.
I in 1 2 1 1
Y in = = þ = þ ð8:32Þ
V in sCR1 R2 R1 sLeq Req
where Leq = CR1R2 and Req = R1/2.
8.5 CCCII
Symbol of the dual-output CCCII (DO-CCCII) is exhibited in Fig. 8.22. If one of the
Z- or Z+ terminal of this DO-CCCII is removed, plus-type CCCII (CCCII+) and
minus-type CCCII (CCCII-) are respectively obtained. This DO-CCCII is defined
in the matrix equation (8.33), where RX = VT/(2Io) and VT ffi 26 mV at room
temperature [19].
VX 1 RX
IY 0 0 VY
= ð8:33Þ
IZ - 0 -1 IX
I Zþ 0 1
Example 8.15 Find the input impedance of the SGI in Fig. 8.23 [12]. This SGI is
obtained by removing both resistors of one in Fig. 8.12 [12].
Solution 8.15 According to the solution given in Example 8.7 (for circuit of
Fig. 8.12), the input impedance of the SGI in Fig. 8.23 is evaluated as
Fig. 8.22 Symbol of the VY Y VZ+

Z+
DO-CCCII IY IZ+
RX
DO-CCCII
VX X Z- VZ-
IX IZ-
Io
Fig. 8.23 The SGI based on X

the CCCII
Z- CCCII
(1) Y
Vin Io1
Iin C
Z+
Y CCCII
Zin (2) X
Io2
Fig. 8.24 Symbol of the VY Y VZ+

Z+
DO-ICCII IY IZ+
DO-ICCII
VX X Z- VZ-
IX IZ-
V in
Z in = = sCRX1 RX2 = sLeq ð8:34Þ
I in
Here, Leq = CRX1RX2.
8.6 ICCII
Symbol of the dual-output ICCII (DO-ICCII) is demonstrated in Fig. 8.24. If one of

the Z- or Z+ terminal of this DO-ICCII is removed, plus-type ICCII (ICCII+) and
minus-type ICCII (ICCII-) are respectively obtained. This DO-ICCII is defined in
the matrix equation (8.35).
VX -1 0
IY 0 0 VY
= ð8:35Þ
I Zþ 0 1 IX
IZ - 0 -1
Example 8.16 Find the transfer functions (TFs) of the first-order current-mode
(CM) universal filter in Fig. 8.25 [20].
8.6 ICCII 205
Fig. 8.25 The DO-ICCII- C

based first-order CM
universal filter
Vtest
Iin Z-
ILP
Y
R ICCII
X Z+
IAP
Solution 8.16 The input current of the universal filter of Fig. 8.25 is expressed as
2V test
I in = þ V test × sC ð8:36Þ
R
From above equation, Vtest is found as follows:
RI in
V test = ð8:37Þ
2 þ sCR
The first-order low-pass filter (LPF) response by using the equation denoted in (8.37)
is evaluated by
2V test 2I in
I LP = = ð8:38Þ
R 2 þ sCR
From above equation, TF of the LPF is computed as
I LP 1
= ð8:39Þ
I in 1 þ 0:5sCR
TF of the first-order CM all-pass filter (APF) is calculated as follows:
I AP 1 - 0:5sCR
=- ð8:40Þ
I in 1 þ 0:5sCR
From equations indicated in (8.39) and (8.40), the angular pole frequency is calcu-
lated as ω0 = 1/(0.5RC). The phase angle is also evaluated as
∠ðI AP =I in Þ = 180o - 2 tan - 1 ð0:5ωCRÞ ð8:41Þ
By interconnection of low-pass and all-pass currents in Fig. 8.25, a first-order high-

pass current is easily obtained. Thus, the TF of the high-pass filter is found as
I HP 0:5sCR
= ð8:42Þ
I in 1 þ 0:5sCR
8.7 DCCII
Symbol of the dual-output DCCII (DO-DCCII) is demonstrated in Fig. 8.26. If one

of the Z- or Z+ terminal of this DO-DCCII is removed, plus-type DCCII (DCCII+)
and minus-type DCCII (DCCII-) are respectively obtained. This DO-DCCII is
defined in the matrix equation (8.43).
V XP 1 0 0
V XN 1 0 0 VY
IY = 0 0 0 I XP ð8:43Þ
I Zþ 0 1 -1 I XN
IZ - 0 -1 1
Example 8.17 Find the input impedance of the SGI in Fig. 8.27 [21].
Solution 8.17 The input impedance of the SGI of Fig. 8.27 is evaluated by using the
following seven equations:
V in
Z in = ð8:44aÞ
I in
I Zþ = I XP - I XN ð8:44bÞ
I Z - = I XN - I XP ð8:44cÞ
V Y sC = - I Zþ ð8:44dÞ
VY Y
IY Z+ VZ+
IZ+
VXN XN DO-DCCII
IXN
VXP XP
Z- VZ-
IXP IZ-
Fig. 8.26 The symbol of the DO-DCCII

8.7 DCCII 207
Fig. 8.27 The DO-DCCII-

based SGI
C
Y IZ+
Z+
IXN
XN DO-DCCII
R2 IXP IZ- Iin
XP Z- Vin
R1
Zin
VY Y
IY ZP+ VZP+
IZP+
VXN XN DXCCII
IXN
VXP XP ZN- VZN-
IXP IZN-
Fig. 8.28 The symbol of the DXCCII
VY
I XN = - ð8:44eÞ
R2
V in - V Y
I in = I Z - þ ð8:44fÞ
R1
V in - V Y
I XP = ð8:44gÞ
R1
From above equations, input impedance is calculated as
V in
Z in = = sCR1 R2 þ R1 - R2 = sLeq þ Req ð8:45Þ
I in
Here, Leq = CR1R2 and Req = R1 - R2. If R1 = R2 in Fig. 8.27 is chosen, a positive
lossless SGI is obtained.
8.8 DXCCII
Symbol of the DXCCII is exhibited in Fig. 8.28. This DXCCII is defined in the
matrix equation (8.46).
V XP 1 0 0
V XN -1 0 0 VY
IY = 0 0 0 I XP ð8:46Þ
I ZPþ 0 1 0 I XN
I ZN - 0 0 -1
Example 8.18 Find the input admittance of the SGI in Fig. 8.29 [22].
Solution 8.18 The input admittance of the SGI of Fig. 8.29 is evaluated by using the
I in
Y in = ð8:47aÞ
V in
V test
I in = ðV in - V test ÞsC - ð8:47bÞ
R2
V in
- = ðV test - V in ÞsC ð8:47cÞ
R1
From above equations, input admittance is computed as follows:
Fig. 8.29 The DXCCII-

based SGI
R1
Vin XP XN
Y
Iin
DXCCII
ZP+ ZN-
Zin
Vtest
C
R2
8.9 DVCC 209
I in 1 1 1 1 1
Y in = = þ - = þ ð8:48Þ
V in sCR1 R2 R1 R2 sLeq Req
where Leq = CR1R2 and 1/Req = 1/R1- 1/R2. If R1 = R2 in Fig. 8.27 is chosen, a
positive lossless SGI is obtained.
8.9 DVCC
Symbol of the dual-output DVCC (DO-DVCC) is demonstrated in Fig. 8.30. If one

of the Z- or Z+ terminal of this DO-DVCC is removed, plus-type DVCC (DVCC+)
and minus-type DVCC (DVCC-) are, respectively, obtained. This DO-DVCC is
defined in the matrix equation (8.49).
VX 1 -1 0
I Y1 0 0 0 V Y1
I Y2 = 0 0 0 V Y2 ð8:49Þ
I Zþ 0 0 1 IX
IZ - 0 0 -1
Fig. 8.30 The symbol of VY1 VZ+

Y1 Z+
the DO-DVCC IY1 IZ+
DO-DVCC
VY2 Y2 X Z- VZ-
IY2 IZ-
IX
VX
Fig. 8.31 The DVCC+ V2 Y1

based IA Vout
Z+
DVCC
V1 Y2 X
R2
R1
X
R1
Z+ DVCC
Y2 (1) Y1
Vin Vtest
Iin C
Y1 Z+
Y2 DVCC
Zin (2) X
R2
Fig. 8.32 The DVCC+ based SGI
Fig. 8.33 The DVCC+ Vin X Y2

(1)
based SGI Iin
DVCC
Z+ Y1
Zin
Vtest Y2 (2) Z+
DVCC
Y1 X
R1 R2
Example 8.19 Find the output voltage of the IA in Fig. 8.31 [23].
Solution 8.19 The output voltage of the IA in Fig. 8.31 is found by
R2
V out = ðV - V 1 Þ ð8:50Þ
R1 2
Example 8.20 Find the input impedances of the SGIs in Fig. 8.32 [24] and
Fig. 8.33 [25].
Solution 8.20 The input impedances of the SGIs in Figs. 8.32 and 8.33 are found by
using the following three equations:
8.9 DVCC 211
R1
V1 Y1 X Y2 V2
I1 I2
DVCC (1)
Z+ Z-
C
Vtest
Z- Y1 Z+
DVCC (2)
Y2 X
R2
Fig. 8.34 The DVCC-based SFI
V in
Z in = ð8:51aÞ
I in
V test
I in = - ð8:51bÞ
R1
V in V
V test sC = - ) V test = - in ð8:51cÞ
R2 sCR2
From above equations, the input impedance is evaluated as below.
V in
I in
Here, Leq = CR1R2.

Example 8.21 Find the admittance matrix equation for the SFI in Fig. 8.34 [26].
Solution 8.21 The admittance matrix equation for the SFI in Fig. 8.34 is obtained
by using the following three equations:
I2 = - I1 ð8:53aÞ
Fig. 8.35 The DVCC-

based non-inverting first-
order VM APF Vin X Y2
R
DVCC
Vout
Z- Y1
Vtest
V test
I1 = ð8:53bÞ
R2
V1 - V2 V - V2
V test sC = ) V test = 1 ð8:53cÞ
R1 sCR1
From above equations, the admittance matrix equation for the SFI in Fig. 8.34 is
expressed as
I1 1 1 -1 V1
= ð8:54Þ
I2 s C R1 R2 -1 1 V2
Example 8.22 Find the TF of the APF depicted in Fig. 8.35 [27].
Solution 8.22 The TF of the APF in 8.35 is found by using the following two
equations:
V in - V out
= V test sC ð8:55aÞ
R
V out = V test - V in ð8:55bÞ
From above equations, the TF of the non-inverting first-order VM APF is computed

as
V out 1 - sCR
= ð8:56Þ
V in 1 þ sCR
Example 8.23 Find the output voltage of the VM full-wave rectifier (FWR) in
Fig. 8.36 [28].
Solution 8.23 Analysis of the FWR of Fig. 8.36 is achieved as in the following:
If vin(t) ≥ 0 is taken, D1 is ON and D2 is OFF. Thus, the following output voltage
is obtained:
8.10 DDCC 213
Y2
(2)
vin(t) Y1 D1 DVCC X vout(t)
(1)
DVCC Z+ Y1 Z+
Y2 X R2
D2
R1
Fig. 8.36 The DVCC-based VM FWR
R2
vout ðt Þ = - 1 vin ðt Þ ð8:57Þ
R1
If R2 = 2R1 for the equation denoted in (8.57) is chosen, the output voltage simplifies
as
vout ðt Þ = vin ðt Þ ð8:58Þ
If vin(t) < 0 is selected, D1 is OFF and D2 is ON. Hence, the output voltage becomes
as follows:
vout ðt Þ = - vin ðt Þ ð8:59Þ
From combination of the equations in (8.58) and (8.59), the following output voltage
is obtained:
vout ðt Þ = jvin ðt Þj ð8:60Þ
8.10 DDCC
Symbol of the dual-output DDCC (DO-DDCC) is given in Fig. 8.37. If one of the
Z- or Z+ terminal of this DO-DDCC is removed, plus-type DDCC (DVCC+) and
minus-type DDCC (DDCC-) are, respectively, obtained. This DO-DDCC is defined
in the matrix equation (8.61).

VY1 Y1 Z+ VZ+
the DO-DDCC IY1 IZ+
VY2 Y2 DO-DDCC
IY2
VY3 Y3 X Z- VZ-
IY3 IZ-
IX
VX
Y2
Y3 DDCC X Vout
Vin Y1 Z+
R
Vtest
C
Fig. 8.38 The DDCC-based first-order VM APF
VX 1 -1 1 0
I Y1 0 0 0 0 V Y1
I Y2 0 0 0 0 V Y2
= ð8:61Þ
I Y3 0 0 0 0 V Y3
I Zþ 0 0 0 1 IX
IZ - 0 0 0 -1
Example 8.24 Find the TF of the APF depicted in Fig. 8.38 [29].
Solution 8.24 The TF of the APF in Fig. 8.38 is found by using the following two
equations:
V in
V test = ð8:62aÞ
1 þ sCR
V out = 2V test - V in ð8:62bÞ
From above equations, the TF of the APF in Fig. 8.38 is evaluated as
V out 1 - sCR
= ð8:63Þ
V in 1 þ sCR
8.10 DDCC 215
Y2 (2)
DDCC X Vout
Vin Y1 (1) Z+ Y1 Z+ Y3
Y3 DDCC Y2 Vtest
X
C
Y1 (2)
DDCC X Vout
Vin Y1 (1) Z+ Y2 Z+ Y3
Y3 DDCC Y2 Vtest
X
C
Example 8.25 Find the TF of the APF shown in Fig. 8.39 [30].
Solution 8.25 The TF of the APF of Fig. 8.39 is computed by using the following
two equations:
2V in
V test = ð8:64aÞ
1 þ sCR
V out = V test - V in ð8:64bÞ
From above equations, the TF of the APF in Fig. 8.39 is found as follows:
V out 1 - sCR
= ð8:65Þ
V in 1 þ sCR
Example 8.26 Find the TF of the APF shown in Fig. 8.40 [30]. This circuit is found
from the one given in Example 8.25 by interchanging the Y1 and Y2 terminals of the
second DDCC.
Solution 8.26 The TF of the APF of Fig. 8.40 is calculated by using the following
two equations:
2V in
V test = ð8:66aÞ
1 þ sCR
V out = V in - V test ð8:66bÞ
From above equations, the TF of the APF in Fig. 8.40 is found as follows:
V out 1 - sCR
=- ð8:67Þ
V in 1 þ sCR
8.11 FDCCII
The symbol of the FDCCII is demonstrated in Fig. 8.41, while representation of the
FDCCII with matrix equation is given in (8.68).
VY1 Y1 ZA+ VZA+

IY1 IZA+
VY2 Y2 ZA- VZA-
IY2
VY3
FDCCII IZA-
Y3 ZB+ VZB+
IY3 IZB+
VY4 Y4 XA XB ZB- VZB-
IY4 IZB-
IXA IXB
VXA VXB
Fig. 8.41 The symbol of the FDCCII

8.11 FDCCII 217
Fig. 8.42 The FDCCII-

based SGI
Y1 Y2 ZA- ZB+
Vin ZB- Y4
Iin FDCCII
Y3 ZA+
XA XB
Zin
C
R1 R2
V XA 1 -1 1 0 0 0
V XB -1 1 0 1 0 0
I Y1 0 0 0 0 0 0 V Y1
I Y2 0 0 0 0 0 0 V Y2
I Y3 0 0 0 0 0 0 V Y3
= ð8:68Þ
I Y4 0 0 0 0 0 0 V Y4
I ZAþ 0 0 0 0 1 0 I XA
I ZA - 0 0 0 0 -1 0 I XB
I ZBþ 0 0 0 0 0 1
I ZB - 0 0 0 0 0 -1
Example 8.27 Find the input impedance of the SGI shown in Fig. 8.42 [31].
Solution 8.27 The input impedance of the SGI in Fig. 8.42 is found by using the
following six equations:
V in
Z in = ð8:69aÞ
I in
V Y3 = V in ð8:69bÞ
V XA = V Y3 ð8:69cÞ
V XB = V Y4 ð8:69dÞ
V XB
I in = ð8:69eÞ
R2
IY1
VY1 Y1 Z+ VZA+
(1) IZA+
VY2 Y2 DO-DDCC
IY2
VY3 Y3 X Z- VZA-
IY3 IZA-
IXA
VXA
Y1 Z+ VZB+
(2) IZB+
Y2 DO-DDCC
VY4 Y3 X Z- VZB-
IY4 IZB-
IXB
VXB
Fig. 8.43 Realization of the FDCCII by utilizing two DO-DDCCs
V XA V V
= V Y4 sC ) in = V Y4 sC = V XB sC ) V XB = in ð8:69fÞ
R1 R1 sCR1
From above equations, input impedance is found below.
V in
I in
Here, Leq = CR1R2.

Example 8.28 Realize the FDCCII by using the DO-DDCCs.
Solution 8.28 Implementation of the FDCCII by using two DO-DDCCs is given in
Fig. 8.43.
8.12 CDCC
The symbol of the CDCC is exhibited in Fig. 8.44, while representation of the
CDCC with matrix equation is given in (8.71).
8.12 CDCC 219

VP P W+ VW+
the CDCC IP IW+
CDCC
VN N Z X W- VW-
IN IW-
IZ IX
VZ VX
Fig. 8.45 The CDCC-

based topology
Vin P W+
Iin R1
CDCC
N Z X W-
VZ
Zin
C R2
VP 0 0 0 0
VN 0 0 0 0 IP
IZ 1 -1 0 0 IN
= ð8:71Þ
VX 0 0 1 0 VZ
I Wþ 0 0 0 1 IX
IW - 0 0 0 -1
Example 8.29 Find the input admittance of the circuit in Fig. 8.45 [32].
Solution 8.29 The input admittance of the circuit given in Fig. 8.45 is computed by
using the following six equations:
I in
Y in = ð8:72aÞ
V in
IN = 0 ð8:72bÞ
V in V
I Z = I P ) - V Z sC = ) V Z = - in ð8:72cÞ
R1 sCR1
(1)
Vin Y VF X P (2) W+
Iin R1
CDCC
N Z X W-
VZ
Zin
C R2
Fig. 8.46 The CDCC-based SGI
- VX V
I Wþ = I X = =- Z ð8:72dÞ
R2 R2
V in
I in = I Wþ þ ð8:72eÞ
R1
V in V
I in = þ in ð8:72fÞ
sCR1 R2 R1
From above equations, input admittance is evaluated as
I in 1 1 1 1
Y in = = þ = þ ð8:73Þ
where Leq = CR1R2 and Req = R1. So, the circuit realizes parallel Req and Leq.
Example 8.30 Find the input admittance of the circuit in Fig. 8.46 [33].
Solution 8.30 The input admittance of the SGI in Fig. 8.46 is computed by using
the following six equations:
I in
Y in = ð8:74aÞ
V in
IN = 0 ð8:74bÞ
V in V
I Z = I P ) - V Z sC = ) V Z = - in ð8:74cÞ
R1 sCR1
- VX V
I Wþ = I X = =- Z ð8:74dÞ
R2 R2
I in = I Wþ ð8:74eÞ
8.13 EX-CCCII 221
V in
I in = ð8:74fÞ
sCR1 R2
From above equations, input admittance is computed as follows:
I in 1 1
Y in = = = ð8:75Þ
V in sCR1 R2 sLeq
where Leq = CR1R2. So, the circuit realizes pure (lossless) inductance Leq.
8.13 EX-CCCII
The symbol of the EX-CCCII is exhibited in Fig. 8.47, while presentation of the
EX-CCCII with matrix equation is given in (8.76). In this active block, RX is a
function of external current Io.
IY 0 0 0
V X1 1 RX1 0
V X2 1 0 RX2 VY
I Z1þ = 0 1 0 I X1 ð8:76Þ
I Z1 - 0 -1 0 I X2
I Z2þ 0 0 1
I Z2 - 0 0 -1
Io
Z1+ VZ1+
IZ1+
Z1- VZ1-
VY
IY
Y EX-CCCII Z2+
IZ1-
VZ2+
IZ2+
X1 X2 Z2- VZ2-
IZ2-
IX1 IX2
VX1 VX2
Fig. 8.47 The symbol of the EX-CCCII

Fig. 8.48 The EX-CCCII-

based SGI Io
I2
Z1-
Iin
Vin Y
EX-CCCII
Z2+
I1
X1 X2 Z2- Z1+
Zin
Vtest
C
Example 8.31 Find the input impedance of the SGI shown in Fig. 8.48 [34].
Solution 8.31 The input impedance of the SGI is calculated by using the following
five equations:
V in
Z in = ð8:77aÞ
I in
I in = I 1 þ I 2 ð8:77bÞ
V test - V in
I1 = ð8:77cÞ
RX2
I 2 = V test sC ð8:77dÞ
V in
I2 = ð8:77eÞ
RX1
From above equations and considering IZ2- = -IX2, the input impedance of the SGI
in Fig. 8.48 is found by
V in sCRX1 RX2
Z in = = ð8:78Þ
I in 1 þ sC ðRX2 - RX1 Þ
One observes from the equation denoted in (8.78) that the SGI in Fig. 8.48 needs a
single active element matching condition, RX1 = RX2, to provide a positive lossless
SGI.
References 223
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Chapter 9
Other Active Devices
9.1 Introduction
In this chapter, other active elements such as current feedback operational amplifier
(CFOA), operational transresistance amplifier (OTRA), four-terminal floating nullor
(FTFN), operational transconductance amplifier (OTA), voltage differencing
inverting buffered amplifier (VDIBA), voltage differencing buffer amplifier
(VDBA), current differencing buffered amplifier (CDBA), current amplifier (CA),
current follower transconductance amplifier (CFTA), current differencing
transconductance amplifier (CDTA), differential voltage current conveyor
transconductance amplifier (DVCCTA), and current operational amplifier (COA)
are treated. Moreover, implementation of the OTRA, FTFN, and CDBA by using
two CFOAs is given.
9.2 CFOA
CFOA is a commercially available active device. In other words, the CFOA can be
easily obtained by using one AD844 [1]. The symbol of the CFOA is shown in
Fig. 9.1, while the current-voltage relationships among terminals of the CFOA can
be expressed in the matrix equation (9.1). Implementation of the CFOA by using one
plus-type second-generation current conveyor (CCII+) and one voltage follower
(VF) is given in Fig. 9.2.
https://doi.org/10.1007/978-3-031-44966-6_9
226 9 Other Active Devices
Fig. 9.1 The symbol of the IY

CFOA VY Y
IW
CFOA W VW
IX Z
VX X
IZ
VZ
IY
VY Y
(1) (2)
CCII Z+ Y VF X VW
IX IW
VX X
IZ
VZ
Fig. 9.2 Realization of the CFOA by using one CCII+ and one VF
Fig. 9.3 The CFOA-based R1

series RL
Vin Y
Iin
CFOA W
Z
X Vtest
R2
Zin
IY 0 0 0 0 IX
IZ 1 0 0 0 VY
= ð9:1Þ
VX 0 1 0 0 VZ
VW 0 0 1 0 IW
Example 9.1 Find the input impedance of the series RL in Fig. 9.3 [2].
Solution 9.1 The input impedance of the series RL in Fig. 9.3 is obtained by using
the following three equations:
9.2 CFOA 227
V in
Z in = ð9:2aÞ
I in
V in - V test
I in = ð9:2bÞ
R1
V test
ðV test - V in ÞsC = - ð9:2cÞ
R2
Rearrangement of the equation in (9.2c), Vtest, is found below.
V in sC
V test = ð9:3Þ
sC þ R12
If Vtest in Eq. (9.3) is replaced into (9.2b), the input current is evaluated as follows:
1
V in sC þ
V in sC R2 V in sC
V in - -
1 1 1
sC þ sC þ sC þ
R2 R2 R2
I in = =
R1 R1
1 1
V in V in × R2
R2 R2
ð9:4Þ
1 1
sC þ sC þ × R2
R2 R2
= =
R1 R1
V in V in 1
×
sCR2 þ 1 sCR2 þ 1 R1 V in
= = =
R1 1 sCR1 R2 þ R1
R1 ×
R1
From above equation, the input impedance is computed as
V in
Z in = = sCR1 R2 þ R1 = sLeq þ Req ð9:5Þ
I in
Here, Leq = CR1R2 and Req = R1.

Example 9.2 Find the input impedance of the simulated grounded inductor (SGI) in
Fig. 9.4 [3].
Solution 9.2 The input impedance of the SGI in Fig. 9.4 is obtained by using the
Vin Y
Iin R2
CFOA W X
(1) Z Z
X CFOA W
Vtest (2)
Y
Zin R1 C
Fig. 9.4 The CFOA-based SGI
V in
Z in = ð9:6aÞ
I in
V test
I in = ð9:6bÞ
R2
V in V
= V test sC ) V test = in ð9:6cÞ
R1 sCR1
If Vtest indicated in (9.6c) is replaced into the equation in (9.6b), the following input
current is obtained:
V in
sCR1 V in
I in = = ð9:7Þ
R2 sCR1 R2
From above equation, the input impedance is calculated as
V in
I in
where Leq = CR1R2.

Example 9.3 Find the input impedance of the CFOA-based SGI demonstrated in
Fig. 9.5 [4]. Also, this SGI has the feature of improved low-frequency performance.
V in
Z in = ð9:9aÞ
I in
V test
I in = - ð9:9bÞ
R1
9.2 CFOA 229
X
(1)
W CFOA
Z
Y
Y
(2)
Vtest CFOA W
C R3 Z R2
X
R1 Iin
Zin Vin
Fig. 9.5 The CFOA-based SGI with the property of improved low-frequency performance
Y
(1) R
CFOA W X
Z (2)
Vin X CFOA W
Iin Vtest Z
Y
C1
C2
Zin
Fig. 9.6 The CFOA-based grounded FDNR
V in - V test - V test
= - V test sC ð9:9cÞ
R2 R3
From above equations, the input impedance is calculated as
V in R
Z in = = sCR1 R2 þ R1 2 - 1 ð9:10Þ
I in R3
In equation denoted in (9.10), if R3 = R2 is taken, a positive lossless SGI is obtained.

Example 9.4 Find the input impedance of the CFOA-based grounded frequency-
dependent negative resistor (FDNR) in Fig. 9.6 [5].
Solution 9.4 The input impedance of the FDNR in Fig. 9.6 is obtained by using the
R1
X X
V1 Z Z V2
I1 W CFOA CFOA W I2
(2)
(1)
Y Y
Y C
Z Vtest
CFOA W
(3)
X
R2
Fig. 9.7 The CFOA-based positive lossless SFI
V in
Z in = ð9:11aÞ
I in
I in = - V test sC 1 ð9:11bÞ
V test
= - V in sC 2 ) V test = - V in sC 2 R ð9:11cÞ
R
From above equations, the input impedance is found as
V in 1 1
Z in = = 2 = ð9:12Þ
I in s C 1 C 2 R s2 D
Here, D = C1C2R.
Example 9.5 Find the admittance matrix equation of the CFOA-based simulated
floating inductor (SFI) in Fig. 9.7 [6].
Solution 9.5 The admittance matrix equation of the SFI given in Fig. 9.7 is obtained
by using the following three equations:
I2 = - I1 ð9:13aÞ
V test
I1 = ð9:13bÞ
R1
V1 - V2 V - V2
= V test sC ) V test = 1 ð9:13cÞ
R2 sCR2
From above equations, the following admittance matrix equation is obtained:

9.2 CFOA 231
X
(1)
Vo1 W CFOA
Z
Y
Y
(2)
CFOA W
C1 R3 Z R2
X Vo2
R1
C2
Fig. 9.8 The CFOA-based QO
I1 1 1 -1 V1 1 1 -1 V1
= = ð9:14Þ
I2 s C R1 R2 -1 1 V2 s Leq -1 1 V2
where Leq = CR1R2.

Example 9.6 Find the characteristic eq. (D(s)), oscillation condition (OC), and
oscillation frequency (OF) of the CFOA-based quadrature oscillator (QO) in
Fig. 9.8 [7].
Solution 9.6 The D(s), OC, and OF of the CFOA-based QO shown in Fig. 9.8 are
obtained by using the following two equations:
V o1
= V o2 sC 2 ) V o1 = V o2 sC 2 R1 ð9:15aÞ
R1
V o2 - V o1 V V R
= - V o1 sC 1 - o1 ) V o2 - V o1 = - V o1 sC 1 R2 - o1 2 ð9:15bÞ
R2 R3 R3
From above equations, the D(s), OC, and OF of the CFOA-based QO in Fig. 9.8 are,
respectively, evaluated by
R2
DðsÞ = s2 C 1 C 2 R1 R2 þ sC 2 R1 -1 þ 1=0 ð9:16aÞ
R3
R3 ≥ R2 ð9:16bÞ
1 1
f0 = p ð9:16cÞ
2π C 1 C 2 R1 R2
This QO can be controlled orthogonally by changing value of R1.

9.3 OTRA
The symbol of the OTRA is depicted in Fig. 9.9, while the OTRA can be expressed
by the following matrix equation:
VP 0 0 0 IP
VN = 0 0 0 IN ð9:17Þ
VO Rm - Rm 0 IO
Here, Rm is ideally infinity.

Example 9.7 Find the input impedance of the OTRA-based SGI demonstrated in
Fig. 9.10 [8].
following five equations:
V in
Z in = ð9:18aÞ
I in
V in V - Vo
I in = þ V in s3C þ in ð9:18bÞ
R R
V o = I P Rm - I N Rm ð9:18cÞ
I P = V in s3C ð9:18dÞ
Fig. 9.9 The symbol of the

VP P
OTRA IP
OTRA O VO
IO
VN N
IN
Fig. 9.10 The OTRA- R

based SGI
R C
R
Vin N
Iin
OTRA O
P
3C
Zin
9.3 OTRA 233
Fig. 9.11 The OTRA-

P
based non-inverting first-
order VM APF OTRA O
R/
R/ C
Vin Vout
R
V in Vo
= IN - ð9:18eÞ
R R þ sC
1
From above equations, input impedance is computed as
V in R2 ðsCR þ sCR þ 1Þ
Z in = = 2 2 3 m ð9:19Þ
I in s 3C R þ s5CR2 þ 2R þ Rm
Here, if Rm goes to infinity, the input impedance simplifies as
V in R2 sCRm
Z in = = = sCR2 = sLeq ð9:20Þ
I in Rm
where Leq = CR2.

Example 9.8 Find the transfer function (TF) of the OTRA-based non-inverting
first-order voltage-mode (VM) all-pass filter (APF) in Fig. 9.11 [9].
Solution 9.8 The TF of the OTRA-based non-inverting first-order VM APF in
Fig. 9.11 is calculated by using the following four equations:
V out
H ðsÞ = ð9:21aÞ
V in
V in V o
IN = þ ð9:21bÞ
R= R=
I P = 0 ) V o = - I N Rm ð9:21cÞ
V in - V out
= ðV out - V o ÞsC ð9:21dÞ
R
From above equations, and assuming Rm goes to infinity, the TF is found and
simplified as follows:
Fig. 9.12 Implementation

of the OTRA by using two Y
(1)
CFOAs
CFOA W
IP Z
VP X
VN X
IN (2) IO
CFOA W VO
Z
Y
Fig. 9.13 The symbol of VZ

VX X Z
the FTFN IX IZ
FTFN
VY Y W VW
IY IW
V out R= þ Rm ð1 - sCRÞ
H ðsÞ = = =
V in R þ Rm ð1 þ sCRÞ
ð9:22Þ
R ð1 - sCRÞ 1 - sCR
= m =
Rm ð1 þ sCRÞ 1 þ sCR
Note The topology in Fig. 9.11 has a single passive resistive matching condition.
Also, if R and C are interchanged in Fig. 9.11, an inverting first-order VM APF can
be easily obtained.
Example 9.9 Realize the OTRA with CFOAs.
Solution 9.9 Realization of the OTRA by using two CFOAs is demonstrated in
Fig. 9.12.
9.4 FTFN
The symbol of the FTFN is illustrated in Fig. 9.13, while the FTFN can be expressed
with the matrix equation in (9.23).
9.4 FTFN 235
Fig. 9.14 The NFTFN- C

based inverting first-order
VM APF circuit
Vin X Z Vout
NFTFN
Y W R
IY 0 0 0 0 VY
IX 0 0 0 0 IZ
= ð9:23Þ
VX 1 0 0 0 VZ
IW 0 ∓1 0 0 VW
Here, - and + sign correspond to minus-type FTFN (NFTFN) and plus-type FTFN
(PFTFN), respectively.
Example 9.10 Find the TF of the NFTFN-based inverting first-order VM APF in
Fig. 9.14 [10].
Solution 9.10 The TF of the NFTFN-based inverting first-order VM APF in
Fig. 9.14 is computed by using the following two equations:
V out
H ðsÞ = ð9:24aÞ
V in
V in V out
ðV in - V out ÞsC = þ ð9:24bÞ
R R
From above equations, the following TF is found:
V out 1 - sCR
H ðsÞ = =- ð9:25Þ
V in 1 þ sCR
Example 9.11 Find the input admittance of the PFTFN-based SGI depicted in
Fig. 9.15 [11].
Solution 9.11 The input admittance of the PFTFN-based SGI in Fig. 9.15 is found
by using the following five equations:
Fig. 9.15 The PFTFN- R3

based SGI
R4
R2
Vin W X
Iin I1
PFTFN V1
Z Y
I1
Zin V2
C
R1
I in
Y in = ð9:26aÞ
V in
V in - V 1 V in - V 1
I in = I 1 þ þ ð9:26bÞ
R4 R3
V in - V 1 V 1
= ð9:26cÞ
R4 R2
V2
ðV 1 - V 2 ÞsC = I 1 þ ð9:26dÞ
R1
V in - V 1
= ðV 1 - V 2 ÞsC ð9:26eÞ
R3
From above equations, the input admittance is evaluated as
I in 1 1 R R 1 1
Y in = = þ 1þ2 4 - 2 = þ ð9:27Þ
V in sCR R 1 þ R2 R2 þ R4 R3 R1 sLeq Req
1 3 R4
where Leq and Req are, respectively, found by
R2
Leq = CR1 R3 1 þ ð9:28aÞ
R4
1
Req = ð9:28bÞ
1
R2 þR4 1 þ 2 RR43 - R2
R1
If Req is taken as infinity, a positive lossless SGI is obtained, which is achieved with
the following condition:
9.4 FTFN 237
Fig. 9.16 The PFTFN- R2

based parallel RL topology
Vin W X
Iin I1
PFTFN
Z Y
I1
Zin Vtest
C
R1
R4 R2
1þ2 = ð9:29Þ
R3 R1
Example 9.12 Find the input admittance of the PFTFN-based parallel RL circuit in
Fig. 9.16 [11].
Solution 9.12 The input admittance of the PFTFN-based parallel RL structure in
Fig. 9.16 is found by using the following four equations:
I in
Y in = ð9:30aÞ
V in
V in
I in = I 1 þ ð9:30bÞ
R2
V test
- V test sC = I 1 þ ð9:30cÞ
R1
V in
= - V test sC ð9:30dÞ
R2
From above equations, the input admittance is calculated as follows:
I in 1 2 1 1
Y in = = þ = þ ð9:31Þ
Here, Leq = CR1R2 and Req = R2/2.

Example 9.13 Find the input impedance of the PFTFN and INIC-based parallel
SGI in Fig. 9.17 [12].
Solution 9.13 The input impedance of the PFTFN and INIC-based parallel SGI in
Fig. 9.17 is found by using the following four equations:
R2
1 INIC 2
Vin W X
Iin I1
PFTFN
Z Y
I1
Zin Vtest
C
R1
Fig. 9.17 The PFTFN and INIC-based positive lossless SGI
V in
Z in = ð9:32aÞ
I in
V in
I in = I 1 - ð9:32bÞ
R2
V test
- V test sC = I 1 þ ð9:32cÞ
R1
V in
= - V test sC ð9:32dÞ
R2
From above equations, the input impedance is calculated by
V in
I in
Here, Leq = CR1R2.

Example 9.14 Implement the NFTFN and PFTFN by using the CFOAs.
Solution 9.14 Implementations of the NFTFN and PFTFN by using two CFOAs
are, respectively, shown in Figs. 9.18 and 9.19 [13].
9.5 OTA
The symbol of the dual output OTA (DO-OTA) is given in Fig. 9.20. The DO-OTA
can be expressed with the following matrix equation:
9.5 OTA 239
Fig. 9.18 NFTFN IX

implementation based on VX Y IW
VW
two CFOAs (1) Z
CFOA W
X
X
(2)
CFOA W
Z VZ
VY Y IZ
IY
IW
VW
X
(2)
IX CFOA W
VX X Z
Y VZ
(1) Z IZ
CFOA W
VY Y
IY
Fig. 9.19 PFTFN realization based on two CFOAs

V1 +
the DO-OTA I1 O+ VO+
DO-OTA IO+
O- VO-
V2 - IO-
I2
I1 0 0 0 0 V1
I2 0 0 0 0 V2
= ð9:34Þ
I Oþ - gm gm 0 0 V Oþ
IO - gm - gm 0 0 VO -
Example 9.15 Find the input impedance of the OTA-based positive lossless SGI in
Fig. 9.21 [14].
Solution 9.15 The input impedance of the OTA-based positive lossless SGI in
Fig. 9.21 is found by using the following five equations:
Vin + Vtest
Iin (1)
OTA O+ -
(2)
- OTA O+
C +
Zin
Fig. 9.21 The OTA-based SGI topology

V1 + W VW
the VDIBA I1 IW
VDIBA
V2 - Z VZ
I2 IZ
V in
Z in = ð9:35aÞ
I in
I O1þ = - V 1þ gm1 ð9:35bÞ
V in = V 1þ ð9:35cÞ
I O1þ = - V test sC ð9:35dÞ
I in = V 2 - gm2 = V test gm2 ð9:35eÞ
From above equations, the input impedance is computed as
V in sC
Z in = = = sLeq ð9:36Þ
I in gm1 gm2
where Leq = C/(gm1gm2).
9.6 VDIBA
The symbol of the VDIBA is shown in Fig. 9.22. The VDIBA can be defined with
the following matrix equation:
9.6 VDIBA 241
Fig. 9.23 The VDIBA-

based first-order VM APF
structure + W Vo1
VDIBA
Vin - Z Vo2
I1 0 0 0 0 V1
I2 0 0 0 0 V2
= ð9:37Þ
IZ - gm gm 0 0 VZ
VW 0 0 -1 0 IW
Example 9.16 Find the TFs of the VDIBA-based first-order VM APF in Fig. 9.23
[15]. This filter simultaneously provides both non-inverting and inverting responses.
Solution 9.16 The TFs of the VDIBA-based first-order VM APF in Fig. 9.23 are
evaluated by using the following four equations:
V o1
H 1 ðsÞ = ð9:38aÞ
V in
V o2
H 2 ðsÞ = ð9:38bÞ
V in
V o1 = - V o2 ð9:38cÞ
I Z = ðV in - V o2 ÞsC = gm ðV in - V o1 Þ ð9:38dÞ
From above equations, the following non-inverting and inverting first-order VM TFs
are, respectively, obtained:
V o1 g - sC 1 - gsC
H 1 ðsÞ = = m = m
ð9:39aÞ
V in gm þ sC 1 þ sC
g m
V o2 g - sC 1 - sC
gm
H 2 ðsÞ = =- m =- ð9:39bÞ
V in gm þ sC 1 þ sC
g m
9.7 VDBA
The symbol of the VDBA is demonstrated in Fig. 9.24. The VDBA can be expressed
with the following matrix equation:
IP 0 0 0
IN 0 0 0 VP
IZ = - gm gm 0 VN ð9:40Þ
I ZC - gm - gm 0 VZ
VW 0 0 1
Example 9.17 Find the input impedance of the VDBA-based positive lossless SGI
in Fig. 9.25 [16].
Solution 9.17 The input impedance of the VDBA-based positive lossless SGI in
Fig. 9.25 is calculated by using the following three equations:

VP P W VW
the VDBA IP IW
VDBA
VN N ZC- Z VZ
IN IZ
IZC-
VZC-
Fig. 9.25 The VDBA- R

based SGI circuit
P W
VDBA
Vin N ZC- Z
Iin
Vtest
C
Zin
9.8 CDBA 243
V in
Z in = ð9:41aÞ
I in
V in - V test
I in = ð9:41bÞ
R
I Z = V in gm = ðV in - V test ÞsC ð9:41cÞ
From above equations, the input impedance is found below.
V in sCR
I in gm
Here, Leq = CR/gm.
9.8 CDBA
The symbol of the CDBA is depicted in Fig. 9.26. The CDBA can be defined with
the following matrix equation:
VP 0 0 0 0 IP
VN 0 0 0 0 IN
= ð9:43Þ
IZ -1 1 0 0 VZ
VW 0 0 1 0 IW
Example 9.18 Find the input impedance of the CDBA-based positive lossless SGI
in Fig. 9.27 [17].
Solution 9.18 The input impedance of the CDBA-based positive lossless SGI in
Fig. 9.27 is computed by using the following five equations:
V in
Z in = ð9:44aÞ
I in
V test
I in = I Z1 = I N1 = ð9:44bÞ
R2

VP P W VW
the CDBA IP IW
CDBA
VN N Z VZ
IN IZ
Fig. 9.27 The CDBA-

Vin Z (1) P
based SGI circuit Iin
CDBA
W N
Zin R1 R2
P (2) W
CDBA
Vtest
N Z
Fig. 9.28 Implementation

of the CDBA by using two Y
(1)
CFOAs
CFOA W
IP Z
VP X
VN X IZ
IN VZ
(2) Z
VW
CFOA W IW
Y
I Z2 = - I P2 ð9:44cÞ
V in
I P2 = ð9:44dÞ
R1
I Z2 = - V test sC ð9:44eÞ
V in
I in
where Leq = CR1R2.

Example 9.19 Realize the CDBA by using CFOAs.
Solution 9.19 Realization of the CDBA by using two CFOAs is depicted in
Fig. 9.28.
9.9 CA 245
9.9 CA
The symbol of the CA is given in Fig. 9.29. The CA can be defined with the
following matrix equation:
I in gm 0 0 V in
I outþ = - gm 0 0 V outþ ð9:46Þ
I out - gm 0 0 V out -
Example 9.20 Find the input impedance of the CA-based positive lossless SGI in
Fig. 9.30 [18].
Solution 9.20 The input impedance of the CA-based positive lossless SGI in
Fig. 9.30 is calculated by using the following three equations:
V in
Z in = ð9:47aÞ
I in
I in = V test gm2 ð9:47bÞ
gm1 V in
gm1 V in = V test sC ) V test = ð9:47cÞ
sC

the CA
OUT+ Vout+
Iout+
Vin IN CA
Iin OUT- Vout-
Iout-
Fig. 9.30 The CA-based

SGI topology
(1) OUT+
Vin IN CA Vtest
Iin OUT+
C
Zin OUT- (2)

CA IN
OUT+
V in sC
I in gm1 gm2
9.10 CFTA
The symbol of the CFTA is shown in Fig. 9.31. The CFTA can be defined with the
VF 0 0 0 0 IF
IZ 1 0 0 0 VZ
= ð9:49Þ
I Xþ 0 gm 0 0 V Xþ
IX - 0 - gm 0 0 VX -
Example 9.21 Find the input impedance of the CFTA-based positive lossless SGI
in Fig. 9.32 [19].
Solution 9.21 The input impedance of the CFTA-based positive lossless SGI in
Fig. 9.32 is evaluated by using the following four equations:

VF F X+ VX+
the CFTA IF IX+
CFTA
VZ Z X- VX-
IZ IX-
Fig. 9.32 The CFTA-based X+

(1)
SGI structure
Vin Z CFTA
Iin
X- F
Zin F (2) X+
CFTA
Z X-
C
9.11 CDTA 247
V in
Z in = ð9:50aÞ
I in
I in = I F1 = - I X2þ = - gm2 V Z2 ð9:50bÞ
I F2 = I Z2 = - I X1 - = gm1 V in ð9:50cÞ
I Z2
V Z2 = - ð9:50dÞ
sC
From above equations, the input impedance is found as follows:
V in sC
I in gm1 gm2
9.11 CDTA
The symbol of the CDTA is given in Fig. 9.33. The CDTA can be expressed with the
VP 0 0 0 0 0 IP
VN 0 0 0 0 0 IN
IZ = -1 1 0 0 0 VZ ð9:52Þ
I Xþ 0 0 - gm 0 0 V Xþ
IX - 0 0 gm 0 0 VX -
Example 9.22 Find the input impedance of the CDTA-based SGI in Fig. 9.34 [20].
Solution 9.22 The input impedance of the CDTA-based positive lossless SGI in
Fig. 9.34 is found by using the following eight equations:

VP P X+ VX+
the CDTA IP IX+
CDTA
VN N Z X- VX-
IN IX-
IZ
VZ
N (1) X+ P (2) X+
CDTA CDTA
P Z X- N Z X-
Vin C
Iin
Zin
Fig. 9.34 The CDTA-based SGI circuit
V in
Z in = ð9:53aÞ
I in
I in = I N1 - I P1 ð9:53bÞ
I N1 = gm2 V Z2 ð9:53cÞ
I P1 = - gm2 V Z2 ð9:53dÞ
I Z2 = - sCV Z2 ð9:53eÞ
I Z2 = I N2 - I P2 ð9:53f Þ
I N2 = - gm1 V in ð9:53gÞ
I P2 = gm1 V in ð9:53gÞ
From above equations, the input impedance is found below.
V in sC
I in 4gm1 gm2
Here, Leq = C/(4gm1gm2).
9.12 DVCCTA
The symbol of the dual output DVCCTA (DO-DVCCTA) is demonstrated in

Fig. 9.35. The DO-DVCCTA can be defined with the following matrix equation:
9.12 DVCCTA 249
Fig. 9.35 The symbol of IY1

the DO-DVCCTA VY1 Y1 O+ VO+
IO+
DO-DVCCTA
VY2 Y2 X Z O- VO-
IY2 IO-
IX IZ
VX VZ
Fig. 9.36 The DO-

DVCCTA-based SFI circuit I1
V1 Y1 O-
DO-DVCCTA
V2 Y2 X Z O+
I2
R C
I Y1 0 0 0 0 0 0 V Y1
I Y2 0 0 0 0 0 0 V Y2
VX 1 -1 0 0 0 0 IX
= ð9:55Þ
IZ 0 0 1 0 0 0 VZ
I Oþ 0 0 0 - gm 0 0 V Oþ
IO - 0 0 0 gm 0 0 VO -
Example 9.23 Find the admittance matrix equation of the DO-DVCCTA-based

positive lossless SFI in Fig. 9.36 [21].
Solution 9.23 The admittance matrix equation of the DO-DVCCTA-based positive
lossless SFI in Fig. 9.36 is calculated by using the following five equations:
I2 = - I1 ð9:56aÞ
VX = V1 - V2 ð9:56bÞ
VX
= V Z sC ð9:56cÞ
R
I 1 = gm V Z ð9:56dÞ
I 2 = - gm V Z ð9:56eÞ
From above equations, the admittance matrix equation is computed by
I1 g 1 -1 V1 1 1 -1 V1
= m = ð9:57Þ
I2 sCR -1 1 V2 sLeq -1 1 V2
where Leq = CR/gm.
9.13 COA
The symbol of the COA is given in Fig. 9.37. The COA can be expressed by the
following four equations:
VP = 0 ð9:58aÞ
VN = 0 ð9:58bÞ
I Z = B ðI N - I P Þ ð9:58cÞ
IW = - IZ ð9:58dÞ
Here, B is ideally infinity.

Example 9.24 Find the TF of the COA-based non-inverting first-order current-
mode APF in Fig. 9.38 [22].
Solution 9.24 The TF of the COA-based non-inverting first-order current-mode
APF in Fig. 9.38 is computed by using the following six equations:
Fig. 9.37 The symbol of IP

the COA VP P IZ
Z VZ
COA
W VW
VN N IW
IN
Fig. 9.38 The COA-based C

first-order APF circuit P Iout
Z
Vtest COA
Iin W
N
R
References 251
1
I in = V test sC þ ð9:59aÞ
R
I out = - I Z ð9:59bÞ
IW = - IZ ð9:59cÞ
I Z = B ðI N - I P Þ ð9:59dÞ
V test
IN = - IW ð9:59eÞ
R
I P = V test sC ð9:59f Þ
From above equations, the TF is computed as follows:
I out ð1 - sCRÞ
= ð9:60Þ
I in 1 - B1 ð1 þ sCRÞ
If B is infinity, equation given in (9.60) simplifies as
I out 1 - sCR
= ð9:61Þ
I in 1 þ sCR
It is observed from equation in (9.61) that a non-inverting first-order APF TF is

obtained. If R and C are interchanged, an inverting first-order APF TF is obtained.
Note One observes throughout of this chapter that other active devices can be easily
obtained from combination of the OTA(s) and CC(s).
References
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16. A. Yesil, F. Kacar, K. Gurkan, Lossless grounded inductance simulator employing single
VDBA and its experimental band-pass filter application. AEU Int. J. Electron. Commun.
68(2), 143–150 (2014)
17. A. Toker, S. Ozoguz, C. Acar, CDBA-based fully-integrated gyrator circuit suitable for
electronically tunable inductance simulation. AEU Int. J. Electron. Commun. 54(5), 293–296
(2000)
18. C. Psychalinos, A. Spanidou, Current amplifier based grounded and floating inductance simu-
lators. AEU Int. J. Electron. Commun. 60(2), 168–171 (2006)
19. N. Herencsar, J. Koton, K. Vrbra, CFTA-based active-C grounded positive inductance simula-
tor and its application. Elektrorevue 1(1), 24–27 (2010)
20. D. Prasad, D.R. Bhaskar, A.K. Singh, New grounded and floating simulated inductance circuits
using current differencing transconductance amplifiers. Radioengineering 19(1), 194–198
(2010)
21. W. Tangsrirat, Floating simulator with a single DVCCTA. Indian J. Eng. Mater. Sci. 20(2),
79–86 (2013)
22. S. Kilinc, U. Cam, Current-mode first-order allpass filter employing single current operational
amplifier. Analog Integr. Circ. Sig. Process 41, 47–53 (2004)
Index
A Current differencing buffered amplifier

Admittance, 35, 36, 42–44, 169, 170, 185, 186, (CDBA), 225, 243–244
196, 197, 202, 203, 208, 211, 212, Current differencing transconductance
219–221, 230, 235–237, 249, 250 amplifier (CDTA), 225, 247–248
All-pass filter (APF), 17–19, 21, 23, 26, 27, 29, Current feedback operational amplifier
31, 75, 78–79, 82, 85, 138, 158–162, (CFOA), 225–231
164, 176–178, 205, 212, 214–216, Current follower (CF), 151–153, 157–163,
233–235, 241, 250 165, 194
Amplifiers, 13, 92–96, 98, 99, 108–120, 144, Current follower transconductance amplifier
149, 154, 191 (CFTA), 225, 246–247
Angular pole frequency, 31, 76, 80, 81, 110, Current-mode (CM), 73, 74, 79–81, 84–86,
111, 116, 205 151, 158, 159, 164, 165, 167, 175, 176,
Angular resonance frequency, 8, 18, 22, 139 178, 179, 204, 205, 250
Attenuator, 154 Current operational amplifier (COA), 225,
250–251
B
Band-pass filter (BPF), 17–20, 22–24, 26, 29, D
82, 83, 85, 86, 141–143 DCCII, 206–207
Bandwidth (BW), 17, 18, 22, 65, 91, Delta function, 2
118–120, 189 Differential difference CC (DDCC), 189,
Bipolar junction transistor (BJT), 9, 98, 99 213–216
Differential voltage CC (DVCC), 189, 209–213
Differential voltage current conveyor
C transconductance amplifier (DVCCTA),
C, 73, 75, 77, 79, 234, 251 225, 248–250
Capacitors, 35–43, 46–49, 51–53, 59–61, Dual output DCCII (DO-DCCII), 206
64, 91 Dual output ICCII (DO-ICCII), 204
Causality, 12, 15 Dual X CCII (DX-CCII), 189
Complex frequency domain, 35
Constant function, 1, 3
Current amplifier, 225 E
Current controlled CCII (CCCII), 189, 203–204 EX-CCCII, 189, 221, 222
Current conveyors (CCs), 189–222, 251 Exponential function, 2, 7, 63
© The Editor(s) (if applicable) and The Author(s), under exclusive license to 253
Springer Nature Switzerland AG 2024
https://doi.org/10.1007/978-3-031-44966-6
254 Index
F Linear time-invariant (LTI), 11, 12, 16, 73

First-generation CC (CCI), 189–193 Linearity, 11, 189
First-order, 29–33, 46, 56, 75–81, 101–103, Lossless, 57–61, 123, 128–132, 165, 169,
138, 156–162, 164, 167, 176–180, 171–173, 184, 185, 190, 207, 209, 221,
204, 205, 212, 214, 215, 233–235, 241, 222, 229, 230, 236, 238, 239, 242, 243,
250, 251 245–247, 249
First-order analog filters, 138 Lossy, 123–128, 168–171, 182, 183, 190,
First-order transfer function, 75–78, 160–162, 201–203
176–178, 180, 204, 212, 233, 235, Low-pass filter (LPF), 17, 19, 22–24, 26–30,
241, 250 32–34, 75–76, 80, 82, 84–86, 101, 102,
Floating, 35, 40–42, 78, 123, 164, 185, 186 139–141, 156, 168, 205
Fourier transforms, 15–16
Four-terminal floating nullor (FTFN), 225,
234, 235 M
Frequency dependent negative resistor Magnitude, 8, 16, 27, 36–40, 43, 44, 57–59,
(FDNR), 229 61, 66–72, 89, 110, 116, 132, 168,
Frequency domain, 16, 22, 23, 26, 27, 31, 35, 169, 171
37, 38, 43, 44, 56, 58–60, 66, 68, 69, 71,
76–78, 110, 116–118, 169, 170
Full-power bandwidth, 149–150 N
Full-wave rectified function, 1 Negative impedance converter (NIC), 175,
Full-wave rectifier (FWR), 2, 4, 11, 132–135, 179–188, 194
212, 213 Non-linearity, v
Fully differential CCII (FDCCII), 189, 216–218 Notch filter (NF), 17–20, 22, 23, 25–27, 82,
83, 85
G
Grounded, 35–39, 123, 181, 229 O
Operating frequency range, 57–60, 168,
169, 171
H Operational amplifier (OA), 89–150, 189
Half-wave rectifiers (HWRs), 132 Operational transconductance amplifier (OTA),
High-order transfer function, vi, 86 225, 238–241, 251
High-pass filter (HPF), 17–19, 21, 23, 25–27, Operational transresistance amplifier (OTRA),
29, 30, 32, 75, 77–78, 80–83, 85, 101, 225, 232–234
102, 157, 168, 205
P
I Parallel, 8, 42, 43, 53, 57–61, 63, 65–68, 70,
ICCII, 189, 204–206 71, 123, 124, 168–171, 182, 202, 203,
Ideal filters, 17–19 220, 237
Ideal first-order filter, 29–34 Passive elements, 8, 35, 36, 86
Ideal OAs, 90–92 Phase, 1, 16, 19–27, 29–34, 36–40, 43, 44,
Ideal second-order filters, 19–29 56–59, 61, 65–72, 76, 77, 79, 86, 92,
Impedance, 2, 73, 123, 151, 181, 190, 226 116, 168, 169, 171, 205
Inductor, 35, 36, 38–42, 46, 54–58, 61, 64, 123, Positive half-wave rectified function, 1
169, 171, 190, 195–198, 201–203 Practical OA, 90
Instrumentation amplifier (IA), 163, 195, 209, Prefixes, 1, 3
210
Q
L Quadrature oscillator (QA), 192, 231
L, 73, 75, 77, 79 Quality factor, 18–22, 24–26, 56, 139
Laplace transform, 15, 73
Index 255
R 218, 219, 221, 225, 226, 232, 234,

R, 73, 75, 79, 155, 156, 178, 182–184, 188, 238–240, 242, 243, 245–250
234, 251 Systems, 1, 2, 11–15, 73
RC circuit, 46, 56, 59, 60, 79
Resistor, 9, 11, 35–41, 43, 46–49, 51, 53, 54,
56, 61, 64, 91, 96, 99, 107, 120, 164, T
203, 229 Third-generation CC (CCIII), 189, 201–203
RL topology, 56, 57, 237 Time domain, 16, 35, 39, 47–56, 97
RLC structure, 64, 71 Time-invariant, 12
Time-variant, v
Total harmonic distortion (THD), 13, 14, 91
S Transadmittance-mode (TAM), 73–75
Sawtooth wave function, 2, 6 Triangular wave function, 2, 6
s domain, 35, 40, 44, 45, 56, 57, 59, 60, 97, 110,
145, 146, 169, 170
Second-generation CC (CCII), 189, 193–201, U
225, 226 Unit ramp functions, 1, 3
Second-order analog filters, 138 Unit step function, 2
Second-order filters, 138 Units, 1–3, 145
Second-order transfer function, 139–143 Unity gain cells (UGCs), 151–173
Second-order universal filter, 19, 27 Unity gain inverting amplifier (UGIA), 82,
Sensitivity, 6–10 175–179, 191
Series, 8, 42, 43, 56, 57, 59, 64–66, 69,
125–127, 183, 201, 202, 226
Signal, 2, 11–15, 39, 92, 144–146 V
Simulated floating inductor (SFI), 190, Voltage differencing buffer amplifier, 225
196–198, 211, 212, 230, 249 Voltage differencing inverting buffered
Simulated grounded inductor (SGI), 123–132, amplifier, 225
165, 168–173, 182–185, 190–192, 195, Voltage follower (VF), 105, 108, 110, 112,
196, 203, 204, 206–210, 217, 220, 222, 145–149, 151, 166, 167, 176, 177, 187,
227–229, 232, 235–240, 242–248 191, 194, 225, 226
Sine wave function, 1, 4 Voltage-mode (VM), 73–79, 81–84, 86,
Slew rate (SR), 91, 145–149 153–162, 167, 176–178, 180, 187, 188,
Some basic circuits, 92–108 212–215, 233–235, 241
Square wave function, 2, 5
Stability, 15, 44, 92
Subtractor connected CCI (S-CCI), 189 W
Symbols, 1–3, 35, 89, 151, 152, 163, 164, 166, Wien oscillators, 135–138, 186, 187
175, 176, 179, 180, 189, 190, 193, 194,
201, 203, 204, 206–209, 213, 214, 216,

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Erkan Yuce

Passive and Active Circuits

ISBN 978-3-031-44965-9 ISBN 978-3-031-44966-6 (eBook)

Paper in this product is recyclable.

Denizli, Türkiye Erkan Yuce

4.3 First-Order CM FTFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8.3.1 Realizations of the Other Active Devices

Erkan Yuce was born in 1969 in Nigde, Turkey. He

Shahram Minaei received the B.Sc. degree in Electrical

1.1 Symbols, Units, and Preﬁxes

1.2 Some Fundamental Functions

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 1

Table 1.1 International sys- Fundamental physical quantity SI SI symbol

Table 1.2 A number of units derived from the SI

δðt Þ = lim δΔ ðt Þ ð1:1Þ

Table 1.3 Unit preﬁxes Name Symbol Preﬁx multiplier

Fig. 1.1 A constant x1(t)

uðt Þ = lim uΔ ðt Þ ð1:2Þ

r ðt Þ = uðτÞdτ = tuðt Þ ð1:3Þ

Fig. 1.2 A sine wave function at 1 MHz

Fig. 1.3 A full-wave rectiﬁer function at 1 MHz

Fig. 1.4 A half-wave rectiﬁer function at 1 MHz

Fig. 1.5 A square wave function at 1 MHz

Fig. 1.6 A triangular wave function at 1 MHz

Fig. 1.7 A sawtooth wave function at 1 MHz

Fig. 1.8 An exponential function

Fig. 1.9 Representation of G'(t)

Fig. 1.10 Representation of u'(t)

Fig. 1.11 Representation of u(t)

Fig. 1.12 Representation of r(t)

Note It is desired that sensitivities of any functions should be small in magnitude

Note It is observed from Eq. (1.7) that if x approaches to B, sensitivity goes to

Solution 1.3 The sensitivities of ω0 to both passive elements are found as

Fig. 1.13 A simple VCC

Fig. 1.14 A BJT-based VCC

In order to express sensitivity more, bipolar junction transistor (BJT)-based

dI C2 ðV BB - V BE ÞðRB þ ðβF þ 1ÞRE Þ - βF ðV BB - V BE ÞRE

2.1 Fundamentals of the Signals and Systems

where v0in(t) = 1, ak(t) (k = 0, 1, 2, . . .) is a complex number and k of vkin(t)

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 11

Fig. 2.1 A circuit used in

Fig. 2.2 A circuit utilized

vout ðt Þ = a1 ðt Þvin ðt Þ ð2:3Þ

However, equation in (2.3) is time-varying. Apart from this, if the circuit in

If the conﬁguration in Fig. 2.1 is LTI, it can be deﬁned below.

vout ðt Þ = a1 vin ðt Þ ð2:5Þ

An LTI circuit can be generally shown as

where a0(d0v(t)/dt0) = a0v(t), bk (k = 0, 1, 2, . . . , n), and ai (i = 0, 1, 2, . . ., m) are

vin ðt Þ = A sinðωt Þ ð2:7aÞ

Fig. 2.3 An NMOS VDD

From Eq. (2.7b), the total harmonic distortion (THD) is deﬁned as

Here, VTN is the threshold voltage of the NMOS transistor, while kn is

vout(t) of the circuit exhibited in Fig. 2.3 is found as in the following:

Here, B1 = RD × kn(-VA-VTN)A and B2 = RD × knA2/4. Finally, THD of the circuit

2.2 Laplace and Fourier Transforms

V out ðsÞ = vout ðt Þe - st dt ð2:16bÞ

By using equations given in (2.6), (2.16a), and (2.16b), a transfer function

If real part of pi = σ i > 0, it is stable. If σ i = 0 and ωi ≠ ωk (k = 1, 2, 3, . . ., n and

V in ðωÞ = vin ðt Þe - jωt dt ð2:20aÞ

V out ðωÞ = vout ðt Þe - jωt dt ð2:20bÞ