Pci-Express Edge Connector: BI IN

8 7 6 5 4 3 2 1
PCI-EXPRESS EDGE CONNECTOR
+3.3V_BUS
1
+1.8V
R50 PWR_RST
D 10K
1% D
3
DNI
2
PWR_IN 5
R3 Q1B
1
10K MMDT3904-7
1% DNI
6
DNI C50
4
1.8V_IN 2 0.1uF
Q1A
+3.3V_BUS +12V_BUS +12V_BUS 10V
MMDT3904-7 DNI
2
1
DNI
1
+3.3V_BUS +3.3V_BUS R4
10K
+3.3V_BUS DNI
2
1
1
MPCIE1
R1 R2 B1 A1 PRESENCE
45.3K 45.3K +12V PRSNT1_A1 1
1% 1% B2 +12V +12V A2
B3 A3 +3.3V_BUS
+12V +12V
2
B4 GND GND A4 +3.3V_BUS
5 SMBCLK B5 SMCLK
IN
2
SMBDATA B6 A6 JTDIO_LOOP
5 SMDAT JTAG3
BI
B7 GND JTAG4 A7
10K U4
B8 +3.3V R1005
A9 +1.8V_EN R23 1 2 0R DNI 3 5 C1011 1 20.1uF 6.3V
+3.3V 15,14
IN
1
A VCC
+3.3V A10 1 4 PERST#_BUF 2,16
B Y OUT
PERST_ A11 PERST# 6 GND 2
C
Mechanical Key
GND A12 74AUP1G57GM
B13 GND REFCLK+ A13 PCIE_REFCLKP 2 R1007 1 DNI 2 0R
OUT
2 PETP0_GFXRP0 B14 PETp0 REFCLK- A14 PCIE_REFCLKN 2 Place R1007 in U4
OUT OUT
2 PETN0_GFXRN0 B15 PETn0 GND A15
OUT
B16 GND PERp0 A16 PERP0 2
IN
PERn0 A17 PERN0 2
IN
B18 GND GND A18
2 PETP1_GFXRP1 B19 PETp1
OUT
OUT
IN
B22 GND PERn1 A22 PERN1 2
IN
2 PETP2_GFXRP2 B23 PETp2 GND A23
C 2
OUT
PETN2_GFXRN2 B24 PETn2 GND A24 C
OUT
IN
IN
OUT
OUT
IN
PERn3 A30 PERN3 2
IN
GND A31
B32 GND
2 PETP4_GFXRP4 B33 PETp4
OUT
OUT
Place these caps as close to the PCIE B35 GND PERp4 A35 PERP4 2
IN
CAP CER 10UF 20% 16V X5R B36 GND PERn4 A36 PERN4 2
IN
connector as possible
OUT
(1206)1.8MM H MAX
OUT
IN
IN
OUT
+12V_BUS 2 PETN6_GFXRN6 B42 PETn6 GND A42
OUT
IN
1 +12V_BUS B44 GND PERn6 A44 PERN6 2
IN
OUT
1

OUT
C1001 B47 GND PERp7 A47 PERP7 2
10uF PRESENCE
IN
1 B48 PRSNT2_B48 PERn7 A48 PERN7 2
16V IN
B49 GND GND A49
2
+12V_BUS x8 PCIe
1 +12V_BUS
1
C1002 C1003
0.15uF 0.15uF
16V 16V
B B
2
SYMBOL LEGEND
+3.3V_BUS
DNI DO NOT
1 +3.3V_BUS CAP CER 10UF 10% 6.3V X5R INSTALL
(0805)1.4MM MAX THICK
1
# ACTIVE
C1004 LOW
10uF
6.3V
DIGITAL
2
GROUND
+3.3V_BUS ANALOG
GROUND
1 +3.3V_BUS
BUO BRING UP
1
ONLY
C1005 C1006 C1007

0.1uF 1uF 0.01uF
6.3V 6.3V 10V
2
+12V_BUS
1 +12V_BUS
1
C1008 C1009 C1010

0.1uF 0.1uF 0.1uF
16V 16V 16V
2
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
A AMD - PLATFORM HARDWARE ENG C <COPYRIGHT> Advanced Micro Devices

A
#48, No. 1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and
SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
SHEET: PCI-E Edge Connector
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the
DATE: Tue Sep 22 06:34:19 2015 REV: 2.0
information included herein.
SHEET NUMBER: 1 OF 20 TITLE:
Oland G5 2GB VGA/sDVI-I+HDMI/DP

DOCUMENT NUMBER: 105-C869xx-00B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Oland PCIe Interface
NOTE: Some of the PCIE testpoints will
be available through vias on traces.
D U1A
220nF for GEN3
D
TP110
PETP0_GFXRP0 AA38 Y33 PCIE_TX0P C1101 1 20.22uF 10V PERP0
1 PCIE_RX0P PCIE_TX0P 1
IN PCIE_TX0N
OUT
1 PETN0_GFXRN0 Y37 PCIE_RX0N PCIE_TX0N Y32 C1102 1 20.22uF 10V PERN0 1
IN OUT
TP109
PETP1_GFXRP1 Y35 W33 PCIE_TX1P C1103 1 20.22uF 10V PERP1
1
1 IN PCIE_RX1P PCIE_TX1P OUT 1
PETN1_GFXRN1 W36 W32 PCIE_TX1N C1104 1 20.22uF 10V PERN1
1 PCIE_RX1N PCIE_TX1N
IN OUT
PETP2_GFXRP2 W38 U33 PCIE_TX2P C1105 1 20.22uF 10V PERP2
IN PCIE_TX2N
OUT
1 PETN2_GFXRN2 V37 PCIE_RX2N PCIE_TX2N U32 C1106 1 20.22uF 10V PERN2 1
IN OUT
PETP3_GFXRP3 V35 U30 PCIE_TX3P C1107 1 20.22uF 10V PERP3
IN PCIE_TX3N
OUT
1 PETN3_GFXRN3 U36 PCIE_RX3N PCIE_TX3N U29 C1108 1 20.22uF 10V PERN3 1
IN OUT
TP107
PETP4_GFXRP4 U38 T33 PCIE_TX4P C1109 1 20.22uF 10V PERP4
IN PCIE_TX4N
OUT
1 PETN4_GFXRN4 T37 PCIE_RX4N PCIE_TX4N T32 C1110 1 20.22uF 10V PERN4 1
IN OUT
TP108
PETP5_GFXRP5 T35 T30 PCIE_TX5P C1111 1 20.22uF 10V PERP5
1 IN PCIE_RX5P PCIE_TX5P OUT 1
PETN5_GFXRN5 R36 T29 PCIE_TX5N C1112 1 20.22uF 10V PERN5
1 PCIE_RX5N PCIE_TX5N 1
IN OUT
PETP6_GFXRP6 R38 P33 PCIE_TX6P C1113 1 20.22uF 10V PERP6
IN PCIE_TX6N
OUT
1 PETN6_GFXRN6 P37 PCIE_RX6N PCIE_TX6N P32 C1114 1 20.22uF 10V PERN6 1
IN OUT
PETP7_GFXRP7 P35 P30 PCIE_TX7P C1115 1 20.22uF 10V PERP7
IN PCIE_TX7N
OUT
1 PETN7_GFXRN7 N36 PCIE_RX7N PCIE_TX7N P29 C1116 1 20.22uF 10V PERN7 1
IN OUT
N38 NC#N38 NC#N33 N33
M37 NC#M37 NC#N32 N32
M35 NC#M35 NC#N30 N30

L36 NC#L36 NC#N29 N29
L38 NC#L38 NC#L33 L33

K37 NC#K37 NC#L32 L32
C K35 NC#K35 NC#L30 L30 C

J36 NC#J36 NC#L29 L29
J38 NC#J38 NC#K33 K33

H37 NC#H37 NC#K32 K32
H35 NC#H35 NC#J33 J33

G36 NC#G36 NC#J32 J32
G38 NC#G38 NC#K30 K30

F37 NC#F37 NC#K29 K29
F35 NC#F35 NC#H33 H33

E37 H32 +0.95V
NC#E37 NC#H32
1 PCIE_REFCLKP AB35 PCIE_REFCLKP PCIE_CALR_TX Y30 PCIE_CALRP R1013 1 2 1.69K 1% PCIE_CALR_TX 1.69k pull up for Oland
IN PCIE_CALRN
1 PCIE_REFCLKN AA36 PCIE_REFCLKN PCIE_CALR_RX Y29 R1014 1 2 1K 1%
IN PCIE_CALR_RX 1k pull up for Oland
R1015 1 DNI 2 1K AL21 UNNAMED_2_OLANDM2GDDR5_I166_PXEN

PX_EN VSS AB39
VSS E39
VSS F34
1,16 PERST#_BUF AA30 PERSTB VSS F39
IN
+1.8V VSS G33
VSS G34
VSS H31
B11
+PCIE_PVDD 1.8V 200mA VSS H34
1 2 AB37 PCIE_PVDD VSS H39
1
1
120R J31
VSS
C1143 C1189 C1173 C1175 VSS J34
10uF 1uF 1uF 0.1uF K31
6.3V 6.3V 6.3V 6.3V VSS
AA31 NC#33 VSS K34
2
AA32 NC#34 VSS K39

B AA33 NC#35 VSS L31 B
AA34 NC#36 VSS L34
W30 NC#37 VSS M34
Y31 NC#38 VSS M39
VSS N31
V28 NC_BIF_VDDC VSS N34
W29 NC_BIF_VDDC VSS P31
VSS P34
VSS P39
G30 PCIE_VDDC VSS R34
G31 PCIE_VDDC VSS T31
H29 PCIE_VDDC VSS T34
H30 PCIE_VDDC VSS T39
+0.95V J29 PCIE_VDDC VSS U31
J30 PCIE_VDDC VSS U34
L28 PCIE_VDDC VSS V34
1
1
M28 PCIE_VDDC VSS Y39
C1161 C1160 C1159 C1158 C1150 C1151 C1152 C1153 C1154 C1155 N28 PCIE_VDDC VSS V39
1uF 10uF 10uF 10uF 1uF 1uF 1uF 1uF 1uF 1uF R28 W31
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V PCIE_VDDC VSS
T28 PCIE_VDDC VSS W34
2
U28 PCIE_VDDC VSS Y34
OLAND M2 GDDR5

A
SHEET: Oland PCIE Interface

DATE: Mon Sep 21 10:05:43 2015 REV: 2.0

8 7 6 5 4 3 2 1
(3) Oland MEM Interface Ch A&B
U1B U1C
4,3 DQA0_<0> C37 DQA0_0 4 3C18

DQA1_0 DQA1_<0> 4,3 4,3 DQB0_<0> C5 DQB0_0 4 3AA4
DQB1_0 DQB1_<0> 4,3
BI BI BI BI
4,3 DQA0_<1> C35 DQA0_1 4 3A18
DQA1_1 DQA1_<1> 4,3 4,3 DQB0_<1> C3 DQB0_1 4 3AB6
DQB1_1 DQB1_<1> 4,3
BI BI BI BI
4,3 DQA0_<2> A35 DQA0_2 4 3F18
DQA1_2 DQA1_<2> 4,3 4,3 DQB0_<2> E3 DQB0_2 4 3AB1
DQB1_2 DQB1_<2> 4,3
BI BI BI BI
4,3 DQA0_<3> E34 DQA0_3 4 3D17
DQA1_3 DQA1_<3> 4,3 4,3 DQB0_<3> E1 DQB0_3 4 3AB3
DQB1_3 DQB1_<3> 4,3
BI BI BI BI
4,3 DQA0_<4> G32 DQA0_4 4 3A16
DQA1_4 DQA1_<4> 4,3 4,3 DQB0_<4> F1 DQB0_4 4 3AD6
DQB1_4 DQB1_<4> 4,3
BI BI BI BI
4,3 DQA0_<5> D33 DQA0_5 4 3F16
DQB1_5 DQB1_<5> 4,3
BI BI BI BI
4,3 DQA0_<6> F32 DQA0_6 4 3D15
DQB1_6 DQB1_<6> 4,3
BI BI BI BI
4,3 DQA0_<7> E32 DQA0_7 4 3E14
DQA1_7 DQA1_<7> 4,3 4,3 DQB0_<7> G4 DQB0_7 4 3AD5
DQB1_7 DQB1_<7> 4,3
BI BI BI BI
4,3 DQA0_<8> D31 DQA0_8 4 3F14
DQA1_8 DQA1_<8> 4,3 4,3 DQB0_<8> H5 DQB0_8 4 3AF1
DQB1_8 DQB1_<8> 4,3
BI BI BI BI
4,3 DQA0_<9> F30 DQA0_9 4 3D13
DQA1_9 DQA1_<9> 4,3 4,3 DQB0_<9> H6 DQB0_9 4 3AF3
DQB1_9 DQB1_<9> 4,3
BI BI BI BI
4,3 DQA0_<10> C30 DQA0_10 4 3F12
DQA1_10 DQA1_<10> 4,3 4,3 DQB0_<10> J4 DQB0_10 4 3AF6
DQB1_10 DQB1_<10> 4,3
BI BI BI BI
4,3 DQA0_<11> A30 DQA0_11 4 3A12
DQA1_11 DQA1_<11> 4,3 4,3 DQB0_<11> K6 DQB0_11 4 3AG4
DQB1_11 DQB1_<11> 4,3
BI BI BI BI
4,3 DQA0_<12> F28 DQA0_12 4 3D11
DQA1_12 DQA1_<12> 4,3 4,3 DQB0_<12> K5 DQB0_12 4 3AH5
DQB1_12 DQB1_<12> 4,3
BI BI BI BI
4,3 DQA0_<13> C28 DQA0_13 4 3F10
DQA1_13 DQA1_<13> 4,3 4,3 DQB0_<13> L4 DQB0_13 4 3AH6
DQB1_13 DQB1_<13> 4,3
BI BI BI BI
4,3 DQA0_<14> A28 DQA0_14 4 3A10
DQA1_14 DQA1_<14> 4,3 4,3 DQB0_<14> M6 DQB0_14 4 3AJ4
DQB1_14 DQB1_<14> 4,3
BI BI BI BI
4,3 DQA0_<15> E28 DQA0_15 4 3C10
DQA1_15 DQA1_<15> 4,3 4,3 DQB0_<15> M1 DQB0_15 4 3AK3
DQB1_15 DQB1_<15> 4,3
BI BI BI BI
4,3 DQA0_<16> D27 DQA0_16 4 3G13
DQA1_16 DQA1_<16> 4,3 4,3 DQB0_<16> M3 DQB0_16 4 3AF8
DQB1_16 DQB1_<16> 4,3
BI BI BI BI
4,3 DQA0_<17> F26 DQA0_17 4 3H13
DQA1_17 DQA1_<17> 4,3 4,3 DQB0_<17> M5 DQB0_17 4 3AF9
DQB1_17 DQB1_<17> 4,3
BI BI BI BI
4,3 DQA0_<18> C26 DQA0_18 4 3J13
DQA1_18 DQA1_<18> 4,3 4,3 DQB0_<18> N4 DQB0_18 4 3AG8
DQB1_18 DQB1_<18> 4,3
BI BI BI BI
4,3 DQA0_<19> A26 DQA0_19 4 3H11
DQA1_19 DQA1_<19> 4,3 4,3 DQB0_<19> P6 DQB0_19 4 3AG7
DQB1_19 DQB1_<19> 4,3
BI BI BI BI
4,3 DQA0_<20> F24 DQA0_20 4 3G10
DQA1_20 DQA1_<20> 4,3 4,3 DQB0_<20> P5 DQB0_20 4 3AK9
DQB1_20 DQB1_<20> 4,3
BI BI BI BI
4,3 DQA0_<21> C24 DQA0_21 4 3G8
DQA1_21 DQA1_<21> 4,3 4,3 DQB0_<21> R4 DQB0_21 4 3AL7
DQB1_21 DQB1_<21> 4,3
BI BI BI BI
4,3 DQA0_<22> A24 DQA0_22 4 3K9
DQA1_22 DQA1_<22> 4,3 4,3 DQB0_<22> T6 DQB0_22 4 3AM8
DQB1_22 DQB1_<22> 4,3
BI BI BI BI
4,3 DQA0_<23> E24 DQA0_23 4 3K10
DQA1_23 DQA1_<23> 4,3 4,3 DQB0_<23> T1 DQB0_23 4 3AM7
DQB1_23 DQB1_<23> 4,3
BI BI BI BI
4,3 DQA0_<24> C22 DQA0_24 4 3G9
DQA1_24 DQA1_<24> 4,3 4,3 DQB0_<24> U4 DQB0_24 4 3AK1
DQB1_24 DQB1_<24> 4,3
BI BI BI BI
4,3 DQA0_<25> A22 DQA0_25 4 3A8
DQA1_25 DQA1_<25> 4,3 4,3 DQB0_<25> V6 DQB0_25 4 3AL4
DQB1_25 DQB1_<25> 4,3
BI BI BI BI
4,3 DQA0_<26> F22 DQA0_26 4 3C8
DQA1_26 DQA1_<26> 4,3 4,3 DQB0_<26> V1 DQB0_26 4 3AM6
DQB1_26 DQB1_<26> 4,3
BI BI BI BI
4,3 DQA0_<27> D21 DQA0_27 4 3E8
DQA1_27 DQA1_<27> 4,3 4,3 DQB0_<27> V3 DQB0_27 4 3AM1
DQB1_27 DQB1_<27> 4,3
BI BI BI BI
4,3 DQA0_<28> A20 DQA0_28 4 3A6
DQA1_28 DQA1_<28> 4,3 4,3 DQB0_<28> Y6 DQB0_28 4 3AN4
DQB1_28 DQB1_<28> 4,3
BI BI BI BI
4,3 DQA0_<29> F20 DQA0_29 4 3C6
DQA1_29 DQA1_<29> 4,3 4,3 DQB0_<29> Y1 DQB0_29 4 3AP3
DQB1_29 DQB1_<29> 4,3
BI BI BI BI
4,3 DQA0_<30> D19 DQA0_30 4 3E6
DQB1_30 DQB1_<30> 4,3
BI BI BI BI
4,3 DQA0_<31> E18 DQA0_31 4 3A5
DQB1_31 DQB1_<31> 4,3
BI BI BI BI
4,3 MAA0_<0> G24 MAA0_0 4 3H19

MAA1_0 MAA1_<0> 4,3 4,3 MAB0_<0> P8 MAB0_0 4 3Y9
MAB1_0 MAB1_<0> 4,3
BI BI BI BI
4,3 MAA0_<1> J23 MAA0_1 4 3H20
MAA1_1 MAA1_<1> 4,3 4,3 MAB0_<1> T9 MAB0_1 4 3W9
MAB1_1 MAB1_<1> 4,3
BI BI BI BI
4,3 MAA0_<2> H24 MAA0_2 4 3L13
MAA1_2 MAA1_<2> 4,3 4,3 MAB0_<2> P9 MAB0_2 4 3AC8
MAB1_2 MAB1_<2> 4,3
BI BI BI BI
4,3 MAA0_<3> J24 MAA0_3 4 3G16
MAA1_3 MAA1_<3> 4,3 4,3 MAB0_<3> N7 MAB0_3 4 3AC9
MAB1_3 MAB1_<3> 4,3
BI BI BI BI
4,3 MAA0_<4> H26 MAA0_4 4 3J16
MAA1_4 MAA1_<4> 4,3 4,3 MAB0_<4> N8 MAB0_4 4 3AA7
MAB1_4 MAB1_<4> 4,3
BI BI BI BI
4,3 MAA0_<5> J26 MAA0_5 4 3H16
MAA1_5 MAA1_<5> 4,3 4,3 MAB0_<5> N9 MAB0_5 4 3AA8
MAB1_5 MAB1_<5> 4,3
BI BI BI BI
4,3 MAA0_<6> H21 MAA0_6 4 3J17
MAA1_6 MAA1_<6> 4,3 4,3 MAB0_<6> U9 MAB0_6 4 3Y8
MAB1_6 MAB1_<6> 4,3
BI BI BI BI
4,3 MAA0_<7> G21 MAA0_7 4 3H17
MAA1_7 MAA1_<7> 4,3 4,3 MAB0_<7> U8 MAB0_7 4 3AA9
MAB1_7 MAB1_<7> 4,3
BI BI BI BI
4,3 MAA0_<8> H23 MAA0_8 4 3J19
MAA1_8 MAA1_<8> 4,3 4,3 MAB0_<8> T8 MAB0_8 4 3W8
MAB1_8 MAB1_<8> 4,3
BI BI BI BI
M21 MAA0_9 MAA1_9 M20 U12 MAB0_9 MAB1_9 V12
4 WCKA0_0 A32 WCKA0_0 WCKA1_0 C14 WCKA1_0 4 4 WCKB0_0 H3 WCKB0_0 WCKB1_0 AE4 WCKB1_0 4
BI BI BI BI
4 WCKA0B_0 C32 WCKA0B_0 WCKA1B_0 A14 WCKA1B_0 4 4 WCKB0B_0 H1 WCKB0B_0 WCKB1B_0 AF5 WCKB1B_0 4
BI BI BI BI
4 WCKA0_1 D23 WCKA0_1 WCKA1_1 E10 WCKA1_1 4 4 WCKB0_1 T3 WCKB0_1 WCKB1_1 AK6 WCKB1_1 4
BI BI BI BI
4 WCKA0B_1 E22 WCKA0B_1 WCKA1B_1 D9 WCKA1B_1 4 4 WCKB0B_1 T5 WCKB0B_1 WCKB1B_1 AK5 WCKB1B_1 4
BI BI BI BI
4 EDCA0_0 C34 EDCA0_0 EDCA1_0 E16 EDCA1_0 4 4 EDCB0_0 F6 EDCB0_0 EDCB1_0 AB5 EDCB1_0 4
BI BI BI BI
4 EDCA0_1 D29 EDCA0_1 EDCA1_1 E12 EDCA1_1 4 4 EDCB0_1 K3 EDCB0_1 EDCB1_1 AH1 EDCB1_1 4
BI BI BI BI
4 EDCA0_2 D25 EDCA0_2 EDCA1_2 J10 EDCA1_2 4 4 EDCB0_2 P3 EDCB0_2 EDCB1_2 AJ9 EDCB1_2 4
BI BI BI BI
4 EDCA0_3 E20 EDCA0_3 EDCA1_3 D7 EDCA1_3 4 4 EDCB0_3 V5 EDCB0_3 EDCB1_3 AM5 EDCB1_3 4
BI BI BI BI
4 DDBIA0_0 A34 DDBIA0_0 DDBIA1_0 C16 DDBIA1_0 4 4 DDBIB0_0 G7 DDBIB0_0 DDBIB1_0 AC4 DDBIB1_0 4
BI BI BI BI
4 DDBIA0_1 E30 DDBIA0_1 DDBIA1_1 C12 DDBIA1_1 4 4 DDBIB0_1 K1 DDBIB0_1 DDBIB1_1 AH3 DDBIB1_1 4
BI BI BI BI
4 DDBIA0_2 E26 DDBIA0_2 DDBIA1_2 J11 DDBIA1_2 4 4 DDBIB0_2 P1 DDBIB0_2 DDBIB1_2 AJ8 DDBIB1_2 4
BI BI BI BI
4 DDBIA0_3 C20 DDBIA0_3 DDBIA1_3 F8 DDBIA1_3 4 4 DDBIB0_3 W4 DDBIB0_3 DDBIB1_3 AM3 DDBIB1_3 4
BI BI BI BI
4 ADBIA0 J21 ADBIA0 ADBIA1 G19 ADBIA1 4 4 ADBIB0 T7 ADBIB0 ADBIB1 W7 ADBIB1 4
BI BI BI BI
4 CSA0B_0 K24 CSA0B_0 CSA1B_0 M13 CSA1B_0 4 4 CSB0B_0 P10 CSB0B_0 CSB1B_0 AD10 CSB1B_0 4
OUT OUT OUT OUT
K27 CSA0B_1 CSA1B_1 K16 L10 CSB0B_1 CSB1B_1 AC10
4 CASA0B K20 CASA0B CASA1B K17 CASA1B 4 4 CASB0B W10 CASB0B CASB1B AA10 CASB1B 4
OUT OUT OUT OUT
4 RASA0B K23 RASA0B RASA1B K19 RASA1B 4 4 RASB0B T10 RASB0B RASB1B Y10 RASB1B 4
OUT OUT OUT OUT
4 WEA0B K26 WEA0B WEA1B L15 WEA1B 4 4 WEB0B N10 WEB0B WEB1B AB11 WEB1B 4
OUT OUT OUT OUT
4 CKEA0 K21 CKEA0 CKEA1 J20 CKEA1 4 4 CKEB0 U10 CKEB0 CKEB1 AA11 CKEB1 4
OUT OUT OUT OUT
4 CLKA0 H27 CLKA0 CLKA1 J14 CLKA1 4 4 CLKB0 L9 CLKB0 CLKB1 AD8 CLKB1 4
OUT OUT OUT OUT
4 CLKA0B G27 CLKA0B CLKA1B H14 CLKA1B 4 4 CLKB0B L8 CLKB0B CLKB1B AD7 CLKB1B 4
OUT OUT OUT OUT
+MVDD +MVDD
1
R3602 R3603
40.2R 40.2R
MVREFD_A MVREFD_B 1%
MVREFDA L18 1% MVREFDB Y12
2
1
1
1
1
C3602 C3603
1uF 1uF
6.3V R3606 6.3V R3607
MVREFD/S =0.7* 100R 243R MEM_CALRP0 100R
1
R3601 2 M27 MEM_CALRP0
2
2
1% MVREFD/S =0.7* 1%
VDDR1
2
2
VDDR1
(GDDR3/4/5)
(GDDR3/4/5)
DRAM_RST 1 2 DRAM_RST_RR 1 2 DRAM_RST_R AH11 L20 AA12

4 OUT R3630 R3615 DRAM_RST MVREFSA MVREFSB
1
49.9R 10R
2
C3607
120pF OLAND M2 GDDR5 OLAND M2 GDDR5
50V R3612
5.1K
2
AMD - PLATFORM HARDWARE ENG C <COPYRIGHT> Advanced Micro Devices

SHEET: VDDCI

DATE: Tue Sep 22 06:32:59 2015 REV: 2.0

NOTES: NOTE
(4) GDDR5 Memory Channel A&B
GDDR5
23CNOPN001 +MVDD
U2600
GDDR5
GDDR5 3,4 DQB1_<18> M2 DQ31__DQ7 VDDQ_B1 B1
BI
23CNOPN001 +MVDD 23CNOPN001 +MVDD 23CNOPN001 +MVDD 3,4 DQB1_<20> M4 DQ30__DQ6 VDDQ_B3 B3
U2000 U2200 U2400 BI
3,4 DQB1_<16> N2 DQ29__DQ5 VDDQ_B12 B12
BI
3,4 DQA0_<30> M2 DQ31__DQ7 VDDQ_B1 B1 3,4 DQA1_<17> M2 DQ31__DQ7 VDDQ_B1 B1 3,4 DQB0_<24> M2 DQ31__DQ7 VDDQ_B1 B1 3,4 DQB1_<19> N4 DQ28__DQ4 VDDQ_B14 B14
BI BI BI BI
3,4 DQA0_<31> M4 DQ30__DQ6 VDDQ_B3 B3 3,4 DQA1_<23> M4 DQ30__DQ6 VDDQ_B3 B3 3,4 DQB0_<25> M4 DQ30__DQ6 VDDQ_B3 B3 3,4 DQB1_<17> T2 DQ27__DQ3 VDDQ_D1 D1
BI BI BI BI
3,4 DQA0_<29> N2 DQ29__DQ5 VDDQ_B12 B12 3,4 DQA1_<16> N2 DQ29__DQ5 VDDQ_B12 B12 3,4 DQB0_<31> N2 DQ29__DQ5 VDDQ_B12 B12 3,4 DQB1_<22> T4 DQ26__DQ2 VDDQ_D3 D3
BI BI BI BI
3,4 DQA0_<28> N4 DQ28__DQ4 VDDQ_B14 B14 3,4 DQA1_<20> N4 DQ28__DQ4 VDDQ_B14 B14 3,4 DQB0_<30> N4 DQ28__DQ4 VDDQ_B14 B14 3,4 DQB1_<21> V2 DQ25__DQ1 VDDQ_D12 D12
BI BI BI BI
3,4 DQA0_<27> T2 DQ27__DQ3 VDDQ_D1 D1 3,4 DQA1_<19> T2 DQ27__DQ3 VDDQ_D1 D1 3,4 DQB0_<29> T2 DQ27__DQ3 VDDQ_D1 D1 3,4 DQB1_<23> V4 DQ24__DQ0 VDDQ_D14 D14
BI BI BI BI
3,4 DQA0_<24> T4 DQ26__DQ2 VDDQ_D3 D3 3,4 DQA1_<22> T4 DQ26__DQ2 VDDQ_D3 D3 3,4 DQB0_<26> T4 DQ26__DQ2 VDDQ_D3 D3 3,4 DQB1_<30> M13 DQ23__DQ15 VDDQ_E5 E5
BI BI BI BI
3,4 DQA0_<26> V2 DQ25__DQ1 VDDQ_D12 D12 3,4 DQA1_<18> V2 DQ25__DQ1 VDDQ_D12 D12 3,4 DQB0_<28> V2 DQ25__DQ1 VDDQ_D12 D12 3,4 DQB1_<27> M11 DQ22__DQ14 VDDQ_E10 E10
BI BI BI BI
3,4 DQA0_<25> V4 DQ24__DQ0 VDDQ_D14 D14 3,4 DQA1_<21> V4 DQ24__DQ0 VDDQ_D14 D14 3,4 DQB0_<27> V4 DQ24__DQ0 VDDQ_D14 D14 3,4 DQB1_<29> N13 DQ21__DQ13 VDDQ_F1 F1
BI BI BI BI
3,4 DQA0_<17> M13 DQ23__DQ15 VDDQ_E5 E5 3,4 DQA1_<30> M13 DQ23__DQ15 VDDQ_E5 E5 3,4 DQB0_<16> M13 DQ23__DQ15 VDDQ_E5 E5 3,4 DQB1_<25> N11 DQ20__DQ12 VDDQ_F3 F3
BI BI BI BI
3,4 DQA0_<16> M11 DQ22__DQ14 VDDQ_E10 E10 3,4 DQA1_<24> M11 DQ22__DQ14 VDDQ_E10 E10 3,4 DQB0_<17> M11 DQ22__DQ14 VDDQ_E10 E10 3,4 DQB1_<26> T13 DQ19__DQ11 VDDQ_F12 F12
BI BI BI BI
3,4 DQA0_<18> N13 DQ21__DQ13 VDDQ_F1 F1 3,4 DQA1_<29> N13 DQ21__DQ13 VDDQ_F1 F1 3,4 DQB0_<18> N13 DQ21__DQ13 VDDQ_F1 F1 3,4 DQB1_<24> T11 DQ18__DQ10 VDDQ_F14 F14
BI BI BI BI
3,4 DQA0_<21> N11 DQ20__DQ12 VDDQ_F3 F3 3,4 DQA1_<27> N11 DQ20__DQ12 VDDQ_F3 F3 3,4 DQB0_<23> N11 DQ20__DQ12 VDDQ_F3 F3 3,4 DQB1_<28> V13 DQ17__DQ9 VDDQ_G2 G2
BI BI BI BI
3,4 DQA0_<19> T13 DQ19__DQ11 VDDQ_F12 F12 3,4 DQA1_<28> T13 DQ19__DQ11 VDDQ_F12 F12 3,4 DQB0_<20> T13 DQ19__DQ11 VDDQ_F12 F12 3,4 DQB1_<31> V11 DQ16__DQ8 VDDQ_G13 G13
BI BI BI BI
3,4 DQA0_<23> T11 DQ18__DQ10 VDDQ_F14 F14 3,4 DQA1_<25> T11 DQ18__DQ10 VDDQ_F14 F14 3,4 DQB0_<21> T11 DQ18__DQ10 VDDQ_F14 F14 3,4 DQB1_<14> F13 DQ15__DQ23 VDDQ_H3 H3
BI BI BI BI
3,4 DQA0_<20> V13 DQ17__DQ9 VDDQ_G2 G2 3,4 DQA1_<31> V13 DQ17__DQ9 VDDQ_G2 G2 3,4 DQB0_<19> V13 DQ17__DQ9 VDDQ_G2 G2 3,4 DQB1_<15> F11 DQ14__DQ22 VDDQ_H12 H12
BI BI BI BI
3,4 DQA0_<22> V11 DQ16__DQ8 VDDQ_G13 G13 3,4 DQA1_<26> V11 DQ16__DQ8 VDDQ_G13 G13 3,4 DQB0_<22> V11 DQ16__DQ8 VDDQ_G13 G13 3,4 DQB1_<13> E13 DQ13__DQ21 VDDQ_K3 K3
BI BI BI BI
3,4 DQA0_<2> F13 DQ15__DQ23 VDDQ_H3 H3 3,4 DQA1_<14> F13 DQ15__DQ23 VDDQ_H3 H3 3,4 DQB0_<5> F13 DQ15__DQ23 VDDQ_H3 H3 3,4 DQB1_<8> E11 DQ12__DQ20 VDDQ_K12 K12
BI BI BI BI
3,4 DQA0_<3> F11 DQ14__DQ22 VDDQ_H12 H12 3,4 DQA1_<15> F11 DQ14__DQ22 VDDQ_H12 H12 3,4 DQB0_<4> F11 DQ14__DQ22 VDDQ_H12 H12 3,4 DQB1_<11> B13 DQ11__DQ19 VDDQ_L2 L2
BI BI BI BI
3,4 DQA0_<1> E13 DQ13__DQ21 VDDQ_K3 K3 3,4 DQA1_<12> E13 DQ13__DQ21 VDDQ_K3 K3 3,4 DQB0_<2> E13 DQ13__DQ21 VDDQ_K3 K3 3,4 DQB1_<9> B11 DQ10__DQ18 VDDQ_L13 L13
BI BI BI BI
3,4 DQA0_<4> E11 DQ12__DQ20 VDDQ_K12 K12 3,4 DQA1_<8> E11 DQ12__DQ20 VDDQ_K12 K12 3,4 DQB0_<3> E11 DQ12__DQ20 VDDQ_K12 K12 3,4 DQB1_<12> A13 DQ9__DQ17 VDDQ_M1 M1
BI BI BI BI
3,4 DQA0_<0> B13 DQ11__DQ19 VDDQ_L2 L2 3,4 DQA1_<13> B13 DQ11__DQ19 VDDQ_L2 L2 3,4 DQB0_<1> B13 DQ11__DQ19 VDDQ_L2 L2 3,4 DQB1_<10> A11 DQ8__DQ16 VDDQ_M3 M3
BI BI BI BI
3,4 DQA0_<6> B11 DQ10__DQ18 VDDQ_L13 L13 3,4 DQA1_<9> B11 DQ10__DQ18 VDDQ_L13 L13 3,4 DQB0_<7> B11 DQ10__DQ18 VDDQ_L13 L13 3,4 DQB1_<3> F2 DQ7__DQ31 VDDQ_M12 M12
BI BI BI BI
3,4 DQA0_<7> A13 DQ9__DQ17 VDDQ_M1 M1 3,4 DQA1_<11> A13 DQ9__DQ17 VDDQ_M1 M1 3,4 DQB0_<0> A13 DQ9__DQ17 VDDQ_M1 M1 3,4 DQB1_<0> F4 DQ6__DQ30 VDDQ_M14 M14
BI BI BI BI
3,4 DQA0_<5> A11 DQ8__DQ16 VDDQ_M3 M3 3,4 DQA1_<10> A11 DQ8__DQ16 VDDQ_M3 M3 3,4 DQB0_<6> A11 DQ8__DQ16 VDDQ_M3 M3 3,4 DQB1_<2> E2 DQ5__DQ29 VDDQ_N5 N5
BI BI BI BI
3,4 DQA0_<15> F2 DQ7__DQ31 VDDQ_M12 M12 3,4 DQA1_<1> F2 DQ7__DQ31 VDDQ_M12 M12 3,4 DQB0_<13> F2 DQ7__DQ31 VDDQ_M12 M12 3,4 DQB1_<1> E4 DQ4__DQ28 VDDQ_N10 N10
BI BI BI BI
3,4 DQA0_<13> F4 DQ6__DQ30 VDDQ_M14 M14 3,4 DQA1_<0> F4 DQ6__DQ30 VDDQ_M14 M14 3,4 DQB0_<15> F4 DQ6__DQ30 VDDQ_M14 M14 3,4 DQB1_<5> B2 DQ3__DQ27 VDDQ_P1 P1
BI BI BI BI
3,4 DQA0_<14> E2 DQ5__DQ29 VDDQ_N5 N5 3,4 DQA1_<6> E2 DQ5__DQ29 VDDQ_N5 N5 3,4 DQB0_<14> E2 DQ5__DQ29 VDDQ_N5 N5 3,4 DQB1_<6> B4 DQ2__DQ26 VDDQ_P3 P3
BI BI BI BI
3,4 DQA0_<12> E4 DQ4__DQ28 VDDQ_N10 N10 3,4 DQA1_<5> E4 DQ4__DQ28 VDDQ_N10 N10 3,4 DQB0_<12> E4 DQ4__DQ28 VDDQ_N10 N10 3,4 DQB1_<4> A2 DQ1__DQ25 VDDQ_P12 P12
BI BI BI BI
3,4 DQA0_<11> B2 DQ3__DQ27 VDDQ_P1 P1 3,4 DQA1_<2> B2 DQ3__DQ27 VDDQ_P1 P1 3,4 DQB0_<10> B2 DQ3__DQ27 VDDQ_P1 P1 3,4 DQB1_<7> A4 DQ0__DQ24 VDDQ_P14 P14
BI BI BI BI
3,4 DQA0_<8> B4 DQ2__DQ26 VDDQ_P3 P3 3,4 DQA1_<4> B4 DQ2__DQ26 VDDQ_P3 P3 3,4 DQB0_<11> B4 DQ2__DQ26 VDDQ_P3 P3 VDDQ_T1 T1
BI BI BI
3,4 DQA0_<10> A2 DQ1__DQ25 VDDQ_P12 P12 3,4 DQA1_<3> A2 DQ1__DQ25 VDDQ_P12 P12 3,4 DQB0_<8> A2 DQ1__DQ25 VDDQ_P12 P12 VDDQ_T3 T3
BI BI BI
3,4 DQA0_<9> A4 DQ0__DQ24 VDDQ_P14 P14 3,4 DQA1_<7> A4 DQ0__DQ24 VDDQ_P14 P14 3,4 DQB0_<9> A4 DQ0__DQ24 VDDQ_P14 P14 VDDQ_T12 T12
BI BI BI
VDDQ_T1 T1 VDDQ_T1 T1 VDDQ_T1 T1 VDDQ_T14 T14
VDDQ_T3 T3 VDDQ_T3 T3 VDDQ_T3 T3
VDDQ_T12 T12 VDDQ_T12 T12 VDDQ_T12 T12 3,4 MAB1_<8> J5 RFU_A12_NC +MVDD
BI
VDDQ_T14 T14 VDDQ_T14 T14 VDDQ_T14 T14 3,4 MAB1_<0> K4 A7_A8__A0_A10 VDD_C5 C5
BI
+MVDD 3,4 MAB1_<1> K5 A6_A11__A1_A9 VDD_C10 C10
BI
3,4 MAA0_<8> J5 RFU_A12_NC 3,4 MAA1_<8> J5 RFU_A12_NC +MVDD 3,4 MAB0_<8> J5 RFU_A12_NC +MVDD 3,4 MAB1_<3> K10 A5_BA1__A3_BA3 VDD_D11 D11
BI BI BI BI
3,4 MAA0_<7> K4 A7_A8__A0_A10 VDD_C5 C5 3,4 MAA1_<0> K4 A7_A8__A0_A10 VDD_C5 C5 3,4 MAB0_<7> K4 A7_A8__A0_A10 VDD_C5 C5 3,4 MAB1_<2> K11 A4_BA2__A2_BA0 VDD_G1 G1
BI BI BI BI
3,4 MAA0_<6> K5 A6_A11__A1_A9 VDD_C10 C10 3,4 MAA1_<1> K5 A6_A11__A1_A9 VDD_C10 C10 3,4 MAB0_<6> K5 A6_A11__A1_A9 VDD_C10 C10 3,4 MAB1_<5> H10 A3_BA3__A5_BA1 VDD_G4 G4
BI BI BI BI
3,4 MAA0_<5> K10 A5_BA1__A3_BA3 VDD_D11 D11 3,4 MAA1_<3> K10 A5_BA1__A3_BA3 VDD_D11 D11 3,4 MAB0_<5> K10 A5_BA1__A3_BA3 VDD_D11 D11 3,4 MAB1_<4> H11 A2_BA0__A4_BA2 VDD_G11 G11
BI BI BI BI
3,4 MAA0_<4> K11 A4_BA2__A2_BA0 VDD_G1 G1 3,4 MAA1_<2> K11 A4_BA2__A2_BA0 VDD_G1 G1 3,4 MAB0_<4> K11 A4_BA2__A2_BA0 VDD_G1 G1 3,4 MAB1_<6> H5 A1_A9__A6_A11 VDD_G14 G14
BI BI BI BI
3,4 MAA0_<3> H10 A3_BA3__A5_BA1 VDD_G4 G4 3,4 MAA1_<5> H10 A3_BA3__A5_BA1 VDD_G4 G4 3,4 MAB0_<3> H10 A3_BA3__A5_BA1 VDD_G4 G4 3,4 MAB1_<7> H4 A0_A10__A7_A8 VDD_L1 L1
BI BI BI BI
3,4 MAA0_<2> H11 A2_BA0__A4_BA2 VDD_G11 G11 3,4 MAA1_<4> H11 A2_BA0__A4_BA2 VDD_G11 G11 3,4 MAB0_<2> H11 A2_BA0__A4_BA2 VDD_G11 G11 VDD_L4 L4
BI BI BI
3,4 MAA0_<1> H5 A1_A9__A6_A11 VDD_G14 G14 3,4 MAA1_<6> H5 A1_A9__A6_A11 VDD_G14 G14 3,4 MAB0_<1> H5 A1_A9__A6_A11 VDD_G14 G14 VDD_L11 L11
BI BI BI
3,4 MAA0_<0> H4 A0_A10__A7_A8 VDD_L1 L1 3,4 MAA1_<7> H4 A0_A10__A7_A8 VDD_L1 L1 3,4 MAB0_<0> H4 A0_A10__A7_A8 VDD_L1 L1 VDD_L14 L14
BI BI BI
VDD_L4 L4 VDD_L4 L4 VDD_L4 L4 3 WCKB1_0 D4 WCK01__WCK23 VDD_P11 P11
IN
VDD_L11 L11 VDD_L11 L11 VDD_L11 L11 3 WCKB1B_0 D5 WCK01#__WCK23# VDD_R5 R5
IN
VDD_L14 L14 VDD_L14 L14 VDD_L14 L14 VDD_R10 R10
WCKA0_0 D4 P11 WCKA1_0 D4 P11 WCKB0_0 D4 P11 WCKB1_1 P4 +MVDD
3 WCK01__WCK23 VDD_P11 3 WCK01__WCK23 VDD_P11 3 WCK01__WCK23 VDD_P11 3 WCK23__WCK01
IN IN IN IN
3 WCKA0B_0 D5 WCK01#__WCK23# VDD_R5 R5 3 WCKA1B_0 D5 WCK01#__WCK23# VDD_R5 R5 3 WCKB0B_0 D5 WCK01#__WCK23# VDD_R5 R5 3 WCKB1B_1 P5 WCK23#__WCK01#
IN IN IN IN
VDD_R10 R10 VDD_R10 R10 VDD_R10 R10 VSSQ_A1 A1
3 WCKA0_1 P4 WCK23__WCK01 3 WCKA1_1 P4 WCK23__WCK01 3 WCKB0_1 P4 WCK23__WCK01 3 EDCB1_2 R2 EDC3__EDC0 VSSQ_A3 A3
C2305
C2311
C2312
C2313
C2314
C2315
C2316
C2317
C2318
C2319
C2320
C2321
C2322
IN IN IN OUT
1
3 WCKA0B_1 P5 WCK23#__WCK01# 3 WCKA1B_1 P5 WCK23#__WCK01# 3 WCKB0B_1 P5 WCK23#__WCK01# 3 EDCB1_3 R13 EDC2__EDC1 VSSQ_A12 A12
IN IN IN OUT
1uF
VSSQ_A1 A1 VSSQ_A1 A1 VSSQ_A1 A1 3 EDCB1_1 C13 EDC1__EDC2 VSSQ_A14 A14
OUT
3 EDCA0_3 R2 EDC3__EDC0 VSSQ_A3 A3 3 EDCA1_2 R2 EDC3__EDC0 VSSQ_A3 A3 3 EDCB0_3 R2 EDC3__EDC0 VSSQ_A3 A3 3 EDCB1_0 C2 EDC0__EDC3 VSSQ_C1 C1
OUT OUT OUT OUT 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
3 EDCA0_2 R13 EDC2__EDC1 VSSQ_A12 A12 3 EDCA1_3 R13 EDC2__EDC1 VSSQ_A12 A12 3 EDCB0_2 R13 EDC2__EDC1 VSSQ_A12 A12 VSSQ_C3 C3
OUT OUT OUT
2
3 EDCA0_0 C13 EDC1__EDC2 VSSQ_A14 A14 3 EDCA1_1 C13 EDC1__EDC2 VSSQ_A14 A14 3 EDCB0_0 C13 EDC1__EDC2 VSSQ_A14 A14 3 DDBIB1_2 P2 DBI3#__DBI0# VSSQ_C4 C4
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
OUT OUT OUT BI
3 EDCA0_1 C2 EDC0__EDC3 VSSQ_C1 C1 3 EDCA1_0 C2 EDC0__EDC3 VSSQ_C1 C1 3 EDCB0_1 C2 EDC0__EDC3 VSSQ_C1 C1 3 DDBIB1_3 P13 DBI2#__DBI1# VSSQ_C11 C11
OUT OUT OUT BI
VSSQ_C3 C3 VSSQ_C3 C3 VSSQ_C3 C3 3 DDBIB1_1 D13 DBI1#__DBI2# VSSQ_C12 C12
BI
3 DDBIA0_3 P2 DBI3#__DBI0# VSSQ_C4 C4 3 DDBIA1_2 P2 DBI3#__DBI0# VSSQ_C4 C4 3 DDBIB0_3 P2 DBI3#__DBI0# VSSQ_C4 C4 3 DDBIB1_0 D2 DBI0#__DBI3# VSSQ_C14 C14
BI BI BI BI
3 DDBIA0_2 P13 DBI2#__DBI1# VSSQ_C11 C11 3 DDBIA1_3 P13 DBI2#__DBI1# VSSQ_C11 C11 3 DDBIB0_2 P13 DBI2#__DBI1# VSSQ_C11 C11 VSSQ_E1 E1
BI BI BI
3 DDBIA0_0 D13 DBI1#__DBI2# VSSQ_C12 C12 3 DDBIA1_1 D13 DBI1#__DBI2# VSSQ_C12 C12 3 DDBIB0_0 D13 DBI1#__DBI2# VSSQ_C12 C12 VSSQ_E3 E3 +MVDD
BI BI BI
3 DDBIA0_1 D2 DBI0#__DBI3# VSSQ_C14 C14 3 DDBIA1_0 D2 DBI0#__DBI3# VSSQ_C14 C14 3 DDBIB0_1 D2 DBI0#__DBI3# VSSQ_C14 C14 VSSQ_E12 E12
BI BI BI
VSSQ_E1 E1 VSSQ_E1 E1 VSSQ_E1 E1 +MVDD 3 CASB1B G3 RAS#__CAS# VSSQ_E14 E14
IN
VSSQ_E3 E3 VSSQ_E3 E3 VSSQ_E3 E3 3 RASB1B L3 CAS#__RAS# VSSQ_F5 F5
R2603 IN
VSSQ_E12 E12 +MVDD VSSQ_E12 E12 VSSQ_E12 E12 1 2 CLKB1B VSSQ_F10 F10
R2604 60.4R
+MVDD 3 RASA0B G3 RAS#__CAS# VSSQ_E14 E14 3 CASA1B G3 RAS#__CAS# VSSQ_E14 E14 +MVDD 3 RASB0B G3 RAS#__CAS# VSSQ_E14 E14 1 2 CLKB1 VSSQ_H2 H2 C2340 C2325 C2327 C2332 C2328
IN IN IN 60.4R
3 CASA0B L3 CAS#__RAS# VSSQ_F5 F5 3 RASA1B L3 CAS#__RAS# VSSQ_F5 F5 3 CASB0B L3 CAS#__RAS# VSSQ_F5 F5 3 CKEB1 J3 CKE# VSSQ_H13 H13 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF
R2003 IN R2203 IN R2403 IN IN
1 2 CLKA0B VSSQ_F10 F10 1 2 CLKA1B VSSQ_F10 F10 1 2 CLKB0B VSSQ_F10 F10 3 J11 CK# VSSQ_K2 K2 4V 4V 4V 4V 4V
60.4R 60.4R 60.4R
IN
1 2 CLKA0 VSSQ_H2 H2 1 2 CLKA1 VSSQ_H2 H2 1 2 CLKB0 VSSQ_H2 H2 3 J12 CK VSSQ_K13 K13
R2004 60.4R R2204 60.4R R2404 60.4R
IN
3 CKEA0 J3 CKE# VSSQ_H13 H13 3 CKEA1 J3 CKE# VSSQ_H13 H13 3 CKEB0 J3 CKE# VSSQ_H13 H13 VSSQ_M5 M5
IN IN IN
3 J11 CK# VSSQ_K2 K2 3 J11 CK# VSSQ_K2 K2 3 J11 CK# VSSQ_K2 K2 VSSQ_M10 M10
IN IN IN
3 J12 CK VSSQ_K13 K13 3 J12 CK VSSQ_K13 K13 3 J12 CK VSSQ_K13 K13 3 WEB1B G12 CS#__WE# VSSQ_N1 N1
IN IN IN IN
VSSQ_M5 M5 VSSQ_M5 M5 VSSQ_M5 M5 3 CSB1B_0 L12 WE#__CS# VSSQ_N3 N3
IN
VSSQ_M10 M10 VSSQ_M10 M10 VSSQ_M10 M10 VSSQ_N12 N12
3 CSA0B_0 G12 CS#__WE# VSSQ_N1 N1 3 WEA1B G12 CS#__WE# VSSQ_N1 N1 3 CSB0B_0 G12 CS#__WE# VSSQ_N1 N1 VSSQ_N14 N14
IN IN IN R2601
3 WEA0B L12 WE#__CS# VSSQ_N3 N3 3 CSA1B_0 L12 WE#__CS# VSSQ_N3 N3 3 WEB0B L12 WE#__CS# VSSQ_N3 N3 1 2 1% J13 UNNAMED_4_170BALLGDDR5_I263_ZQ
ZQ VSSQ_R1 R1
IN IN IN 120R
VSSQ_N12 N12 VSSQ_N12 N12 VSSQ_N12 N12 J10 SEN VSSQ_R3 R3
VSSQ_N14 N14 VSSQ_N14 N14 VSSQ_N14 N14 VSSQ_R4 R4
R2002 R2201 R2400
1 2 1% J13 UNNAMED_4_170BALLGDDR5_I12_ZQ
ZQ VSSQ_R1 R1 1 2 1% J13 UNNAMED_4_170BALLGDDR5_I163_ZQ
ZQ VSSQ_R1 R1 1 2 1% J13 UNNAMED_4_170BALLGDDR5_I178_ZQ
ZQ VSSQ_R1 R1 VSSQ_R11 R11
120R J10 SEN R3 120R J10 SEN R3 120R J10 SEN R3 DRAM_RST J2 R12
VSSQ_R3 VSSQ_R3 VSSQ_R3 3,4 IN RESET# VSSQ_R12
VSSQ_R4 R4 VSSQ_R4 R4 VSSQ_R4 R4 +MVDD J1 MF VSSQ_R14 R14 +MVDD
VSSQ_R11 R11 VSSQ_R11 R11 VSSQ_R11 R11 VSSQ_V1 V1

3,4 DRAM_RST J2 RESET# VSSQ_R12 R12 3,4 DRAM_RST J2 RESET# VSSQ_R12 R12 3,4 DRAM_RST J2 RESET# VSSQ_R12 R12 VSSQ_V3 V3
IN IN IN
J1 MF VSSQ_R14 R14 +MVDD J1 MF VSSQ_R14 R14 J1 MF VSSQ_R14 R14 VSSQ_V12 V12
VSSQ_V1 V1 VSSQ_V1 V1 VSSQ_V1 V1 VSSQ_V14 V14
VSSQ_V3 V3 VSSQ_V3 V3 VSSQ_V3 V3 A5 Vpp_NC C2041 C2042 C2033 C2039 C2035 C2036
R2699
VSSQ_V12 V12 VSSQ_V12 V12 VSSQ_V12 V12 +MVDD 1 2 1% V5 Vpp_NC1 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF
R2698 2.37K
VSSQ_V14 V14 VSSQ_V14 V14 VSSQ_V14 V14 1 2 1% VSS_B5 B5 4V 4V 4V 4V 4V 4V
A5 A5 A5 1 5.49K
2 REFD_B1 A10 B10
Vpp_NC Vpp_NC Vpp_NC VREFD1 VSS_B10
+MVDD 1R2099 2 1% V5 Vpp_NC1 +MVDD 1R2299 2 1% V5 Vpp_NC1 +MVDD
R2499
1 2 1% V5 Vpp_NC1 C2698
1uF V10 VREFD2 VSS_D10 D10
R2098 R2298 R2498 6.3V
1 2.37K
2 B5 1 2.37K
2 B5 1 2.37K
2 B5 G5
1% VSS_B5 1% VSS_B5 1% VSS_B5 VSS_G5
1 5.49K
2 REFD_A0 A10 B10 1 5.49K
2 REFD_A1 A10 B10 1 5.49K
2 REFD_B0 A10 B10 G10
VREFD1 VSS_B10 VREFD1 VSS_B10 VREFD1 VSS_B10 VSS_G10
1uF V10 D10 1uF V10 D10 1uF V10 D10 H1
C2003 6.3V VREFD2 VSS_D10 C2298 6.3V VREFD2 VSS_D10 C2498 6.3V VREFD2 VSS_D10 VSS_H1
VSS_G5 G5 VSS_G5 G5 VSS_G5 G5 VSS_H14 H14
VSS_G10 G10 VSS_G10 G10 VSS_G10 G10 VSS_K1 K1
VSS_H1 H1 VSS_H1 H1 VSS_H1 H1 J14 VREFC VSS_K14 K14
VSS_H14 H14 VSS_H14 H14 VSS_H14 H14 VSS_L5 L5
R2697
VSS_K1 K1 VSS_K1 K1 VSS_K1 K1 +MVDD 1 2 1% VSS_L10 L10
R2696 2.37K
J14 VREFC VSS_K14 K14 J14 VREFC VSS_K14 K14 J14 VREFC VSS_K14 K14 1 2 1% VSS_P10 P10
L5 L5 L5 1 5.49K
2 VREFC_U2600 J4 T5
VSS_L5 VSS_L5 VSS_L5 ABI# VSS_T5
R2497 1% 1uF
VSS_L10 L10 VSS_L10 L10 +MVDD 1 2 1% VSS_L10 L10 C2696 6.3V VSS_T10 T10
R2297 1% R2209 1% R2496 2.37K
+MVDD 1 2 1% VSS_P10 P10 +MVDD 1 2 1% VSS_P10 P10 1 2 1% VSS_P10 P10
R2296 2.37K R2210 2.37K 5.49K VREFC_U2400
1 2 1% J4 ABI# VSS_T5 T5 1 2 1% J4 ABI# VSS_T5 T5 1 2 J4 ABI# VSS_T5 T5
1 5.49K
2 VREFC_U2000 T10 1 5.49K
2 VREFC_U2200 T10 1uF T10 ADBIB1
VSS_T10 VSS_T10 C2496 6.3V VSS_T10 3 IN
1uF 1uF
C2296 6.3V 6.3V
C2241
3 ADBIA0 3 ADBIA1 3 ADBIB0
IN IN IN
+MVDD +MVDD
+MVDD
C2007
C2008
C2010
C2000
C2001
C2011
C2012
C2013
C2014
C2015
C2016
C2017
C2018
C2019
C2020
C2021
C2022
C2023
C2024
C2025
C2201
C2205
1
1
C2145
C2100
C2101
C2102
C2103
C2104
C2105
C2106
C2107
C2108
C2109
C2110
C2111
C2112
C2113
C2114
C2115
C2116
C2117
C2118
1
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
2
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
+MVDD
+MVDD
+MVDD +MVDD +MVDD +MVDD
C2135 C2136 C2137 C2127 C2122 C2126 C2131

4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF
1
1
C2337
C2338
C2339
C2032
4V 4V 4V 4V 4V 4V 4V C2236 C2237 C2238 C2227 C2235 C2228 C2234

C2124
C2125
C2130
C2030
C2031
C2233
C2230
1
4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF

4V 4V 4V 4V 4V 4V 4V
6.3V 6.3V 6.3V
10uF
10uF
2
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V

10uF
10uF
10uF
10uF
10uF
10uF
2
2
10uF
10uF
10uF

SHEET: VDDCI

DATE: Tue Sep 22 06:32:59 2015 REV: 2.0

NOTES: NOTE
9 8 7 6 5 4 3 2 1
OLAND GPIOs Strap CF XTAL OSC
PN 2280007900G for 1Mbit (PM25LV010A-100SCE)

U1D
BIOS1
+3.3V_BUS
60mA +3.3V_BUS VIDEO BIOS
AF23 VDDR3 GPIO_0 AH20 FIRMWARE
BIOS
1
AF24 VDDR3 GPIO_1 AH18
C1 AG23 VDDR3 GPIO_2 AN16
1
1uF R14
AG24 VDDR3
6.3V
R4017 R4018 BIOS(113?)
2
4.7K 4.7K AH17
GPIO_5_AC_BATT +3.3V_BUS
E GPIO_6_TACH AJ17 4.7K U11 E
2
SCL AK26 AK17 GPIO_7_VDDCI_VID0 GPIO_22_R 1 8
15 SCL GPIO_7_BLON 15 CE VDD
OUT OUT
1
SDA AJ26 AJ13 GPIO_8 3 6 GPIO_8_R 2 7
15 SDA GPIO_8_ROMSO RP1C SO HOLD
BI GPIO_9 33R
33R
GPIO_9_ROMSI AH15 1 8
RP1A 3 WP SCK 6 C4
AJ16 GPIO_10 2 7 4 5 0.1uF
GPIO_10_ROMSCK RP1B GND SI 6.3V
AK16 33R
GPIO_11
2
GPIO_12 AL16 PM25LD010C-SCE
SMBCLK AJ23 AM16 GPIO_9_R
1 SMBCLK GPIO_13
OUT GPIO_10_R
1 SMBDATA AH23 SMBDATA GPIO_14_HPD2 AM14 GPIO_14_HPD2 8
BI IN
GPIO_15_PWRCNTL_0 AM13 GPIO_15_VID0 15
OUT
GPIO_16 AK14 GPIO_16_VDDCI_VID1 15
OUT PIN BASED STRAPS
GPIO_17_THERMAL_INT AG30
GPIO_18_HPD3 AN14
GPIO_19_CTF AM17 GPIO_19_CTF 16
OUT
AF35 NC#75 GPIO_20_PWRCNTL_1 AL13 GPIO_20_VID1 15
OUT
AG36 NC#74 GPIO_21 AJ14
AJ27 AK13 GPIO_22 4 5
RSVD#AJ27 GPIO_22_ROMCSB RP1D
AK27 AG32 GPIO_29_VID2 33R
RSVD#AK27 GPIO_29 15
OUT
GPIO_30 AG33 GPIO_30_VID3 15
OUT
AN36 NC#73 CLKREQB AN13 CONNECT AT ASIC
AP37 NC#72 GENERICA AJ19
CLKREQ# requires open drain connection,
AK19 GENERICB R32 1 DNI 2 10K
GENERICB and cannot be used as pinstrap
GENERICC AJ20
GENERICD AK20
GENERICE_HPD4 AJ24
GENERICF_HPD5 AH26
GENERICG_HPD6 AH24
HPD1 AK24 HPD1 7

TEST_PG
IN
AH16 TEST_PG
1
R33
1K
2
OLAND M2 GDDR5
D D
+3.3V_BUS
AUD[1:0]:
DNI R10 1 2 4.7K V1SYNC 6 AUD[1] HSYNC 00 - No audio function;
OUT
1
MR10 2 4.7K AUD[0] VSYNC 01 - Audio for DisplayPort only;
10 - Audio for DisplayPort and HDMI if dongle is detected;
DNI 11 - Audio for both DisplayPort and HDMI.
U1E
DNI 1
R11 2 4.7K H1SYNC 6 HDMI must only be enabled on systems that are legally entitled
4.7K OUT
+1.8V 1
MR11 2 . It is the responsibility of the system designer to
ensure that the system is entitled to support this feature
180mA 10mA/bit AF15 VDDR4 DBG_DATA0 AU1
AG11 VDDR4 DBG_DATA1 AU3
1
AG13 VDDR4 DBG_DATA2 AW3

C6 AD12 VDDR4 DBG_DATA3 AP6
1uF AF11 AW5
6.3V VDDR4 DBG_DATA4
AG15 VDDR4 DBG_DATA5 AU5
2
AF12 VDDR4 DBG_DATA6 AR6

AF13 VDDR4 DBG_DATA7 AW6
DBG_DATA8 AU6
DBG_DATA9 AT7
DBG_DATA10 AV7
DBG_DATA11 AN7
DBG_DATA12 AV9
AR1 NC#1 DBG_DATA13 AT9
DBG_DATA14 AR10
AP8 DBG_CNTL0 DBG_DATA15 AW10
AW8 NC#2 DBG_DATA16 AU10
C AR3 NC#3 DBG_DATA17 AP10 C
DBG_DATA18 AV11
AR8 NC#4 DBG_DATA19 AT11
AU8 NC#5 DBG_DATA20 AR12
DBG_DATA21 AW12
+1.8V DBG_DATA22 AU12
1 221R
2 VREFG AH13 AP12
R17 DBG_VREFG DBG_DATA23
1 110R
2
R18
1C8 20.1uF
6.3V
OLAND M2 GDDR5
Place the crossfire

testpoints near the ASIC and
not the connector
Please pay attention to the grounding

strategies for these filter capacitors to
maintain a close loop for current.

U1F
+1.8V
75mA AM32 C46 2 112pF
UNNAMED_21_CAP_I273_B 50V
DP_VDDR
1
NC_XTAL_PVDD AF30
1
C13 C14 C15
27.000MHz
10uF 1uF 0.1uF AF31 R41
NC_XTAL_PVSS
B 6.3V 6.3V 6.3V 1M
B
Y3
AN32 DP_VSSR 1%
2
+0.95V
1
140mA XO_IN2 AW35 C47 2 112pF
UNNAMED_21_CAP_I271_B
50V
1
C31 C16 C17 AN31 DP_VDDC

4.7uF 1uF 0.1uF
6.3V 6.3V 6.3V
XO_IN AW34
2
+1.8V
1st source: 502G270001G
B5 +SPV18
1 2 75mA AM10 SPLL_PVDD C45 1 212pF
UNNAMED_21_CAP_I289_A 50V
1
120R
1
C18 C19 MR36 2 1 0R

C20
3
4
27.000MHz
4.7uF 1uF 0.1uF AN10 AV33 XTALIN R36 2 1 0R R37
6.3V SPLL_PVSS XTALIN 1M
6.3V 6.3V
Y1
1%
2
1
2
+0.95V MR40 2 1 0R
B6
1 2 150mA +SPV10 AN9 AU34 XTALOUT R40 2 1 0R C23 1 212pF
SPLL_VDDC XTALOUT
1
120R
C21 C22
1uF 0.1uF
6.3V 6.3V
+1.8V
2
B7
1 2 UNNAMED_21_BEAD_I209_B 200mA CLKTESTA AK10
1
120R H7 MPLL_PVDD
C24 C34 C35 C26 C27 H8 MPLL_PVDD CLKTESTB AL10
10uF 4.7uF 4.7uF 1uF 0.1uF
6.3V 6.3V 6.3V 6.3V 6.3V
2
OLAND M2 GDDR5
A SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD A

SHEET: Oland GPIO STRAP PLL

DATE: Mon Sep 21 10:05:39 2015 REV: 2.0

NOTES: NOTE
9 8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OPTIONAL ESD PROTECTION DIODES
D1700
DNI 2 1 ESD5V3U1U-02LRH A_R_DAC1_OUT
6
D1701
DNI 2 1 ESD5V3U1U-02LRH A_G_DAC1_OUT
6
See BOM for qualified filters
D1702
DNI 2 1 ESD5V3U1U-02LRH A_B_DAC1_OUT
Pseudo differential RGB should be routed from the ASIC to the display 6
D1703
connector without switching reference plane or running over split plane.
DNI 2 1 ESD8V0R1B-02LRH DDCDATA_DAC1_R
6 8
U1G
D1704
L1710
L1700
DNI 2 1 ESD8V0R1B-02LRH DDCCLK_DAC1_R
6 8
+1.8V B1700 VGA(3230000000G) D1705
2 1 +VDD1DI AC33 AD39 R_DAC1 1 2 UNNAMED_28_CAP_I296_A 1 2 DNI 2 1 ESD8V0R1B-02LRH A_HS_DAC1_OUT
VDD1DI R VGA 6
1
D 120R AVSSN AD37 VGA 0.047uH VGA 0.047uH VGA D1706 D
1
R1701 C1704 C1707 DNI 2 1 ESD8V0R1B-02LRH A_VS_DAC1_OUT
C1700 C1701 VGA 150R 6
1uF 0.1uF AC34 R1711 1% 8pF 12pF
6.3V 6.3V VSS1DI 150R 402 50V 402 50V
1%
2
G AE36 +5V_VESA
L1711
L1701
+1.8V AVSSN AD35
B1701 VGA(3230000000G)
2 1 +AVDD_DAC1 AD34 G_DAC1 1 2 UNNAMED_28_CAP_I285_A 1 2
AVDD VGA
1
120R VGA 0.047uH VGA 0.047uH VGA
1
AF37 B_DAC1 R1702 C1705 C1708 R1704 R1705
C1702 C1703 B VGA 150R 2.2K 2.2K
1uF 0.1uF AE34 AE38 R1712 1% 8pF 12pF VGA VGA MR1715 1VGA-CON 2 0R VGA_R
6.3V 6.3V AVSSQ AVSSN 150R 6
402 50V 50V VGA_G
1% 402 MR1716 1VGA-CON 2 0R 6
2
MR1717 1 VGA-CON 2 0R VGA_B
6
L1712
L1702
6 A_R_DAC1_OUT R1715 1 DVII 2 0R A_R_DAC1_F 8
OUT
HSYNC AC36 VGA(3230000000G) 6 A_G_DAC1_OUT R1716 1 DVII 2 0R A_G_DAC1_F 8
R1700 RSET
OUT
1 2 AB34 RSET VSYNC AC38 1 2 UNNAMED_28_CAP_I284_A 1 VGA 2 6 A_B_DAC1_OUT R1717 1 DVII 2 0R A_B_DAC1_F 8
OUT
1
499R 0.047uH
VGA 0.047uH VGA VGA
1
R1703 C1706 C1709 DDC1DATA R1707 1 VGA 2 33R DDCDATA_DAC1_R
VGA 150R 8 BI BI 8,6
R1713
DDCVGACLK AJ30 150R
1% 8pF 12pF
DDCVGADATA AJ31 1%
402 50V 402 50V
8 DDC1CLK R1706 1 VGA 2 33R DDCCLK_DAC1_R 6,8
TO DVI CONNECTOR
IN OUT
2
2
A_HSYNC_DAC1_R 8
OUT
A_VSYNC_DAC1_R 8
OLAND M2 GDDR5 OUT
U1700A
MJ1500 VGA-CON
VGA
A_HS_DAC1_OUT
H1SYNC 2 4 HSYNC_DAC1_B R1708 1 VGA 2 24R 6 A_HS_DAC1_OUT R1718 1 DVII 2 0R VGA_R 1
5 OUT 6 R
1
MR1718 1VGA-CON 2 0R VGA_HS VGA_G 2
6 6 G
C 74AHCT1G126GW C1711
6
VGA_B 3 B C
12pF 11 MS0
1
50V DDCDATA_DAC1_R
8 6 12 MS1
2
+5V_VESA
+5V_VESA 4 MS2
1
DDCCLK_DAC1_R 15
8 6 MS3
74AHCT1G126GW 9 NC
1
V1SYNC 2 4 VSYNC_DAC1_B R1709 1 VGA 2 24R 6 A_VS_DAC1_OUT R1719 1 DVII 2 0R VGA_HS 13
5 OUT
A_VS_DAC1_OUT 6 HS
1
MR1719 1
VGA-CON 2 0R VGA_VS C1712 C1713 VGA_VS 14
VGA 6 6 VS
C1710 1uF 68pF 5
+5V_VESA VSS
U1701A 6.3V 50V
12pF VGA-CON VGA-CON 6 VSS
2
50V
7 VSS
2
8 VSS
5
10 VSS
1
U1700B U1701B 16 CASE
C1781 C1782 17
VGA VGA CASE
0.1uF 0.1uF
6.3V 74AHCT1G126GW 74AHCT1G126GW 6.3V
VGA VGA
2
G3179C219-005
3
B B
U1H
PCIE3.0 Support: R1054=2K, R1053=8.45K
PCIE2.0 Support: R1054=4.75K,R1053=NC
+1.8V R1051 1 2 3.24K 1%

R1052 1 2 5.62K 1% PS_0 AM34 PS_0
C1052 1 20.082uF 16V
AD31 PS_1 CEC_1 AC30
+1.8V R1053 1 2 8.45k 1%
R1054 1 2 2K 1% PS_1 AG31 PS_2
C1054 1 20.1uF 6.3V
DNI AD33 PS_3
+1.8V R1055 1 2 4.75K 1% GENLK_CLK AD29
PS_2
R1056 1 DNI 2 5.1K GENLK_VSYNC AC29
C1056 1 20.68uF 4V
R1057 1 DNI 2 8.45K PS_3

+1.8V
R1058 1 2 4.75K 1% AF32 NC#25 SWAPLOCKA AJ21
C1058 1 20.082uF 16V V13 NC#28 SWAPLOCKB AK21
DNI U13 NC#27
MEM CONFIG ID: SEE MLPS Bit[3:1] AG21 NC#26
AC32 NC#24
PS_3[3:1] PU[R1057] PD[R1058] AA29 NC#23
000 NC 4.75K_3160475100G AC31 NC_SVI2
001 8.45K_3160845100G 2.00K_3160200100G AD30 NC_SVI2
010 4.53K_3160453100G 2.00K_3160200100G AD32 NC_SVI2 NC#39 AF33
011 6.98K_3160398100G 4.99K_3160499100G
100 4.53_3160453100G 4.99K_3160499100G
101 3.24K_3160324100G 5.62K_3160562100G
110 3.40K_3160340100G 10.0K_3160100200G
OLAND M2 GDDR5 AMD - PLATFORM HARDWARE ENG C <COPYRIGHT> Advanced Micro Devices
111 4.75K_3160475100G NC #48, No. 1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and
A A

SHEET: Oland DAC and MLPS

DATE: Tue Sep 22 06:32:58 2015 REV: 2.0

NOTES: NOTE
8 7 6 5 4 3 2 1
OPTIONAL ESD protection diodes
D2506
D2500 2 1ESD5V3U1U-02LRH DPA_AUXN DPA_3N 1 10 DPA_3N

7 7 A Y1 7
DPA_3P 2 9 DPA_3P
U1I 7 B Y2 7
D2501 2 1ESD5V3U1U-02LRH DPA_AUXP GND 3 8 GND
7 GND GND1
DPA_2N 4 7 DPA_2N
7 C Y3 7
AH12 DPA_2P 5 6 DPA_2P
NC#6 7 D Y4 7
NC#7 AP13
D2505
AP14 2 1ESD5V3U1U-02LRH HPD_DPA
NC#8 7 RCLAMP0524P
NC#9 AP15
NC#10 AT13
D2504
NC#11 AN24 GND DPA_1N
AN17 AP20 1 10 DPA_1N
DP_VSS NC#12 7 A Y1 7
AN19 AP21 DPA_1P 2 9 DPA_1P
DP_VSS NC#13 7 B Y2 7
AN27 AP22 GND 3 8 GND
DP_VSS NC#14 GND GND1
AN29 AP23 DPA_0N 4 7 DPA_0N
DP_VSS NC#15 7 C Y3 7
AP16 AP24 DPA_0P 5 6 DPA_0P
DP_VSS NC#16 7 D Y4 7
AP17 DP_VSS NC#17 AP25
AP18 DP_VSS NC#18 AP26
AP19 DP_VSS NC#19 AU18 RCLAMP0524P
AP27 DP_VSS NC#20 AU28
AP28 DP_VSS NC#21 AV19
AP29 DP_VSS NC#22 AV29
AP30 DP_VSS NC#29 L27
AR18 DP_VSS NC#30 N12
AR28 DP_VSS NC#31 AG12
AV17 DP_VSS NC#32 M12
AV27 DP_VSS NC#40 AR24
AW14 DP_VSS NC#41 AR14
AW16 DP_VSS NC#42 AT25
AW20 DP_VSS NC#43 AT15
AW22 DP_VSS NC#44 AV25
AW24 DP_VSS NC#45 AV15
AW26 DP_VSS NC#46 AU26
AW30 DP_VSS NC#47 AU16
AW32 DP_VSS NC#48 AR26
NC#49 AR16
NC#50 AT27
AL30 NC#AL30 NC#51 AT17 DP;HDMI
AL29 NC#AL29 NC#52 AU30 8 DPA_A0P C3530 1 20.1uF 6.3V 7 DPA_0P
IN
AN21 NC#AN21 NC#53 AR20 DP;HDMI
AK30 NC#AK30 NC#54 AV31 8 DPA_A0N C3531 1 20.1uF 6.3V 7 DPA_0N
IN
AM30 NC#AM30 NC#55 AT21 DP;HDMI
AM29 NC#AM29 NC#56 AT31 8 DPA_A1P C3532 1 20.1uF 6.3V 7 DPA_1P
IN
AM21 NC#AM21 NC#57 AV21 DP;HDMI
AK29 NC#AK29 NC#58 AR32 8 DPA_A1N C3533 1 20.1uF 6.3V 7 DPA_1N
IN
NC#59 AU22 DP;HDMI
AW28 NC#AW28 NC#60 AU32 8 DPA_A2P C3534 1 20.1uF 6.3V 7 DPA_2P
IN
AW18 NC#AW18 NC#61 AR22 DP;HDMI
NC#62 AT33 8 DPA_A2N C3536 1 20.1uF 6.3V 7 DPA_2N
IN
NC#63 AT23 DP;HDMI
NC#64 AV23 8 DPA_A3P C3537 1 20.1uF 6.3V 7 DPA_3P
IN
NC#65 AU24 DP;HDMI
NC#66 AT29 8 DPA_A3N C3538 1 20.1uF 6.3V 7 DPA_3N
IN
NC#67 AR30
NC#68 AV13 +5V_VESA R2701 1 HDMI 2 2.2K
NC#69 AU14 R2703 1 HDMI 2 2.2K
NC#70 AT19
NC#71 AU20 7 DPA_AUXP
7 DPA_AUXN
HPD_DPA
8 DDC2CLK R2528 1 DNI 2 0R DPA_AUXP

IN
OLAND M2 GDDR5
8 DDC2DATA R2529 1 DNI 2 0R DPA_AUXN

BI
1
DP;HDMI
1MMR2528 2
UNNAMED_7_MOSN_I328_D
MMR2529 DP;HDMI
0R
0R +12V_BUS
DP;HDMI
2
Q1801A
1 MR2529 2 +3.3V_BUS
2N7002DW
1
Q1801B
0R DP;HDMI 7
2N7002DW
4 UNNAMED_7_MOSN_I327_S 3 UNNAMED_7_MOSN_I327_D R1804 7 HPD_DPA
DP;HDMI DP;HDMI 10K
3
1 MR2528 2 1 UNNAMED_7_MOSN_I328_S 6 DP;HDMI
R2527
0R Q2513 1 1
UNNAMED_7_NPN_I268_B
2
2
MMBT3904 10K DP;HDMI
5
DP;HDMI
2
AUX1_BYPSS_EN HPD1
5 OUT
1
R2530
10K
DP;HDMI
2
J1
21
DPA_0P
SHELL1
7 1
D2+
2
DPA_0N
D2 Shield
7 3
DPA_1P
D2-
7 4 23
D1+
5
DPA_1N
D1 Shield
7 6
DPA_2P
D1-
7 7
D0+
8
DPA_2N
D0 Shield
7 9 MEC1
DPA_3P
D0-
7 10
CK+
11
DPA_3N
CK Shield
7 12
CK-
13
CE Remote
14
NC
1 DPA_0N
1 DPA_1N
1 DPA_2N
1 DPA_3N
1 DPA_0P
1 DPA_1P
1 DPA_2P
1 DPA_3P
+5V_VESA DPA_AUXP 15
DPA_AUXN
DDC CLK
16
DDC DATA
R2713 R2714 R2715 R2716 R2717 R2718 R2719 R2720 17 22
499R 499R 499R 499R 499R 499R 499R 499R
GND
18
HDMI HDMI HDMI HDMI HDMI HDMI HDMI HDMI
HPD_DPA
+5V
19
HP DET
2
SHELL2 20
1
DPA_GND
C2722 HDMI19PM_BLACK-HF
1uF N5Y-19M0231-L06
3
HDMI
HDMI_D19_4
2
Q2701
TMDP_EN 1 2N7002E
8 IN HDMI
2 OVERLAP HDMI WITH DP D


SHEET: HDMI

DATE: Tue Sep 22 06:32:59 2015 REV: 2.0

NOTES: NOTE
8 7 6 5 4 3 2 1
U1J
TXCAP_DPA3P AP34 DPA_A3P 7

+0.95V AK33 DP_VDDC TXCAM_DPA3N AR34 DPA_A3N 7
AK34 DP_VDDC TX0P_DPA2P AW37 DPA_A2P 7
AL33 DP_VDDC TX0M_DPA2N AU35 DPA_A2N 7
1
10V AM33 DP_VDDC TX1P_DPA1P AR37 DPA_A1P 7
C1523 C1524 C1525 AN33 DP_VDDC TX1M_DPA1N AU39 DPA_A1N 7
4.7uF 1uF AP31 AP35 DPA_A0P
6.3V 6.3V DP_VDDC TX2P_DPA0P 7
0.1uF
AP32 DP_VDDC TX2M_DPA0N AR35 DPA_A0N 7
2
AP33 DP_VDDC
AK35 DPB_TXCAP
TXCBP_DPB3P 8
AL36 DPB_TXCAN
TXCBM_DPB3N 8
D +1.8V
TX3P_DPB2P AJ38 DPB_TX0P
8
D
AF34 AK37 DPB_TX0N
DP_VDDR TX3M_DPB2N 8
AG34 AH35 DPB_TX1P
DP_VDDR TX4P_DPB1P 8
1
10V AH34 AJ36 DPB_TX1N
DP_VDDR TX4M_DPB1N 8
AJ34 AG38 DPB_TX2P
C1520 C1521 C1522 DP_VDDR TX5P_DPB0P 8
4.7uF 1uF 0.1uF DPB_TX2N
AL38 DP_VDDR TX5M_DPB0N AH37 8
6.3V 6.3V
AM37 DP_VDDR
2
AF39 DP_VSSR
AH39 DP_VSSR
AK39 DP_VSSR
AL34 DP_VSSR
AM35 DP_VSSR
AN34 DP_VSSR AUX1N AL27
AN38 DP_VSSR AUX1P AM27
AP39 DP_VSSR
AR39 DP_VSSR DDC1CLK AM26 DDC1CLK 6
OUT
AU37 DP_VSSR DDC1DATA AN26 DDC1DATA 6
BI
AUX2N AM20 AUX2N

7
BI
AUX2P AN20 AUX2P
7 DVI DPB_GND
BI
DVI 1BTX2PR1501 2
AM19 DDC2CLK DPB_TX2P 1 2 C1501 0.1uF 6.3V 499R BTX2P
DDC2CLK OUT 7 8 8
2 1 DPEF_CALR AM39 AL19 DDC2DATA
R1500 DP_CALR DDC2DATA BI 7 DVI
150R DPB_TX2N 1 2 C1502 0.1uF 6.3V BTX2M
8 DVI DVI 8
DVI 2BTX1PR1503 1 1BTX2M
R1502 2
DPB_TX1P 1 2 C1503 0.1uF 6.3V 499R 499R BTX1P
OLAND M2 GDDR5 8 8
DVI
DPB_TX1N 1 2 C1504 0.1uF 6.3V BTX1M
8 DVI DVI 8
C DVI 2 R1505 1 2BTX1MR1504 1 C
DPB_TX0P 1 2 C1505 0.1uF 6.3V 499R 499R BTX0P
8 8
DVI
DPB_TX0N 1 2 C1506 0.1uF 6.3V BTX0M
8 DVI DVI 8
2BTXCP
R1507 1 R1506
2BTX0M 1
DVI
DPB_TXCAP 1 2 C1507 0.1uF 6.3V 499R 499R BTXCP
8 8
DVI
DPB_TXCAN 1 2 C1508 0.1uF 6.3V BTXCM
8 BTXCM
DVI 8
2 R1508 1
499R
+12V_BUS
3
DVI
R1544 DVI
10K
Q1501
1 2N7002E
2
+5V_VESA
7 TMDP_EN DVI
OUT
2
J1500
1
DVI 25 CASE
C1543
0.1uF BTX2M 1 TMDS_Data2-
16V 8
BTX2P 2 TMDS_Data2+
8
2
3 TMDS_Data2/4_Shield
4 TMDS_Data4-
OPTIONAL ESD PROTECTION DIODES 5 TMDS_Data4+
6 DDCCLK_DAC1_R 6 DDC_Clock
IN
6 DDCDATA_DAC1_R 7 DDC_Data
BI
6 A_VSYNC_DAC1_R 8 Analog_VSYNC DVII
IN BTX1M
8 9 TMDS_Data1- 1st source:NTK 6140106400G
BTX1P 10 TMDS_Data1+
8 2nd source:FOXCONN 6140068701G
DNI 11 TMDS_Data1/3_Shield
12 TMDS_Data3-
D1600
13 TMDS_Data3+
B 8
BTX2P 5 6 BTX2P
8
C1526 2 11uF 10V 14 +5V_Power B
BTX2M 4 D Y4 7 BTX2M DVI 15 GND_(for_+5V)
8 8
3 C Y3 8 16HPD_DVIB
Hot_Plug_Detect
BTX1P 2 GND GND1 9 BTX1P BTX0M 17 TMDS_Data0-
8 8 8
BTX1M 1 B Y2 10 BTX1M BTX0P 18 TMDS_Data0+
8 8 8
A Y1 19 TMDS_Data0/5_Shield
DNI DNI
RCLAMP0524P 2 1ESD5V3U1U-02LRH HPD_DVIB 20 TMDS_Data5-
8
21 TMDS_Data5+
D2503
22 TMDS_Clock_Shield
BTXCP 23 TMDS_Clock+
DNI 8
BTXCM 24 TMDS_Clock-
8
D1602
BTX0P 5 6 BTX0P +3.3V_BUS A_R_DAC1_F C1

8 8 6 IN Analog_Red
BTX0M 4 D Y4 7 BTX0M A_G_DAC1_F C2
8 8 6 IN Analog_Green
3 C Y3 8 A_B_DAC1_F C3
6 IN Analog_Blue
BTXCP 2 GND GND1 9 BTXCP A_HSYNC_DAC1_R C4
8 8 DVI 6 IN Analog_HYNC
3
BTXCM 1 B Y2 10 BTXCM C5 27
8 8 Analog_GND CASE#M3
A Y1 Q1502
DNI 1 HPD2_IN 1 R1518 2 HPD_DVIB
8 C6 Analog_GND#C6 CASE#M4 28
MMBT3904 10K DVI CASE#M5 29
RCLAMP0524P
26 CASE#M2 CASE#M6 30
2
GPIO_14_HPD2
5 OUT
DVI-I
1
DVI
R1517
10K
2

A
SHEET: Oland TMDP sDVI

DATE: Mon Sep 21 10:05:46 2015 REV: 2.0

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+VDDC
OLAND Power & GND
1
C117 C118 C119 C88 C89 C106 C107 C108
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2
D D
1
C109 C110 C111 C112 C113 C114 C115 C116
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
+MVDD 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
+MVDD U1L
2
U1K
B9 VSS VSS A3
AC7 VDDR1 VDDC AA15 C1 VSS VSS A37
1
AD11 VDDR1 VDDC AA17 C39 VSS VSS AA16
AF7 VDDR1 VDDC AA20 C182 C168 C169 C170 C171 C172 C173 C85 E35 VSS VSS AA18
AG10 AA22 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF E5 AA2
VDDR1 VDDC 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VSS VSS
AJ7 VDDR1 VDDC AA24 F11 VSS VSS AA21
2
AK8 VDDR1 VDDC AA27 F13 VSS VSS AA23
AL9 VDDR1 VDDC AB16 F15 VSS VSS AA26
1
G11 VDDR1 VDDC AB18 F17 VSS VSS AA28
G14 VDDR1 VDDC AB21 C183 C184 C185 C186 C187 C188 C189 C190 C79 F19 VSS VSS AA6
1
G17 AB23 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF F21 AB12
VDDR1 VDDC 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VSS VSS
C141 G20 VDDR1 VDDC AB26 F23 VSS VSS AB15
2
0.1uF G23 AB28 F25 AB17
10V VDDR1 VDDC VSS VSS
G26 VDDR1 VDDC AC17 F27 VSS VSS AB20
2
G29 VDDR1 VDDC AC20 F29 VSS VSS AB22
H10 VDDR1 VDDC AC22 F31 VSS VSS AB24
J7 VDDR1 VDDC AC24 F33 VSS VSS AB27
1
1
J9 VDDR1 VDDC AC27 F7 VSS VSS AC11
C134 C135 C136 C137 C138 C139 C140 K11 VDDR1 VDDC AD18 C176 C177 C178 C191 C192 C300 C301 C302 F9 VSS VSS AC13
1uF 1uF 1uF 1uF 1uF 1uF 1uF K13 AD21 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF G2 AC16
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VDDR1 VDDC 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VSS VSS
K8 VDDR1 VDDC AD23 G6 VSS VSS AC18
2
2
L12 VDDR1 VDDC AD26 H9 VSS VSS AC2
1
L16 VDDR1 VDDC AF17 J2 VSS VSS AC21
1
L21 VDDR1 VDDC AF20 MC176 MC177 MC178 MC191 MC192 MC300 MC301 MC302 J27 VSS VSS AC23
1
L23 AF22 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF J6 AC26
MC131 VDDR1 VDDC 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VSS VSS
4.7uF L26 AG16 J8 AC28
MC130 VDDR1 VDDC VSS VSS
2
6.3V
4.7uF L7 AG18 K14 AC6
VDDR1 VDDC Overlap cap pair foorprints (0805 with 0603) VSS VSS
2
6.3V
M11 VDDR1 K7 VSS VSS AD15
2
N11 VDDR1 VDDC AH27 L11 VSS VSS AD17

C P7 VDDR1 VDDC Y23 L17 VSS VSS AD20 C
R11 VDDR1 VDDC Y26 L2 VSS VSS AD22
1
U11 VDDR1 VDDC AH22 L22 VSS VSS AD24

C130 C131 U7 VDDR1 L24 VSS VSS AD27
10uF 10uF Y11 L6 AD9
6.3V 6.3V VDDR1 VSS VSS
Y7 VDDR1 VDDC AH28 M17 VSS VSS AE2
2
VDDC M26 M22 VSS VSS AE6

VDDC N24 M24 VSS VSS AF10
VDDC R18 N16 VSS VSS AF16
VDDC R26 N21 VSS VSS AG17
VDDC T17 N23 VSS VSS AG2
N26 VSS VSS AG6
VDDC T20 N6 VSS VSS AG9
VDDC T22 R15 VSS VSS AJ10
VDDC T24 R17 VSS VSS AJ11
VDDC U16 R2 VSS VSS AJ2
VDDC U23 R24 VSS VSS AK11
VDDC U26 R27 VSS VSS AK31
VDDC V17 R6 VSS VSS AK7
VDDC V20 T11 VSS VSS AL11
VDDC Y16 T21 VSS VSS AL20
VDDC Y18 T23 VSS VSS AL23
+1.8V VDDC Y21 T26 VSS VSS AL26
+1.8V VDDC Y28 U15 VSS VSS AL32
+0.95V U17 VSS
U2 VSS VSS AL6
250 mA AF26 VDD_CT VSS AL8
AF27 VDD_CT U20 VSS VSS AM11
1
AG26 VDD_CT BIF_VDDC T27 U22 VSS VSS AM31

B C161 C162 C163 AG27 VDD_CT U24 VSS VSS AM9 B
1uF 1uF 0.1uF N27 U27 AN11
6.3V 6.3V 6.3V BIF_VDDC VSS VSS
1
M18 VDDCI U6 VSS VSS AN2
2
R13 VDDCI C75 C77 C76 V11 VSS VSS AN30

AA13 4.7uF 1uF 1uF V16 AN6
VDDCI 6.3V 6.3V 6.3V VSS VSS
AB13 VDDCI 2 V18 VSS VSS AN8
2
AC12 VDDCI V21 VSS VSS AP11
+VDDCI AC15 VDDCI V23 VSS VSS AP7
Overlap cap pair foorprints AD13 VDDCI V26 VSS VSS AP9
+VDDCI (0805 with 0603) T12 W2 AR5
VDDCI VSS VSS
AD16 VDDCI W6 VSS VSS B11
M15 VDDCI Y15 VSS VSS B13
1
M16 VDDCI Y17 VSS VSS B15

C196 MC196 C195 C194 C193 C87 C86 T15 VDDCI Y20 VSS
10uF 4.7uF 1uF 1uF 0.1uF 0.1uF 0.1uF M23 Y22 B17
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VDDCI VSS VSS
N13 VDDCI Y24 VSS VSS B19
2
N15 VDDCI Y27 VSS VSS B21

N17 VDDCI AH21 VSS VSS B23
V15 VDDCI TS_A AL31 AG20 VSS VSS B25
N20 VDDCI VSS B27
N22 VDDCI AG22 NC VSS B29
Y13 VDDCI A39 VSS_MECH#1 VSS B31
ASIC_FB_VDDC AW1 VSS_MECH#2 VSS B33
R12 VDDCI FB_VDDC AF28 13 AW39 VSS_MECH#3 VSS B7
OUT
1
R16 VDDCI ASIC_FB_GND

MC103 C90 C91 C92 13 AH29 FB_GND
4.7uF 0.1uF 0.1uF 0.1uF OUT
6.3V 6.3V 6.3V 6.3V
AG28 FB_VDDCI OLAND M2 GDDR5
2
OLAND M2 GDDR5

A
SHEET: Oland Power&GND

DATE: Mon Sep 21 10:05:46 2015 REV: 2.0

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Linear Regulators
LDO #1: Vin = +1.5V +/-2% Vout = +0.95V +/- 2%; Iout = 1.44A (TBV) RMS MAX
PCB: 50 to 70mm sq. copper area for cooling
+MVDD +3.3V_BUS
1
C800
10uF R800 R801

10K 5.1K GS7166 2480154800G
6.3V
1% +0.95V
2
+5V DNI U800 COMMON(2480154800G)
VOUT = 0.8 x (1 + FBR1/FBR2)
2
3 VIN VOUT 6
1
4 7 0.95V_FB C802 C803 C804
VDD FB
1
10uF 10uF 0.1uF
1
1
0.95V_REFIN FBR2 FBR1 6.3V 6.3V 16V
15 +0.95V_EN 2 EN NC 5 DNI NS800
C IN C
2
1
C805 FBR800 R803
THMPAD
NS_VIA
5.36K 1.02K
1
1uF +0.95V_PG 1 8 1% 1% C801

15 OUT POK GND
2
6.3V C806 680pF
2
2
50V
UNNAMED_8_CAP_I21_B
0.1uF GS7133SO
2
6.3V
DNI
2
R805 1 DNI 2 0R
B B

A
SHEET: 0.95V

DATE: Mon Sep 21 10:05:44 2015 REV: 2.0

8 7 6 5 4 3 2 1
+12V_BUS
1
B703
ER1801
SMD 1uH
1R
2
+MVDD_Source
EC1801 +MVDD_SOURCE
uP1537 U603 1000pF

0805 0805 0805
EC183 EC182 EC181
+3.3V_BUS EC124 ER1596 10uF 10uF 10uF
15 OUT
MVDD_POK MVDD_POK 1 10 MVDD_BOOT MVDD_BOOT MVDD_BOOT_C
POK BOOT
1
R617 10K 0.1uF 0R
2
R730 2 1 2 9 MVDD_UG ER307 EQ40
5.49K CS UGATE
1% MVDD_UG MVDD_UG_R 1 4
MVDD
2
15 MVDD_EN MVDD_EN 3 8 MVDD_PHASE 0R APM3023 SOT223 +MVDD

IN
3
EN PHASE
1
C730 MVDD_PHASE
0.1uF MVDD_FB_GS 4 7 U603_VDD EL64 +MVDD +MVDD
10V VFB VCC5
MVDD Dip 1.6uH
2
5 6 MVDD_LG
RF LGATE
1
GND
ER308 EQ41
R620 MVDD_LG MVDD_LG_R 1 4 + C726 C725 C727 C728
10K
820uF 0.1uF 0.015uF 390pF
11
2
2.5V 10V 10V 50V
0R APM3023 SOT223 MVDD MVDD MVDD MVDD
2
NS900
+5V
1
C777 1uF 6.3V R711 1K 0.1%
1 2
UNNAMED_25_NETSHORT_I42_N1 1 2
0402
ER20 R710 1K 0.1%
2.2 ohm 1 2
MVDD_FB_GS 15
IN
MVDD_FB_GS 11
OUT
U603_VDD
1
FBR702
11K
0402 1%
EC168
2
0.1uF

SHEET: MVDD

DATE: Tue Sep 22 06:32:59 2015 REV: 2.0
SHEET NUMBER: 11 OF 20 TITLE:17ci203

TITLE:

NOTES: NOTE
ER1802
+VDDC_Source
1R
+VDDCI
EC1802
1000pF
1
0805 0805 0805 C912 C913 C914 + C915
EC184 EC186 EC187 22uF 22uF 22uF 820uF C916 C917 C918
10V 10V 10V
EC125 ER1597 22uF 22uF 22uF VDDCI VDDCI VDDCI
2.5V
VDDCI 0.1uF 0.015uF 390pF
2
10V 10V 50V
VDDCI_BOOT VDDCI VDDCI VDDCI
2
6
0.1uF 0R 1G2D1S D 5
Q9B
ER309
SO08_I190X150
VDDCI_UG VDDCI_UG_R 4G COMMON
S 3 EL65 +VDDCI
EMU42 0R Dip 1.6uH
30V
10A@25C
1 8 VDDCI_PHASE 0.018R@10V, [email protected]
BOOT Phase 20A
1.2W
20V
2 7
HG COMP
8
R234
1 2 3 6 1G2D1S D 7
GND FB
Q9A
PGND
0R
4 5 ER310
LG VCC
2
SO08_I190X150
VDDCI_LG VDDCI_LG_R 2G COMMON
NS901
uP1543SSU8 S 1
9
0R 30V
10A@25C
0.018R@10V, [email protected]
1
20A
1.2W
20V
Rtop
ER12
+12V_BUS 1.62K
1
EC7 ER11
R236
0R
0402 4700pF 0 ohm
2
ER21
2.2 ohm
EMU42_VCC ER22 VDDCI_FB_GS 15

IN
30K
0402 EC1693
EC170 10pF
0.1uF
EC1694
0.022uF
VDDCI_EN
VDDCI_FB_GS 12
OUT
+3.3V_BUS
1
VDDCI_FB VDDCI_FB
1
R919 R920 VDDCI_FB
VDDCI_EN 10.5K 53.6K
15 R921
IN
2
VDDCI_FB
10.5K
2
402
R915
2
10K RFB2
3
1
Q901A
GPIO_7_VDDCI_VID0 5 2N7002DW
5
IN VDDCI_FB
4
VDDCI_FB
2
R916
10K
+3.3V_BUS
VDDCI Low Side Divider
1
VDDCI_FB
R917
10K 6
1
Q901B
GPIO_16_VDDCI_VID1 2 2N7002DW
5 IN VDDCI_FB
2
VDDCI_FB
1
R918
10K
1

SHEET: VDDCI

DATE: Tue Sep 22 06:32:59 2015 REV: 2.0

NOTES: NOTE
+VDDC_Source
1
C633 C615 C616 C617 C619 +
C631
0.15uF 10uF 10uF 10uF 10uF 270uF
16V 16V 16V 16V 16V 16V
603 1206 1206 1206 1206
2
VDDC VDDC VDDC VDDC VDDC
DNI
Mirrored on PCB Mirrored on PCB 6.3x7 TH
9
8
7
6
5
Input Bulk CAP
Input MLCC
9
8
7
6
5
820pF
Q601 C614
MDU1514U Q602 VDDC_FB
MDU1514U 1 VDDC 2 25V 13 15
VDDC VDDC
DNI Connect to C626 +VDDC
R613
4
3
2
1
1 VDDC 2 47K 1% 1 VDDC 2
13
VDDC_UGATE_CTR R601 1 VDDC 2 0R VDDC_UGATE1
100NF
+VDDC
4
3
2
1
C612
R602 1VDDC_UGATE_CTR
VDDC 2 0R VDDC_UGATE2 L601 0.47uH
13 VDDC_PHASE 1 2
VDDC
VDDC and MVDD source
1
R619 +12V_BUS
2.2R
VDDC C623 C624 C629 + C625 + C626
C630
9
8
7
6
5
805 10uF 10uF

0.1uF 0.015uF 820uF 820uF
2
10V 10V 6.3V 6.3V 2.5V 2.5V
UNNAMED_24_CAP_I23_A
402 402 0805 6.3V 6.3 x 9 mm, TH 6.3 x 9 mm, TH
2
0805 6.3V
1
VDDC VDDC VDDC VDDC VDDC VDDC
Q603
C608
MDU1517 DNI DNI DNI
1
VDDC 1.8NF B702
50V
VDDC
2
603
SMD 1uH
Output MLCC
4
3
2
1
Output Bulk CAPs
2
9
8
7
6
5
Place across
LS MOSFET +VDDC_Source
Overlap
Q604
MDU1517
9
RC snubber values shown
VDDC
are for reference only, +3.3V_BUS
IN
tuning is required
603
1
VDDC_LGATE_CTR R603 1 VDDC 2 0R VDDC_LGATE_1
13
4
3
2
1
R604 1VDDC_LGATE_CTR
VDDC 2 0R VDDC_LGATE_2 R699
5.49K
603 1%
ASIC_FB_GND
VDDC
2
VDDC_EN 15
IN
1
C699
+12V_BUS 0.1uF R696
8.45K
1
10V
VDDC 1%
2
MR666 R666 VDDC
DNI DNI
2
0R 0R
VDDC VDDC <PositionInPackage>
1
2
2
R612
UNNAMED_24_GS7210A_I35_NC
412k
1% C611
VDDC
6.8nF
2
R618 1 VDDC 2
1 VDDC 2 0R VDDC_BOOT
1
0603
R609,MR609 share pad

C605
0.1uF R609 1 VDDC 2 0R VDDC_FB

13 13 15
14
15
16
18
17
16V
VDDC
2
MR609 1 VDDC 2 0R ASIC_FB_VDDC

9 13
VOUT
NC
EN
TON
GND
GND
BOOT
VDDC_UGATE_CTR 12
13 UGATE
U601 1
R605 VOUT
1 VDDC 2 9.1K 1% VDDC_PHASE 13 VDDC_PHASE 11 PHASE
VDDC VDDA 2 UNNAMED_24_CAP_I100_A R607 1 VDDC 2 2.2R
+5V
+5V 0603
10 UNNAMED_24_GS7210A_I35_OCSET
OCSET RFB
GS7210A-ATQ ASIC_FB_VDDC
FB 3 UNNAMED_24_GS7210A_I35_FB
R690 1 VDDC 2 0R R611 1 VDDC 2 10K 1% 9,13
IN
1
1 VDDC 2 UNNAMED_24_CAP_I102_A 9 VDDP PGOOD 4 C613 1 2 56pF ASIC_FB_VDDC
1
1
C606
R614
2.2R C603 1uF MR690 VDDC_FB
13,15
10V 0R OUT
1uF VDDC VDDC
2
LGATE
VSSP
GND
REFIN
10V
VDDC
2
2
VDDC_LGATE_CTR
13
VDDC_PWR_GOOD
15
OUT
1
C622
0.1uF
10V
VDDC_REF_IN
DNI
2
15IN

SHEET: VDDC

DATE: Tue Sep 22 06:32:59 2015 REV: 2.0

TITLE:

NOTES: NOTE
Linear Regulators
LDO #2: Vin = 3.00V to 3.60V (3.3V +/- 9%) Vout = +1.8V +/- 2%; Iout = 1.6A (TBV) RMS MAX
PCB: 50 to 70mm sq. copper area for cooling
+3.3V_BUS +3.3V_BUS
1
1
C866
10uF R863 R862

6.3V 5.49K 10K GS7166 2480154800G
1% +1.8V
2
DNI U861 COMMON(2480154800G)

+5V
2
2
VOUT = 0.8 x (1 + FBR3/FBR4)
3 VIN VOUT 6
1
+5V Power
1
4 7 1.8V_FB C865 C862 C861 C864
VDD FB
R865 180pF 10uF 10uF 0.1uF
13K 50V 6.3V 6.3V 16V
+1.8V_EN 2 5 1.8V_REFIN FBR3 1%
15,1 IN EN NC DNI
2
1
THMPAD
+12V_BUS +5V
2
C868 +1.8V_LDO_POK 1 8 REG400
15 OUT POK GND
1
1uF 3 IN 5V OUT 2
1
1
6.3V C870
GS7135-ASO AZ1117CH-5.0
2
1
R870 0.1uF FBR4 FBR861 +5V_VESA
GND
7.15K 10K
TAB
10V C807 C808 C809
1% DNI 402 1%
2
DNI
10uF 22uF 10uF
2
4
0805 0805 0805 F400 5V
R866 1 DNI 2 0R 1 2
2
200mA 24V
1
R1710
100
2
1
1
C867
R1714
0.1uF 300
DNI
2

SHEET: VDDCI

DATE: Tue Sep 22 06:32:59 2015 REV: 2.0

NOTES: NOTE
Power Management - Power Gating and Dynamic Voltage Control
+3.3V_BUS
POWER SEQUENCE
1
+1.8V-2.8ms->MVDD-3.4ms->0.95V-4.3ms->VDDC +12V_BUS
R857 +1.8V_EN 1,14
0.95V must ramp up before VDDC
10K
1%
OUT VDDC Low Side Divider
3
2
R852 PSEQ_PU R839 1 2 5.1K PSEQ_PU_R 1
11.3K Q851
1
1% MMBT3904 +3.3V_BUS
6
C846
Place close
2
Don't support BACO PSEQ_12V 2 Q850A 0.1uF to its CTLR +3.3V_BUS
1
MMDT3904-7 10V
Support CTF(Internal) Node 3 DNI +5V
2
1
C681
1
R853
3P3_RAMP
+3.3V_BUS 0.1uF
1K
1
10V R688
1% DAC
2
U680 DAC
4.32K
1% R622
2
10K
1
GPIO_15_VID0 DAC
1 VCC VID0 8 5 15 GPIO
2
R850 2 7 GPIO_20_VID1
GND VID1 5 15
2
2.32K
1% MR877 1 PSD 2 0R MVDD_EN SCL 3 6 VDDC_REF R689 1 DAC 2 0R VDDC_REF_IN
OUT 11 5 IN SCL VREF OUT 13
3
+12V_BUS 5 SDA 4 SDA R1 5 UNNAMED_14_RES_I110_A
BI
1
PSEQ_3V3 5 Q850B
1
MMDT3904-7 C680
uP1801AMT8
1
0.033uF R687
I2C Adress: 0xA2
4
16V 3.74K
R851 1%
DAC
2
1K
1
DAC
1% Symbol should use uP1801(it is bigger one)
2
R843
1st Source: 2480111500G GS8601
2
5.1K
PSM 2nd Source: 2480105100G uP1801
+1.8V
3
MVDD_ENABLE# R846 1 PSM 2 5.1K PSEQ_MVDD_EN 5 Q840B
1
MMDT3904-7
PSM
R841
4
1K
1%
PSM
6
14 +1.8V_LDO_POK R804 1 2 0R R877 1 PSM 2 0R 2 Q840A
IN
1
MMDT3904-7
PSM
CTF_PWROFF_B C841
16 IN
1
1
1uF
R845 6.3V
DNI
2
8.45K
1%
DNI
2
Rf24 Rf23 Rf22=60K. Rf21=80K. Rf20=30K.
Rf22=40.2K. Rf21=120K. Rf20=29.4K.
13 VDDC_FB
IN
1
MR806 1 PSD 2 0R +0.95V_EN R678 R676 R671 R672 R650 RFB2
OUT 10 20K 20K 30K 40.2K 29.4K
+12V_BUS 1% 1% 1% 1% 1%
DNI DNI GPIO GPIO GPIO
2
1
R832
5.1K
PSM
3
+MVDD +3.3V_BUS
SEQ_VDDC_0.95V# R831 1 PSM 2 5.1K 5 UNNAMED_14_NPN_I67_B Q839B
MMDT3904-7
PSM VDDC_FB_IN2
1
1
VDD_FB_IN1
6
R885 R673
1K 20K
1% DNI
6
PSM
Q606B
2
2
MVDD_POK R806 1 PSM 2 0R MVDD_GD 2 GPIO_15_VID0 2 2N7002DW
11 IN Q839A 5,15 IN GPIO
1
MMDT3904-7
PSM
1
1
C848 +3.3V_BUS
1
R886 1uF MR673
1.6K 6.3V 20K
1% DNI DNI
2
1
PSM
2
3
R674
20K
DNI
Q606A
2
GPIO_20_VID1 5 2N7002DW
5,15 IN GPIO
4
MR674
20K
DNI
2
+3.3V_BUS
MR894 1 PSD 2 0R VDDC_EN 13 VDDC_FB_IN3

OUT
6
R675
20K
DNI
Q607B
2
5 IN INT
1
MR675
20K
+3.3V_BUS DNI VDDC_FB_IN4
2
10 +0.95V_PG
IN
3
R677
20K
DNI
Q607A
2
5 IN INT
4
MR677
20K
+MVDD DNI
2
+12V_BUS
1
R9 VDDCI_EN
10K OUT 12
1
PSM
3
R890
2
1K
1% 5 Q838B
PSM MMDT3904-7
2
PSM
4
13 VDDC_PWR_GOOD 2 Q838A
IN MMDT3904-7
PSM
1

SHEET: VDDC

DATE: Tue Sep 22 06:32:59 2015 REV: 2.0

NOTES: NOTE
8 7 6 5 4 3 2 1
For 2-WIRE FAN ONLY

GPIO6 is 0: Fan stop
GPIO6 is PWM: Fan running FANOUT_P
16
1
Install R4520
C4103
GPIO6 is 1: Fan stop
Fan Control
1uF
Mechanical and Thermal Management Install R4516 Q4511,R4519 GPIO6 is PWM: Fan running 16V
2
FANOUT_N
16
D D
DVI/DVI SCREWS with top tab
+1.8V +12V_BUS
This circuit provides a minimum voltage for the fan,
independent of PWM input -> check if needed for RV710
2 FANOUT_P
1
U1M
1
D1721 C4008
BAT54S
C4020 AJ32 AF29 R4105 C4403 1uF
TSVDD DPLUS 1K DNI
16V
1uF 3 22uF 0805
2
6.3V 16V
AJ33 TSVSS DMINUS AG29 DNI
2
+3.3V_BUS +12V_BUS
Q4102
UNNAMED_15_PNP_I428_E
GPIO_28_FDO AK32
UNNAMED_15_OLANDM2GDDR5_I347_GPIO28FDO
Q4101 JU4001
1
MMBT3906
2
PWM_B MMBT3906 16 FANOUT_P 1
1
PFB 1 1 NFB R4107 1 2 820R 16 FANOUT_N 2
1
OLAND M2 GDDR5 R4100
2.61K
1
1% R4112 C4104 HEADER_1X2_SHROUDED
3
DNI 5.1K
DNI R4108 1uF R4110
Q4100
2
1M 0R
2
R4410 TS_FDO 2N7002E 16V
1 2 1 DNI DNI
2
D4100
BAT54KFILM BU ONLY
20K
2
1
DNI
2
1
R4409
1
20K
MR4104 DNI
10K
UNNAMED_15_RES_I420_A
2
2
4
2
R4113
6.8K
DNI VDIFF 1 Add Copper under pad 4
Q4103
PBSS4350Z (at least 1cm^2)
3
1
Warning: TS_FDO is not 5V tolerant. MAX sink current 1.65mA C4102
If Critical Temperature is reached this will force the fan to run at full 1uF R4106
6.3V 1K
speed while power is removed from GPU & rest of the board.
2
This is an open collector signal. Active level is hard pull down to ground. overlap
2
footprints for
D4101 and
MD4101
Critial Temperature Fault
6
C R4057 1 2 20K PWM_ENB 2 Q4010A
C
MMDT3904-7
1
C4402 R4063 +12V_BUS
100K
0.1uF DNI
16V
DNI
1
R4102 +12V_BUS
3K
2
R4103 1 2 10K
1
1
1
MB4001
R4111 C4100 R4109 26R
Place close to its CTLR
1K 1M
1
FAN12VC
1% 1uF DNI B4001
2
DNI 16V
26R
2
FAN12DC
UNNAMED_15_BEAD_I458_B
CTF2: R4051=20K, R4053 DNI, C4401=0.1UF; CTF_PWROFF_B 15
OUT
1
Critial Temperature Fault
2
3
R4150
10K
GPIO_19_CTF R4051 1 2 20K CTF_PWROFF 5 FAN12VC
5 IN Q4010B
2
MMDT3904-7
2
1
1
1 UNNAMED_15_MOSP_I468_G Q4150
4
C4401 R4053
R4411 100K EMF60P02J
10K 0.01uF DNI
1
50V FAN12VC
2
R4151
2nd source 2020003202G(AO3515L)
3
10K
FAN12VC
2
FANOUT_P
UNNAMED_15_NPN_I465_C
16
3
1,2 PERST#_BUF R4152 1FAN12VC 2 UNNAMED_15_CAP_I464_A
5.1K 1 Q4151
IN
1
MMBT3904
C4150 FAN12VC
2
22uF
4V
DNI
B B
2
For HDMI Connector
ASSY-SCREW203
HDMI_Fee
BK1
BRACKET
BRACKET
SCREW
HDMITABSCREW;DPTABSCREW Caicos_Fansink Caicos_Fansink Caicos_Fansink Caicos_Fansink

HS4D HS4C HS4B HS4A
Single-slot fansink 14W Single-slot fansink 17W

HS2 HS3
For DVI Connector 8020055300G

8020055300G
ASSY200 ASSY201 7120036200G 7123281100G
DVI;VGA DVI;VGA
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
7020000800G 7020000800G
MT200
TurksPro_Fansink
25WHS(7122107700G) 25WHS(7122107700G) 25WHS(7122107700G)
SCREW202
HS1A
HS1B
HS1C HS1D
Rectangular Heatsink 8W CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
A AMD - PLATFORM HARDWARE ENG A

SCREW
BRACKSCREW(7020005200G)
C <COPYRIGHT> Advanced Micro Devices
Bracket, VGA, HDMI, DVI

25WHS(7122107700G) #48, No. 1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and
7020005200G 8020055200G
Bracket, VGA, DP(tab), DVI prohibited. Use of this schematic and design for any purpose other than
80200552A0G evaluation requires a Board Technology License Agreement with AMD.
9 17
16 25
24 32
SHEET: Mech/Thermal Management
Bracket, LP, DP(tab), DVI
1
2
3
4
5
6
7
8
10
11
12
13
14
15
18
19
20
21
22
23
26
27
28
29
30
31
PCB1
8020055300G of merchantability or fitness for a particular purpose, and disclaims
AMD
PCB
DATE: Mon Sep 21 10:05:42 2015 REV: 2.0
PCB(109-C86951-00)
Bracket, LP, HDMI, DVI 80200553A0G
33W FANSINK 7120481200G
8 7 6 5 4 3 2 1
(19) Debug Circuits
J2 J4 J3 J5
3 1 3 1
4 2 4 2
JTAG
X_PIN1*2 X_PIN1*2 impedence impedence
U1N
AD28 TESTEN
TESTEN 17
AM23 JTAG_TRSTB
JTAG_TRSTB 17
JTAG_TCK AK23 JTAG_TCK
17 TOP Bottom TOP Bottom
AN23 JTAG_TDI
JTAG_TDI 17
JTAG_TDO AM24 JTAG_TDO
17
Single end Single end Different Different
JTAG_TMS
JTAG_TMS AL24 17 RGB Address trunk TMDS PEX_PCIE
OLAND M2 GDDR5 +3.3V_BUS 50 ohm +/- 10% 37 ohm +/- 5 ohm 85 ohm +/- 10 % 85 ohm +/- 10 %
J4004
HEADER_RECEPT_2X4 +3.3V_BUS 4.02 mils 7.05mils 4.33 mils / 5.511 mils 4.33 mils / 5.51 mils
DEBUG
JTAG_TDO 7 8
17
1
JTAG_TDI 5 6 J10
17 J9 J7 J8
JTAG_TMS 3 4
17 R436
JTAG_TCK 1K 3 1 3 1
17 1 2 DNI
4 2 4 2
2
17 TESTEN X_PIN1*2 X_PIN1*2 impedence impedence
1
R437
JTAG_TRSTB R38 2 1 1K 1K
17 +3.3V_BUS L3_INNER L4_INNER L3_INNER L4_INNER
2
1
Single end Single end Different Different
R39
1K
DNI
Memory data Memory data TMDS Mem Clock
JTAG_TRSTB
45 ohm +/- 5 ohm 45 ohm +/- 5 ohm 85 ohm +/- 10 % 80 ohm +/- 10 %
2
engineering board pull high
production board pull down 6.89 mils 6.89 mils 4.33 mils / 5.511 mils 5.12 mils / 7.48 mils
FM1
1 SW_FB
FM2
1 SW_FB
FM3
1 SW_FB
FM4
EM2 1 SW_FB
1
1 FM5
1 SW_FB
E23-5611010-RH
GND FM6
1 SW_FB

SHEET: VDDCI

DATE: Tue Sep 22 06:32:59 2015 REV: 2.0

NOTES: NOTE
8 7 6 5 4 3 2 1
MVDD SOURCE
D 1.5A
1.5V@10A D
DVI-I HPD4 DDC/AUX4
HDMI HPD1 DDC/AUX1

12V_BUS
DP HPD3 DDC/AUX5
5.5A VDDCI SOURCE 1.05V@6A
0.6A
VDDC PHASE1 SOURCE

VDDC@25A
2.7A
C C
VDDC PHASE2 SOURCE
2.7A VDDC@25A
GPIO15 VDDC_VID0
GPIO20 VDDC_VID1
FAN
0.5A
GPIO7 VDDCI_VID DEFAULT 1
GPIO5 VR_HOT
0.95V SOURCE 0.95V@1A

B B
1A
3.3V_BUS 1.8V_LDO
0.5A [email protected]
3A
3.3V@60mA
A SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD A

SHEET: GPIO DDC HPD map

DATE: Tue Sep 22 06:32:59 2015 REV: 2.0

TITLE:

NOTES: NOTE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY CHANNEL A & B
Debug
GDDR5 4pcs 128Mx32 (2GB)
D D
CH A&B
JTAG/I2C
GPIO
POWER REGULATORS
From +12V
+VDDC
+MVDD
FAN
From +12V LINEAR:
ROM
Straps
+5V_VESA, +5V_VESA2
C From +12V_BUS SL TMDS HDMI

C
TMDP-A AC Coupling Caps Connector
+5V BIOS
From +3.3V_BUS converter(+0.95V):

5V_VESA
Thermal
PCIE_VDDC, DPLL_VDDC, DDC AUXDDC2

Speed control
DPx_VDD10, SPV10, MEM_VREF
DisplayPort
GPIO17
& temperature
INTERRUPT HPD1 Connector
From +3.3V Direct:
sense D+/D-
VDDR3, AVDD
FAN Temp. Sensing
TS_FDO
Built-in PWM
From 3.3V Linear (1.8V)
Overlap
PCIE_PVDD, PCIE_VDDR, VDDR4,
Dynamic Power Management

DPLL_PVDD, SPV18, MPV18, DL TMDS
VDD1DI, VDD2DI, AVDD, AVDDQ, AC Coupling Caps sDVI-I

TMDPB
DPx_PVDD, DPx_VDD18, VDD_CT,

POWER DELIVERY
TSVDD
DACVGA Connector
RGB Filters
Oland AUXDDC1
B B
HPD2 5V_VESA
XO_IN2
XO_IN VGA CONN
Temperature Critical
CTF XTALIN
PCI-Expressx8 27MHz Xtal

Power Sequencing
Circuit
Oland GDDR5 2GB

+3.3V_BUS
HDMI/DP SL-DVI-I
+12V_BUS
PCI-Express Bus

A
SHEET: BLOCK DIAGRAM

DATE: Fri Sep 18 08:34:41 2015 REV: 2.0

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AMD
TITLE:
Oland G5 2GB VGA/sDVI-I+HDMI/DP DOCUMENT NUMBER: 105-C869xx-00B DATE: Tue Sep 22 02:20:17 2015 SHEET NUMBER: 20 OF 20 REV: 2.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC. C <COPYRIGHT>Advanced Micro Devices
ENGINEER: NOTES:
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
AMD - PLATFORM HARDWARE ENG
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than #48, No. 1387, ZHANGDONG ROAD
REVISION HISTORY Tony Yang NOTE evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
SHANGHAI, CHINA 201203
responsibility for any consequences resulting from use of the information included herein.
SCH PCB Date REVISION DESCRIPTON

Rev Rev
1.00 00A 04/15/14 1. Initial release
2.00 00B 09/22/15 2. Add VGA, etc
D D
C C
B B
A A
8 7 6 5 4 3 2 1

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Pci-Express Edge Connector: BI IN

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8 7 6 5 4 3 2 1

PCI-EXPRESS EDGE CONNECTOR

2 PETN7_GFXRN7 B46 PETn7 GND A46

C1005 C1006 C1007

C1008 C1009 C1010

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

A AMD - PLATFORM HARDWARE ENG C <COPYRIGHT> Advanced Micro Devices

of merchantability or fitness for a particular purpose, and disclaims

SHEET NUMBER: 1 OF 20 TITLE:

Oland G5 2GB VGA/sDVI-I+HDMI/DP

Oland PCIe Interface

NOTE: Some of the PCIE testpoints will

be available through vias on traces.

M35 NC#M35 NC#N30 N30

L38 NC#L38 NC#L33 L33

C K35 NC#K35 NC#L30 L30 C

J38 NC#J38 NC#K33 K33

H35 NC#H35 NC#J33 J33

G38 NC#G38 NC#K30 K30

F35 NC#F35 NC#H33 H33

R1015 1 DNI 2 1K AL21 UNNAMED_2_OLANDM2GDDR5_I166_PXEN

AA32 NC#34 VSS K39

U28 PCIE_VDDC VSS Y34

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

A AMD - PLATFORM HARDWARE ENG C <COPYRIGHT> Advanced Micro Devices

of merchantability or fitness for a particular purpose, and disclaims

SHEET NUMBER: 2 OF 20 TITLE:

Oland G5 2GB VGA/sDVI-I+HDMI/DP

4,3 DQA0_<0> C37 DQA0_0 4 3C18

4,3 MAA0_<0> G24 MAA0_0 4 3H19

DRAM_RST 1 2 DRAM_RST_RR 1 2 DRAM_RST_R AH11 L20 AA12

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

AMD - PLATFORM HARDWARE ENG C <COPYRIGHT> Advanced Micro Devices

for evaluation purposes. Further distribution or disclosure is strictly

AMD makes no representations or warranties of any kind regarding this

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

SHEET NUMBER: 03 OF 20 TITLE:

Oland G5 2GB VGA/sDVI-I+HDMI/DP

VSSQ_R11 R11 VSSQ_R11 R11 VSSQ_R11 R11 VSSQ_V1 V1

C2135 C2136 C2137 C2127 C2122 C2126 C2131

4V 4V 4V 4V 4V 4V 4V C2236 C2237 C2238 C2227 C2235 C2228 C2234

4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF

6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

AMD - PLATFORM HARDWARE ENG C <COPYRIGHT> Advanced Micro Devices

for evaluation purposes. Further distribution or disclosure is strictly

evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

SHEET NUMBER: 04 OF 20 TITLE:

Oland G5 2GB VGA/sDVI-I+HDMI/DP

OLAND GPIOs Strap CF XTAL OSC

PN 2280007900G for 1Mbit (PM25LV010A-100SCE)

HPD1 AK24 HPD1 7

AG13 VDDR4 DBG_DATA2 AW3

AF12 VDDR4 DBG_DATA6 AR6

Place the crossfire