Scribd Logo
Upload

Welcome to Scribd!

  • 8 views

    CDF DLD Lab 2020

    Uploaded by

    Muhammad Fayyaz Khan AP Electronics ABT
    This document describes a 3rd semester Digital Logic Design Lab course offered at UET Abbottabad Campus in Fall 2021. The course is worth 1 credit hour and meets for 3 hours per week over 15 weeks. The course objectives are to design and implement logical circuits through experiments and introduce Verilog HDL programming. Upon completing the course, students will be able to implement combinational and sequential logic circuits and design a mini project. The course covers experiments with logic gates, flip-flops, registers, counters and more. Student learning is assessed through lab experiments and a project report.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    CDF DLD Lab 2020

    Uploaded by

    Muhammad Fayyaz Khan AP Electronics ABT
    8 views3 pages
    This document describes a 3rd semester Digital Logic Design Lab course offered at UET Abbottabad Campus in Fall 2021. The course is worth 1 credit hour and meets for 3 hours per week over 15 weeks. The course objectives are to design and implement logical circuits through experiments and introduce Verilog HDL programming. Upon completing the course, students will be able to implement combinational and sequential logic circuits and design a mini project. The course covers experiments with logic gates, flip-flops, registers, counters and more. Student learning is assessed through lab experiments and a project report.

    Original Description:

    cdf dld lab 2020

    Original Title

    cdf dld lab 2020

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document describes a 3rd semester Digital Logic Design Lab course offered at UET Abbottabad Campus in Fall 2021. The course is worth 1 credit hour and meets for 3 hours per week over 15 weeks. The course objectives are to design and implement logical circuits through experiments and introduce Verilog HDL programming. Upon completing the course, students will be able to implement combinational and sequential logic circuits and design a mini project. The course covers experiments with logic gates, flip-flops, registers, counters and more. Student learning is assessed through lab experiments and a project report.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    8 views3 pages

    CDF DLD Lab 2020

    Uploaded by

    Muhammad Fayyaz Khan AP Electronics ABT
    This document describes a 3rd semester Digital Logic Design Lab course offered at UET Abbottabad Campus in Fall 2021. The course is worth 1 credit hour and meets for 3 hours per week over 15 weeks. The course objectives are to design and implement logical circuits through experiments and introduce Verilog HDL programming. Upon completing the course, students will be able to implement combinational and sequential logic circuits and design a mini project. The course covers experiments with logic gates, flip-flops, registers, counters and more. Student learning is assessed through lab experiments and a project report.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    You are on page 1of 3

    Starting: Sep 2021

    DEPARTMENT OF ELECTRONIC ENGINEERING

    UET ABBOTTABAD CAMPUS

    Course Description File


    Semester: 3rd Fall 2021
    Instructor: Muhammad Fayaz Khan

    ELE-210L DIGITAL LOGIC DESIGN LAB

    Credit Hours Contact Hours Pre-requisite(s)

    1 3 hrs. /week x 15 weeks= 4 hrs. -

    COURSE OBJECTIVES:

    The aim of this Lab is the design and implementation of logical circuits. Experiments are intended to
    enhance students learning about logic circuits implementation using ICs and introduction to Verilog HDL
    programming (ISim).

    COURSE LEARNING OUTCOMES (CLOS):


    Upon successful completion of the course, the student will be able to:

    Taxonomy
    No. Statement of CLO Domain PLO
    Level

    CLO-1 Implement combinational logic circuits Psychomotor P2 3

    CLO-2 Implement sequential logic circuits Psychomotor P2 3

    CLO-3 Design mini project Psychomotor P3 11


    RELEVANT PROGRAM LEARNING OUTCOMES (PLOS):
    The course is designed so that students will achieve the following PLOs:
    1 Engineering Knowledge 7 Environment and Sustainability

    2 Problem Analysis 8 Ethics

    3 Design/Development of Solutions  9 Individual and Team Work

    4 Investigation 10 Communication

    5 Modern Tool Usage 11 Project Management 

    6 The Engineer and Society 12 Lifelong Learning

    RECOMMENDED BOOK:

    Laboratory Manual

    COURSE CONTENTS:

    Lab Experiments:

    1. Verify truth tables for basic logic gates i.e. AND OR NOT gates.
    2. NOT gate using BC 548.
    3. Construct implementation of Boolean functions using logic gates ICs.
    4. Canonical forms of Boolean function.
    5. Conversion of Boolean function from one canonical form to other form and compare results.
    6. Implement AND OR and NOT gates using NAND IC 7400.(Verilog also)
    7. Construct NAND using Transisters.
    8. Implementation and verification of half adder, full adder, half subtracter and full subtracter using
    logic gates . Also verify 4 bit adder using 7483 IC.(verilog also)
    9. Study the operation of decoder, demultiplexer , multiplexer and BCD adder on Logic trainers.(Verilog
    also)
    10. Study the operation of flipflops i.e RS, D and JK.(Verilog also)
    11. Implement registers and counters on advanced logic trainers.(Verilog also)
    Sr. # Course Learning Psychomotor Assessment Assessment
    Outcomes %marks
    Lab 1,2,3,4 40
    Lab5,6,7 30
    1 CLO1 P2
    Lab8,9 30

    Lab10 100
    2
    CLO2 P2

    Lab
    1,2,3,4,5,6,7,8,9 25
    3 CLO3 P4 Lab10 25
    Project report 50

    Assessment Plan for Course Learning Outcomes (Lab)

    You might also like