Experiment 7 - Flip-Flops

Experiment No: 7
FLIP-FLOPS
AIM:
To verify the truth tables of RS, D, JK, Master-Slave JK, T Flip flops using NAND gate.
OBJECTIVES:
At the end of the experiment, the student should be able to
1) Understand Master-slave flip-flop.

2) Implement different flip-flops and verify their truth tables using NAND gates alone.
COMPONENTS AND EQUIPMENTS REQUIRED:
S. No. Name Type Quantity

1 NAND gate (2 input) IC 7400 2
2 NAND gate (3 input) IC 7410 1
3 Digital IC trainer kit 1
4 Connecting Wires
THEORY:
Sequential Circuits:
The logic circuits whose outputs at any instant of time depend not only on the present
input but also on the past outputs are called sequential circuits. The simplest kind of sequential
circuit which is capable of storing one bit of information is called latch. The operation of basic
latch can be modified, by providing an additional control input that determines when the state of
the circuit is to be changed. The latch with additional control input is called the Flip-Flop. The
additional control input is either the clock or enable input.
Flip-flops:
Flip-flops are basic memory elements which can store one bit (either 0 or 1) of data. They
are synchronous bistable devices, also known as bistable multivibrators. Here synchronous
means that the output changes state only at a specific point on a triggering input called the clock
(CLK). That is, changes in the output occur in synchronization with the clock. An edge-triggered
flip-flop changes state either at the positive edge (rising edge) or at the negative edge (falling
edge) of the clock pulse and is sensitive to its inputs only at this transition of the clock. There are
four basic types, namely, S-R, D, J-K and T Flip-Flops. Shift registers, memory and counters are
built by using flip-flops.
SR Flip-flop: S and R stands for SET and RESET. There are four input combinations possible at
the inputs. S = R = 1 is called forbidden state since the output will be indeterminate.
D Flip-flop: It has only one input referred to as D input or Data input. The input data is
transferred to the output after a clock pulse applied. IC 7474 is a positive edge triggered dual D
Flip-flop.
JK Flip-flop: The indeterminate output state of SR FF when S = R = 1 is avoided by converting

it to a JK FF.
Master-slave JK Flip-flop: The race around condition of JK FF is rectified in master slave

JKFF. Racing is the toggling of the output more than once during a positive clock edge. It is
created by cascading two JK FFs. IC 7476 is a negative edge triggered dual Master-Slave JK
Flip-flop.
T Flip-flop: T stands for toggle. The output toggles when a clock pulse is applied. That is the
output of the flip flop changes state for an input pulse. T flip flop can be derived from JK Flip
flop by shorting J and K inputs.
PROCEDURE:
1) Test all the components using a digital IC tester

2) Verify the pin out of IC and ensure that the ICs have been perfectly plugged into the
breadboard or sockets before feeding the inputs
3) Write the identification number of ICs and input, output pin numbers of ICs in your
logic diagram.
4) Connect VCC = 5V & GND to the respective pin numbers of each ICs.
5) Set up the circuits of each flip-flops one by one. Complete the connection as per the
logic diagram
6) Apply inputs to the circuit from switches block of the trainer kit.
7) Connect output of the circuit to the LED indicators of the trainer kit.
8) Switch on VCC and apply clock pulses either manually (mono-shot pulse) or from
fixed frequency clock signals.
9) Verify output of the logic gates at LED indicators of the trainer kit.
10) Change the input, apply clock pulses and verify the truth table.
RESULT:
Verified the truth tables of SR, D, JK, Master Slave JK and T Flip Flops using NAND
gates.
SR FLIP-FLOP USING NAND GATES:
Circuit: Truth Table:

S R
0 0
0 1 0
1 0 1
1 1 x
D FLIP-FLOP USING NAND GATES:

D
0 0
1 1
JK FLIP-FLOP USING NAND GATES:

J K
0 0
0 1 0
1 0 1
1 1 ̅̅̅̅
MASTER-SLAVE JK FLIP-FLOP USING NAND GATES:

J K
0 0
0 1 0
1 0 1
1 1 ̅̅̅̅
T FLIP-FLOP USING NAND GATES:

T
0
1 ̅̅̅̅

Experiment 7 - Flip-Flops

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Experiment No: 7

At the end of the experiment, the student should be able to

1) Understand Master-slave flip-flop.

COMPONENTS AND EQUIPMENTS REQUIRED:

S. No. Name Type Quantity

JK Flip-flop: The indeterminate output state of SR FF when S = R = 1 is avoided by converting

Master-slave JK Flip-flop: The race around condition of JK FF is rectified in master slave

1) Test all the components using a digital IC tester

Circuit: Truth Table:

D FLIP-FLOP USING NAND GATES:

Circuit: Truth Table:

JK FLIP-FLOP USING NAND GATES:

Circuit: Truth Table:

Circuit: Truth Table:

T FLIP-FLOP USING NAND GATES:

Circuit: Truth Table:

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