High-Speed Switching Operation For A Sic Cmos and Power Module
High-Speed Switching Operation For A Sic Cmos and Power Module
High-Speed Switching Operation For A Sic Cmos and Power Module
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LETTER
High-speed switching operation for a SiC CMOS and power module
Atsushi Yao1, a) , Mitsuo Okamoto1 , Fumiki Kato1 , Hiroshi Hozoji1 , Shinji Sato1 , Shinsuke Harada1 , and Hiroshi Sato1
Abstract This paper deals with the high-speed switching operation of imental turn-on and turn-off switching speeds of about 24
a main circuit when using a silicon carbide (SiC) complementary metal- V/ns and −30 V/ns, respectively, at room temperature and a
oxide semiconductor (CMOS) and power module for the high-speed drive. DC bus voltage of 300 V using a SiC CMOS gate driver [17].
When using the developed power module and SiC CMOS gate buffer, we
experimentally achieved the turn-on and turn-off switching speeds of about Our study explores the further faster switching of main cir-
−100 and 80 V/ns at a DC bus voltage of 600 V and a load current of 20 cuits by using a power module for high-speed drive and SiC
A. Based on the I -V characteristics of the developed SiC CMOS and the CMOS gate buffer with large output current characteristics
gate charge of the SiC power MOSFET, the approximate switching time of several amperes during the Miller plateau.
was calculated. Modules for the high-speed switching of the SiC power
Keywords: module, SiC CMOS, high-speed switching, wide-bandgap
power semiconductors, gate driver, SiC MOSFET MOSFET in the main circuit has been studied recently [14,
Classification: Power devices and circuits 15, 16]. In previous studies [15, 16], a Si gate driver was
placed outside the module and then the inductance of the
1. Introduction main circuit in the module was reduced to realize the high-
speed switching. Based on these studies [15, 16], in addition
Wide-bandgap (WBG) power semiconductors such as sil- to reducing the inductance of the gate wire, a way of reducing
icon carbide (SiC) and gallium nitride (GaN) have been the inductance of the main circuit in the module using the
widely researched owing to their advantages of high with- developed SiC CMOS was explored.
stand voltage, fast switching and high-frequency operation, This study focuses on a high-speed switching operation
high-temperature tolerance, and low on-resistance [1, 2, 3, of the SiC power MOSFET in the main circuit when using
4, 5, 6, 7, 8]. For instance, miniaturization and high output a low-inductance module for the high-speed drive and the
power density of power converters can be achieved by the SiC CMOS gate buffer. To quickly charge and discharge
high-frequency operation [1, 9, 10, 11]. For high-frequency the gate capacitor, the current required for SiC CMOS gate
operation, it is important to reduce the switching time of buffer was estimated, and then the parallelized SiC CMOS
main circuits. To realize high-speed switching of the main was developed to achieve a large output current of the SiC
circuit, the gate capacitor of power devices should be quickly CMOS. In addition, we developed a module that can in-
charged and discharged [12]; in other words, a high-output- corporates both this SiC CMOS gate buffer and the power
current gate buffer is required and then the inductance be- MOSFET. In this module, the inductance of the main cir-
tween the gate buffer and power metal-oxide semiconductor cuit in the module was reduced by connecting two substrates
field-effect-transistor (MOSFET) should be low [13], and together and by incorporating a snubber circuit within the
the inductance of the main circuit should be reduced to sup- module [15, 16]. We experimentally examined the switch-
press current and voltage surges [14, 15, 16]. In this study, ing speed of the main circuit in a double-pulse-test when
the main circuit inductance was reduced and a SiC comple- using the developed module and SiC CMOS gate buffer. In
mentary metal-oxide semiconductor (CMOS), which can be addition, the switching time was estimated by calculations
operated at high-temperatures [17], and power SiC MOS- based on the gate (Qg ) charge of the SiC power MOSFET
FET were installed in the same module to shorten the gate and the I-V characteristics of the developed SiC CMOS.
wire. Such a design cannot be achieved using a Si gate driver
owing to the effects of heat. 2. Design, fabrication, and method
The recent SiC devices function as not only switching
elements of main circuits, but also various gate drive cir- Figure 1(a) shows a schematic circuit of the system to mea-
cuits [17, 18, 19]. In addition, several researchers focused sure the switching phenomenon. This circuit primarily con-
on SiC integrated circuits with CMOS designs [17, 20, 21, sists of the SiC power MOSFET of the main circuit and
22, 23, 24, 25]. Recently, M. Barlow et al. realized exper- the SiC CMOS-based final output transistor (gate buffer)
of the gate driver. To measure the current and the volt-
1 National Institute of Advanced Industrial Science and Technol- age in the double-pulse-test, a voltage probe (TPP0850,
ogy (AIST), 16-1 Onogawa, Tsukuba 305-8569, Japan Tektronix, Inc.), a Rogowski coil current probe (SS-284A,
a) a.yao@aist.go.jp Iwatsu Electric Co., Ltd.), and a digital phosphor oscillo-
scope (DPO5104, Tektronix, Inc.) were used. The induc-
DOI: 10.1587/elex.18.20210234 tance L was 5 mH.
Received May 24, 2021
Accepted June 4, 2021
Figure 1(b) shows a photograph of the developed module.
Publicized June 14, 2021 This module consists of a SiC MOSFET (UMOS [26] of
Copyedited July 25, 2021
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Copyright © 2021 The Institute of Electronics, Information and Communication Engineers
IEICE Electronics Express, Vol.18, No.14, 1–5
Fig. 2 Typical gate charge waveform for the UMOS at 600 V and 20 A.
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of parallels is 1,200 and one unit is 100 µm. The approx- obtained an output current on the order of several amperes.
imate dimensions of SiC CMOS gate buffer are 1.2 × 2.8 Figure 4(a) shows the experimental turn-off and turn-on
mm (active area) without pads. The thickness of the gate waveforms of Vds and Ids under a switching condition of a DC
oxide film is 90 nm. In our SiC CMOS gate buffer, the ratio bus voltage of 600 V and a load current of 20 A with Vdd of
of the areas PMOS and NMOS is 1:1. For further details, 20 V in the double-pulse-test. Figures 4(b) and (c) indicate
see the fabrication process of the SiC CMOS component the experimental turn-off and turn-on waveforms of Vds at
in Ref [25], wherein the process employed was almost the
same as that in this study. The internal resistance of the SiC
CMOS gate buffer acted as the gate resistor, and no external
gate resistor was used [17]. Note that this internal resistance
is a nonliear resistor that depends on the applied voltage.
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