BITS Pilani

presentation
R.K.Tiwary
BITS Pilani EEE
Pilani Campus [email protected]
 BITS Pilani
Pilani Campus

Physics and Modelling of Microelectronic Devices

Lecture No.16 ( MOSFET’s Ideal and non Ideal
Characteristis)
Semiconductor Physics
and Devices
Basic Principles 4e

Donald A. Neamen

Chapter 10 & 11
MOSFET operation and
Nonideal effects

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 Current–Voltage Relationship
a very small VDS voltage

small VDS voltage ID = gd VDS

where gd is defined as the channel conductance in
the limit as VDS → 0
 µn is the mobility of the electrons in the inversion
layer and |Qn‘| is the magnitude of the inversion
layer charge per unit area
 MOS transistor action is the modulation of the
channel conductance by the gate voltage

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 Current–Voltage Relationship

a larger VDS

a small VDS

value VDS = VDS (sat)

value VDS > VDS (sat)
VDS(sat) =VGS - VT

gd=0

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 Current–Voltage Relationship
In the non-saturation region

Family of ID versus VDS curves for an n-

channel enhancement mode MOSFET.

When the transistor is biased in the saturation region, the ideal current–voltage
relation is given by

In general, for a given technology, the process conduction parameter, kn’, is a constant. design of
a MOSFET, in terms of current capability, is determined by the width-to-length parameter

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 Current–Voltage Relationship

Cross section of an n-channel depletion Family of ID versus VDS curves for an n-

mode MOSFET channel depletion mode MOSFET

Thickness tc must be less than the maximum induced space charge width in
order to be able to turn the device off

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 NONIDEAL EFFECT(Channel Length Modulation)
 We assumed in the derivation of the ideal current–voltage relationship that the channel length
L was a constant.
 However, when the MOSFET is biased in the saturation region, the depletion region at the
drain terminal extends laterally into the channel, reducing the effective channel length
The depletion width extending into the p-region of a pn
junction under zero bias

For a one-sided n+p junction, essentially all of the applied

reverse-biased voltage is across the low-doped p region. The
space charge width of the drain–substrate junction is

Cross-section of an n-channel MOSFET

showing the channel length modulation effect

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 NONIDEAL EFFECT(Channel Length Modulation)
the space charge region defined by ∆L, as shown in Figure
, does not begin to form until VDS > VDS (sat)

Where ∆VDS = VDS - VDS (sat)

Since the drain current is inversely proportional to the
channel length, we may write

drain current in saturation

Current–voltage characteristics of a Since λ is normally small

MOSFET showing short-channel effects
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 NONIDEAL EFFECT(Channel Length Modulation)
Determine the increase in drain current due to short channel modulation.
Consider an n-channel MOSFET with a substrate doping concentration of Na= 2X1016 cm-3 , a
threshold voltage of VT = 0.4 V, and a channel length of L =1µm. The device is biased at VGS=1V
and VDS = 2.5 V. Determine the ratio of actual drain current compared to the ideal value

∆L= 0.1807 µm

The actual drain current increases as the effective channel length decreases
when the transistor is biased in the saturation region.

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 Breakdown mechanisms in the MOSFET
A Condition at which the drain-to-substrate space charge
Near Punch-Through Effects
region extends completely across the channel region to the
source-to-substrate space charge region. In this situation,
the barrier between the source and drain is completely
eliminated and a very large drain current would exist.
Drain-Induced Barrier Lowering (DIBL): drain current will
begin to increase rapidly before the actual punch-through
condition is reached
 The large potential barriers prevent significant current between the drain and source

The pn junction built-in potential barrier is given by

The zero-biased source–substrate pn junction width is

The reverse-biased drain-substrate pn junction width is given by
At punch-through, we will have xd0 +xd = L and xd = L - xd0
Thus

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 Drain-Induced Barrier Lowering (DIBL):
As the two space charge regions approach punch-through, the abrupt junction approximation is no
longer a good assumption.
The drain current will begin to increase rapidly before the theoretical punch-through voltage is
reached.
DIBL, occurs is significantly less than the ideal punch-through voltage
Near punch-through occurs when the two depletion regions are within approximately six Debye
lengths (LD ) of each other; Where

At near punch-through, we will have 𝑥𝑑𝑂 + 6𝐿𝐷 + 𝑥𝑑 = 𝐿

𝑥𝑑 = 𝐿 − 6𝐿𝑑 − 𝑥𝑑𝑜

Then, at near punch-through we have 𝑥𝑑2 𝑒𝑁𝑎

𝑉𝑏𝑖 + 𝑉𝐷𝑆 =
2 ∈𝑠

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 breakdown mechanisms in the MOSFET
 Oxide Breakdown: If the electric field in the oxide becomes large enough
 Electricfield on breakdown is the order of 6 X106 V /cm
 A gate voltage of approximately 30 V would produce breakdown in an oxide with a
thickness of 500 Å.
 safety margin of a factor of 3 is common
A MOS device has a silicon dioxide insulator with a thickness of tox =20 nm =200 Å. Determine
the ideal breakdown voltage. If a safety factor of 3 is required determine the maximum safe
gate voltage that may be applied.
𝑉𝐺 𝑉𝐺 12
𝛦𝑜𝑥 ≅ 6× 106 = ⇒ 𝑉𝐺 = 12V 𝑉𝐺 = = 4V
𝑡𝑜𝑥 200 × 10−8 3

for an oxide thickness of tox =8 nm = 80 Å

6
𝑉𝐺 4.8
6 × 10 = ⇒ 𝑉𝐺 = 4.8V 𝑉𝐺 = = 1.6V
80 × 10−8 3

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 Near Avalanche and Snapback Breakdown

circuit including the parasitic bipolar transistor.

n-channel MOSFET

snapback breakdown effect.

Substrate current–induced voltage drop

Currents in the parasitic bipolar transistor
IC= αIE + ICB0
For open Base IC= αIC + ICB0

At breakdown IC= M( αIC + ICB0 ) and

Avalanche breakdown just begins An empirical relation for the multiplication factor is usually written as

m is an empirical constant in the range of 3 to 6 and VBD is the junction breakdown voltage
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 I–V relations to experimentally determine
µ & VT
for very small values of VDS,

mobility  The extrapolation of the straight line to zero current gives

the threshold voltage, and the slope is proportional to the
inversion carrier mobility.
subthreshold conduction  we can obtain the same information from both curves

ID versus VGS (for small VDS) for

enhancement mode MOSFET

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NONIDEAL EFFECT(mobility variation)
 variation in mobility with gate voltage Schematic of carrier
surface scattering
 the velocity saturation limit
effects.

 A positive gate voltage produces a force on the

electrons in the inversion layer toward the surface
 electrons travel through the channel toward the drain,
they are attracted to the surface, but then are repelled
by localized coulombic forces called surface scattering
Vertical electric field in an
n-channel MOSFET.  The surface scattering effect reduces mobility
 If there is a positive fixed oxide charge near the oxide-semiconductor interface, the mobility
will be further reduced due to the additional coulomb interaction
 The relationship between the inversion charge mobility and the transverse electric field is
usually measured experimentally.
 Effective transverse electric field Eeff Q’SD(max)= eNa xdT & Q’n is the
 The effective mobility µeff inversion layer charge/ Area

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NONIDEAL EFFECT(Velocity Saturation)
 Prominent in shorter-channel devices
 since the corresponding horizontal electric field is generally larger
 carrier velocity saturates with increasing electric field.
 Velocity saturation occurs at 104V/cm
 If VDS = 5 V in a device with a channel length of L= 1µm => E= 5 X 104 V/Cm
 The modified ID(sat) characteristics are described approximately by
 ID (sat) = W Cox (VGS - VT)vsat
 vsat (saturation velocity) = 107cm/sec
 The saturation velocity will decrease somewhat with applied gate
voltage because of the vertical electric field and surface scattering

The transconductance is independent of V GS and VDS.

fT the cutoff frequency

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 Substrate Bias Effects
(a)Applied voltages on an
n-channel MOSFET.
(b) Energy-band diagram
at inversion point when
VSB = 0.
(c) Energy-band diagram
at inversion point when
VSB > 0 is applied.

When VSB = 0, we had

When VSB >0, the space charge width increases and we now have

The change in the space charge density is then

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 Substrate Bias Effects
To reach the threshold condition, the applied gate voltage must be increased

where ∆VT = VT (VSB > 0) - VT (VSB = 0).

VSB must always be positive so that, for the n-channel device, VT is always positive
The threshold voltage of the n-channel MOSFET will increase as a function of the source–
substrate junction voltage
we may define

where γ is defined as the body-effect coefficient.

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 Substrate Bias Effects
Calculate the body-effect coefficient and the change in the threshold voltage due to an
applied source-to-body voltage. Consider an n-channel silicon MOSFET at T = 300 K.
Assume the substrate is doped to Na =3 X 1016 cm-3 and assume the oxide is silicon
dioxide with a thickness of tox =20 nm =200 Å. Let VSB =1 V.

The change in threshold voltage for VSB = 1 V is

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 Transconductance
 change in drain current with respect to the corresponding change in gate voltage
 The transconductance is sometimes referred to as the transistor gain
 in the non-saturation region

=>

 in the saturation region

=>

The transconductance is a function of the geometry of the device as well as of

carrier mobility and threshold voltage

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 Small-Signal Equivalent Circuit
Inherent resistances and capacitances What about substrate to source capacitance?
in the n-channel MOSFET structure

Small-signal equivalent circuit of a

commonsource n-channel MOSFET
Simplified, low-frequency small-signal
equivalent circuit

source resistance rs can have a significant effect

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 Frequency Limitation Factors and Cutoff
Frequency
 There are two basic frequency limitation
 the channel transit time
 gate or capacitance charging time

High-frequency small signal equivalent circuit

CM is the Miller capacitance

in the saturation region, Cgd essentially becomes zero, but Cgdp is a constant

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 fT the cutoff frequency
The cutoff frequency fT is defined to be the
frequency at which the magnitude of the current
gain of the device is unity

And Id = gm Vgs

=1 =>

In the ideal MOSFET Cgsp and Cgdp = 0, in the saturation region, Cgd 0 and Cgs is
approximately CoxWL

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 MOSFET SCALING
K ≈ 0.7 per generation of a given technology
original NMOS transistor

scaled NMOS transistor

 The channel length is scaled from L to kL

 To maintain a constant horizontal electric field, the drain voltage must also be scaled from VD
to kVD
 The maximum gate voltage will also be scaled from VG to kVG so that the gate and drain
voltages remain compatible
 To maintain a constant vertical electric field tox to ktox .
 Since the channel length is being reduced, the depletion widths also need to be reduced. If
the substrate doping concentration is increased by the factor (1/k),
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 MOSFET SCALING
The drain current per channel width, in saturation

 The drift current per channel width remains essentially a constant,

 If channel width is reduced by k, then the drain current is also reduced by k.
 The area of the device, A=WL, is then reduced by k 2 and the power, P=IV, is also
reduced by k2 . The power density in the chip remains unchanged
Threshold Voltage does not scale directly with the scaling factor k.

Consequences of increased electric fields

Device dimensions shrink but not the voltage with the
same scaling factor

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Summary of constant-field device scaling

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 THRESHOLD VOLTAGE MODIFICATIONS
Short-Channel Effects
 A reduction in channel
 length increases the transconductance and frequency response of the MOSFET,
 width increases the packing density in an integrated circuit.
 length and width can affect the threshold voltage.
long n-channel MOSFET at inversion
long n-channel MOSFET at flat band
channel region at inversion
zero source and drain voltage

short n-channel MOSFET at flat band

Charge sharing in the short-channel threshold voltage model

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 THRESHOLD VOLTAGE MODIFICATIONS
Short-Channel Effects

Assuming

Using the geometrical approximation, the average bulk

charge per unit area Q’B in the trapezoid is

Since QSD(max) = eNa xdT

Where ∆VT = VT (short channel) - VT(long channel)

As the channel length decreases, the threshold voltage shifts in the negative direction so that an n-
channel MOSFET shifts toward depletion mode

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 Example Threshold in Short channel
Calculate the threshold voltage shift due to short-channel effects.
Consider an n-channel MOSFET with Na = 3 X 1016 cm-3 , L = 1.0 µm, rj = 0.3 µm,
and tox = 20 nm =200 Å

=0.18 X10-4 cm = 0.18µm

∆VT = -0.0726 V

For design value of VT = 0.35 V shift due to short-channel effects is significant and must be
accounted

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 Threshold Adjustment by Ion Implantation
 Factors affecting Threshold voltage
 fixed oxide charge
 metal–semiconductor work function difference,
 oxide thickness,
 and semiconductor doping

 An implant of acceptor ions into a p-type substrate will shift the threshold voltage to
more positive values, while an implant of donor ions will shift the threshold voltage
to more negative values
 Ion implantation can be carried out to change a depletion-mode device to
enhancement-mode or an enhancement-mode device to depletion-mode

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 Threshold Adjustment by Ion Implantation
DI acceptor atoms per cm2 are implanted into a p-type
Substrate
Ion-implanted profile
approximated by a delta function
If donor atoms were implanted into the p-type
substrate, the space charge density would be
reduced; thus, the threshold voltage would shift in the
negative voltage direction

Ion implanted profile approximated by a step function

in which the depth xi is less than the space charge
width xdT

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 Threshold Adjustment by Ion Implantation
If the induced space charge width at the threshold
inversion point is less than xI, then the threshold
voltage is determined on the basis of a
semiconductor with a uniform doping
concentration of Ns atoms per cm3 .

if the induced space charge width is greater than xI (ion implant depth) at the threshold
inversion point, then a new expression for xdT must be derived.

The threshold voltage after a step implant for the case when xdT >xI is

where VT0 is the preimplant threshold voltage

And DI = (Ns - Na)xI which is the number per cm2 of implanted ions

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 Example:Threshold Adjustment by Ion
Implantation
Design the ion implant dose required to adjust the threshold voltage to a specified
value.
Consider an n-channel silicon MOSFET with a doping of Na = 5X1015 cm-3 , an oxide
thickness of tox =18 nm =180 Å, and an initial flat-band voltage of VFBO =-1.25 V.
Determine the ion implantation dose such that V T of 0.4 V is obtained

=0.4130 X10-4 cm= 0.413µm

=-0.419 V

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Example:contnd

The threshold voltage after implant

DI = 9.815 X 1011 cm2

Assume that uniform step implant extends to a depth of xI = 0.15µm

Then equivalent acceptor concentration at the surface is

Ns = 7.04X 1016 cm-3

It is assumed in the above calculation that the induced space charge width
in the channel region is greater than the ion implant dept xI

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