CoE 168: Base Microblaze System

This document gives an overview of how to use Xilinx Vivado and Xilinx SDK to build a simple Microblaze-
based system on the Arty A7 FPGA development kit.
This document assumes that you have already activated the EEEI VPN and are able to connect to the
Microlab workstations remotely through NoMachine (NX). All our activities will be conducted remotely using
the software tools and FPGA hardware connected to the Microlab workstations. If you wish to install and use
the software tools on your own local PC’s, you may refer to the last section of this document.

Invoking Vivado and Creating a Project

The first step will be to run Vivado and create a project. A project will contain the hardware system that we
will configure our FPGA with.

1. Connect remotely to the Microlab workstation using the EEEI VPN and NX. Login to the workstation.

2. Open a command line terminal. Source the Vivado configuration script to set the executable paths to
properly locate the Xilinx software tools as shown in the image below. You can check if the script was run
successfully by using the which command to show the directory where the vivado executable is located.

3. Invoke Xilinx Vivado by typing vivado in the command line and pressing enter. This should open the
main window as shown below. For this tutorial, we will be relying heavily on the Tcl console to input
commands instead of using the GUI. Console commands have the advantage of being able to be scripted,
as we will see in the second to the last section of this guide. The Tcl console is located at the bottom of
the main window. In the image below, we have already run a single command, which will be discussed in
the next step.

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4. Hardware designs in Vivado are organized into projects. For this demo, we will create a project named
microblaze_base and store it in the directory $HOME/microblaze_base, where $HOME is your home direc-
tory. In the example, the home directory is /nfs/home/snap, so the project directory is
/nfs/home/snap/microblaze_base. We will also create a design named design_1 which will contain the
default hardware design for the project. To create the project, run the following commands in the Tcl
console. Make sure to replace the home directory with your own.

set projectName microblaze_base

set projectDir /nfs/home/snap/$projectName
set designName design_1
create_project $projectName $projectDir -part xc7a35ticsg324-1L

5. After running the last command in the previous step, a project window will pop up similar to the one
shown below. The Tcl console will still be located at the bottom of the window by default.

6. Configure the project to use the Arty A7 FPGA development kit as our hardware target and create a new
block diagram using the following commands in the Tcl console.

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 set_property board_part digilentinc.com:arty-a7-35:part0:1.1 [current_project]
create_bd_design "$designName"

7. Creating a block diagram will open the an empty Block Design subwindow similar to the one shown below.

Building a Microblaze-based system using Vivado block diagrams

Once you have created a new block design, we will run several Tcl commands to instantiate and connect internal
blocks of our Microblaze-based system.
1. The first component we will instantiate will be the clock generator. This clock generator will be connected
to the external oscillator in the development board and will use the FPGA’s internal PLLs to generate
an internal clock that will be used by the Microblaze system. The clocking wizard block can be used to
generate different internal clock frequencies, but for now we will use the default 100MHz clock. Run the
following command to instantiate the clocking wizard/clock generator block. After running the command,
a graphical representation of the block will be shown in the block design window.

create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 clk_wiz_0

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2. Connect the clocking wizard to the external oscillator and board reset signals. Each command shown
below is now prepended with a # to show where the command starts in case of long commands which
may need to be broken into multiple lines in this document. Take note that the # is purely for convenience
and should not be entered into the Tcl console (just enter everything after it).

#apply_board_connection -board_interface "sys_clock" -ip_intf "clk_wiz_0/clock_CLK_IN1"

-diagram "$designName"
#set_property -dict [list CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.RESET_PORT {resetn}]
[get_bd_cells clk_wiz_0]
#apply_bd_automation -rule xilinx.com:bd_rule:board -config {Board_Interface
"reset ( System Reset ) " } [get_bd_pins clk_wiz_0/resetn]

3. Add the Microblaze microprocessor and connect it to the clocking wizard. Most of the connections when
using Vivado will be done automatically, we will only need to specify the source and destination interfaces.

#create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.6 microblaze_0

#apply_bd_automation -rule xilinx.com:bd_rule:microblaze -config {local_mem "64KB"
ecc "None" cache "None" debug_module "Debug Only" axi_periph "Enabled" axi_intc "0"
clk "/clk_wiz_0/clk_out1 (100 MHz)" } [get_bd_cells microblaze_0]

4. You should now have a block design similar to the one shown below. You can let the tool rearrange the
blocks by running the following command:

regenerate_bd_layout

5. We will now connect peripherals to the Microblaze processor. The first peripheral will be the USB
UART module, which we will use to communicate with the system. UART is an asynchronous serial
communications protocol and is used in many embedded systems. We will use the default baud rate of
9600 for this UART module.

#create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0

#apply_board_connection -board_interface "usb_uart" -ip_intf "axi_uartlite_0/UART"
-diagram "$designName"

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6. We will also connect the LEDs in the board to serve as outputs. To do this, we will need to instantiate a
GPIO module. The GPIO module will map our outputs to registers that can be read/written as memory
locations.

#create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0

#apply_board_connection -board_interface "led_4bits" -ip_intf "axi_gpio_0/GPIO"
-diagram "$designName"

7. We will create a timer module which we can use to create precise time delays which we can use in our
programs. Unlike th eUART and GPIO, the timer is fully internal (to the FPGA) will not be mapped to
any external board components.

create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0

8. Now that all peripherals are instantiated, we will now connect them to the processor. Microblaze uses
the AXI bus protocol for peripheral connections. The AXI protocol uses several signals (data, address,
control, etc) to facilitate communication. However, Vivado will automatically connect those individual
signals. Run the following commands to connect the peripherals.

#apply_bd_automation -rule xilinx.com:bd_rule:board -config {Board_Interface

"reset ( System Reset ) " } [get_bd_pins rst_clk_wiz_0_100M/ext_reset_in]
#apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config
{Master "/microblaze_0 (Periph)" Clk "Auto" } [get_bd_intf_pins axi_uartlite_0/S_AXI]
#apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config
{Master "/microblaze_0 (Periph)" Clk "Auto" } [get_bd_intf_pins axi_gpio_0/S_AXI]
#apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config
{Master "/microblaze_0 (Periph)" Clk "Auto" } [get_bd_intf_pins axi_timer_0/S_AXI]

9. All peripherals should now be connected, similar to the image shown below. You can use the regener-
ate_bd_layout command to rearrange the blocks.

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10. Some of our peripherals have an option to be interrupt-driven. Multiple interrupts will require an interrupt
controller. Instantiate the interrupt controller and connect it to the processor system using the following
commands:

#create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0

#apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config
{Master "/microblaze_0 (Periph)" Clk "Auto" } [get_bd_intf_pins axi_intc_0/s_axi]

11. Individual peripheral interrupt lines will need to be connected manually. Use the following commands to
connect the UART and timer blocks to the interrupt controller.

#create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0

#connect_bd_net [get_bd_pins axi_timer_0/interrupt] [get_bd_pins xlconcat_0/In0]
#connect_bd_net [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins xlconcat_0/In1]
#connect_bd_net [get_bd_pins xlconcat_0/dout] [get_bd_pins axi_intc_0/intr]
#connect_bd_intf_net [get_bd_intf_pins axi_intc_0/interrupt] [get_bd_intf_pins
microblaze_0/INTERRUPT]

12. After connecting the interrupt lines manually, the interrupt subsystem should look similar to the one
shown below. Interrupt lines from the timer and UART are connected to the interrupt controller through
the Concat module. The Interrupt controller is then connected to the Microblaze interrupt port.

13. Validate your block design and save it if there are no errors.

#validate_bd_design
#save_bd_design

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Bitstream Generation and Hardware export to SDK
After completing the block design, we will now use Vivado to automatically map the design to logic gates,
flip-flops, and RAM in the FPGA. A file that contains information on how program hardware connections in
the FPGA, called a bitstream, will be generated. Along with the bitstream, all other pertinent information
regarding the hardware configuration of the design will be exported into files which will be used by the SDK
when we start to program the Microblaze processor.

1. In the Sources sub-window, expand the Design Sources item to reveal the block design we just made in
the previous section. If you ever close the Block Design sub-window, you can just double click on this to
open it again.

2. Right click on the block design (design_1 in our example) and select Create HDL Wrapper on the menu.
This will create a Verilog file of the top-level module of the block design. A new window will appear asking
if you want to automatically let Vivado handle any updates on the file. Select that option and click OK.

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3. Any actions done using the GUI will have an equivalent Tcl command or commands executeed in the Tcl
console. You can view the equivalent commands of the HDL Wrapper creation in the Tcl console log.
They will be shown in blue.

4. Locate the Flow Navigator sub-window. It is located in the left side of the Vivado project window by
default. Double click on the option Program and Debug -> Generate Bitstream to start generating the
bitstream. A new window will appear prompting to start Synthesis and Implementation. Select Yes.

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5. All the processes required by bitstream generation will take a considerable amount of time. You may view
the progress in the Design Runs tab (located in the same area as the Tcl console).

6. A window will pop up once bitstream generation is finished. Select View Reports and click OK.

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7. Before exporting our design to SDK, let us first check device utilization. Close the Block Design window
to review the Project Summary as shown. This view will contain pertinent information regarding the
project such as our hardware target and paths where project data is stored.

8. Scroll down to the Utilization sub-window to see the current device utilization. This represents how much
of each resource in the FPGA is used. The FPGA has a finite amount of resources which limits the
complexity and size of the system that we can build with it.

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 9. Finally, let us export our hardware design to SDK. On the File menu, select Export -> Export Hardware.
A new window will appear. Select Include bitstream to include the bitstream we generated to the exported
files. You may also manually set the location of the exported files, but for this demo we will just export
it locally to the project (inside the project directory). Click OK to proceed.

Using Xilinx SDK to program Microblaze

Once the hardware design has been implemented and exported using Vivado, we will need to use the SDK to
load a program to be executed in the Microblaze processor. The SDK will use C as the programming language
by default.

1. To launch Xilinx SDK, go to the File menu of Vivado and select Launch SDK. A window will pop up
asking where the exported project files are located and where files generated by the SDK will be stored.
Since we exported project files local to the project, we select this option accordingly.

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2. Xilinx SDK will automatically load our exported design files. The SDK main window will look similar to
the one shown below. Exported design files describing our hardware platform are shown in the Project
Explorer sub-window to the left.

3. To create a new program to run in the platform, select File -> New -> Application Project

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4. A New Project window will appear. We will configure the project to use our exported hardware platform
as shown below. You may set the project name to your liking, but for this demo the project name is set
to microblaze_base. We use default location, set OS Platform to standalone, and the Target Hardware to
the loaded platform. Click Next to continue.

5. Select Hello World for the application template. This template will generate all necessary configuration
files and code for building an application that will display output to STDOUT, which is mapped to the
UART interface in our platform. Click Finish to create the application project.

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6. The created application project can now be seen in the Project Explorer window. Navigate to its src
directory and double-click on the helloworld.c option to display the contents of helloworld.c, which contains
the main function of our program.

7. The main function will be displayed in the middle of the SDK window, as shown. As you can see, the
program only uses a print function and several initialization and cleanup functions specific to our platform.
All necessary libraries for implementing the said functions are automatically included in the application
project and exported platform files.

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8. We will use the SDK Debugger to download and run our code in the Microblaze processor. From the main
menu, select Run -> Debug Configurations to open the Debug Configurations window.

9. Create a new debug configuration by selecting the System Debugger as shown, right-clicking on it and
selecting New.

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10. A window will pop up for setting the debug configuration. In this demo, we set the debug configuration
name to Debug_base as shown below. We also set the following parameters and click Apply to apply
changes:

• Debug Type: Standalone Application Debug

• Connection: Local
• Hardware platform: (exported hardware, automatic)
• Bitstream: (exported bitstream, automatic)
• Reset entire system: selected
• Program FPGA: selected

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11. Go to the Application tab and set the following parameters, then click Apply to apply changes.

• Download application: selected

• Project name: (our created application project)

12. Begin the debug procedure (download program to platform and run) by clicking the Debug button. A
window will appear prompting to change perspective. The SDK has two perspectives. The first is the
code perspective that displays source code and the project explorer (which is what we have already seen).
The second is the debug perspective which shows relevant windows for debugging the running program.
Select Yes to continue. You may change perspective anytime by selecting it on the upper right part of the
SDK window.

13. The SDK will download the bitstream and application to the platform. You can see the progress and
any errors in the SDK Log sub-window (bottom-right by default). By default, the debugger inserts a
breakpoint at the start of the main function, so the program will pause at this point.

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14. Before continuing to run the main function, we need to setup the SDK to display the UART communication
with the board. Select the SDK Terminal tab (at the bottom of the Debug perspective by default). Click
on the ’+’ icon to add a port to the terminal.

15. A window for serial port configuration will appear. Select a baud rate of 9600 (which is the default when
we instantiated the USB UART peripheral in Vivado). Set the port to /dev/ttyUSB2 (sometimes it will
be /dev/ttyUSB1). Click OK to continue. The SDK Terminal should now indicate that it is connected to
the specified serial port with our selected baud rate.

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16. To resume our application’s execution in the platform, click on the ’play’ button as shown below.

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17. We go back to the SDK Terminal to confirm that the print function successfully transmits the ”Hello
World” text through UART.

18. We can try to add a single line of code to the main function. Return to the code perspective and go to
the helloworld.c file. Add an arbitrary print statement after the default ”Hello World” print function.
Compile the code by clicking on the ’hammer’ icon at the top of the perspective.

19. Open the Debug Configurations window again. The configuration we created should now be listed under
the System Debugger listing. Click Debug to begin the debug process. A window will appear prompting
that our previous debug session is still active. Select OK to relaunch our updated application.

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 20. Resume the program (after entering the default breakpoint) and check the SDK Terminal if the changes
you made have been reflected.

Vivado scripting
All the commands we entered manually to the Tcl console in Vivado can be conveniently scripted. Just open
a text editor (vi or gedit) and place all the commands (from project creation to connection automation) in a
text file similar to the one shown below. You may want to change the project name and project directory since
project creation will fail if the directory already exists.

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 Comments can be inserted into the script by prepending the line with a ’#’ symbol. Save the text file (in this
demo, its filename is build_base_2016.tcl and invoke Vivado. In the Tcl console, run the following command:

source build_base_2016.tcl

You may need to modify the path in the command or change into the directory where you saved the script.
You can run Linux terminal commands like cd in the Tcl console to do this.
Running the source command on the script should automatically go through all the steps we did manually
in the first part of this guide. Just monitor the Tcl console for any potential errors that might have occured
when executing the script.

Using local Vivado installations with Microlab license

If you want to replicate the remote setup, you can install Xilinx Vivado on your own systems. The version we
use in the lab is 2016.1. However, you will not be able to download and debug to the FPGA board since the
boards are only available at the lab.
When installing Vivado, you will be prompted to specify a license file. You can generate your own free
license file (Webpack) in the Xilinx website. Another option would be to use the licenses already available in
the lab’s server. Just connect to the EEEI VPN set the license manager to point to the license server by setting
the environment variable shown below when running Vivado:

[email protected]

For portability, we suggest that you use Tcl scripts (for rebuilding the system) instead of copying the whole
project directory. Vivado generates a lot of files and executables and may result in large accumulated filesizes
if you try to copy whole project directories between your home workstation and the remote.

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