CHAPTER 5

MOSFET
 MOSFET (metal-oxide-semiconductor field-effect transistor)
is the most important device for advanced logic ICs such as
the microprocessor and volatile memories such as DRAM
and SRAM

 MOSFET offers high density, low power consumption,

simpler manufacturing processes and high yield

 In this chapter we consider :

 Basic characteristics of MOSFET
 MOSFET scaling and short-channel effects
 Complementary MOS (CMOS) logic circuit
 Silicon-on-insulator devices
 DRAM and SRAM
 Power MOSFET
 HISTORICAL DEVELOPMENT
OF MOSFET
YEAR DEVICE/CIRCUIT INVENTOR(S)/AUTHOR(S) ORGANIZATION
Depletion-mode J. E. Lilienfeld ―
1930 MOSFET

1935 Depletion-mode O. Heil ―

MOSFET
*1960 Enhancement- D. Kahng, M. M. Atalla Bell Labs
mode MOSFET
1962 Thin-film transistor P. K. Weimer RCA
*1963 CMOS F. M. Wanlass, C. T. Sah Fairchild
*1967 DRAM R. H. Dennard IBM
1968 SB-IGFET M. P. Lepselter, S. M. Sze Bell Labs
*1971 Microprocessor M. E. Hoff et al Intel
1974 Scaling rules R. H. Dennard et al IBM
2004 Nanowire MOSFET F. L. Yang et al TSMC
2013 7nm FinFET CMOS S. Gupta et al Stanford U.
 INTRODUCTION
 MOSFET is composed of an MOS capacitor and two p-n
junctions placed immediately adjacent to the MOS capacitor

 Figure below shows a perspective view of an MOSFET

 INTRODUCTION (Cont.)
 It is a 4-terminal device: Gate, source, drain, and substrate
 Gate material: metal, heavily doped poly-silicon, or silicide
(e.g., WSi2)
 Source and drain: n+ regions formed in p-type substrate
(for n-channel MOSFET)
 4th terminal is an ohmic contact to the substrate
 Device parameters:
𝑳𝑳, channel length (distance between two
metallurgical 𝒏𝒏+ 𝒑𝒑 junctions)
𝒁𝒁, channel width
𝒅𝒅, oxide thickness
𝒓𝒓𝒋𝒋 , junction depth
𝑵𝑵𝑨𝑨 , substrate doping (for n-channel MOSFET)
 BASIC CHARACTERISTICS
 Low drain voltage: When
𝑽𝑽𝑮𝑮 > 𝑽𝑽𝑻𝑻 , a channel is formed.
For small drain voltage (𝑽𝑽𝑫𝑫
small) channel acts as a
resistor, the drain current (𝑰𝑰𝑫𝑫 )
varies linearly with 𝑽𝑽𝑫𝑫 . This is
the linear region.

 Onset of saturation: As 𝑽𝑽𝑫𝑫 ↑,

𝒙𝒙𝒊𝒊 →0 at the drain. This is the
pinch-off point 𝑷𝑷. 𝑰𝑰𝑫𝑫
approaches a maximum value.

 Beyond saturation: 𝑰𝑰𝑫𝑫

remains the same. This is the
saturation region.
 BASIC CHARACTERISTICS (Cont.)
y

 Figure 23 shows (a) MOSFET

operated in the linear region. (b) x
Enlarged view of the channel. (c)
Drain voltage drop along the
channel.

Assumptions :
 Gate structure: Ideal MOS capacitor
 Drift current only in the channel
 Constant mobility
 Uniform substrate doping
 Zero leakage current
 εx > εy: The transverse field (εx) is
much larger than the longitudinal
field (εy). This is called the gradual
channel approximation
 BASIC CHARACTERISTICS (Cont.)
 From Fig. 23(a), the total charge induced in the semiconductor per unit
area is 𝑸𝑸𝒔𝒔 (𝒚𝒚).

Since 𝑽𝑽𝑮𝑮 = 𝑽𝑽𝒐𝒐 + 𝝍𝝍𝒔𝒔 (𝒚𝒚) (same as Eq. 13, Ch 4)

𝑸𝑸𝒔𝒔 (𝒚𝒚) 𝝐𝝐𝒐𝒐𝒐𝒐
𝑽𝑽𝒐𝒐 = (same as Eq. 14, Ch 4) 𝑪𝑪𝒐𝒐 =
𝑪𝑪𝒐𝒐 𝒅𝒅

At point 𝒚𝒚
𝑸𝑸𝒔𝒔 𝒚𝒚 = −𝑽𝑽𝒐𝒐 𝑪𝑪𝒐𝒐 = −[𝑽𝑽𝑮𝑮 − 𝝍𝝍𝒔𝒔 (𝒚𝒚)]𝑪𝑪𝒐𝒐

 The inversion charge per unit area 𝑸𝑸𝒏𝒏 (𝒚𝒚) is

𝑸𝑸𝒏𝒏 𝒚𝒚 = 𝑸𝑸𝒔𝒔 𝒚𝒚 − 𝑸𝑸𝒔𝒔𝒔𝒔 𝒚𝒚 = −[𝑽𝑽𝑮𝑮 − 𝝍𝝍𝒔𝒔 (𝒚𝒚)]𝑪𝑪𝒐𝒐 − 𝑸𝑸𝒔𝒔𝒔𝒔 (𝒚𝒚) (27)

 The potential 𝝍𝝍𝒔𝒔 (𝒚𝒚) at 𝒚𝒚:

𝝍𝝍𝒔𝒔 (𝒚𝒚) = surface potential at strong inversion due to 𝑽𝑽𝑮𝑮 plus the
applied drain voltage at 𝒚𝒚 (note : potentials are scalars
not vectors)
= 2𝝍𝝍𝑩𝑩 + 𝑽𝑽(𝒚𝒚)
 BASIC CHARACTERISTICS (Cont.)
 The space-charge 𝑸𝑸𝒔𝒔𝒔𝒔 (𝒚𝒚) in the surface depletion region is

𝑸𝑸𝒔𝒔𝒔𝒔 (𝒚𝒚) = −𝒒𝒒𝑵𝑵𝑨𝑨 𝑾𝑾𝒎𝒎 ≅ − 𝟐𝟐𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 [𝟐𝟐𝝍𝝍𝑩𝑩 + 𝑽𝑽(𝒚𝒚)] (28)

 The inversion charge is obtained by substituting Eq. 28 into Eq. 27

𝑸𝑸𝒏𝒏 𝒚𝒚 = − 𝑽𝑽𝑮𝑮 − 𝟐𝟐𝝍𝝍𝑩𝑩 − 𝑽𝑽 𝒚𝒚 𝑪𝑪𝒐𝒐 + 𝟐𝟐𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 [𝟐𝟐𝝍𝝍𝑩𝑩 + 𝑽𝑽(𝒚𝒚)] (29)

 Conductivity of the channel

𝝈𝝈 𝒙𝒙 = 𝒒𝒒𝒒𝒒(𝒙𝒙)𝝁𝝁𝒏𝒏 (𝒙𝒙) (30)
For 𝝁𝝁𝒏𝒏 = constant, the channel conductance is
𝒙𝒙𝒊𝒊
𝟏𝟏 𝟏𝟏 𝝈𝝈𝑨𝑨 𝝈𝝈 𝒙𝒙 𝒁𝒁𝒁𝒁𝒁𝒁 𝒁𝒁 𝒙𝒙𝒊𝒊
𝒈𝒈 = = = =� = � 𝝈𝝈 𝒙𝒙 𝒅𝒅𝒅𝒅
𝑹𝑹 𝝆𝝆 𝑳𝑳 𝑳𝑳 𝟎𝟎 𝑳𝑳 𝑳𝑳 𝟎𝟎
𝑨𝑨
𝒁𝒁𝝁𝝁𝒏𝒏 𝒙𝒙𝒊𝒊 𝒁𝒁𝝁𝝁𝒏𝒏
= � 𝒒𝒒𝒒𝒒 𝒙𝒙 𝒅𝒅𝒅𝒅 = 𝑸𝑸𝒏𝒏
𝑳𝑳 𝟎𝟎 𝑳𝑳

𝑸𝑸𝒏𝒏
 BASIC CHARACTERISTICS (Cont.)
 Channel resistance of an elemental section dy is

𝝆𝝆𝒅𝒅𝒅𝒅 𝝆𝝆𝑳𝑳 𝒅𝒅𝒅𝒅 𝒅𝒅𝒅𝒅 𝒅𝒅𝒅𝒅

𝒅𝒅𝒅𝒅 = = = =
𝑨𝑨 𝑨𝑨 𝑳𝑳 𝒈𝒈𝒈𝒈 𝒁𝒁𝝁𝝁𝒏𝒏 𝑸𝑸𝒏𝒏
𝟏𝟏
( )
𝒈𝒈
 The voltage drop across 𝒅𝒅𝒅𝒅 is

𝑰𝑰𝑫𝑫 𝒅𝒅𝒅𝒅
𝒅𝒅𝒅𝒅 = 𝑰𝑰𝑫𝑫 𝒅𝒅𝒅𝒅 = or 𝑰𝑰𝑫𝑫 𝒅𝒅𝒅𝒅 = 𝒁𝒁𝝁𝝁𝒏𝒏 𝑸𝑸𝒏𝒏 𝒅𝒅𝒅𝒅
𝒁𝒁𝝁𝝁𝒏𝒏 𝑸𝑸𝒏𝒏
𝑳𝑳 𝑽𝑽𝑫𝑫 𝑳𝑳
∫𝟎𝟎 𝑰𝑰𝑫𝑫 𝒅𝒅𝒅𝒅
= 𝑰𝑰𝑫𝑫 𝑳𝑳
� 𝑰𝑰𝑫𝑫 𝒅𝒅𝒅𝒅 = � 𝒁𝒁𝝁𝝁𝒏𝒏 𝑸𝑸𝒏𝒏 𝒅𝒅𝒅𝒅
𝟎𝟎 𝟎𝟎
( and 𝑰𝑰𝑫𝑫 = constant
)
𝒁𝒁 𝑽𝑽𝑫𝑫
𝑰𝑰𝑫𝑫 = � 𝝁𝝁𝒏𝒏 𝑸𝑸𝒏𝒏 𝒅𝒅𝒅𝒅
𝑳𝑳 𝟎𝟎
 BASIC CHARACTERISTICS (Cont.)
 The drain current is

𝒁𝒁 𝑽𝑽𝑫𝑫
𝑰𝑰𝑫𝑫 = � 𝝁𝝁𝒏𝒏 𝑽𝑽𝑮𝑮 − 𝟐𝟐𝝍𝝍𝑩𝑩 − 𝑽𝑽 𝒚𝒚 𝑪𝑪𝒐𝒐 − 𝟐𝟐𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 [𝟐𝟐𝝍𝝍𝑩𝑩 + 𝑽𝑽(𝒚𝒚)] 𝒅𝒅𝒅𝒅
𝑳𝑳 𝟎𝟎
Integrating from source 𝒚𝒚 = 𝟎𝟎, 𝑽𝑽 = 𝟎𝟎 to the drain 𝒚𝒚 = 𝑳𝑳, 𝑽𝑽 = 𝑽𝑽𝑫𝑫 ,

 The idealized I-V characteristics of long-channel MOSFET

∴ 𝑰𝑰𝑫𝑫 =
𝒁𝒁 𝑽𝑽𝑫𝑫 𝟐𝟐 𝟐𝟐𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 𝟑𝟑� 𝟑𝟑�
𝝁𝝁 𝑪𝑪 𝑽𝑽𝑫𝑫 − 𝟐𝟐𝝍𝝍𝑩𝑩 − 𝑽𝑽𝑫𝑫 − [ 𝑽𝑽𝑫𝑫 + 𝟐𝟐𝝍𝝍𝑩𝑩 𝟐𝟐 − (𝟐𝟐𝝍𝝍𝑩𝑩 ) 𝟐𝟐 ]
𝑳𝑳 𝒏𝒏 𝒐𝒐 𝟐𝟐 𝟑𝟑 𝑪𝑪𝒐𝒐
(35)

This is the I-V characteristics of an idealized long-channel MOSFET

 BASIC CHARACTERISTICS (Cont.)
 Figure 24 shows the idealized 𝑰𝑰𝑫𝑫 − 𝑽𝑽𝑫𝑫 characteristics of
MOSFET. For 𝑽𝑽𝑫𝑫 ≥ 𝑽𝑽𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫 the drain current remains constant.

Linear
𝑰𝑰𝑫𝑫 𝒗𝒗𝒗𝒗 𝑽𝑽𝑫𝑫

𝑰𝑰𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫 for
𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻 = 𝟖𝟖 𝐕𝐕
𝑽𝑽𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫
 LINEAR REGION
 In the linear region, 𝑽𝑽𝑫𝑫 is small. Eq. 35 reduces to

𝒁𝒁 𝑽𝑽𝑫𝑫
𝑰𝑰𝑫𝑫 ≅ 𝝁𝝁𝒏𝒏 𝑪𝑪𝒐𝒐 (𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻 − )𝑽𝑽𝑫𝑫 for 𝑽𝑽𝑫𝑫 < (𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻 )
𝑳𝑳 𝟐𝟐

𝟐𝟐𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 𝟐𝟐𝝍𝝍𝑩𝑩

where 𝑽𝑽𝑻𝑻 = threshold voltage ≡ + 𝟐𝟐𝝍𝝍𝑩𝑩 (37)
𝑪𝑪𝒐𝒐
(same as Eq. 17, Ch. 4)

 The drain conductance 𝒈𝒈𝑫𝑫 and the transconductance 𝒈𝒈𝒎𝒎 are :

𝝏𝝏𝑰𝑰𝑫𝑫 𝒁𝒁 Slope = 𝒈𝒈𝒎𝒎
𝒈𝒈𝑫𝑫 ≡ ≅ 𝝁𝝁𝒏𝒏 𝑪𝑪𝒐𝒐 (𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻 − 𝑽𝑽𝑫𝑫 ) 𝑰𝑰𝑫𝑫
𝝏𝝏𝑽𝑽𝑫𝑫 VG = constant 𝑳𝑳
𝝏𝝏𝑰𝑰𝑫𝑫 𝒁𝒁
𝒈𝒈𝒎𝒎 ≡ ≅ 𝝁𝝁𝒏𝒏 𝑪𝑪𝒐𝒐 𝑽𝑽𝑫𝑫
𝝏𝝏𝑽𝑽𝑮𝑮 D
V = constant 𝑳𝑳

0 (𝑽𝑽𝑻𝑻 +
𝑽𝑽𝑫𝑫
) 𝑽𝑽𝑮𝑮
𝟐𝟐
 SATURATION REGION
 As 𝑽𝑽𝑫𝑫 ↑ to a point 𝑸𝑸𝒏𝒏 (𝒚𝒚) in the inversion layer at 𝒚𝒚 = 𝑳𝑳 becomes zero
(saturation region), the corresponding 𝑽𝑽𝑫𝑫 and 𝑰𝑰𝑫𝑫 are designated as 𝑽𝑽𝑫𝑫𝒔𝒔𝒔𝒔𝒔𝒔
and 𝑰𝑰𝑫𝑫𝒔𝒔𝒔𝒔𝒔𝒔

From Eq. 29 with 𝑸𝑸𝒏𝒏 𝑳𝑳 = 𝟎𝟎

𝟎𝟎 = − 𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑫𝑫𝑫𝑫𝒂𝒂𝒕𝒕 − 𝟐𝟐𝝍𝝍𝑩𝑩 𝑪𝑪𝒐𝒐 + 𝟐𝟐𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 (𝟐𝟐𝝍𝝍𝑩𝑩 + 𝑽𝑽𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫 ) (40)

∴ 𝑽𝑽𝑫𝑫𝒔𝒔𝒔𝒔𝒕𝒕 ≅ 𝑽𝑽𝑮𝑮 − 𝟐𝟐𝝍𝝍𝑩𝑩 + 𝑲𝑲𝟐𝟐 (𝟏𝟏 − 𝟏𝟏 + 𝟐𝟐 𝑽𝑽𝑮𝑮 ⁄𝑲𝑲𝟐𝟐 )

where 𝑲𝑲 ≡ 𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 �𝑪𝑪𝒐𝒐, and the saturation current is obtained by

substituting Eq. 40 into Eq. 35
𝒁𝒁𝝁𝝁𝒏𝒏 𝑪𝑪𝒐𝒐
𝑰𝑰𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫 = (𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻 )𝟐𝟐
𝟐𝟐𝟐𝟐
For low substrate doping and thin oxide, 𝑽𝑽𝑻𝑻 is the same as Eq. 37.
At higher doping 𝑽𝑽𝑻𝑻 becomes 𝑽𝑽𝑮𝑮 dependent
 SATURATION REGION (Cont.)
 The transconductance in the saturation region is

𝝏𝝏𝑰𝑰𝑫𝑫 𝒁𝒁𝝁𝝁𝒏𝒏 𝝐𝝐𝒐𝒐𝒐𝒐

𝒈𝒈𝒎𝒎 ≡ = 𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻
𝝏𝝏𝑽𝑽𝑮𝑮 VD = constant 𝒅𝒅𝒅𝒅

 EXAMPLE 5
For an n-channel n+-polysilicon-SiO2-Si MOSFET with gate oxide = 8 nm,
𝑵𝑵𝑨𝑨 = 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm–3 and 𝑽𝑽𝑮𝑮 = 3 V, calculate 𝑽𝑽𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫 .

SOLUTION
𝝐𝝐𝒐𝒐𝒐𝒐 𝟑𝟑. 𝟗𝟗 × 𝟖𝟖. 𝟖𝟖𝟖𝟖 × 𝟏𝟏𝟏𝟏−𝟏𝟏𝟏𝟏
𝑪𝑪𝒐𝒐 = = 𝟖𝟖 × 𝟏𝟏𝟏𝟏−𝟕𝟕
= 𝟒𝟒. 𝟑𝟑𝟑𝟑 × 𝟏𝟏𝟏𝟏−𝟕𝟕 𝐅𝐅⁄𝐜𝐜𝐜𝐜𝟐𝟐
𝒅𝒅
𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 𝟏𝟏𝟏𝟏. 𝟗𝟗 × 𝟖𝟖. 𝟖𝟖𝟖𝟖 × 𝟏𝟏𝟏𝟏−𝟏𝟏𝟏𝟏 × 𝟏𝟏. 𝟔𝟔 × 𝟏𝟏𝟏𝟏−𝟏𝟏𝟏𝟏 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏
𝑲𝑲 = = = 𝟎𝟎. 𝟑𝟑
𝑪𝑪𝒐𝒐 𝟒𝟒. 𝟑𝟑𝟑𝟑 × 𝟏𝟏𝟏𝟏−𝟕𝟕
 EXAMPLE 5 (Cont.)

𝟐𝟐𝝍𝝍𝑩𝑩 = 𝟎𝟎. 𝟖𝟖𝟖𝟖 𝐕𝐕 from Ex. 2. Therefore, from Eq. 40,

𝟐𝟐
𝟐𝟐𝑽𝑽𝑮𝑮
𝑽𝑽𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫 ≅ 𝑽𝑽𝑮𝑮 − 𝟐𝟐𝝍𝝍𝑩𝑩 + 𝑲𝑲 𝟏𝟏 − 𝟏𝟏 + 𝟐𝟐
𝑲𝑲

𝟐𝟐
𝟐𝟐 × 𝟑𝟑
= 𝟑𝟑 − 𝟎𝟎. 𝟖𝟖𝟖𝟖 + 𝟎𝟎. 𝟑𝟑 𝟏𝟏 − 𝟏𝟏 +
(𝟎𝟎. 𝟑𝟑)𝟐𝟐

= 𝟑𝟑 − 𝟎𝟎. 𝟖𝟖𝟖𝟖 − 𝟎𝟎. 𝟔𝟔𝟔𝟔 = 𝟏𝟏. 𝟓𝟓𝟓𝟓 𝐕𝐕

 SUBTHRESHOLD REGION
 For 𝑽𝑽𝑮𝑮 < 𝑽𝑽𝑻𝑻 , surface is weakly inverted
𝑳𝑳
𝒏𝒏+ 𝒑𝒑 𝒏𝒏+

The current is dominated by diffusion current

𝒅𝒅𝒅𝒅 𝒏𝒏 𝟎𝟎 − 𝒏𝒏(𝑳𝑳)
𝑰𝑰𝑫𝑫 = −𝒒𝒒𝒒𝒒𝑫𝑫𝒏𝒏 = 𝒒𝒒𝒒𝒒𝑫𝑫𝒏𝒏 (43)
𝒅𝒅𝒅𝒅 𝑳𝑳

𝒏𝒏 𝟎𝟎 = 𝒏𝒏𝒊𝒊 exp[𝒒𝒒 (𝝍𝝍𝑺𝑺 − 𝝍𝝍𝑩𝑩 )⁄𝒌𝒌𝒌𝒌]

(44)
𝒏𝒏 𝑳𝑳 = 𝒏𝒏𝒊𝒊 exp[𝒒𝒒 (𝝍𝝍𝑺𝑺 − 𝝍𝝍𝑩𝑩 − 𝑽𝑽𝑫𝑫 )⁄𝒌𝒌𝒌𝒌]
same as Eq. 5 in Ch. 4
Surface potential at the source
 SUBTHRESHOLD REGION (Cont.)

 Substituting Eq. 44 into Eq. 43 gives

𝒒𝒒𝒒𝒒𝑫𝑫𝒏𝒏 𝒏𝒏𝒊𝒊 𝒆𝒆−𝒒𝒒𝝍𝝍𝑩𝑩⁄𝒌𝒌𝒌𝒌

𝑰𝑰𝑫𝑫 = (𝟏𝟏 − 𝒆𝒆−𝒒𝒒𝑽𝑽𝑫𝑫⁄𝒌𝒌𝒌𝒌 )𝒆𝒆𝒒𝒒𝝍𝝍𝒔𝒔⁄𝒌𝒌𝒌𝒌 (45)
𝑳𝑳

since 𝝍𝝍𝒔𝒔 ≅ 𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻 , the

𝑰𝑰𝑫𝑫 ~𝒆𝒆𝒒𝒒𝝍𝝍𝒔𝒔 ⁄𝒌𝒌𝒌𝒌 ~exp[𝒒𝒒 (𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻 )⁄𝒌𝒌𝒌𝒌]

𝑰𝑰𝑫𝑫 will decrease exponentially when 𝑽𝑽𝑮𝑮 is less than 𝑽𝑽𝑻𝑻

 SUBTHRESHOLD REGION (Cont.)
 Figure 25 shows the subthreshold characteristics of an MOSFET.

Subthreshold Linear Saturation

region region region

𝑺𝑺~𝟕𝟕𝟕𝟕 mV⁄decade
 SUBTHRESHOLD REGION (Cont.)
 Note the exponential dependence of 𝑰𝑰𝑫𝑫 on (𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑫𝑫 ) for 𝑽𝑽𝑮𝑮 < 𝑽𝑽𝑻𝑻

 Subthreshold swing 𝑺𝑺 shows how sharply the device is turned off by 𝑽𝑽𝑮𝑮 :

𝑺𝑺 ≡ (𝐥𝐥𝐥𝐥𝟏𝟏𝟏𝟏)[𝒅𝒅𝑽𝑽𝑮𝑮 ⁄𝒅𝒅(𝐥𝐥𝐥𝐥𝑰𝑰𝑫𝑫 )]

Since 𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑭𝑭𝑭𝑭 = 𝝍𝝍𝒔𝒔 + 𝟐𝟐𝝐𝝐𝒔𝒔 𝝍𝝍𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 �𝑪𝑪𝒐𝒐

𝒅𝒅𝑽𝑽𝑮𝑮 𝟏𝟏 𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 𝑪𝑪𝒐𝒐 + 𝑪𝑪𝒋𝒋

= 𝟏𝟏 + = (Eq. 34, Ch.3)
𝒅𝒅𝝍𝝍𝒔𝒔 𝑪𝑪𝒐𝒐 𝟐𝟐𝝍𝝍𝒔𝒔 𝑪𝑪𝒐𝒐

 From Eq. 45 𝐥𝐥𝐥𝐥 𝑰𝑰𝑫𝑫 ≅ 𝐥𝐥𝐥𝐥 a weak function of 𝝍𝝍𝒔𝒔 + 𝐥𝐥𝐥𝐥(𝒒𝒒𝝍𝝍𝒔𝒔 ⁄𝒌𝒌𝒌𝒌)

𝒅𝒅𝑽𝑽𝑮𝑮 𝒌𝒌𝒌𝒌 𝑪𝑪𝒐𝒐 + 𝑪𝑪𝒋𝒋 𝑪𝑪𝒐𝒐 + 𝑪𝑪𝒋𝒋

∴ 𝑺𝑺 = 𝐥𝐥𝐥𝐥𝟏𝟏𝟏𝟏 = 𝐥𝐥𝐥𝐥𝟏𝟏𝟏𝟏 = (𝟔𝟔𝟔𝟔 𝐦𝐦𝐦𝐦)
𝒅𝒅(𝒒𝒒𝝍𝝍𝒔𝒔 ⁄𝒌𝒌𝒌𝒌) 𝒒𝒒 𝑪𝑪𝒐𝒐 𝑪𝑪𝒐𝒐

When 𝑪𝑪𝒐𝒐 ≫ 𝑪𝑪𝒋𝒋 , 𝑺𝑺 → 𝟔𝟔𝟔𝟔 𝐦𝐦𝐦𝐦⁄𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝 = ideal p-n junction forward current
 VELOCITY SATURATION CONDITION

 As the channel length is reduced below 100 nm, the longitudinal

field is high enough to cause velocity saturation in the
inversion channel.

 The inversion charge at the source is given by Eq. 29 :

𝑸𝑸𝒏𝒏 (𝒚𝒚 = 𝟎𝟎) = 𝑽𝑽𝑮𝑮 − 𝟎𝟎 − 𝟐𝟐𝝍𝝍𝑩𝑩 𝑪𝑪𝒐𝒐 + 𝟐𝟐𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 (𝟐𝟐𝝍𝝍𝑩𝑩 )

𝟐𝟐𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 𝟐𝟐𝝍𝝍𝑩𝑩

= 𝑽𝑽𝑮𝑮 − 𝟐𝟐𝝍𝝍𝑩𝑩 + 𝑪𝑪𝒐𝒐
𝑪𝑪𝒐𝒐

𝑽𝑽𝑻𝑻

= (𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻 )𝑪𝑪𝒐𝒐

 VELOCITY SATURATION CONDITION (Cont.)
 The channel current at 𝒚𝒚 is

𝑰𝑰𝑫𝑫 (𝒚𝒚) = 𝒁𝒁|𝑸𝑸𝒏𝒏 𝒚𝒚 |𝒗𝒗 𝒚𝒚

𝑳𝑳 𝑳𝑳
or � 𝑰𝑰𝑫𝑫 𝒅𝒅𝒅𝒅 = � 𝒁𝒁|𝑸𝑸𝒏𝒏 𝒚𝒚 |𝒗𝒗 𝒚𝒚 𝒅𝒅𝒅𝒅
𝟎𝟎 𝟎𝟎
𝒁𝒁 𝑳𝑳
𝑰𝑰𝑫𝑫 = � |𝑸𝑸𝒏𝒏 𝒚𝒚 |𝒗𝒗𝒔𝒔 𝒅𝒅𝒅𝒅
𝑳𝑳 𝟎𝟎

under velocity saturation condition, 𝒗𝒗 𝒚𝒚 = 𝒗𝒗𝒔𝒔 (saturation velocity),

𝑸𝑸𝒏𝒏 = (𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻 )𝑪𝑪𝒐𝒐 ∴ 𝑰𝑰𝑫𝑫 = 𝒁𝒁(𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻 )𝑪𝑪𝒐𝒐 𝒗𝒗𝒔𝒔

 The transconductance is
𝝏𝝏𝑰𝑰𝑫𝑫
𝒈𝒈𝒎𝒎 = = 𝒁𝒁𝑪𝑪𝒐𝒐 𝒗𝒗𝒔𝒔 ≠ 𝒇𝒇(𝑽𝑽𝑮𝑮 )
𝝏𝝏𝑽𝑽𝑮𝑮
 VELOCITY SATURATION CONDITION (Cont.)
 Figure 12 shows a comparison of I-V characteristics for (a) constant
mobility and (b) velocity-saturation. All other parameters are the same.
 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 and 𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 are lowered in velocity saturation case
 𝑔𝑔𝑚𝑚 (the current difference between 𝑉𝑉𝐺𝐺 steps) becomes a constant
 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 is not dependent on 𝐿𝐿
 Most advanced MOSFETs with 𝐿𝐿<100 nm are operated in the velocity-
saturation condition
 TYPES OF MOSFET
 There are 4 types of MOSFET, depending on the inversion layer.

 Figure. 26 shows cross section, output, and transfer characteristics of four

types of MOSFETs.
 THRESHOLD VOLTAGE CONTROL

 The threshold voltage is: reverse bias on substrate

𝟐𝟐𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 (𝟐𝟐𝝍𝝍𝑩𝑩 + 𝑽𝑽𝑩𝑩𝑩𝑩 )

𝑽𝑽𝑻𝑻 = 𝑽𝑽𝑭𝑭𝑭𝑭 + 𝟐𝟐𝝍𝝍𝑩𝑩 + (47)
𝑪𝑪𝒐𝒐

 The most important parameter of an MOSFET is 𝑽𝑽𝑻𝑻 , which

depends on 𝑽𝑽𝑭𝑭𝑭𝑭 , doping concentration (𝝍𝝍𝑩𝑩 , 𝑵𝑵𝑨𝑨 ), oxide thickness
(𝑪𝑪𝒐𝒐 ), and substrate bias (𝑽𝑽𝑩𝑩𝑩𝑩 )

 Mid-gap work function gate electrode has

𝑬𝑬𝒈𝒈
𝒒𝒒𝝓𝝓𝒎𝒎 = 𝒒𝒒𝝌𝝌 + = 𝟒𝟒. 𝟎𝟎𝟎𝟎 + 𝟎𝟎. 𝟓𝟓𝟓𝟓 = 𝟒𝟒. 𝟔𝟔𝟔𝟔 𝐞𝐞𝐞𝐞
𝟐𝟐
 THRESHOLD VOLTAGE CONTROL (Cont.)
 Figure 27 shows the calculated threshold voltage of n-channel
(𝑽𝑽𝑻𝑻𝑻𝑻 ) and p-channel (𝑽𝑽𝑻𝑻𝒑𝒑 ) MOSFETs as a function of impurity
concentration, for devices with n+-, p+-polysilicon, and mid-gap
work function gates assuming zero fixed charge. The thickness
of the gate oxide is 5 nm. NMOS is an n-channel MOSFET; PMOS
is a p-channel MOSFET.
 EXAMPLE 6
 For an n-channel n+-polysilicon-SiO2-Si MOSFET with 𝑵𝑵𝑨𝑨 = 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 𝐜𝐜𝐜𝐜−𝟑𝟑 and
𝑸𝑸𝒇𝒇 ⁄𝒒𝒒 = 𝟓𝟓 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 𝐜𝐜𝐜𝐜−𝟐𝟐, calculate 𝑽𝑽𝑻𝑻 for a gate oxide of 5 nm. What is the
boron ion dose required to increase 𝑽𝑽𝑻𝑻 to 0.6 V? Assume that the
implanted acceptors form a sheet of negative charge at the Si-SiO2
interface.

SOLUTION From Exs. 1 and 2 in Ch. 4, we have 𝑪𝑪𝒐𝒐 = 𝟔𝟔. 𝟗𝟗 × 𝟏𝟏𝟏𝟏−𝟕𝟕 𝐅𝐅/𝐜𝐜𝐜𝐜𝟐𝟐 ,
𝟐𝟐𝝍𝝍𝑩𝑩 = 0.84 V, and VFB = ‒1.1 V. Therefore, from Eq. 47 (with VBS =0).

𝟐𝟐𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 (𝟐𝟐𝝍𝝍𝑩𝑩 )

𝑽𝑽𝑻𝑻 = 𝑽𝑽𝑭𝑭𝑭𝑭 + 𝟐𝟐𝝍𝝍𝑩𝑩 +
𝑪𝑪𝒐𝒐
_ _
𝟐𝟐 × 𝟏𝟏𝟏𝟏. 𝟗𝟗 × 𝟏𝟏𝟏𝟏 𝟏𝟏𝟏𝟏 × 𝟏𝟏. 𝟔𝟔 × 𝟏𝟏𝟏𝟏 𝟏𝟏𝟏𝟏 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟕𝟕 × 𝟎𝟎. 𝟖𝟖𝟖𝟖
= −𝟏𝟏. 𝟏𝟏 + 𝟎𝟎. 𝟖𝟖𝟖𝟖 + _
𝟔𝟔. 𝟗𝟗 × 𝟏𝟏𝟏𝟏 𝟕𝟕

= −𝟎𝟎. 𝟎𝟎𝟎𝟎 𝐕𝐕
 EXAMPLE 6 (Cont.)

The boron charge causes a flat-band shift of 𝒒𝒒𝑭𝑭𝑩𝑩⁄𝑪𝑪𝒐𝒐 . Thus,

𝒒𝒒𝑭𝑭𝑩𝑩
𝟎𝟎. 𝟔𝟔 = −𝟎𝟎. 𝟎𝟎𝟎𝟎 + _
𝟔𝟔. 𝟗𝟗 × 𝟏𝟏𝟏𝟏 𝟕𝟕
_
𝟎𝟎. 𝟔𝟔𝟔𝟔 × 𝟔𝟔. 𝟗𝟗 × 𝟏𝟏𝟏𝟏 𝟕𝟕
𝑭𝑭𝑩𝑩 = _𝟏𝟏𝟏𝟏 = 𝟐𝟐. 𝟔𝟔𝟔𝟔 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 𝐜𝐜𝐜𝐜−𝟐𝟐
𝟏𝟏. 𝟔𝟔 × 𝟏𝟏𝟏𝟏

 The negatively charged boron acceptors increase the doping

level of the n-channel MOSFET, and 𝑽𝑽𝑻𝑻 ↑ . A shallow boron
implant into a p-channel MOSFET will reduce 𝑽𝑽𝑻𝑻 .
 THRESHOLD VOLTAGE CONTROL (Cont.)

 The threshold voltage can be controlled by varying the oxide

thickness.
 Figure 28 shows the cross-section of a parasitic field-effect
transistor in an n-well structure.
 EXAMPLE 7
 For an n-channel field transistor with 𝑵𝑵𝑨𝑨 = 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 𝐜𝐜𝐜𝐜−𝟑𝟑 and 𝑸𝑸𝒇𝒇 ⁄𝒒𝒒 = 𝟓𝟓 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm-2
calculate 𝑽𝑽𝑻𝑻 for or a gate oxide (i.e., the field oxide) of 500 nm.

SOLUTION
𝝐𝝐𝒐𝒐𝒐𝒐 _
𝑪𝑪𝒐𝒐 = = 𝟔𝟔. 𝟗𝟗 × 𝟏𝟏𝟏𝟏 𝟗𝟗 𝐅𝐅⁄𝐜𝐜𝐜𝐜𝟐𝟐
𝒅𝒅
From Exs. 2 and 3, we have 𝟐𝟐𝝍𝝍𝑩𝑩 = 𝟎𝟎. 𝟖𝟖𝟖𝟖 𝐕𝐕, and
_
𝑸𝑸𝒇𝒇 + 𝑸𝑸𝒎𝒎 + 𝑸𝑸𝒐𝒐𝒐𝒐 𝟏𝟏. 𝟔𝟔 × 𝟏𝟏𝟏𝟏 𝟏𝟏𝟏𝟏 × 𝟓𝟓 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏
𝑽𝑽𝑭𝑭𝑭𝑭 = 𝝓𝝓𝒎𝒎𝒎𝒎 − = −𝟎𝟎. 𝟗𝟗𝟗𝟗 − _ = −𝟏𝟏𝟏𝟏. 𝟗𝟗𝟗𝟗 𝐕𝐕
𝑪𝑪𝒐𝒐 𝟔𝟔. 𝟗𝟗 × 𝟏𝟏𝟏𝟏 𝟗𝟗

Therefore, from Eq. 47 (with 𝑽𝑽𝑩𝑩𝑩𝑩 = 𝟎𝟎)

𝟐𝟐𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 (𝟐𝟐𝝍𝝍𝑩𝑩 )

𝑽𝑽𝑻𝑻 = 𝑽𝑽𝑭𝑭𝑭𝑭 + 𝟐𝟐𝝍𝝍𝑩𝑩 +
𝑪𝑪𝒐𝒐
_ _
𝟐𝟐 × 𝟏𝟏𝟏𝟏. 𝟗𝟗 × 𝟏𝟏𝟏𝟏 𝟏𝟏𝟏𝟏 × 𝟏𝟏. 𝟔𝟔 × 𝟏𝟏𝟏𝟏 𝟏𝟏𝟏𝟏 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 × 𝟎𝟎. 𝟖𝟖𝟖𝟖
= −𝟏𝟏𝟏𝟏. 𝟗𝟗𝟗𝟗 + 𝟎𝟎. 𝟖𝟖𝟖𝟖 + _
𝟔𝟔. 𝟗𝟗 × 𝟏𝟏𝟏𝟏 𝟗𝟗

= 𝟏𝟏𝟏𝟏. 𝟐𝟐𝟐𝟐 𝐕𝐕
 THRESHOLD VOLTAGE CONTROL (Cont.)
 The threshold voltage can also be controlled by the substrate bias 𝑽𝑽𝑩𝑩𝑩𝑩 :

𝟐𝟐𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨
∆𝑽𝑽𝑻𝑻 = ( 𝟐𝟐𝝍𝝍𝑩𝑩 + 𝑽𝑽𝑩𝑩𝑩𝑩 − 𝟐𝟐𝝍𝝍𝑩𝑩 ) (48)
𝑪𝑪𝒐𝒐
 Figure 29 shows the threshold voltage adjustment using substrate bias.
 EXAMPLE 8

 For the MOSFET discussed in Ex. 6 with 𝑽𝑽𝑻𝑻 of −𝟎𝟎. 𝟎𝟎𝟎𝟎 𝐕𝐕, if the reverse
bias is increased from zero to 𝟐𝟐 𝐕𝐕, calculate the change in threshold
voltage.

SOLUTION

From Eq. 48,

𝟐𝟐𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨
∆𝑽𝑽𝑻𝑻 = ( 𝟐𝟐𝝍𝝍𝑩𝑩 + 𝑽𝑽𝑩𝑩𝑩𝑩 − 𝟐𝟐𝝍𝝍𝑩𝑩 )
𝑪𝑪𝒐𝒐
_ _
𝟐𝟐 × 𝟏𝟏𝟏𝟏. 𝟗𝟗 × 𝟖𝟖. 𝟖𝟖𝟖𝟖 × 𝟏𝟏𝟏𝟏 𝟏𝟏𝟏𝟏 × 𝟏𝟏. 𝟔𝟔 × 𝟏𝟏𝟏𝟏 𝟏𝟏𝟏𝟏 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 ( 𝟎𝟎. 𝟖𝟖𝟖𝟖 + 𝟐𝟐 − 𝟎𝟎. 𝟖𝟖𝟖𝟖)
= _
𝟔𝟔. 𝟗𝟗 × 𝟏𝟏𝟏𝟏 𝟕𝟕

= 𝟎𝟎. 𝟐𝟐𝟐𝟐 × 𝟏𝟏. 𝟔𝟔𝟔𝟔 − 𝟎𝟎. 𝟗𝟗𝟗𝟗 = 𝟎𝟎. 𝟐𝟐𝟐𝟐 𝐕𝐕

 MOSFET SCALING
 Advantages of device scaling (miniaturization)
 higher device density ― more circuit function per unit chip area

 higher driving current ― 𝐼𝐼𝐷𝐷 ~ 1/𝐿𝐿

 higher speed ― transit time across channel ~ 1/𝐿𝐿

 lower power consumption per device

 reduced cost per circuit function

 Disadvantages of device scaling ― short channel effects

 𝑉𝑉𝑇𝑇 roll-off

 drain-induces barrier lowering (DIBL)

 bulk punch-through

 reduction of mobility and transconductance

 generation of hot carriers (substrate current, oxide charge)

 THRESHOLD VOLTAGE ROLL-OFF
 As 𝑳𝑳 ↓ fields originating from source/drain regions will influence the charge
distribution in the surface depletion region

 Figure shows the charge-conservation model, (a) 𝑽𝑽𝑫𝑫 > 𝟎𝟎, (b) 𝑽𝑽𝑫𝑫 = 𝟎𝟎, and (c)
Charge-sharing model.
𝒓𝒓𝒋𝒋
𝑾𝑾𝑫𝑫𝑫𝑫 𝑾𝑾𝑫𝑫𝑫𝑫

𝒓𝒓𝒋𝒋

∆= (𝑳𝑳 − 𝑳𝑳𝑳)⁄𝟐𝟐

(𝑾𝑾𝑫𝑫𝑫𝑫 + 𝒓𝒓𝒋𝒋 )𝟐𝟐 = (∆ + 𝒓𝒓𝒋𝒋 )𝟐𝟐 +𝑾𝑾𝟐𝟐𝑫𝑫𝑫𝑫

so ∆𝟐𝟐 + 𝟐𝟐∆𝒓𝒓𝒋𝒋 − 𝟐𝟐𝑾𝑾𝑫𝑫𝑫𝑫 𝒓𝒓𝒋𝒋 = 𝟎𝟎

∴ ∆= (𝑳𝑳 − 𝑳𝑳𝑳)⁄𝟐𝟐
= −𝒓𝒓𝒋𝒋 + 𝒓𝒓𝟐𝟐𝒋𝒋 + 𝟐𝟐𝑾𝑾𝑫𝑫𝑫𝑫 𝒓𝒓𝒋𝒋
 THRESHOLD VOLTAGE ROLL-OFF (Cont.)

𝑳𝑳 + 𝑳𝑳′ 𝑳𝑳 + (𝑳𝑳 − 𝟐𝟐∆) 𝟐𝟐𝟐𝟐 − 𝟐𝟐∆ ∆ 𝒓𝒓𝒋𝒋 𝟐𝟐𝑾𝑾𝑫𝑫𝑫𝑫

= = = 𝟏𝟏 − = 𝟏𝟏 − 𝟏𝟏 + − 𝟏𝟏
𝟐𝟐𝟐𝟐 𝟐𝟐𝟐𝟐 𝟐𝟐𝟐𝟐 𝑳𝑳 𝑳𝑳 𝒓𝒓𝒋𝒋

𝟏𝟏 𝑸𝑸′𝑩𝑩 𝒒𝒒𝑵𝑵𝑨𝑨 𝑾𝑾𝑫𝑫𝑫𝑫 𝑳𝑳 + 𝑳𝑳′

∆𝑽𝑽𝑻𝑻 = − 𝒒𝒒𝑵𝑵𝑨𝑨 𝑾𝑾𝑫𝑫𝑫𝑫 = − 𝟏𝟏
𝑪𝑪𝒐𝒐 𝒁𝒁𝒁𝒁 𝑪𝑪𝒐𝒐 𝟐𝟐𝟐𝟐

−𝒒𝒒𝑵𝑵𝑨𝑨 𝑾𝑾𝑫𝑫𝑫𝑫 𝒓𝒓𝒋𝒋 𝟐𝟐𝑾𝑾𝑫𝑫𝑫𝑫 (1)

= 𝟏𝟏 + − 𝟏𝟏
𝑪𝑪𝒐𝒐 𝑳𝑳 𝒓𝒓𝒋𝒋

 As 𝑳𝑳 ↓, ∆𝑽𝑽𝑻𝑻 ↑. 𝑽𝑽𝑻𝑻 decreases with decreasing channel length, due to the

reduction of charge in the depletion layer from rectangular 𝑳𝑳 × 𝑾𝑾𝑫𝑫𝑫𝑫 to
the trapezoidal region (𝑳𝑳 + 𝑳𝑳𝑳)𝑾𝑾𝑫𝑫𝑫𝑫 ⁄𝟐𝟐
 THRESHOLD VOLTAGE ROLL-OFF (Cont.)
 Figure shows the threshold voltage roll-off characteristics in a 0.15 μm
complementary metal-oxide-semiconductor (CMOS) field-effect transistor
technology.
 DRAIN-INDUCED BARRIER LOWERING (DIBL)
 The potential barrier height at the source will be lowered by increasing
drain bias. DIBL will cause an injection of extra carriers from source to
drain. It forms a leakage path at SiO2/Si interface.

 Figure 3 shows the energy-band diagram at the semiconductor surface

from source to drain, for (a) long-channel and (b) short channel
MOSFETs, showing the DIBL effect in the latter. Dashed lines: 𝑽𝑽𝑫𝑫 = 𝟎𝟎.
Solid lines: 𝑽𝑽𝑫𝑫 > 𝟎𝟎.
 DRAIN-INDUCED BARRIER LOWERING (DIBL)
(Cont.)
 Figure 4 shows the subthreshold characteristics of (a) a long-channel
and (b) a short-channel MOSFET.
 BULK PUNCH-THROUGH
 If 𝒚𝒚𝑺𝑺 + 𝒚𝒚𝑫𝑫 ≤ 𝑳𝑳, punch-through occurs

 Depletion region of the drain junction merges into that of the source
junction
 A leakage current will flow from drain to source via the bulk’s depletion
region

 The dominate current is the space-charge-limited current

𝑰𝑰𝑫𝑫 = 𝟗𝟗𝝐𝝐𝒔𝒔 𝑨𝑨 𝑽𝑽𝟐𝟐𝑫𝑫 ⁄𝟖𝟖𝑳𝑳𝟑𝟑 (2)

where 𝑨𝑨 is the cross-sectional area of the punch-through path

 The punch-through voltage can be obtained from Eq. 27, Ch.3

𝒒𝒒𝑵𝑵𝑨𝑨 (𝑳𝑳 − 𝒚𝒚𝑺𝑺 )𝟐𝟐 (3)

𝑽𝑽𝒑𝒑𝒑𝒑 = 𝑽𝑽𝒃𝒃𝒃𝒃
𝟐𝟐𝝐𝝐𝒔𝒔
 BULK PUNCH-THROUGH AND DIBL
 Figure 5 shows the drain characteristics of MOSFETs having punch-
through characteristics. (a) Above threshold, 𝑳𝑳 = 𝟎𝟎. 𝟐𝟐𝟐𝟐 𝛍𝛍𝐦𝐦. 𝒅𝒅 = 𝟐𝟐𝟐𝟐. 𝟖𝟖 𝐧𝐧𝐧𝐧.
𝑵𝑵𝑨𝑨 = 𝟕𝟕 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 𝐜𝐜𝐜𝐜−𝟑𝟑 . (b) Below threshold. 𝒅𝒅 = 𝟏𝟏𝟏𝟏 𝐧𝐧𝐧𝐧. 𝑵𝑵𝑨𝑨 = 𝟕𝟕 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟒𝟒 𝐜𝐜𝐜𝐜−𝟑𝟑 .

𝒚𝒚𝒔𝒔 + 𝒚𝒚𝑫𝑫 = 𝟎𝟎. 𝟐𝟐𝟐𝟐 𝛍𝛍𝐦𝐦

 BULK PUNCH-THROUGH AND DIBL
(cont.)
 Figure 6 shows the subthreshold characteristics of an n-channel
MOSFET with 𝑽𝑽𝑫𝑫 = 𝟎𝟎. 𝟏𝟏, 𝟏𝟏, and 𝟒𝟒 𝐕𝐕.

Punch-
through

DIBL
 SCALING RULES
 Constant-field scaling: reduce all dimensions and voltages by a
scaling factor 𝜿𝜿 > 𝟏𝟏.

 Therefore, the internal fields are the same as those of a long-

channel MOSFET.

𝟏𝟏
 Device dimensions 𝒅𝒅, 𝑳𝑳, 𝑾𝑾, 𝒓𝒓𝒋𝒋 ~
𝜿𝜿
Doping concentration 𝑵𝑵𝑨𝑨 , 𝑵𝑵𝑫𝑫 ~ 𝜿𝜿
𝟏𝟏
Voltage 𝑽𝑽 ~
𝜿𝜿
 SCALING RULES (Cont.)
 Figure below shows the drain characteristics of a long-
channel (right) and a short-channel (left) device.

𝑽𝑽𝑮𝑮 ⁄𝜿𝜿 𝑽𝑽𝑮𝑮

𝒅𝒅⁄𝜿𝜿 𝒅𝒅
𝑽𝑽𝑫𝑫 ⁄𝜿𝜿 𝑽𝑽𝑫𝑫

n+ n+ n+ n+
𝑳𝑳⁄𝜿𝜿
𝑳𝑳
DOPING 𝜿𝜿𝑵𝑵𝑨𝑨 DOPING 𝑵𝑵𝑨𝑨

𝑰𝑰𝑫𝑫 SCALED-
DOWN LARGE
DEVICE DEVICE
(𝑽𝑽𝑫𝑫⁄𝜿𝜿) (𝑽𝑽𝑫𝑫 )

𝑽𝑽𝑮𝑮
𝑽𝑽𝑻𝑻 ⁄𝜿𝜿 𝑽𝑽𝑻𝑻
 SCALING RULES (Cont.)
 Device parameters:

𝓔𝓔′ electric field = 𝓔𝓔 (constant−field)

𝑾𝑾 ′
Depletion-layer width 𝑾𝑾 =
𝜿𝜿
𝝐𝝐𝒐𝒐𝒐𝒐 𝑨𝑨 𝑪𝑪𝒐𝒐 𝑨𝑨 𝝐𝝐𝒐𝒐𝒐𝒐
Capacitance 𝑪𝑪′𝒐𝒐 𝑨𝑨′ = = , 𝑪𝑪′𝒐𝒐 = = 𝜿𝜿𝑪𝑪𝒐𝒐
𝒅𝒅⁄𝜿𝜿 𝜿𝜿𝟐𝟐 𝜿𝜿 ⁄
𝒅𝒅 𝜿𝜿

 Circuit parameters:
𝒁𝒁 (𝜿𝜿𝑪𝑪𝒐𝒐 ) 𝑰𝑰𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫
𝑰𝑰′𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫 = 𝝁𝝁𝒏𝒏 𝟐𝟐 𝟐𝟐
(𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻 ) �𝜿𝜿 =
𝜿𝜿 ⁄
𝟐𝟐 𝑳𝑳 𝜿𝜿 𝜿𝜿
𝑰𝑰′𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫 𝑰𝑰𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫 𝟏𝟏
𝑱𝑱′𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫 = = = 𝜿𝜿J𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫
𝑨𝑨′ 𝜿𝜿 𝑨𝑨⁄𝜿𝜿𝟐𝟐
 SCALING RULES (Cont.)

 Circuit parameters:
𝒗𝒗𝒔𝒔
𝒇𝒇′𝑻𝑻 = = 𝜿𝜿𝒇𝒇𝑻𝑻
⁄
𝟐𝟐𝝅𝝅 𝑳𝑳 𝜿𝜿

𝟐𝟐
𝟐𝟐 𝑪𝑪𝒐𝒐 𝑨𝑨 𝑽𝑽 𝑷𝑷𝒂𝒂𝒂𝒂
𝑷𝑷′𝒂𝒂𝒂𝒂 = 𝑪𝑪′𝒐𝒐 𝑨𝑨′ 𝑽𝑽′ 𝒇𝒇′𝑻𝑻 = 𝜿𝜿𝒇𝒇𝑻𝑻 =
𝜿𝜿 𝜿𝜿 𝜿𝜿𝟐𝟐
𝑰𝑰 𝑽𝑽 𝑷𝑷𝒂𝒂𝒂𝒂
𝑷𝑷′𝒅𝒅𝒅𝒅 = 𝑰𝑰′ 𝑽𝑽′ = = 𝟐𝟐
𝜿𝜿 𝜿𝜿 𝜿𝜿
𝟐𝟐
′
𝟏𝟏 ′ 𝟐𝟐
𝟏𝟏 𝑪𝑪𝒐𝒐 𝑨𝑨 𝑽𝑽 𝑬𝑬
𝑬𝑬 = (𝑪𝑪𝒐𝒐 𝑨𝑨) 𝑽𝑽𝑽 = = 𝟑𝟑
𝟐𝟐 𝟐𝟐 𝜿𝜿 𝜿𝜿 𝜿𝜿
 MOSFET STRUCTURES
 Channel doping : low-high-low doping by multiple ion implantations
(1) low concentration at the surface ─ for higher mobility
(2) high peak concentration below the surface ─ to control punch
through
(3) lower concentration below the junction depth ─ to reduce
junction capacitance and substrate ─ bias effect on 𝑉𝑉𝑇𝑇

 Figure 7 shows a high-performance MOSFET planar structure with a

retrograde channel doping profile, two-step source/drain junction, and
self-aligned silicide source/drain contact.

𝑵𝑵𝑨𝑨

𝒑𝒑−
𝒑𝒑
𝒑𝒑−

𝒙𝒙
 MOSFET STRUCTURES (Cont.)
 Effective oxide thickness in the gate stack :
𝝐𝝐𝒊𝒊 𝝐𝝐𝒐𝒐𝒐𝒐 𝝐𝝐𝒐𝒐𝒐𝒐
𝑪𝑪𝒐𝒐 = = =
𝒅𝒅 𝒅𝒅 𝝐𝝐𝒐𝒐𝒐𝒐 𝐄𝐄𝐄𝐄𝐄𝐄
𝝐𝝐𝒊𝒊
𝝐𝝐𝒐𝒐𝒐𝒐
EOT ≡ effective oxide thickness = 𝒅𝒅
𝝐𝝐𝒊𝒊
𝝐𝝐𝒊𝒊 𝝐𝝐𝒐𝒐𝒐𝒐
 Example : = 𝟑𝟑𝟑𝟑 = 𝒌𝒌 = 𝟑𝟑. 𝟗𝟗 (𝐒𝐒𝐒𝐒𝐎𝐎𝟐𝟐 )
𝝐𝝐𝟎𝟎 𝝐𝝐𝟎𝟎

An insulator with a thickness of 10 nm has

𝟑𝟑. 𝟗𝟗
EOT = 𝟏𝟏𝟏𝟏 × = 𝟏𝟏 nm
𝟑𝟑𝟑𝟑
 High-𝒌𝒌 dielectric with thicker physical dimension can be used to
avoid tunneling, e.g., Al2O3, HfO2, La2O3, Ta2O3, TiO2
 MOSFET STRUCTURES (Cont.)

 Figure below shows the trend in reduction of EOT

100 1000
EOT (nm)

(Å)
EOT(A)
EOT(nm)

10 100

EOT
1 10

1970 1980 1990 2000 2010 2020

YEAR
 MOSFET STRUCTURES (Cont.)

 Gate contact materials in the gate stack

 Polysilicon can withstand high-temperature process,

provide self-aligned process and vary the work function (n
or p type)

 But polysilicon has high resistivity and depletion effect. The

depletion effect, due to the depletion region in the n+-
polysilicon, will introduce an additional capacitance in
series with 𝑪𝑪𝒐𝒐 and 𝑪𝑪𝒋𝒋 . Therefore the maximum oxide
capacitance is reduced

 Silicides and metals are being used for advanced MOSFETs,

e.g., TiN, TaN, W, Mo, and NiSi
 MOSFET STRUCTURES (Cont.)

 Figure 8 shows (a) the poly-Si gate depletion effect of an n+-

polysilicon-gate n-channel MOS capacitor biased under
inversion operation, (b) degradation in oxide capacitance of
MOS capacitor with metal and poly-Si gates.
 SOURCE/DRAIN DESIGN
 LDD (lightly doped drain in Fig. 7): less heavily doped near
the channel to minimize impact ionization, deeper junction
away from the channel to minimize series resistance.

 Four components of source/drain resistance

𝑹𝑹𝒂𝒂𝒂𝒂 (accumulation-layer resistance) at gate-drain
overlap region
𝑹𝑹𝒔𝒔𝒔𝒔 (spreading resistance)
𝑹𝑹𝒔𝒔𝒔𝒔 (sheet resistance)
𝑹𝑹𝒄𝒄𝒄𝒄 (contact resistance)
 SOURCE/DRAIN DESIGN (Cont.)
 Figure 9 shows detailed analysis of different components
of parasitic source/drain series resistance.
 SOURCE/DRAIN DESIGN (Cont.)
 To reduce the source/drain resistance:
 Use silicide contact technology i.e., self-aligned silicide or salicide
to reduce 𝑹𝑹𝒔𝒔𝒔𝒔 and 𝑹𝑹𝒄𝒄𝒄𝒄
 Use Schottky-barrier source/drain
 Figure 10 shows MOSFET with Schottky-barrier source and drain.
(a) Cross-sectional view of the device. (b)-(d) Band diagrams along
semiconductor surface under various biases.
 SOURCE/DRAIN DESIGN (cont.)

 For p-type substrate , the Schottky-barrier high 𝒒𝒒𝝋𝝋𝑩𝑩𝑩𝑩 must be high ;

After inversion 𝒒𝒒𝝋𝝋𝑩𝑩𝒏𝒏 on n-type inversion layer will be low enough to
provide sufficient current.
 For example , 𝑞𝑞𝜑𝜑𝐵𝐵𝐵𝐵 (ErSi on p-type Si) = 0.84 eV
∴ 𝑞𝑞𝜑𝜑𝐵𝐵𝑛𝑛 (ErSi on n-type Si) = 𝐸𝐸𝑔𝑔 − 𝑞𝑞𝜑𝜑𝐵𝐵𝐵𝐵 =1.12 – 0.84 = 0.28
thermionic current for 0.28 eV barrier is ~103 A/cm2.
 Advantages of Schottky-barrier source/drain:
1) rj 0 to minimize short-channel effect.
2) avoid latch-up in CMOS.
3) low temperature process. (no high-temperature diffusion or post-implant
annealing required)
 Disadvantages:
1) High series resistance.
2) Higher drain leakage current.
3) Metal/ silicide contact must extend underneath the gate
 EQUIVALENT CIRCUIT AND FREQUENCY RESPONSE
 The equivalent circuit of an MOSFET is shown below
CGS = MOS gate capacitance ≅ 𝒁𝒁𝒁𝒁𝑪𝑪𝟎𝟎
CGD = gate-to-drain capacitance due to gate/drain overlap region
𝒈𝒈𝒎𝒎 = transconductance , Eq.39 or Eq.42.
𝒈𝒈𝑫𝑫 = drain conductance , Eq.38.
 The cutoff frequency is defined as the frequency at which iout / iin = 1

𝒊𝒊𝒊𝒊𝒊𝒊 = 𝝎𝝎 𝑪𝑪𝑮𝑮𝑮𝑮 + 𝑪𝑪𝑮𝑮𝑮𝑮 �

𝝊𝝊𝑮𝑮 𝒊𝒊𝒐𝒐𝒐𝒐𝒐𝒐 = 𝒈𝒈𝒎𝒎 𝝊𝝊�𝑮𝑮
∴ 𝝎𝝎 𝑪𝑪𝑮𝑮𝑮𝑮 + 𝑪𝑪𝑮𝑮𝑮𝑮 �
𝝊𝝊𝑮𝑮 = 𝒈𝒈𝒎𝒎 𝝊𝝊�𝑮𝑮
𝒁𝒁 𝒁𝒁
𝝁𝝁 𝑪𝑪 𝑽𝑽𝑫𝑫 𝝁𝝁𝒏𝒏𝝁𝝁
𝝎𝝎𝝎𝝎 𝒈𝒈𝒎𝒎 𝒈𝒈𝒎𝒎 𝑳𝑳 𝒏𝒏 𝒐𝒐 𝑳𝑳 𝑪𝑪𝒏𝒏𝒐𝒐𝑽𝑽𝑽𝑽𝑫𝑫𝑫𝑫 𝝁𝝁𝒏𝒏 𝑽𝑽𝑫𝑫
𝒇𝒇 = =
𝒇𝒇𝑻𝑻𝑻𝑻 = 𝟐𝟐𝝅𝝅 =𝟐𝟐𝝅𝝅 𝑪𝑪𝑮𝑮𝑮𝑮 +𝑪𝑪𝑮𝑮𝑮𝑮 ≈ 𝟐𝟐𝝅𝝅𝑪𝑪≈
= 𝟐𝟐 = for constant mobility case
𝒐𝒐 𝒁𝒁𝒁𝒁
𝟐𝟐𝝅𝝅 𝟐𝟐𝝅𝝅 𝑪𝑪𝑮𝑮𝑮𝑮 + 𝑪𝑪𝑮𝑮𝑮𝑮 𝟐𝟐𝝅𝝅𝑪𝑪𝟐𝟐𝝅𝝅𝑳𝑳
𝒐𝒐 𝒁𝒁𝒁𝒁 𝟐𝟐𝝅𝝅𝑳𝑳𝟐𝟐

𝒁𝒁𝑪𝑪𝒁𝒁𝑪𝑪
𝒐𝒐 𝒗𝒗
𝒐𝒐 𝒗𝒗𝒔𝒔𝒔𝒔 𝒗𝒗𝒔𝒔𝒔𝒔
𝒗𝒗 𝟏𝟏 𝟏𝟏
𝒇𝒇
𝒇𝒇𝑻𝑻 = 𝑻𝑻 = 𝟐𝟐𝝅𝝅𝑪𝑪 𝒁𝒁𝒁𝒁
= 𝟐𝟐𝝅𝝅𝑳𝑳
==𝟐𝟐𝝅𝝅𝝉𝝉 v for velocity saturation case
𝟐𝟐𝝅𝝅𝑪𝑪𝒐𝒐 𝒁𝒁𝒁𝒁 𝟐𝟐𝝅𝝅𝑳𝑳 𝟐𝟐𝝅𝝅𝝉𝝉𝒕𝒕
𝒐𝒐 𝒕𝒕
𝑪𝑪𝑮𝑮𝑮𝑮
𝑮𝑮 𝑫𝑫
𝒍𝒍 𝑳𝑳
where 𝝉𝝉𝒕𝒕𝝉𝝉≡
𝒕𝒕 ≡ is the transit
𝑪𝑪𝑮𝑮𝑮𝑮 𝒈𝒈𝒎𝒎 𝝊𝝊�𝑮𝑮
𝒗𝒗𝒔𝒔𝒗𝒗𝒔𝒔
𝝊𝝊�𝑮𝑮 𝒈𝒈𝑫𝑫 𝝊𝝊�𝐷𝐷
time across the channel length.
𝑺𝑺 𝑺𝑺
 THE CMOS INVERTER
 The complementary MOS (CMOS) is an enhancement-type PMOS and
NMOS pair.
 CMOS is the most important technology for advanced ICs.
 CMOS inverter is the basic element of CMOS logic circuits , shown below :
Power supply

I/p O/p

D
G

Ground
 THE CMOS INVERTER (Cont.)

 When 𝑽𝑽𝒊𝒊𝒊𝒊 = 𝟎𝟎 , 𝑽𝑽𝑮𝑮𝑮𝑮𝑮𝑮 = 𝟎𝟎 < 𝑽𝑽𝑻𝑻𝑻𝑻 , NMOS is off. PMOS is on

𝑽𝑽𝑮𝑮𝑮𝑮𝑮𝑮 ≡ 𝑽𝑽𝑫𝑫𝑫𝑫 > 𝑽𝑽𝑻𝑻𝑻𝑻 , therefore 𝑽𝑽𝒐𝒐𝒐𝒐𝒐𝒐 → 𝑽𝑽𝑫𝑫𝑫𝑫 , through PMOS.

 When 𝑽𝑽𝒊𝒊𝒊𝒊 = 𝑽𝑽𝑫𝑫𝑫𝑫 , NMOS is on 𝑽𝑽𝑮𝑮𝑮𝑮𝒏𝒏 = 𝑽𝑽𝑫𝑫𝑫𝑫 > 𝑽𝑽𝑻𝑻𝑻𝑻 , PMOS is off
𝑽𝑽𝑮𝑮𝑮𝑮𝒑𝒑 = 𝟎𝟎 < 𝑽𝑽𝑻𝑻𝑻𝑻 , therefore , 𝐕𝐕𝒐𝒐𝒐𝒐𝒐𝒐 → 𝟎𝟎, discharged to ground
through NMOS.

 Thus the output voltage is inverted from the input voltage:

Vin high → Vout low
Vin low → Vout high
 THE CMOS INVERTER (Cont.)
 Figure 13 shows IP and In as functions of Vout. The intercepts Ip and In
(circled) represent the steady-state operation points of the CMOS inverter.
The curves are labeled by the input voltage : 𝟎𝟎 = 𝑽𝑽𝒊𝒊𝒊𝒊𝟎𝟎 < 𝑽𝑽𝒊𝒊𝒊𝒊𝒊𝒊 < 𝑽𝑽𝒊𝒊𝒊𝒊𝟐𝟐 <
𝑽𝑽𝒊𝒊𝒊𝒊𝟑𝟑 < 𝑽𝑽𝒊𝒊𝒊𝒊𝟒𝟒 = 𝑽𝑽𝑫𝑫𝑫𝑫
 The increase in Vin tends to increase In but decrease Ip at fixed Vout.

 In steady state In = Ip.

 For example , for intercept

C : In (Vin1) = Ip (Vin1)
D : In (Vin3) = Ip (Vin3)

E : In (Vin2) = Ip (Vin2)

E
 CMOS INVERTER : TRANSFER CURVE
 Figure 14 shows the transfer curve of a CMOS inverter. Point labeled A, B, C,
D, and E correspond to the points labeled in Fig. 13.
 For a given Vin , we can determine the corresponding Vout from the intercept

of In (Vin) and Ip (Vin) as shows in Fig. 13

 CMOS inverter main characteristic : when the output Vout = 0 , or VDD only one

transistor is on .The current from VDD to ground is very low (the leakage
current of the off device). Significant current flow only during the transient
period when both devices are temporarily on.
 CMOS has the lowest power consumption as compared to other logic circuits.

E
 MOSFET ON INSULATOR
 There are two kinds of MOSFET on Insulator
1) Thin-film transistor (TFT) : channel layer is an amorphous or
polycrystalline silicon.
2) Silicon-on-insulator (SOI): channel layer is a monocrystalline silicon.

 For the amorphous TFT , usually it is hydrogenated (a-Si:H) to reduce

defect density.
 Inverted staggered structure.

 Glass is used as the substrate , low temperature process (200 - 400℃)

 Carrier mobility is low (<1 cm2/V-s). Subthreshold swing is large (~1000

mV/decade)
 For large-area application : flat-panel display.
 MOSFET ON INSULATOR (Cont.)

 Figure 21 shows the subthreshold characteristic of an a-Si:H TFT (L / Z

= 10/60 μm/μm). The field-effect carrier mobility is 0.23 cm2/V-s. The
insert shows the device structure.
 MOSFET ON INSULATOR (Cont.)
 For the polysilicon TFT , it is also hydrogenated to reduce defeats at the
grain boundaries.
 Polysilicon consists of many Si grains.

 Top-gate structure.

 Quartz is used as the substrate , higher temperature process ( > 600 ℃ )

 Higher mobility than that of (a-Si:H) TFT, 10~100 cm2/V-s ,

 To increase the grain size, laser can be used to melt the polysilicon locally,

after cooling , large-grain size ( >1 μm) can be obtained .

 Figure 22 shows a polysilicon TFT structure
 MOSFET ON INSULATOR (Cont.)
 For SOI Device:
 Isolation is simpler than conventional MOSFET.

 Higher device density.

 Reduce parasitic capacitance.

 More radiation-damage tolerance (due to small volume of Si available).

 No latch-up phenomenon (at certain voltage a large current will flow from

𝑉𝑉𝐷𝐷𝐷𝐷 to the ground , and may destroy the chip itself , see Thyristor and
Related Power Device , p 149)
 Figure 23 shows the cross section of the silicon-on-insulator (SOI).
 MOSFET ON INSULATOR (Cont.)
 For partially depleted (PD) type SOI:
 Channel layer thickness > Wm (at heavy inversion)
 Majority carriers (holes in p-substrate) generated by impact ionization at
the drain will be stored in the substrate → will result in VT ↘ → an increase
in the drain current (kink effect).
 To eliminate the kink effect , a substrate contact to the source is required.
 For fully depleted (FD) type SOI:
 Chanel layer thickness < Wm.

 Lower voltage operation , no kink effect caused by impact ionization.

 It characteristics are sensitive to Si thickness.

 Figure 24 shows the kink effect in the output characteristics of an n-channel

SOI MOSFET.
 EXAMPLE 1
 Calculate the threshold voltage for an n-channel SOI device having
𝑸𝑸𝒇𝒇𝒇𝒇
𝑸𝑸
𝑵𝑵𝑨𝑨 = 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 𝐜𝐜𝐦𝐦−𝟑𝟑 , 𝒅𝒅 = 𝟓𝟓 𝐧𝐧𝐧𝐧, and 𝒒𝒒𝒒𝒒
= 𝟓𝟓 × 𝟏𝟏𝟎𝟎𝟏𝟏𝟏𝟏 𝐜𝐜𝐦𝐦−𝟐𝟐 . Si thickness 𝒅𝒅𝑺𝑺𝑺𝑺 for the

device is 50 nm.

 SOLUTION
From Ex1 , Chapter 5 , the maximum depletion width , Wm , for a bulk NMOS
device is 100 nm .Therefore , the SOI device is a fully depleted type . Since the
width of the depletion region is now the Si thickness , Wm used in Eq.17 and
Eq.47, Chapter 5 for calculating the threshold voltage should be replaced by dSi:
𝑞𝑞𝑁𝑁𝐴𝐴 𝑑𝑑𝑆𝑆𝑆𝑆
𝑉𝑉𝑇𝑇 = 𝑉𝑉𝐹𝐹𝐹𝐹 + 2𝜓𝜓𝐵𝐵 +
𝐶𝐶𝑜𝑜
From Exs.2 and 3, Chapter 5, we have 𝐶𝐶𝑜𝑜 = 6.9×10-7 F/cm2, 𝑉𝑉𝐹𝐹𝐹𝐹 = -1.1V, and
2𝜓𝜓𝐵𝐵 = 0.84 V .Therefore ,

1.6 × 10−19 × 1017 × 5 × 10−6

𝑉𝑉𝑇𝑇 = −1.1 + 0.84 + = −0.14 𝑉𝑉
6.9 × 10−7
 THREE-DIMENSIONAL MOSFET
 FinFET – this is a horizontal transistor , because the current flow is
parallel to the substrate.
 Vertical transistor – current flow is perpendicular to the substrate.
 Both devices are more difficult to make – such as smooth surface from
etching , deposition of gate dielectric , silicide formation ,etc.
 Below 20 nm , most MOSFETs are FinFET type (with 3 gates)
 Around 10 nm , may be nanowire – type MOSFET will be used (with
infinite gates).
 Figure 25 shows schematic three dimensional MOSFETs. (a) Horizontal
structure , FinFET. (b)Vertical structure.
 MOS MEMORY STRUCTURES
 Classification of semiconductor memories (and related device structures).
DRAM
Volatile
SRAM EPROM

NVSM EEPROM
Memory

Flash

Non-volatile FRAM

MRAM

Alternative
PCRAM
memory

RRAM

Others

 Non-volatile semiconductor memories (NVSM) will be considered in Ch.6 .

 MOS MEMORY STRUCTURES (Cont.)

 The volatile memory loses its stored information if the power supply is
switched off:
 DRAM (dynamic random access memory) − high density and low cost.
 SRAM (static random access memory) − high speed.
 The non-volatile memory can retain its stored information, when the
power supply is switched off:
 EPROM (erasable programmable read-only memory)
 EEPROM (electrically erasable programmable read-only memory)
 Flash memory
 Alternative memories
 Ferroelectric memory
 Magnetic memory
 Phase change memory
 Resistive memory
 others
 DRAM
 Figure 26 shows the basic configuration of a dynamic random-access
memory (DRAM) cell.
 DRAM cell is a two-element circuit, which consists of a MOSFET and an MOS

capacitor.
 The MOSFET acts as a switch to control the writing, refreshing, and read-out

of the cell.
 The capacitor is for charge storage.

 During write cycle, the MOSFET is on so that the data on the bit line is

transferred to the storage capacitor.

 Due to leakage current, storage charge will be gradually lost. We have to

refresh the data periodically within a fixed interval − it is “dynamic”.

MOSFET

MOS
Capacitor
 DRAM (Cont.)
 Design of the storage capacitor
 The storage capacitor has a capacitance of 𝐶𝐶 = 𝜖𝜖𝑖𝑖 𝐴𝐴/𝑑𝑑

where ϵi is the dielectric permittivity, A is the area, and d is the dielectric

thickness
 For a given minimum d, C can be increased by increasing ϵi and/or A
 To increase ϵi , dielectric materials with dielectric constants higher than 3.9
(SiO2) can be used, Ta2O5, SrTiO3
 To increase the area, trench cell structure and stacked-capacitor cell are

used.
 Figure 27 shows (a) DRAM with a trench cell structure. (b) DRAM with a
single-layer stacked-capacitor cell.
 SRAM
 SRAM is a bistable flip-flop circuit consisting of two cross-coupled
CMOS inverters (T1, T3 and T2, T4 ) and two access transistors (T5, T6 ).
 The output of an inverter is connected to the input of the other inverter.
 The logic state is sustained as long as the power is applied. No refresh
is required.
 Figure 27 shows the configuration of a CMOS SRAM cell.T1 and T2 are
load transistors (p-channel), T3 and T4 are drive transistors (n-channel),
and T5 and T6 are access transistors (n-channel)
 POWER MOSFET
 Power MOSFET has low gate leakage (insulating gate) and high speed (no
minority carriers).
 It employs thicker d, deeper r and longer 𝐿𝐿 also vertical structure with source
j
at top and drain at bottom.
 Extensively used in cellular phones and cellular base stations.

 Figure 35 shows (a) V-shaped MOS (VMOS), (b) U-shaped MOS(UMOS), and
(c) double diffused MOS (DMOS) power device structures.
 POWER MOSFET (Cont.)
 V – MOSFET: KOH etch, ratio of etch rates for (100), (110), and
(111) planes is 100:16:1; at 80℃ etch rate for (100) is 0.6 μm/min.
Inversion channel is along the V-shape groove.

54.7o

(100)

(111)

 U – MOSFET: reactive ion etching, lower electric field at bottom

corners.
 D – MOSFET: gate serves as the mask for double diffusion. B
moves faster than P, to determine the channel length (very
short L without lithographic mask).
 SUMMARY OF CHAPTER 5
 MOSFET is the most important device for logic circuits and volatile
memories. Its success is mainly due to the high-quality SiO2 and its stable
SiO2− Si interface

 CMOS technology is the most important solution for advanced ICs due to
its low-power consumption.

 Device scaling is a continuous trend to increase device density, operating

speed and functionality of a chip. While implementing device scaling, we
must minimize short channel effects.

 TFT and SOI are MOSFET devices made on insulating substrates. TFT is
used for large-area flat-panel display and SOI is for low-power high-speed
applications.

 MOSFET is also used in power-device applications because it has high-

input impedance and no minority-carrier storage effect.