NETWORKING SYSTEMS

An overview of Controller
Area Network
by M. Farsi, K. Ratcliff and Manuel Barbosa

The Controller Area Network is a well-established networking system

specifically designed with real-time requirements in mind. Developed in
the 1980s by Robert Bosch, its ease of use and low cost has led to its
wide adoption throughout the automotive and automation industries.
However, for the beginner using CAN may seem somewhat bewildering.
This article goes some way into explaining how CAN is used both at the
hardware and the software levels.

T
he Controller Area Network (CAN) was 5 Low-cost physical medium: CAN operates over a simple
originally developed in the 1980s for the twisted wire pair, therefore cabling a CAN network is
interconnection of control components in inexpensive compared to multicore or coaxial cables
automotive vehicles. The complexity of the often required by other bus systems.
control functions implemented by engine management 5 Short data lengths: The short data lengths of CAN
systems, anti-lock brakes and skid controls normally messages mean that CAN has very low latency when
requires dedicated lines for the interconnection of the compared to other systems.
different control components. However, a continuous 5 Fast reaction times: The ability to transmit informa-
increase in complexity has led to a physical maximum tion without requiring a token or permission from a
not only in the quantity of wires required but also in bus arbiter results in extremely fast reaction times.
physical connector size. CAN enabled a huge reduction 5 Multi-master and peer-to-peer communication: Using
in wiring complexity and, additionally, made it possible CAN it is simple to broadcast information to all or a
to interconnect several devices using a single pair of subset of nodes on the bus and just as easy to
wires, allowing data exchange between them at the same implement peer-to-peer communication.
time. 5 Error detection and correction: The high level of error
Needless to say, it was not long before this idea detection and number of error detection mechanisms
migrated from vehicles into the machine and automation provided by the CAN hardware means that CAN is
markets. Nowadays CAN has found its way into such extremely reliable as a networking solution.
diverse areas as agricultural machinery, medical
instrumentation, elevator controls, fairground rides, CAN operating principles
public transportation systems and industrial automation CAN allows the implementation of peer-to-peer and
control components. It is because of its widespread use broadcast or multicast communication functions with
that CAN semiconductors are inexpensive. Furthermore, lean bus bandwidth use. The basic principles of CAN
since a large number of semiconductor manufacturers, communication are explained in the following sub-
such as Philips, Motorola, National Semiconductors, sections.
Siemens and Intel (to name but a few) produce CAN
devices, CAN technology is guaranteed well into the Communication modes and data exchange
future. When data is transmitted over a CAN network no
The basic features of CAN are: individual nodes are addressed. Instead, the message is
assigned an identifier that works as a unique tag on its
5 High-speed serial interface: CAN is configurable to data content. The identifier not only defines the message
operate from a few kilobits per second right up to contents but also the message priority.
1 Mbit/s transmission rates. When a node wishes to transmit information it simply

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NETWORKING SYSTEMS

bus arbitration field control data CRC ACK EOF bus

idle idle

11 bit identifier DLC 0 to 8 bytes 15 bit

RTR r0 interframe
SOF
space
IDE

Fig. 1 Format of a CAN telegram

passes the data and the identifier to its CAN controller supporting purely the standard format will be able to
and sets the relevant transmit request. It is then up to the tolerate other devices transmitting CAN frames using the
CAN controller to format the message contents and extended format (2.0B passive devices) and function
transmit the data in the form of a CAN frame. Once the correctly.
node has gained access to the bus and is transmitting A message in the standard format begins with the start
its message, all other nodes become receivers. Having bit or start of frame (SOF). This is followed by the
received the message correctly, these nodes then perform arbitration field which contains the identifier of the CAN
an acceptance test to determine if the data is relevant to telegram and is used to arbitrate access to the bus. Also
that particular device, based on the part of the arbitration field is the
identifier of the message. RTR bit (remote transmission
Therefore, it is not only possible to request) which indicates whether the
perform communication on a peer- frame is a request frame (without
to-peer basis where a single node The ability to any data, this type of message is
accepts the message but also to used to trigger a transmission by
perform broadcast and synchronised
send data on another node) or a data frame.
communication whereby multiple an event basis The control field contains the IDE
nodes can accept the same message bit (identifier extension), which
using a single transmission. means that bus indicates whether the frame is a
Furthermore, the ability to send data standard format frame or an
on an event basis means that bus load utilisation extended one, the r0 bit that is
load utilisation can be kept to a reserved for future extensions and
minimal amount.
can be kept to a four additional bits containing the
This concept has become known minimal amount length of the data field (data length
in the networking world as the code).
producer/consumer mechanism Next comes the data field which
whereby one node produces data on can be from zero to eight bytes in
the bus for other nodes to consume. length and the CRC field that
One difference with CAN over other fieldbus solutions is contains a 15-bit code that is used to check frame
that this mechanism requires no interaction from a bus integrity.
master or arbiter. The acknowledge (ACK) field comprises an ACK slot
bit and an ACK delimiter bit. The ACK slot is transmitted
Telegram format as a recessive bit (a bit with a value of 1) and receivers
Fig. 1 shows the format of a CAN telegram (standard that retrieve the message correctly (regardless of whether
format). It shows the CAN message format that uses the message is meant for the controller or not) overwrite
11-bit identifiers (2.0A format); however, an extended this field with a dominant bit (a bit with a value of 0). The
CAN format (2.0B format) also exists that uses 29-bit detection of this dominant bit by the transmitter means
identifiers instead. CAN controllers supporting the that the message was accepted by at least one node and
extended format will in general also work with the was therefore error-free (a further explanation of what
standard format communication using 11-bit identifiers are dominant and recessive bits can be found in the next
although the reverse is not always true. Some devices section).

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 NETWORKING SYSTEMS

The end of frame field (EOF) denotes that the frame wasted during the arbitration process. Ethernet (for
terminated. Finally, the intermission (Int) space repre- example) also uses CSMA/CD, but if there is a collision
sents the minimum number of bit periods that need to between two nodes, one node will transmit a jamming
elapse following the frame before another station is signal causing both nodes to abort the transmission. Both
allowed to transmit a message. If no other transmissions nodes will then wait a random period before trying to
follow the frame the bus remains in its bus idle state. retransmit.
The bus arbitration process used by CAN means that
Arbitration the node with the highest priority (lowest value in the
CAN employs the carrier sense multiple access with identifier field) will continue to transmit without any
collision detection (CSMA/CD) mechanism in order to interruption. This gives CAN very predictable behaviour
arbitrate access to the bus. It uses a priority scheme (no random waiting) and very efficient use of the bus. In
based on numerical identifiers in order to resolve fact, it is possible to have CAN networks operating at
collisions between two nodes wishing to transmit at the near 100% bus bandwidth.
same time.
On the CAN bus a ‘zero’ is called a dominant bit Acknowledgment and error checking/signalling
because it overwrites a ‘one’ (a recessive bit). Therefore, a mechanisms
node transmitting a ‘one’ whilst another transmits a ‘zero’ Unlike other bus systems CAN does not use acknow-
will result in a ‘zero’ level on the bus (the one is ledgment messages that by comparison represent a waste
overwritten). This process is shown in Fig. 2. of bandwidth on the bus. As mentioned previously, each
When two or more nodes wish to transmit, they sense receiver that receives the message correctly acknow-
the bus and if there is no bus activity, they begin to ledges the message by transmitting a dominant bit in
transmit their message identifier (most significant bit the ACK slot. This will notify the transmitter that the
first). At the same time that they transmit their message was received correctly by at least one node. All
identifiers, they also monitor the bus levels. If one nodes check all frames for errors and any node in the
node transmits a recessive bit on the bus and the other system that detects an error actively signals this to the
transmits a dominant bit the resulting bus level is transmitter. This means that CAN has network wide data
a dominant bit. Therefore, the node transmitting a security as a transmitted frame is checked for errors by
recessive bit will see a dominant bit on the bus (situation all nodes regardless of any filtering of the CAN telegrams.
where A and B lose in Fig. 2) and stop transmitting any The error-checking mechanisms implemented in CAN
further information. This allows the node with the lowest are:
number in its identifier field to gain access to the bus and
transmit its message. Any node that has lost during the 5 Bit errors: When a transmitter places a bit on the bus
arbitration process then waits until the bus becomes free it simultaneously monitors the bus to determine
before trying to retransmit its message. whether the actual bit level on the bus matches the
Note that this scheme means that no bandwidth is intended one.

resulting bus level

recessive
bus 0 1 0 0 1 1 0 1 1 0

A 0 1 0 0 1 1 1 ID=319=0100111111

B 0 1 0 0 1 1 0 1 1 1 ID=311=0100110111

C 0 1 0 0 1 1 0 1 1 0 ID=310=0100110110

A loses B loses A loses

B loses
Fig. 2 Arbitration
mechanism in
CAN showing the
bit levels as
node A node B node C transmitted by
three nodes A, B
and C and the
resulting bus bit
levels

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NETWORKING SYSTEMS

Fig. 3 CAN controller

organisation

message buffer CPU interface CPU data and

memory logic address bus

bit stream error management

processor logic

bit timing logic clock generator oscillator

transceiver control logic

output driver logic input driver logic

5 Bit stuffing errors: Bit stuffing consists in inserting transmission is aborted by transmission of an active
a bit of opposite polarity when five consecutive bits error frame from at least one node. An active error frame
of the same polarity are transmitted on the bus. The consists of six consecutive dominant bits and it prevents
stuffing bits are removed at the receiver end before the other nodes from accepting the erroneous message.
the message is processed. CAN uses bit stuffing for The active error frame violates bit stuffing and may
two purposes. The first is to provide frequent level corrupt the fixed form of the frame causing other nodes
transitions on the bus to allow receivers to re- to transmit their own active error frames. After an active
synchronise and adjust internal timing accordingly. error frame, the transmitting node begins re-trans-
The second is as an error checking mechanism mission of the erroneous frame automatically.
whereby a violation of the bit stuffing rule is deemed CAN controllers implement two transmit and receive
an error. For example, the reception of six consecutive error counters through which they keep track of the
recessive bits is a bit stuffing error. number of errors detected during transmission and
5 Cyclic redundancy check (CRC): Each CAN telegram reception of frames, respectively. These counters are
carries a 15-bit CRC code. This 15-bit CRC code is implemented in hardware and their operation is regulated
calculated by both the transmitter and the receiver. by a rather intricate set of rules. In a very simplistic view
The transmitter transmits the CRC as part of the frame of this mechanism, we can say that the counters are
and this is compared with the receiver’s own inde- incremented by ‘eight’ every time a frame is found
pendent CRC calculation. If the two calculations do not erroneous and decremented by ‘one’ every time a message
agree, an error has occurred during transmission of is transmitted or received correctly. Over a period of time,
the frame. the error count may increase even if there are fewer
5 Form errors: Incoming CAN frames are checked by the corrupted frames than uncorrupted ones.
receiver to make sure that the size in bits of individual During normal operation, the CAN controller is said to
parts of the frame are as expected, i.e. there are no be in its error-active state. In this state, the node is able to
illegal bits in a predefined field of the frame. transmit an active error frame every time a CAN frame is
5 Acknowledgment errors: As mentioned earlier, frames found to be corrupt. If one of the error counters reaches a
are acknowledged by receivers by inserting a warning limit of 96 error counts (indicating significant
dominant bit into the ACK slot of the frame. If no accumulation of errors) this is signalled by the controller
acknowledgment is detected by the transmitter, there usually using an interrupt. The controller operates in its
may be an error detected by the recipients. It could also error active mode until a limit of 127 error counts has
mean the ACK slot has been corrupted or that no been exceeded.
receivers exist on the network. Once 128 error counts have been reached, the CAN
controller enters an error-passive state. In this state, an
If an error is detected by any of the other nodes (regard- error-passive controller is still able to transmit and
less of whether the message was meant for it or not) the receive messages but signals errors by transmitting a

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 NETWORKING SYSTEMS

passive error frame. A passive error frame consists of six on the CAN bus. It monitors the bus line through a
recessive bits and this frame will only abort trans- differential input comparator. The BTL synchronises
missions performed by the node itself or in situations on a transition at the start of the frame and re-
where the node is the only receiver. Otherwise it will be synchronises on further transitions during reception of
ignored and overwritten by other CAN controllers. If the the frame. The BTL also provides programmable time
error count drops below 128 again the controller then segments to compensate for propagation delays and
becomes error-active again transmitting active error phase shifts.
frames as required. 5 The transceiver control logic (TCL) consists of bit
If the error count reaches or exceeds a limit of 256, stuffing logic, programmable output driver logic, CRC
the controller enters its bus-OFF state. In this state the logic and data shift registers. The BSP co-ordinates the
controller can no longer transmit or receive messages individual elements of the TCL. Message reception,
until it has been reset by the host processor. A node can arbitration, message transmission and error signalling
also recover from its bus-OFF state when a series of 128 are actually performed by the TCL.
frames of 11 recessive bits have been detected on the bus. 5 The message buffer memory stores individual CAN
In this case the error counters are reset to zero by the objects for transmission or reception. The CPU
controller, which then becomes error-active again. communicates only with this area in order to transmit
and receive messages. The bus interface logic manages
CAN controller organisation the bus traffic.
Fig. 3 shows how a typical CAN controller is organised 5 The clock generator is simply used to derive a suitable
at the silicon level: clock frequency for the CAN controller based on the
frequency of an external clock oscillator.
5 The CPU interface logic (CIL) executes commands
from the host processor and controls data transfers on Software register organisation
the serial bus. Global status and control registers bits Due to the popularity of CAN, there is a large variety
as well as the control bits of the communication objects of CAN controllers and integrated microcontrollers
are used primarily by the CPU interface logic. available on the market. However, they all present
5 The bit stream processor (BSP) controls the data common functionality and many of the registers are
stream between the message buffer memory (parallel programmed in a similar manner, from one controller to
data) and the bus line (serial data). It controls the entire another.
protocol, differentiates between the frame types and
detects frame errors. Message filtering
5 The error management logic receives error messages Generally two kinds of CAN controllers exist and these
from the bit stream processor and, in turn, sends back were formerly known as full CAN and basic CAN. The
information about the error state to the bit stream distinction between the two is less important nowadays,
processor and the CPU interface logic. considering most of the newer full CAN controllers also
5 The bit timing logic (BTL) determines the timing of the provide some of the functionality of basic CAN.
bits and synchronises with the edges of the bit stream In full CAN controllers, individual sections or objects

incoming message ID=401 ID=301 receive object 1

incoming message ID=500 ID match, store

ID=401 receive object 2 message in this
object

ID=402 receive object 3

notify CPU
ID=545 receive object N

no ID match with any

object, message rejected

Fig. 4 Principles of full CAN operation

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NETWORKING SYSTEMS

mask
mismatch
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
ID bits
message identifier (ID) ignored

AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 ID1 = 0 1 1 1 1 1 1 1 0 0 1 ✖

acceptance mask (AM) ID2 = 0 1 1 1 1 1 1 1 0 1 1 ✓

AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM = 0 0 0 0 0 0 1 0

acceptance code (AC) AC = 0 1 1 1 0 1 1 1

Fig. 5 Basic CAN acceptance filtering registers

of the message buffer memory (see Fig. 4) are reserved for application. Overheads may be reduced in some instances
the reception or transmission of CAN frames with preset as a basic CAN controller will normally provide a
programmable identifiers. When receiving a message, if rudimentary acceptance filtering scheme that allows the
the identifier matches the one programmed into the controller to reject a subset of the CAN identifier range.
header of the object, the data is stored in that object or In a Philips 8×592 microcontroller, and the Motorola
memory area. If the identifier does not match any of the 68HC05X family of microcontrollers, for example, the
programmed object identifiers, the message is rejected by filter consists of an acceptance mask (AM) register and an
the hardware. acceptance code (AC) register as shown in Fig. 5.
In basic CAN implementations, the controller receives Both the acceptance code and acceptance mask
all messages regardless of their identifier and puts them registers are normally eight bits in length and the
into a receive message buffer. It is then up to software filtering is usually based on the eight most significant
to accept or reject the incoming messages. Therefore, a bits of the CAN identifier. The acceptance mask register
software interrupt routine is invoked every time a CAN defines whether the corresponding bits in the acceptance
message is received, regardless of whether the CAN code register and in the CAN identifier must match to
message is intended for the application or not. This can pass the acceptance test (the acceptance mask bits set to
add a large amount of code and processing overhead to an zero if a match is required). For this reason, in Fig. 5, ID1

7 0
SJW.1 SJW.0 BRP.5 BRP.4 BRP.3 BRP.2 BRP.1 BRP.0

bus timing register 0

7 0
SAM TSEG2.2 TSEG2.1 TSEG2.0 TSEG1.3 TSEG1.2 TSEG1.1 TSEG1.0

bus timing register 1

t(one bit period)

tSYNCSEG

tSJW1 tTSEG1 tSEG2 tSJW2

sample point
1 clock cycle (tSCWL)

Fig. 6 Bus timing registers and bit periods

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 NETWORKING SYSTEMS

fails the acceptance test whilst ID2 passes. It should be Table 1 Worst case inter-frame spacing
noted that the last three bits of the identifier are not taken
baudrate inter-frame space
into consideration. Therefore if the acceptance code in the
example is set to 01110111 binary (952 decimal) and all 1000 kbit/s 47 µs
500 kbit/s 94 µs
bits in the acceptance mask are set to ‘zero’ (meaning that 250 kbit/s 188 µs
the top eight bits of the identifier must equal the eight bits 125 kbit/s 376 µs
of the acceptance code register) then a range of identifiers
from 952 to 960 will pass the filtering test by the CAN three samples is restricted to low-speed applications due
controller. The software is then required to complement to the operating speed of the CAN controller but may help
the filtering if only some of these messages are to be reduce errors in bit sampling.
accepted. The baud rate prescaler (BRP) divides the oscillator
clock to give the BTL cycle time. The BTL cycle time is
Bus timing set to twice the oscillator cycle time multiplied by BRP+1.
In most CAN controllers, two eight bit registers are Therefore, given how one bit period is made up of several
used to program the bit rate for CAN communication. smaller segments it is possible to calculate the overall bit
Additionally, it is also possible to control the bit sample time t(one bit period) in BTL cycles as:
point and the maximum amount of adjustment of bit
width that can be applied in order to resynchronise with 5 SJW1 = SJW2 = 2SJW.1+SJW.0+1 (BTL cycles)
the bit stream on the bus. Fig. 6 shows the two bus timing 5 TSEG1 = 8TSEG1.3+4TSEG1.2+2TSEG1.1+
registers and their relationship with these parameters. TSEG1.0+1 (BTL cycles)
The timing of one bit period, shown as t(one bit period), 5 TSEG2 = 4TSEG2.2+2TSEG2.1+TSEG2.0+1
comprises several bit timing logic (BTL) cycles (tSCL). (BTL cycles)
Furthermore, the bit period is divided into five segments: 5 t(one bit period) = SYNCSEG + SJW1 + TSEG1 + TSEG2
tSYNCSEG, tSJW1, tSJW2, tTSEG1 and tTSEG2. + SJW2 (BTL cycles)
During the period tSYNCSEG the incoming edge of a bit is
expected. This segment corresponds to one BTL cycle. Note that certain restrictions apply to the values placed
The synchronisation jump widths (SJW1 and SJW2) are in these parameters. This is due to restrictions in the
adjusted to compensate for phase shifts between the processing times of the various functional parts of
clock oscillators of the bus nodes. The width of SJW1 the CAN controller.
is increased to a maximum of twice the programmed
width during resynchronisation. The width of SJW2 is Software implementation
reduced or cancelled to shorten the bit time during Consideration of how the application software
resynchronisation. Thus, the overall position and width handles the hardware interface between the CAN
of the bit time are adjusted according to incoming edge controller and processor can play a major part in the
transitions. Both SJW1 and SJW2 are values set between communication process. Whether we are using basic or
one and four BTL cycles and programmed using SJW1 full CAN devices it is vitally important that messages
and SJW0 in bus timing register 0.
The position of the sample point
is defined by tTSEG1 and tTSEG2. These
are periods programmed by TSEG2
and TSEG1 in bus timing register 1.
microcontroller
For most applications, the sample microcontroller
point will be set at around 75 to 88%
external data/address bus integrated
(i.e. TSEG2 normally set to a value
CAN controller
of 1) of the total bit width. This will
standalone
allow for any distortion effects to bit CAN controller RX1 RX0
levels caused by signal propagation
RX1 RX0
and the transmission media, TX1 TX0 TX1 TX0
particularly at higher baud rates.
The bit SAM controls the number of bus driver bus driver
samples that the CAN controller CAN H
makes when determining the bit
level on the bus. If SAM= 0 then one
sample is taken. If SAM=1 then
three samples are taken and a CAN_L
simple majority rule scheme
determines the bit level. The use of Fig. 7 Variants of CAN hardware

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NETWORKING SYSTEMS

Table 2 Selection of transceiver chips one or two of the processors were configured to send 1 or
2 byte messages.
part number max speed manufacturer
Most of all, it is important that a device that does suffer
SN75LBC031D 500 kbit/s Texas Instruments from message overruns is able to detect this situation and
UC5350 1 Mbit/s Unitrode
82C250, 82C251 1 Mbit/s Philips Semiconductors notify the application using predefined error recovery
mechanisms.

Table 3 Standalone and integrated CAN Hardware implementation

semiconductors
Two basic mechanisms exist for integrating CAN
part number extended ID microcontroller manufacturer into a product. For existing products a standalone
FM2C yes 16-bit Fujitsu CAN controller can be interfaced to the same micro-
H8/300H yes 16-bit Hitachi controller using the external address and data bus. For
AN 82527 yes none Intel
AN87C196C4 yes 16-bit Intel new products a different microcontroller with integrated
68HC05X4 no 8-bit Motorola CAN interface can be used. The two are shown in Fig. 7.
M37630 E4/M4 yes 8-bit Mitsubishi
COP684BC passive 8-bit National A number of different manufacturers produce bus
Semiconductors driver or transceiver chips and a few of them are shown
µPD70F3xxx yes 32-bit NEC in Table 2.
P8X592/8 no 8-bit Philips
ST10F167 yes 16-bit SGS Thompson Table 3 shows a list of some of the integrated and
SAE81C90/91 passive none Siemens standalone CAN controllers available. This is by no
C167CR yes 16-bit Siemens
TMP88PP87 yes 8-bit Toshiba means an exhaustive list and many other variants exist.
TCG54AF yes none Toshiba Most of the manufacturers listed here produce more
than one CAN product. Note that most of these CAN
are retrieved from the CAN controller receive buffer controllers support the extended 29-bit identifier range
areas before they are overwritten by further incoming although some only support 29-bit identifiers passively,
messages. This is especially true at high network speeds, i.e. they can be used on the same network as CAN
as shown in Table 1. controllers using the extended 29-bit ID but use standard
Given this data, it is generally not possible for a 11-bit identifiers only.
processor to retrieve a message from the CAN controller
buffer and process it before the next message arrives. In Concluding remarks
some cases, the CAN hardware implements its own The popularity of CAN (11 million chips were sold to
buffering scheme whereby multiple areas of buffer the end of 1997) is due to its ease of use, to its extremely
memory in the hardware are used to store incoming high efficiency and reliability and to the low costs of CAN
telegrams. However, in most cases received messages implementations. CAN is as simple to use as a serial
must be temporarily stored by the software in memory so UART, and currently the cost of CAN controllers is
that they can be processed at a later date. If possible, still decreasing as CAN finds its way into more and
copying to a memory buffer should be done using any more applications, not only in the car and automation
on-chip facilities available for optimum data transfer industries, but also into fields such as medical
speed. For example, Philips 80C592 microcontroller on- instrumentation and domestic appliances.
chip DMA facilities allow transfer of a CAN message
from its CAN controller to internal data memory in a References
period of two instruction cycles. 1 ‘CAN specification 2.0’, Parts A and B, Robert Bosch, September 1991
2 MACLAUGHLIN, R.: ‘Introduction to CAN’, CANopen Workshop,
An important consideration is the fact that when Savoy Place, London, October 1997
assessing the capability of the software avoiding 2 MONK, F.: ‘Producer/consumer the new network paradigm’,
message overruns, the number of back-to-back messages Fieldcomms UK ’97 Conference, Hanover International Hotel,
Leicestershire, October 1997
is not the only important factor. The length of each CAN 4 ‘CAN—a serial bus system not just for vehicles’, CAN in Automation
message also plays a vital role. If all the messages in the Organisation (CiA)
5 ‘P8×592 8-bit microcontroller with on-chip CAN’, datasheet, Philips
‘burst’ are of 8 bytes in length the processor has more Semiconductors, June 1996
time before having to deal with the next message in its 6 ‘8×196 microcontroller family’, datasheet, Intel, June 1995
receive buffer. If the burst contains messages of just a few 7 ‘MC68HC05X4, MC68HC705X4 Technical Data’, datasheet, Motorola,
1996
bytes in length, a particular processor cannot deal with 8 ‘SAE81C90/91 standalone full CAN controller’, datasheet, Siemens,
them in time. In other words, it is not only the number of January 1997
messages in the burst but also the length of each message 9 ‘CAN communication model and its implications’, Holger Zeltwanger
(CiA), CAN Solutions Directory, 1997, Miller Freeman
that counts. This was found out by the authors at an early
stage when, after having built an automation cell where © IEE: 1999
the master (based around a Basic CAN controller) could The authors are with the Department of Electrical and Elec-
quite happily cope with the other microcontrollers on the tronic Engineering, Merz Court, The University of Newcastle,
network sending 8 byte messages, it could not cope when Newcastle upon Tyne NE1 7RU, UK.

120 COMPUTING & CONTROL ENGINEERING JOURNAL JUNE 1999