PLC CL550

PCL and CL550
Programming and Operation

Software Manual
108
Edition
PCL and CL550
Programming and Operation

Software Manual
1070 072 189 - 108 (02.09) GB
 1999 - 2002
Copyright by Robert Bosch GmbH, Erbach / Germany. All rights

reserved, including applications for protective rights.
Reproduction or distribution by any means subject to our prior written
permission.
Discretionary charge 12.00 Euro

Contents I
Table of Contents
1. Safety Instructions..................................................................................................................................1-1
1.1 Standard Operation................................................................................................................................1-1
1.2 Qualified Personnel................................................................................................................................1-2
1.3 Safety Markings on Components ...........................................................................................................1-3
1.4 Safety Instructions in this Manual ..........................................................................................................1-4
1.5 Safety Instructions for the Described Product........................................................................................1-5
1.6 Documentation, Software Release & Trademarks.................................................................................1-7
2. PCL System Features ............................................................................................................................2-1

2.1 Hardware and System Configuration .....................................................................................................2-2
2.2 Hardware Expansion Levels ..................................................................................................................2-2
2.2.1 Real-time guarantee .......................................................................................................................2-2
2.2.2 Interaction between Windows and PCL..........................................................................................2-3
2.2.3 Required PC resources...................................................................................................................2-3
2.2.4 Supplementary hardware (PCI-BMxx Card) ...................................................................................2-4
2.2.5 System clock management.............................................................................................................2-4
2.2.6 Simulation .......................................................................................................................................2-4
2.3 Operating and Displaying.......................................................................................................................2-5
2.3.1 WinPanel.........................................................................................................................................2-5
2.3.2 WinPanel start parameters .............................................................................................................2-6
2.3.3 Status and error messages.............................................................................................................2-8
2.3.4 External control elements ...............................................................................................................2-9
2.4 Control unit startup...............................................................................................................................2-10
2.4.1 Initializing the PCL ........................................................................................................................2-11
2.4.2 Startup...........................................................................................................................................2-12
2.5 PCL Remanence Characteristics & Data Backup................................................................................2-15
2.5.1 Remanence – Normal shutdown .................................................................................................2-15
2.5.2 Remanence – Using Bosch PC Control Panels w/ built-in UPS..................................................2-15
2.5.3 Remanence – Power failure or Power-OFF w/o shutdown .........................................................2-16
2.5.3.1 Cyclical backup of remanent areas .......................................................................................... 2-17
2.5.3.2 Backing up remanent areas on request ................................................................................... 2-17
2.5.3.3 Processing times ...................................................................................................................... 2-18
2.5.3.4 Defining remanence areas in the OM2 .................................................................................... 2-19
2.5.4 Remanence characteristics & hardware used ..............................................................................2-20
2.5.5 Remanent operation .....................................................................................................................2-21
2.5.6 Nonremanent operation ................................................................................................................2-22
2.5.7 Buffer failure, data backup error, RAM test ..................................................................................2-23
2.5.8 Startup characteristics ..................................................................................................................2-24
3. CL550 System Features ........................................................................................................................3-1

3.1 Hardware and System Configuration .....................................................................................................3-2
3.1.1 Control section ................................................................................................................................3-2
3.1.2 Memory ...........................................................................................................................................3-2
3.1.3 Communication interfaces ..............................................................................................................3-2
3.1.4 Peripheral Operation.......................................................................................................................3-3
3.1.5 System clock management.............................................................................................................3-3
3.1.6 Simulation .......................................................................................................................................3-3
3.2 The ZS550 in the CL550 System ...........................................................................................................3-3
3.3 Operating and Displaying.......................................................................................................................3-4
3.3.1 Display and control elements..........................................................................................................3-5
3.3.1.1 Control elements / Displaying PLC control unit functions .......................................................... 3-6
3.3.1.2 Displaying DP bus master functions .......................................................................................... 3-8
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II Contents
3.3.1.3 Displaying TCP/IP COM functions ............................................................................................. 3-9

3.3.1.4 Displaying DP/V1 COM functions ............................................................................................ 3-10
3.3.1.5 Power supply functions ............................................................................................................ 3-11
3.3.1.6 Displaying InterBus-S functionality (ZS550-DP-IBS only)........................................................ 3-12
3.3.2 Function mode & Configuration mode ..........................................................................................3-13
3.4 CL550 Startup ......................................................................................................................................3-16
3.4.1 System start ..................................................................................................................................3-16
3.4.2 Control section startup ..................................................................................................................3-16
3.4.2.1 Startup preparations in Startup-STOP ..................................................................................... 3-16
3.4.2.2 Startup preparations in Module-STOP ..................................................................................... 3-19
3.4.2.3 Control unit startup ................................................................................................................... 3-19
3.5 Remanence Characteristics & Data Backup........................................................................................3-21
3.5.1 Remanence with use of NT4 power supply ..................................................................................3-21
3.5.2 Remanence with use of NT1, NT2, NT3, and NT24 power supplies............................................3-22
3.5.2.1 Cyclical backup of remanent areas .......................................................................................... 3-22
3.5.2.2 Backing up remanent areas on request ................................................................................... 3-22
3.5.2.3 Processing times ...................................................................................................................... 3-23
3.5.2.4 Defining remanence areas in the OM2 .................................................................................... 3-24
3.5.3 Remanent operation .....................................................................................................................3-25
3.5.4 Nonremanent operation ................................................................................................................3-26
3.5.5 Buffer failure, data backup error, RAM test ..................................................................................3-27
3.5.6 Startup characteristics ..................................................................................................................3-28
4. Peripheral Operation ..............................................................................................................................4-1

4.1 Data consistency....................................................................................................................................4-1
4.2 PROFIBUS-DP.......................................................................................................................................4-2
4.3 CAN Bus (CANopen, PCL only).............................................................................................................4-3
4.4 INTERBUS-S..........................................................................................................................................4-4
4.5 Response Intervals ................................................................................................................................4-6
5. Programming Basics ..............................................................................................................................5-1

5.1 Programming..........................................................................................................................................5-1
5.2 Programming Languages and Representations ....................................................................................5-1
5.3 Program Structure ..................................................................................................................................5-2
5.4 Module Types.........................................................................................................................................5-2
5.4.1 Organization modules (OM)............................................................................................................5-2
5.5 Program modules ...................................................................................................................................5-3
5.5.1 Data modules..................................................................................................................................5-3
5.6 Program Processing...............................................................................................................................5-4
5.6.1 Cyclical program processing...........................................................................................................5-4
5.6.2 Error interrupt controlled processing...............................................................................................5-4
5.6.3 Time Controlled Interrupts ..............................................................................................................5-4
5.7 Time Monitoring .....................................................................................................................................5-5
5.8 I/O state..................................................................................................................................................5-6
5.8.1 Image updating for peripheral operation.........................................................................................5-6
5.8.2 Fixing inputs, outputs & markers ....................................................................................................5-6
5.8.3 Updating timers...............................................................................................................................5-7
5.8.4 Cyclical processing .........................................................................................................................5-8
5.8.5 Application program structure .........................................................................................................5-8
5.9 OM2 Initialization Table for PCL and CL550..........................................................................................5-9
5.9.1 Printout of OM2PCL initialization table .........................................................................................5-10
5.9.2 Printout of OM2CL550 ..................................................................................................................5-15
5.10 Module Reference List .........................................................................................................................5-20
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Contents III
5.10.1 Module attendance .......................................................................................................................5-20

5.10.2 Module size ...................................................................................................................................5-20
5.10.3 Module start address ....................................................................................................................5-21
5.11 Module Header.....................................................................................................................................5-22
5.12 OM8 Shutdown module (PCL only) .....................................................................................................5-23
5.13 OM9 Error Module................................................................................................................................5-24
5.14 Fixation.................................................................................................................................................5-25
5.15 Parameterized Modules .......................................................................................................................5-26
5.16 Time Controlled Interrupts....................................................................................................................5-27
5.17 Application Stack..................................................................................................................................5-28
6. Addressing Conventions ........................................................................................................................6-1

6.1 Operand & Module Identifiers, Module List............................................................................................6-1
6.2 Assignments in Special Marker Area .....................................................................................................6-2
6.3 System Area Assignment.......................................................................................................................6-4
6.4 Periphery Status.....................................................................................................................................6-6
6.5 Data Formats..........................................................................................................................................6-8
6.6 Register Structure ................................................................................................................................6-11
6.7 Representing Constants.......................................................................................................................6-12
6.8 Program Module Calls..........................................................................................................................6-12
6.9 Jump Instructions .................................................................................................................................6-12
6.10 Bit & Module Addresses.......................................................................................................................6-13
6.11 Byte, Word & Double Word Addresses................................................................................................6-13
6.12 Addressing Modes ...............................................................................................................................6-14
6.12.1 Absolute addressing operands .....................................................................................................6-14
6.12.2 Direct addressing of all absolute addressable operands..............................................................6-14
6.12.3 Register-to-register addressing ....................................................................................................6-14
6.12.4 Register indirect addressing .........................................................................................................6-15
6.12.5 Indirect addressing........................................................................................................................6-15
6.13 Parameter Transfer ..............................................................................................................................6-17
6.14 Addressing Limits .................................................................................................................................6-18
7. Instruction List ........................................................................................................................................7-1

7.1 Structure of Controller Instructions.........................................................................................................7-1
7.2 Flags.......................................................................................................................................................7-1
7.3 Key to Abbreviations ..............................................................................................................................7-2
7.4 Bit instructions ........................................................................................................................................7-3
7.5 Timer Programming ...............................................................................................................................7-4
7.5.1 Timer instructions............................................................................................................................7-5
7.5.2 Time format .....................................................................................................................................7-6
7.5.3 Timer diagrams ...............................................................................................................................7-7
7.6 Counter Instructions ...............................................................................................................................7-8
7.7 Digital Links ............................................................................................................................................7-9
7.8 SWAP Instructions .................................................................................................................................7-9
7.9 COMPARE Instruction .........................................................................................................................7-10
7.10 LOAD Instructions ................................................................................................................................7-12
7.11 TRANSFER Instructions ......................................................................................................................7-13
7.12 CONVERT Instructions ........................................................................................................................7-14
7.13 INCREMENT & DECREMENT Instructions .........................................................................................7-15
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IV Contents
7.14 STACK Instructions..............................................................................................................................7-15

7.15 No Operation Instructions & CARRY Manipulations ............................................................................7-15
7.16 SHIFT Instructions ...............................................................................................................................7-16
7.17 ROTATE Instructions ...........................................................................................................................7-17
7.18 Fixed Point Arithmetic ..........................................................................................................................7-18
7.18.1 ADD instructions ...........................................................................................................................7-18
7.18.2 SUBTRACT instructions ...............................................................................................................7-19
7.18.3 MULTIPLY instructions .................................................................................................................7-20
7.18.4 IVIDE instructions .........................................................................................................................7-21
7.19 Floating Point Arithmetic ......................................................................................................................7-22
7.19.1 LOAD floating point value .............................................................................................................7-24
7.19.2 TRANSFER floating point value ...................................................................................................7-24
7.19.3 CONVERT number formats ..........................................................................................................7-24
7.19.4 CONVERT data formats ...............................................................................................................7-25
7.19.5 Removing decimal positions .........................................................................................................7-25
7.19.6 COMPARE floating point values ...................................................................................................7-26
7.19.7 Calculating with floating point values............................................................................................7-27
7.19.8 Forming absolute value.................................................................................................................7-27
7.19.9 Extracting square root...................................................................................................................7-28
7.19.10 Exponentiation...........................................................................................................................7-28
7.19.11 Logarithmic functions ................................................................................................................7-29
7.19.12 Trigonometric functions .............................................................................................................7-29
7.20 Parameter Assignments.......................................................................................................................7-30
7.21 Local Symbol Names & Auxiliary Markers for Program Tracking ........................................................7-30
7.22 System Variable ...................................................................................................................................7-30
7.23 Jump Instructions .................................................................................................................................7-31
7.24 Module Calls.........................................................................................................................................7-33
7.25 End of Module Instruction ....................................................................................................................7-35
7.26 FIFO Instructions..................................................................................................................................7-36
7.27 Block Commands .................................................................................................................................7-37
7.28 Interrupt Instructions ............................................................................................................................7-40
7.29 Program Stop & Program End .............................................................................................................7-40
7.30 Backing Up & Loading Remanence Areas...........................................................................................7-40
8. Processing Times...................................................................................................................................8-1
8.1 PCL Processing Intervals.......................................................................................................................8-1
8.2 CL550 Processing Intervals ...................................................................................................................8-6
9. Sample Programs ..................................................................................................................................9-1

9.1 Indirect Addressing ................................................................................................................................9-1
9.2 COMPARE Instruction ...........................................................................................................................9-2
9.3 FIFO Instructions....................................................................................................................................9-3
9.4 Bit-indirect Writing to Inputs ...................................................................................................................9-4
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Safety Instructions 1-1
1. Safety Instructions
Before you start working with the Bosch PCL Software PCL or the CL550
Hardware PLC, we recommend that you thoroughly familiarize yourself
with the contents of this manual. Keep this manual in a place where it is
always accessible to all users.
1.1 Standard Operation
This instruction manual presents a comprehensive set of instructions and

information required for the standard operation of the described products.
The products described hereunder

• Were developed, manufactured, tested and documented in
accordance with the relevant safety standards. In standard operation,
and provided that the specifications and safety instructions relating to
the project phase, installation and correct operation of the product are
followed, there should arise no risk of danger to personnel or property.
• Are certified to be in full compliance with the requirements of the
• COUNCIL DIRECTIVE 89/336/EEC of May 3rd 1989 on the
approximation of the laws of the Member States relating to
electromagnetic compatibility, 93/68/EEC (amendments of
Directives), and 93/44/EEC (relating to machinery)
• COUNCIL DIRECTIVE 73/23/EEC (electrical equipment designed
for use within certain voltage limits)
• Harmonized standards EN 50081–2 and EN 50082–2
• Are designed for operation in an industrial environment (Class A
emissions). The following restrictions apply:
• No direct connection to the public low-voltage power supply is
permitted.
• Connection to the medium and/or high-voltage system must be
provided via transformer.
The following applies for application within a personal residence, in
business areas, on retail premises or in a small-industry setting:
• Installation in a control cabinet or housing with high shield
attenuation.
• Cables that exit the screened area must be provided with filtering
or screening measures.
• The user will be required to obtain a single operating license
issued by the appropriate national authority or approval body. In
Germany, this is the Federal Institute for Posts and
Telecommunications, and/or its local branch offices.
⇒ This is a Class A device. In a residential area, this device may cause

radio interference. In such case, the user may be required to
introduce suitable countermeasures, and to bear the cost of the
same.
Proper transport, handling and storage, placement and installation of the

product are indispensable prerequisites for its subsequent flawless
service and safe operation.
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1-2 Safety Instructions
1.2 Qualified Personnel
This instruction manual is designed for specially trained personnel. The

relevant requirements are based on the job specifications as outlined by
the ZVEI and VDMA professional associations in Germany. Please refer
to the following German–Language publication:
Weiterbildung in der Automatisierungstechnik

Publishers: ZVEI and VDMA Maschinenbau Verlag
Postfach 71 08 64
60498 Frankfurt/Germany
This instruction manual is specifically designed for professional personnel

familiar with all aspects of programmable logic controllers (PLC). They
require special knowledge and skills with regard to the Microsoft
Windows95 and WindowsNT 4.0 operating systems.
Interventions in the hardware and software of our products not described

in this instruction manual may only be performed by our skilled personnel.
Unqualified interventions in the hardware or software or non-compliance

with the warnings listed in this instruction manual or indicated on the
product may result in serious personal injury or damage to property.
Installation and maintenance of the products described hereunder is the

exclusive domain of trained electricians as per VDE 1000-10 who are
familiar with the contents of this manual.
Trained electricians are persons of whom the following is true:

• They are capable, due to their professional training, skills and
expertise, and based upon their knowledge of and familiarity with
applicable technical standards, of assessing the work to be carried
out, and of recognizing possible dangers.
• They possess, subsequent to several years' experience in a
comparable field of endeavour, a level of knowledge and skills that
may be deemed commensurate with that attainable in the course of a
formal professional education.
With regard to the foregoing, please read the information about our
comprehensive training program. The professional staff at our training
centre will be pleased to provide detailed information. You may contact
the centre by telephone at (+49) 6062 78–258.
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1.3 Safety Markings on Components
DANGER! High voltage!
DANGER! Corrosive battery acid!
CAUTION! Electrostatically sensitive devices (ESD)!
Disconnect mains power before opening!
Lug for connecting PE conductor only!
Functional earthing or low-noise earth only!
Screened conductor only!
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1.4 Safety Instructions in this Manual
DANGEROUS ELECTRICAL VOLTAGE

This symbol warns of the presence of a dangerous electrical
voltage. Insufficient or lacking compliance with this warning can
result in personal injury.
DANGER
This symbol is used wherever insufficient or lacking observance of
this instruction can result in personal injury.
CAUTION
This symbol is used wherever insufficient or lacking observance of
instructions can result in damage to equipment or data files.
⇒ This symbol is used to alert the user to an item of special interest.
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1.5 Safety Instructions for the Described Product
DANGER
Fatal injury hazard through ineffective Emergency-STOP devices!
Emergency-OFF safety devices must remain effective and
accessible during all operating modes of the system. The release
of functional locks imposed by Emergency-STOP devices must
never be allowed to cause an uncontrolled system restart! Before
restoring power to the system, test the Emergency-STOP
sequence!
DANGER
Danger to persons and equipment!
Test every new program before operating the system!
DANGER
Retrofits or modifications may interfere with the safety of the
products described hereunder!
The consequences may be severe personal injury or damage to

equipment or the environment. Therefore, any system retrofitting
or modification utilizing equipment components from other
manufacturers will require express approval by Bosch.
DANGEROUS ELECTRICAL VOLTAGE

Unless described otherwise, maintenance procedures must always
be carried out only while the system is isolated from the power
supply. During this process, the system must be blocked to
prevent an unauthorized or inadvertent restart.
If measuring or testing procedures must be carried out on the

active system, these must be carried out by trained electricians.
CAUTION
Danger to the module! Do not insert or remove the module while
the controller is switched ON! This may destroy the module.
Switch off or disconnect controller power supply module, external
power supply and signal voltage. Only then will it be safe to insert
or remove the module!
CAUTION
Only Bosch-approved spare parts may be used!
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CAUTION
All ESD protection measures must be observed when handling
modules and construction elements! Prevent electrostatic
discharges!
Observe the following protective measures for electrostatically sensitive

devices (ESD)!
• The personnel responsible for storage, transport and handling must be
trained in ESD protection.
• ESDs must be stored and transported in the designated protective
packaging.
• Out of principle, ESDs may be handled only at special ESD work
stations equipped for this particular purpose.
• Personnel, work surfaces and all devices and tools that may come into
contact with ESDs must be on the same potential (e.g., earthed).
• An approved earthing wrist strap must be worn. It must be connected
to the work surface via a cable with integrated 1 MΩ resistor.
• ESDs may under no circumstances come into contact with objects
susceptible to accumulating an electrostatic charge. Most items made
of plastic belong to this category.
• When installing ESDs in or removing them from an electronic device,
the power supply of the device must be switched OFF.
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1.6 Documentation, Software Release & Trademarks
Documentation
The present instruction manual provides the user with comprehensive
information about programming and operation of the
! Bosch PCL Software PLC
! Bosch CL550 Hardware PLC
However, commonly accepted procedures for project planning and
installation of controllers and related hardware have been excluded from
the following manuals:
Manuals Language Order no.
PCL, Introduction to the Software PLC, English 1070 072 431

System Description
CL550 Configuration and English 1070 072 262

Commissioning, Software Manual
CL550 Controller Manual English 1070 072 263
⇒ Throughout this manual, the floppy disk drive and hard disk are
always designated drive A: and drive C:, respectively.
Version
⇒ The information in this manual applies to the following versions:
Software WinPanel 2.x
PLC Utility Program 3.x
Trademarks
All trademarks of software installed on Bosch products when shipped
from the factory represent the property of their respective owners. At the
time of shipment from the factory, all installed software is protected by
copyright. Software may therefore be duplicated only with the prior
permission of the respective manufacturer or copyright owner.
MS-DOS and Windows are registered trademarks of Microsoft

Corporation.
PROFIBUS is a registered trademark of PROFIBUS Nutzerorganisation

e.V. (PROFIBUS user organization, an association registered in
Germany).
INTERBUS-S is a registered trademark of Phoenix Contact.
DeviceNet is a registered trademark of ODVA (Open DeviceNet Vendor

Association, Inc.).
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PCL System Features 2-1
2. PCL System Features

Manufacturing plants and machine control systems quite frequently
employ PC technology as a "human interface" for operating and
monitoring activities. Because this fact in itself indicates the presence of
powerful hardware, it makes good sense to utilize these devices for the
purpose of handling control-specific tasks. In addition, PC hardware is
subject to very brief innovation cycles, resulting in continuous
performance increases while the level of hardware costs remains virtually
unchanged.
The programmable logic controller (PLC) software bearing the short-form

description of "PCL" augments the Bosch PLC product family; it thus
provides a high degree of software compatibility with existing hardware
control systems.
The "PCL" product name comprises a combination of the two computer

components, that is:
P C Personal Computer, and
C L Control Logics
An essential characteristic of the PCL is its stable functionality, which is
ensured independently of the Microsoft Windows environment.
As is the case with all Bosch PLC systems, control software programs
are created and placed into operation with the use of the Windows-based
WinSPS programming system. In this context, a significant extension of
features is provided by the option to utilize the "C" high-level language.
The implementation avails itself exclusively of peripherals (inputs and

outputs) consisting of field bus systems, e.g., PROFIBUS-DP. The
interface connection uses a PCI bus card belonging to the PCL.
Communications with the Bosch WinSPS and WinDP programming tools

and other applications are handled by the TCP/IP standard protocol, and
with the use of the BÜP (Bosch transfer protocol) command language.
The present documentation is designed to support the PCL user with his
programming tasks and with the system startup of the controller. It
discusses the following subjects:
• Hardware & System Configuration
• Operating & Displaying
• Interfacing with Peripherals
• Programming Basics
• Addressing Conventions
• Command Set Description
• Programming Samples
⇒ For additional essentials related to the PCL and to operating

decentralized peripherals via the PROFIBUS-DP, refer to the Online
Help of the WinSPS and WinDP programming device software.
Helpful topics in the WinSPS or WinDP appear under the headings:

• Help
• Contents
• PCL – The PC-based controller
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2-2 PCL System Features
2.1 Hardware and System Configuration

The PCL comprises a software solution that is implemented on a
standard PC with the VxWorks real-time operating system running on the
MS-Windows95 or WindowsNT 4.0 platform. Both application program
and user data are held in the dynamic RAM onboard the PC, and are
backed up to the hard disk. The peripherals are interfaced with a field
bus, and communications with other components are handled via the
standard TCP/IP protocol.
2.2 Hardware Expansion Levels

The size of the I/O range and of the PLC program memory is determined
by the type of license obtained for the PCL.
Type Periphery User memory

PCL-S I/O = 16 bytes ea. 105 k words = approx 16 k instructions
PCL-L I/O = 256 bytes ea. 393 k words = approx 64 k instructions
PCL-X I/O = 8 kbytes ea. 777 k words = approx 128 k instructions
In calculating the user memory requirement, a length of 6 words was

assumed for each instruction.
⇒ Because the data field and data buffer are included in every
hardware expansion level, they do not reduce the size of the user
memory! Just like the program and organization modules, the data
modules are stored in the PLC user memory.
2.2.1 Real-time guarantee

To be able to ensure real-time operation under the Windows operating
system, the PCL utilizes a supplementary hardware module that
interrupts Windows each time real-time operation is required within the
system. The essential advantage of this solution is the absolute
independence of possible modifications to the operating system.
The combination of Windows95 / WindowsNT 4.0 with the VxWorks real-

time operating system, plus the PC bus card as supplementary hardware,
(refer to section 2.2.4) provide the prerequisites for the reliable real-time
capability of the Bosch PCL Software PLC.
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2.2.2 Interaction between Windows and PCL

On a PC, and on the BT150/155 and BT200/205 PC-based Control
Terminals in particular, the combination of PCL and Windows95 /
WindowsNT forms a cohesive unit. The PCL is loaded during the
Windows startup phase. At the same time, Autostart loads and starts the
WinPanel Windows-based software.
Because the PCL is incapable of directly accessing the hard disk,

WinPanel assumes, besides operating and display functions, also the
tasks related to data storage and consistency
The following events are relevant to the data flow between WinPanel
(hard disk) and PCL (dynamic RAM):
• Startup Loading application program and data
• Post-loading Adding PCL modules
• Shutdown Saving user/application data
⇒ As operating systems, Windows95 and WindowsNT provide their

own functions for memory resource management and hard disk
handling. This means that a sudden power failure will result in fault
occurrences. Although these faults will be recognized at the time
the operating system is restarted, they will normally result in data
inconsistencies caused by lost clusters on the hard disk. This will
necessitate a correction via the Scandisk utility.
For the PCL Software PLC, this would inevitably result in the loss of
remanent data. This emergency situation will be prevented by a
function that is currently under development, which will be utilizing
the static memory onboard the supplementary hardware for the
storage of remanent data. A sudden power failure will then no
longer cause the loss of remanent data. The manner and extent of
defining this memory area for backup purposes are left to the
individual user.
For the BT150/155 and BT200/205 PC-based Control Terminals, an

integrated buffer with a defined shutdown ensures a controlled
system shutdown.
2.2.3 Required PC resources

The PCL should be operated on a PC featuring a 200 MHz Intel Pentium
CPU, and a minimum of 32 MB RAM. In the event that the MMI-MADAP
or the MADAP Studio software packet is simultaneously run on this PC, a
minimum of 64 MB RAM will be required.
The real-time operating system in combination with Windows95 /

WindowsNT, plus the PCI bus card (PCI-BM-xx: xx = DP, CAN, IBS)
provide the prerequisite for reliable real-time capability.
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2.2.4 Supplementary hardware (PCI-BMxx Card)

A special PCI bus card is available to ensure real-time characteristics, to
save the remanent controller data, and to serve as the interface for
peripherals. It is the prerequisite for PCL operation.
Major features of this supplementary hardware:

• Guaranteed real-time characteristics
• Field bus interface for peripherals
• Hardware watchdog, approx. 2.5 s
• 128 kbytes of buffered static RAM
• Connection for external operating controls
The adaptation to the various field buses comprises a basic component

of the PCL because some of the features (e.g., fixation) may be optimally
executed only in direct interaction with the hardware.
The supplementary hardware, referred to as “PCI-BMXxx card”

throughout this document, is available with the following field bus
interfaces:
• PCI-BM-DP PROFIBUS-DP Master
• PCI-BM-CAN CANopen
• PCI-BM-IBS INTERBUS-S
2.2.5 System clock management

The system timing, which can be processed in the PLC program via the
system area, is generated by the clock source onboard the PC. The clock
is set through a command by the WinSPS editor, and cannot be
influenced via the PLC program.
2.2.6 Simulation
A function which is integrated in WinSPS version 3.2 and WinPanel
version 2.32 and higher allows you to simulate a PCL. This simulation
can be started via a switch on the WinPanel (cf. chapter 2.3.2).
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2.3 Operating and Displaying
2.3.1 WinPanel
“WinPanel” is the designation for the supplementary module required for
operating and displaying PCL functions and statuses which are shown in
plain text. In addition, WinPanel serves to define the Windows calculation
time and the number of real-time accesses.
WinPanel is operated similar to a standard Windows application.
Functionality and operation are described in the WinPanel Online Help.
The WinPanel operator interface uses two windows to indicate the

statuses of the PCL and information about the current project.
Program loading
Back Up Program
Shut Down
Outputs disabled
Run/Stop
Fixation On/Off
Program Information
Online Help Communications

Windows
Connection Status VxWorks (PLC)
Rho4-PLC
Rho4-SPSInterface
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2.3.2 WinPanel start parameters

When starting the PCL by virtue of launching WinPanel, switches can be
used to predefine a variety of properties and controller responses.
⇒ Please note that several communication functions require a valid

user license.
The switches are entered in the "Destination" text box in the WinPanel
Properties window.
Major switches Effect

/H Considers hardware protection device (dongle) during license verification.
/h Disregards hardware protection device (dongle) during license verification.
This switch is used when, at the time of startup, the license for the WinSPS is stored
in a hardlock, and the PCL is software-licensed, for example.
/Knn Selects the means of communication with the PCL.
To handle communications between WinSPS and PCL, a number of channels are
available. Each channel occupies a specific bit significance. The sum of bit
significances is transferred by the switch in the form of a decimal value (nn) in the
switch. When selecting serial communications via COM port, the interface parameters
are predefined as follows: 19.2 kBaud, 1 start bit, 2 stop bits, even parity. However, it
is possible to specify another transmission speed.
Explanation Bit significance

MMF 1 Not to be used with centralized programming.
UDP1 2
UDP2 4
COMx 16
Examples:
MMF only " /K1
MMF + UDP1 " /K3
UDP1 + V24 " /K18COM2-57600 ( COM2, 57.6 kBaud)
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Major switches Effect

/M No dialog boxes to be opened, no user input to be requested.
Important for remanent operation:
Immediate termination of WinPanel without prior security query while saving all data.
/OPC Enables OPC server.
/P Enables passport protection.
WinPanel / PCL rejects write access w/o prior "LogIn".
With these switches specified, the controller checks for each write access whether the
client is logged in. If the controller password was not changed, the PG will use the
default password "BoschPlcSystems" to log in.
/Rnn Enables computer interface function via Ethernet.
Optional value nn states the processing intervals in ms.
/Vnnnn VxWorks to be launched with reserved memory.
Value nnnn indicates memory capacity reserved under Windows.
/V8192: Reserves 8 MB for the PCL. If a value less than 8192 is specified, the
controller internally uses 8192. A larger value increases the reserved memory
capacity.
WinPanel version 2.32 and higher allows you to call the simulator for the PCL and the
CL550 by using this switch: /VSIMU
/Ynn This switch controls various PCL functions. The functions are bit-encoded, and can be
randomly combined. The sum of bit significances is transferred by the switch as a
decimal value (nn).
Explanation Bit significance

Hardware switch enabled 1
INTERBUS-S I/O = byte consistent 4
INTERBUS-S reset w/o physical 32
addressing (CMD software)
Trace information enabled 64
Examples:
/Y1 " Hardware switch enabled
/Y68 " Trace information output to Telnet
port (Y64), and run INTERBUS-S I/O
inconsistently (Y4).
/Znn Fixed cycle time (nn = time in ms)
This switch is used to declare a fixed cycle time for the PCL.
Switches NOT TO Effect

BE CHANGED by
user in normal
operation
/D All instances of write/read hard disk access are logged and stored in the FileIO.txt or
FileIO1.txt protocol files (WinPanel directory).
Because setting this switch burdens system resources in normal operation, it
shall be used only subject to prior consultation and only for the purpose of
troubleshooting support. With the /D switch set, no error messages are output
to the display.
/X All commands sent and received are logged and stored in the RecvUdp.Txt and/or
SendUdp.Txt logfiles (WinPanel directory).
Because setting this switch burdens system resources in normal operation, it
shall be used only subject to prior consultation and only for the purpose of
troubleshooting support.
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2.3.3 Status and error messages

The WinPanel software module is capable of returning PCL statuses in
the form of plain-text messages.
PLC Status Cause Explanation

RUN PLC in RUN status
STOP PCL startup cycle PLC is still in startup cycle
No PLC program available NOTE: This Stop cause takes display precedence over all others
Hardware switch Stop via hardware switch on interface of Bosch module
Command Stop via supplementary device (e.g., WinDP supplementary program)
WinPanel Stop via WinPanel
Faults in system software Non-retriggerable faults in system (e.g., hardware watchdog, page
fault, etc.)
Other application-dependent Stop causes
Cycle time overrun in program
Hardware cycle timeout
Opcode error (possibly caused by incompatible software versions)
Incompatible operator and parameter operand
Program module not available
Interrupt OM not available
DM is too small
No DM is activated
Data module not available
HALT instruction
Division by 0
Parameter in startup module not available
Illegal enter point for indirect jump
Illegal operand number
Module stack overflow
Application stack overflow
Application stack underflow
C-module stack overflow
C-code reentrant error
Illegal size specification (e.g., with FIFO command)
Not unambiguously identifiable error in application program
No valid fixation list available
Unable to allocate dynamic DM
Standard FUN parameter error
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2.3.4 External control elements

Operating the PCL via WinPanel without monitor and keyboard is not
practical because it does not facilitate the visualization of responses and
displays. For this reason, an X72 interface was integrated in the PCI-
BMxx card; the interface provides certain basic PCL functions even in the
absence of keyboard and monitor.
X72 – Pin Assignments and Signal Functions

Inputs Outputs Signal Terminal
name
RUN: contacts closed READY1 1
STOP: contacts open READY2 2
RUN: contacts closed READY3 3

STOP: contacts open READY4 4
NC 5
Run at "0" / Stop at "1" RUN_STOP 6
Outputs disabled A_SPERR 7
Ground for input signals EXT_GND 8
External battery to back up static VBAT_GND 9

RAM, refer to 10
Section. 2.5 Remanence
Characteristics & Data Backup
Field bus
connector
Input characteristics of RUN_STOP and A_SPERR signals

Input characteristic Type1, as per EN 61131-2
Input voltage Nominal value when 0: -3 V thru 5 V
when 1: 11 V thru 30 V
Input current Nominal value when 0: ≤ ≤ 2.5 mA
when 1: 3 mA ≤ I ≤ 6
mA
Input delay typ. 4 ms
0 → 1 and 1 → 0
Input signals are opto-isolated
When using Windows without its own display terminal, the operating
system may pause while waiting for user input. Windows requests this
type of input after an uncontrolled shutdown, for example. If this is the
case, connecting a keyboard and monitor will be mandatory.
⇒ Shutdown
The Bosch PC-based Control Terminals feature an integrated buffer
with defined shutdown which ensures a controlled shutdown of all
Windows applications. This means that the control terminal can still
be switched off once the PLC has been halted via STOP on the PCI-
BMxx card.
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2.4 Control unit startup

The descriptions of individual function blocks follow the startup sequence
depicted in the flow chart below.
Initialization
PCL startup
yes
Startup
STOP?
no
Startup
characteristics
Cyclical
program
processing
I/O state
no
Processing
STOP?
yes
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2.4.1 Initializing the PCL
Initializing special markers

The special markers SM21.0 through SM31.7 (refer to descriptions of
exceptions) are preinitialized during new start and restart. They are
subsequently modified in accordance with their function.
Initialization values
SM26 = FFFFH
SM31.1 = 1
All others = 0
Exceptions
SM20.0 Trigger pulse upon each startup and restart; is set HIGH upon
PCL startup and restart. Marker is deleted if OM1 has been
processed at least once.
SM20.1 Buffer failure; is set upon incorrect buffering of remanent data
into static RAM.
See also Section 2.5.8, Startup Characteristics
SM20.2 Flashing marker; flashes 2 times per sec after PCL startup.
SM20.3 Disable outputs; is set in accordance with the "Disable
Outputs" request. Always updated during I/O state.
SM20.4 Fixation marker; is set in accordance with the "Fixation"
request. Always updated during I/O state.
SM20.5 Data save error; goes HIGH when the system was unable to
save data to the hard disk.
See also Section 2.5.8, Startup Characteristics
SM20.6 Nonremanent cold start; goes HIGH when the cold start has
occurred, and all remanent areas were deleted.
SM20.7 Trigger pulse for restart and program loading; goes HIGH
upon restart, and subsequent to loading of PCl program.
Marker is deleted if OM1 has been processed at least once.
SM21.0 Windows (WinPanel) fails to respond.
SM21.7 Backup of operands into static RAM is not supported by the
hardware version in current use.
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2.4.2 Startup
Startup
The actual startup occurs once the PCL has been initialized. Provided
that no Stop causes or errors are present, the switch position of
WinPanel/external control elements or WinSPS command will determine
one of various available startup modes.
Startup-STOP mode
In the event that during the startup subsequent to Power-ON a hardware
fault or STOP request occurs, the PCL will remain in Startup-STOP
mode. Startup STOP mode is exited as soon as the error has been
corrected and the RUN/STOP switch has been toggled once in the
RUN/STOP/RUN combination. Provided the switch is set to RUN, the
STOP mode can also be exited by means of the Programming Unit (PG).
In the PCL the following causes will result in a Startup-STOP:

• No application program found on hard disk.
• Conflicting STOP request by WinPanel and/or STOP request
command (upon shutdown, PLC status is saved to hard disk, and is
loaded again during controller run-up).
• Superimposed hardware port STOP request.
• Severe fault upon controller run-up, e.g., faults originating in the
installation of peripheral drivers, initialization of PLC operating system,
or communication channel setup. Faults of this type will cause the
return of a System STOP message, and cannot be retriggered, i.e.,
the PCL must again be shut down.
• Flag for remanence test has been set in OM2, and remanence error
has been detected.
• Flag for cyclical backup has been set in the OM2 but saving operands
into static RAM is not possible.
Startup characteristics
Startup-STOP is always followed by a new start (Power-On sequence),
and Processing-STOP is always followed by a restart.
Both startup modes can be executed either nonremanent or partially

remanent, with an organization module available for each startup mode.
OB5: New start OM, nonremanent or partially remanent
OB7: Restart OM, nonremanent or partially remanent
In the event that the respective OMs have not been programmed, the
startup will be carried out without OM processing.
All startup modes adopt the definitions made in the OM2. If an OM2 is
absent, the startup will always be nonremanent.
⇒ The PCL does not utilize default settings for remanence limits.
The data affecting the system area (times for time-controlled OMs,
remanence limits) can then be modified in the respective startup OM.
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Nonremanent new start or restart
The nonremanent startup mode is used in the following cases:

• The system area flag in the OM2, DW2, bit2 = LOW.
• Subsequent to a memory error, as this precludes a remanent startup.
• A nonremanent startup was requested by the Programming Unit (PG).
To describe the process in detail:

• All image areas (remanent and nonremanent) are deleted.
• Fixation is deleted upon new start, and retained upon restart.
• Stored interrupts are deleted.
• Application stack is reset.
• Outputs are enabled.
• Inputs are loaded.
Partially remanent new start or restart
The partially remanent startup mode is used in the following cases:

• No memory error has occurred.
• Remanent startup is required, as per OM2, DW2, bit2 = HIGH.
To describe the process in detail:

• Nonremanent areas are deleted.
• Timer values are transferred.
• Outputs are enabled.
• Inputs are loaded.
The following applies to both nonremanent and partially remanent

startup:
Once the inputs have been loaded, the fixation is superimposed, which
means that it now acts in the case of direct access from within the startup
OM. However, the output to the peripherals does not occur directly, and
the output image is not updated.
As a next step, the STOP switch is queried. If a STOP request is active, a

System STOP is executed. If no STOP request is active, OM5 or OM7 is
processed. This OM permits the use of all PLC instructions, e.g., to set
outputs, to initialize or start timer or counter values, to manipulate values
in the system area (to influence initialization values), or to modify
remanence limits.
Once the startup OM has been processed, the final initialization is

executed, utilizing the values from the system table and system area.
Values such as time monitoring, OM time values, etc., are adopted or
updated.
Provided the respective setting has been made in the OM, the specified
data module is copied into the data buffer.
This initialization is followed by a complete I/O state, and by the start of

program processing in the OM1.
As a next step, the time matrix processing of timer values is started, and
the processing of the time OM is enabled.
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Process-STOP (Stop during program processing)

Once the program processing has begun with the OM1, and an error or a
STOP request occurs, this will cause a Process-STOP condition. This
status is exited as soon as the error has been remedied, or the STOP
cause is no longer current, and the RUN/STOP switch has been moved
through a RUN/STOP/RUN cycle. Exiting the STOP condition can also be
accomplished via command from the Programming Unit (PG), provided
the switch is set to RUN.
Cold start flag

When the cold start flag is set, this forces a nonremanent startup. This
flag is manipulated by either operating system or Programming Unit (PG).
• Operating system: When the PCL is powered up, the PLC program is
loaded from the hard disk into the PC RAM. If an error occurs in the
course of this process, the cold start flag will be set.
• PG: The cold start flag is set when 'loading entire program with reset
of remanent operands'.
Startup without error

This startup occurs when, subsequent to error-free program processing,
the controller is cycled OFF and ON again. The program is still retained in
memory. The remanent areas remain intact. The selected new start OM
is processed. The cold start flag is not set. The startup is executed, and
the cyclical program processing is started. If an error occurs at this
juncture, the module will enter Process-STOP, and will no longer enter
Startup-STOP.
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2.5 PCL Remanence Characteristics & Data Backup

With regard to remanence characteristics and data backup, the PCL
dictates basic handling characteristics that differ from those of a
hardware PLC, in which all data is protected against a power failure
through remanent storage in memory.
The following remanent data of the current project is managed:

• all data modules
• Data field and data buffer
• fixations
Also, some areas of the following:
• Marker
• Timers and counters
Upon the occurrence of a shutdown, the FIFO buffers are backed up to

the hard disk. This means that remanence is ensured in the event of a
normal Power-OFF. The backup of these areas via the static RAM or an
equivalent procedure will be implemented at a later time.
2.5.1 Remanence – Normal shutdown

No special preparations are required for this occurrence because the
remanent data can be backed up and written to the hard disk in a
controlled fashion. At the time of a new startup, the data is again copied
from the hard disk into dynamic RAM onboard the PC, and is again
available to the PLC program.
2.5.2 Remanence – Using Bosch PC Control Panels w/ built-in UPS

With regard to remanent data, this combination presents the most ideal
solution because the effort expended on definition is negligible, and
because the additional PLC processing time required is equal to zero.
Because in this configuration the controller always concludes its PLC

cycle upon Power-OFF and performs a controlled shutdown, the data that
is backed up to the static RAM and to the hard disk originate in the same
cycle.
In the event that an error occurs while backing up to the hard disk, the
data required for initialization will be taken from the static RAM.
To effect the backup, into static RAM, of remanent areas and of the data
modules identified as remanence DMs, only the measures outlined below
are required:
• The remanence identifier "E" for the maximum of 128 data modules
(example: DM1,E DM_K01) must be predefined in the symbol file.
• If the OM2 is available, the remanence areas for M / T / C / DM / DF
must be defined in the OM2.
It is not necessary to predefine the cyclical backup into static RAM.
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2.5.3 Remanence – Power failure or Power-OFF w/o shutdown
⇒ Utilization of the storage capacity on supplementary hardware

described below requires the following minimum release versions:
Hardware: PCI-BM-DP 2, Index ≥ 308
Hardware PCI-BM-CAN 2
Hardware: PCI-BM-IBS 2
WinPanel: 2.0
WinSPS: 3.0
⇒ Please note that the PCL is started with startup switch /M (refer to
section 0). This is the only way to ensure that the controller, in the
case of a panel not equipped with uninterruptible power supply
(UPS), will perform – without security query – a shutdown that
includes the backup of online changes, current DB contents and
remanent data.
If the /M switch has not been set, and the security query "Do you
really want to shut down?" remains unanswered, the modified
and/or remanent data cannot be written to the hard disk when the
PC is shut down.
A subsequent restart of the PCL will cause the controller to use the
"old" modules.
To safeguard the data backup and remanence in the PCL in the case of a
power failure or Power-OFF without shutdown, the supplementary
hardware is equipped with a buffered static RAM. This storage area is
128 kbytes in size, and is backed up for brief interruptions by a gold foil
capacitor. If the static RAM is to be backed up over an extended period of
time, an external backup battery must be used (see also Section 2.3.4,
External control elements).
Backup time
Gold film capacitor 10 – 40 min w/ fully charged capacitor
(standard equipment)
Battery (type .........) on request
Order no. ...............
To utilize the static RAM onboard the supplementary hardware, the

following definitions will be required:
• Definition, of DMs to be backed up, via the remanence identifier in the
symbol file; backing up a max. of 128 DMs is possible.
• Definition, in OM2, of remanence areas for M, T, C, DM, DF.
For each of the operands M, C, T, DM, DF and DM, a bit array in the
OM2 defines whether or not a cyclical backup shall be performed. In
addition, the cyclical backup of the specified areas must be enabled.
Also, the remanent areas for operands M, T, C, DP and DF can be
changed if they deviate from the default setting. See section 2.5.3.4 ,
Defining Remanence Areas in the OM2.
All data modules that are to be backed up are marked with a remanence
identifier in addition to the OM2 entry. The data modules so identified are
written to static RAM, for example, DB1,E DB_K01.
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When created under WinSPS, the fixation lists are written directly to the
hard disk. If an active fixation is recognized during the controller start
sequence, the fixation lists of this file are again loaded. If the file is not
available or faulty, the PCL will remain in Startup-STOP mode until a
fixation list is loaded. Loading an "empty" list deletes the fixation
identifier.
In the event that the backup to the hard disk was faulty or could not be
performed, the remanent data (a subset of all remanent operands) in the
dynamic RAM will be overwritten by those from the static RAM at the time
the PCL is newly started. Subsequent to operand initialization, the
remanent operands are again written back into static RAM.
Shifting remanence limits during ongoing operation (via modifications in

the OM2, or in the system area with subsequent STOP/RUN switchover)
is permitted. During the subsequent startup, and following the operand
initialization, the remanent operands are written into static RAM.
2.5.3.1 Cyclical backup of remanent areas

The cyclical backup of remanent areas is carried out during each I/O
state. The specification that data is to be saved to static RAM via cyclical
backup is defined via entries in the OM2 (refer to Section 2.5.3.4,
Defining remanence areas in the OM2).
Because the process of writing to static RAM is much slower than that of
writing to dynamic RAM, and thus causes the PLC cycle to be extended,
the remanent areas to be selected must be kept as small as possible.
2.5.3.2 Backing up remanent areas on request

The cyclical backup procedure may be replaced by PLC instructions that
perform the backup of remanent areas upon request (refer to Section
7.30 , Backing up & Loading Remanence Areas.
The remanence limit definitions must be declared also in this case

because, when copying from static into dynamic RAM, these areas must
be known already during the startup sequence. The user disables the
definition "Cyclical Backup".
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2.5.3.3 Processing times

The processing times given below are based on the following:
• PC with 200 MHz Pentium processor
• PCI_BM-DP card
Action Processing time Comment

Cyclical backup of: Routine is run through after
• M, C, T, DM, DF approx. 800 µs for 4 each cycle, even if
KB operands were not written.
• DMs w/ remanence approx. 100 µs per DM Cyclical backup of operand
identifier with 512 bytes areas and remanence limits
must be marked in OM2.
Action-driven backup / The operand area specified
loading of: in the instruction is backed
• M, C, T, DM,DF approx. 800 µs for 4 up / loaded in accordance
KB with remanence limits
• DMs w/ remanence approx. 100 µs per DM defined in OM2.
identifier with 512 bytes
Operand area sizes

M Markers 8 kbytes
T Timers 1 kbyte, 4 bytes / timer
C Counters 1 kbyte, 4 bytes / counter
DF Data field 32 kbytes
DB Data buffer 0.5 kbytes
DM Data module 0.5 kbyte per DM
Sample calculation
We shall assume that the entire marker range, the entire data field, and
20 DMs with 512 bytes ea. must be backed up:
Markers: 8 kbytes = 2 x 800 µs 1600 µs
Data field: 32 kbytes = 8 x 800 µs 6400 µs
20 DBs at 512 bytes = 20 x 100 µs 2000 µs
Total: 10000 µs
The PLC cycle is extended by approx. 10 ms.
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2.5.3.4 Defining remanence areas in the OM2
;DW 2: Initialisierungsflag (entries permitted)

;--------------------------------------------------------------------------
; Entry 0 = DO NOT test or execute function
; Entry 1 = Verify and/or execute function
DEFW W 2#0000000100000100
; *******|*****||* *: not used
; | |+------- Check nominal cycle time
; | +-------- Remanent start if possible
; +-------------- Copy data module into data buffer
;DW 3: System settings (entries permitted)

;--------------------------------------------------------------------------
;
DEFW W 2#0000000001000000
; *********||||||| *: not used
; ||||||+------ Markers \ remanent areas/ranges for
; |||||+------- Times \ cyclical backup to
; ||||+-------- Counters \static RAM, as per
; |||+--------- Data field /defined remanence
; ||+---------- Data buffer / limits
; |+----------- Data modules /
; +------------ cyclical backup of marked areas
;DW 7: Number of first remanent timer (entries permitted)

;-----------------------------------------------------------------------
; Entries of 0 and 256 are possible
; 128 = Remanency for timer loops T128 through T255
; 256 = No remanence
DEFW W 128
;DW 8: Number of first remanent counter (entries permitted)

;-----------------------------------------------------------------------
; 128 = Remanence for counters C128 through C255
DEFW W 128
;DW 9: Number of first remanent marker (entries permitted)

;-----------------------------------------------------------------------
; 128 = Remanence from marker byte M128/marker bit M128.0; the remanence
; definition of remanence limit via byte addresses
; 8192= No remanence
DEFW W 128
;DW 10: First remanent address in data buffer (entries permitted)

;-----------------------------------------------------------------------
; 256 = Remanency from data buffer byte DP256
DEFW W 256
;DW 33: First remanent address in data field for backup to

; static RAM (entries permitted)
;------------------------------------------------------------------------
; Entries of 0 and 32768 possible
; 16384 = Remanence from data field byte DF16384 in static RAM
; 32768 = No remanence in static RAM
; Limit applies only to backup into static RAM; this area
; takes precedence over the data field, the remainder of which is completely
; backed up to hard disk for remanent storage;
DEFW W 16384
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2.5.4 Remanence characteristics & hardware used
PC without UPS PC with UPS (Bosch manufacture)

Backup of remanent data into static RAM is required on Backup of remanent data into static RAM is required
a cyclical basis. In the event of a catastrophic power only in the event of a Windows program crash with
failure on a PC without USP, Windows is unable to back subsequent Power-Off.
up data to the hard disk. In the event of a Windows crash, the process can be
This means that a power failure causes an instant brought to a controlled state through the
interruption of program processing, making processing interpretation of SM21.0 (WinPanel no longer
of the OM8 (refer to Section 5.12, Shutdown module responds) because the PCL is still functioning.
(PLC only)) no longer possible, and preventing the data When the PC is subsequently shut down in
and remanent statuses written in this cycle from being preparation of a new startup, the shutdown occurs in
backed up. a controlled fashion, and the remanent data is written
into static RAM.
Processing of the OM8 shutdown module (see
Section 5.12, Shutdown module (PLC only)) can be
carried out.
The entire program management, i.e., which data is to All remanent areas/ranges can be backed up,
be saved under what preconditions, must be handled by provided they have been defined as remanent. In this
the programmer. context it is important that the backed-up data
originates from a single PLC cycle.
Because the process of writing to static RAM is The PLC cycle time is not affected.
considerably slower than that of backing up to dynamic
RAM, the PLC cycle is extended by the former method.
Accordingly, the remanent areas must be defined as
small as possible.
Conclusion: Conclusion:
Absolute data security cannot be ensured despite a The utilization of a PC equipped with UPS and
cyclical and request-specific data backup procedure. manufactured in accordance with Bosch guidelines
Independent of the program position currently being facilitates a data backup of single-cycle accuracy.
processed, a power failure will cause an instant system
stop without the backup of remanent data.
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2.5.5 Remanent operation

The determination of remanent/nonremanent operation occurs in the
OM2 /DW2, Bit2: "Remanent start if possible".
In remanent operation, the statuses of the designated remanent

operands are retained after a STOP/RUN and shutdown.
In the absence of modifications in either OM2 or system area, this affects

the different backup modes as detailed below:
• Backup to hard disk:
• The upper half of the marker range M4096 through M8191 is
remanent.
• The upper half of the counters C128 through C255 is remanent.
• The upper half of the timers T128 through T255 is remanent.
• The entire data field DF0 through DF32767 is always remanent.
• All FIFO buffers are always remanent.
• All data modules are always remanent.
• Backup to static RAM:
remanent.
• The upper half of the data field DF16384 through DF32767 is
always remanent.
• Data modules marked with remanence ID are always remanent.
The user can shift the so-called "remanence limits" as desired. To this
end, both OM2 and system area provide appropriate measures.
In remanent operation, nonremanent operand statuses cannot be

predefined in the startup OM because these will be deleted once the
startup modules have been processed.
⇒ The remanence limit for the data field affects only the backup into
static RAM, and not the backup to hard disk.
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2.5.6 Nonremanent operation

OM2 /DW2, Bit2: „Remanent start if possible“.
In nonremanent operation, a STOP/RUN operating mode change or

Power-Off/On cycle will be followed by clearing all of the following:
• All markers
• All timers
• All counters
This occurs even before processing any startup OM.
As a consequence, nonremanent operation permits predefining all

operands in the startup OM.
The entire data field, DF0 through DF32767, is always remanent,

regardless of the position of the remanence switch.
⇒ Data field backup into static RAM is subject to the defined

remanence limit (default, OM2, or system area).
All data modules are always remanent because they are stored on the
hard disk.
⇒ Backing up the data modules into static RAM accounts for only
those DMs that are marked with the remanence ID (E) in the symbol
file.
A standard rule applying to both the data field and remanent DMs is that
the backup into static RAM takes precedence over the backup to hard
disk. Accordingly, in the event that a backup turns out to be faulty or
could not be carried out, the remanent data (a subset of all remanent
operands) in the dynamic RAM will be overwritten by those from the static
RAM at the time the PCL is newly started.
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2.5.7 Buffer failure, data backup error, RAM test
Buffer failure
The special marker SM20.1 (buffer failure) identifies a backup error when
saving remanent data into the static RAM onboard the PCL hardware.
The marker goes HIGH in the following cases:

• During the PCL startup sequence, it is recognized that a proper
backup of remanent data into the static RAM was possible neither
during program processing nor upon shutdown of the last control
cycle. The special marker is set while processing a startup module,
and is reset once the PLC startup has concluded.
• During program loading or post-loading, the maximum permitted
number of DMs with remanence ID was exceeded. The special marker
remains set during program processing, and is reset while loading,
provided that the maximum permitted number of DMs with remanence
ID is maintained.
• The cyclical backup of remanent data during the I/O state was not
correctly executed, the maximum permitted number of DMs with
remanence ID was exceeded subsequent to online modifications. The
special marker remains set during program processing.
⇒ With the special marker SM20.1 set HIGH, the backup of all
remanent operands into static RAM – both cyclically and via PLC
instruction – are rejected, although the PCL remains in RUN mode.
The interpretation of the SM20.1 and/or of system area word S116
permits error handling.
Data backup error

The special marker SM20.5 (data backup error) is set when, at the time
of shutdown, the backup of remanent data to the hard disk was faulty.
The special marker is set after Power-On, and while processing the OM5
startup module, and is reset prior to the OM1 PLC startup module.
RAM test
During the controller startup sequence, a test of the static RAM is carried
out. If the test fails, special marker SM20.1 will go HIGH, and the test
results are stored in system area S116.
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2.5.8 Startup characteristics

With regard to the controller startup, the backed-up data, the statuses of
the SM20.1 “Buffer Failure" and SM20.5 “Data Backup Error" special
markers, plus the result of the RAM test, are reflected in the table below:
RAM test Backup to Backup to Backup to SM20.1 set SM20.5 set Contents of rem. Remanent startup
static RAM, static RAM, hard disk during during S116 Start w/ data from
shutdown prog. proc. startup startup (binary) up
NOK x x NOK x x 00001xx1 No
OK NOK NOK NOK x x 00001110 No
NOK x x OK x 00000xx1 Yes Hard disk
OK NOK NOK OK x 00000110 Yes Hard disk
OK NOK OK OK 00000010 Yes Hard disk
OK OK NOK OK 00000100 Yes Hard disk
OK OK OK OK 00000000 Yes Hard disk
OK NOK OK NOK x 00001010 Yes Static RAM backup,
last program
processing
OK OK NOK NOK x 00001100 Yes Static RAM backup,
shutdown
OK OK OK NOK x 00001000 Yes Static RAM backup,
shutdown
x = don’t care
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CL550 System Features 3-1
3. CL550 System Features

The CL550 Multiprocessor Hardware PLC is optimized for integration in
decentralized structures, and provides comprehensive communication
options.
Through its modular construction, sophisticated hardware expansion

options, and extensive interfacing capabilities, the CL550 is predestined
for service as the ideal solution to complex applications.
Superior performance is assured by up to 6 asynchronous central

processing units, each equipped with a powerful 32-bit processor.
Each ZS550 central processing unit represents a standalone control

unit equipped with all data areas, and the entire I/O address range.
Ideally suited for industrial applications, the unit also features excellent
EMC characteristics and vibration resistance. All of the above, in concert
with the proverbial excellence of Bosch manufacturing quality, ensures
highest reliability and availability ratings even in critical applications.
The innovative concept inherent in the CL550 supports the consistent im-
plementation of decentralization in automation technology. Distributed
peripheral devices are connected via the PROFIBUS-DP standard field
bus or via InterBus-S, respectively.
To handle communications at the control unit level, an Ethernet-TCP/IP
connection is already integrated. Centralized programming is thus provi-
ded already in the basic unit. The Ethernet-TCP/IP connection also facili-
tates communications between external PLC, control terminals, and PCs.
Programming is accomplished with the proven Bosch WinSPS PLC

programming tool. As regards programming language, the user can freely
choose between the traditional PLC languages, such as ladder diagram,
instruction list (IL), function diagram (FUD), sequential function chart, and
structured text (ST) programming and, as an alternative, the ANSI "C"
high-level language.
Communications with the Bosch WinSPS and WinDP programming tools

and other applications are handled by the TCP/IP standard protocol, and
with the use of the BÜP (Bosch transfer protocol) command language.
The present documentation is designed to support the CL550 user with

his programming tasks and with the system startup of the controller. It
discusses the following subjects:
● Hardware & System Configuration
● Operating & Displaying
● Interfacing with Peripherals
● Programming Basics
● Addressing Conventions
● Command Set Description
● Programming Samples
⇒ For additional essentials related to the CL550, and to operating

decentralized peripherals via the PROFIBUS-DP, refer to the Online
Help of the WinSPS and WinDP programming device software.
Helpful topics in the WinSPS or WinDP appear under the headings:

● Help
● Contents
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3-2 CL550 System Features
3.1 Hardware and System Configuration
Display /control
Pentium 166 MHz elements
platform
under VxWorks V.24 interface
CMD Interface
(ZS550-DP-IBS only)
32 MB RAM
Ethernet Back Front
side B
a
32 MB Ethernet Front c
Flash disk k
s
i
I/O Port d
Buffered SRAM PROFIBUS DP-V1 e
for remanent data
I/O Port
InterBus-S
(ZS550 -DP-IBS only)
3.1.1 Control section

The control section is implemented on the basis of a powerful PC kernel
running under the VxWorks standard operating system.
3.1.2 Memory
To accommodate the memory size of the control program, 1500 k words
were reserved in RAM. At an average length of 6 words per instruction,
approximately 250 instructions can be programmed.
Upon startup, control program and data are loaded from the FLASH Disk,
and written into RAM. This is followed by reading the remanent data from
the buffered SRAM, and writing it to RAM where it is superimposed over
the data that is already there.
3.1.3 Communication interfaces

Each central processing unit provides several communication interfaces:
• One serial interface which can be operated with the use of the Bosch
BÜP03, BÜP64 or BÜP19E transfer protocols.
• Two Ethernet connections utilizing the TCP/IP Internet protocol to

send Bosch BÜP transfer protocol commands. These interfaces can
be operated with a transmission speed of 100 Mbit/s (Fast Ethernet).
One connector is located on the front panel, and the second on the
backplane of the system bus.
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3.1.4 Peripheral Operation

The I/O operation is accomplished via decentralized peripherals utilizing
the DP-V1 protocol on the PROFIBUS-DP or via InterBus-S (ZS550-DP-
IBS) field bus.
3.1.5 System clock management

Each ZS550 features a real-time clock. This clock is backed up the
central battery located in the power supply. This real-time clock
generates the system time which can be processed in the system area of
the PLC program.
The clock is set through a command by the WinSPS editor, and cannot
be influenced via the PLC program.
3.1.6 Simulation
A function which is integrated in WinSPS version 3.2 and WinPanel
version 2.32 and higher allows you to simulate a CL550. This simulation
can be started via a switch on the WinPanel (cf. chapter 2.3.2).
3.2 The ZS550 in the CL550 System
All ZS550 central processing units comprise peer-to-peer devices which

are interconnected through an Ethernet connection on the system bus.
The communication among central processing units is handled by a

CON550 add-on module which serves as a switch on the Ethernet.
Within the rack, each hardware module possesses a clearly assigned slot
ID. In conjunction with the rack ID which can be individually assigned to
each rack, this facilitates the precise identification of the ZS550 within a
system or network.
⇒ Rack ID “0” is reserved, and thus not available for assignment. If

rack ID 0 is recognized during startup, an error message will result.
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3.3 Operating and Displaying

The basic version of the CL550 is shown below as an example. The
variant with InterBus-S interface is equipped with a double width front
panel. This front panel offers an additional InterBus-S interface, a V.24
interface (X33) for communication with the CMD software (configuration
software for InterBus-S interface) and a further V.24 interface (X31) for
the connection to a programming device.
ZS Stop
RUN/STOP switch
Outputs disabled
I/O fixed
Mainboard
SELECT button (scrolling)
SELECT LED
Module status
V.24 interface port Field bus
Ethernet Link LEDs

Ethernet port Ethernet
connection
PROFIBUS DP Link LED

PROFIBUS DP V1 interface
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3.3.1 Display and control elements
Two 7-segment LCD displays provide a visualization of the status code,

and of the various ZS550 functionalities (devices).
Select
Dev
Top display: ZS550 functionality (device)
Status Bottom display: Status code
The status code indicated in the bottom display always refers to the
ZS550 functionality indicated in the top display.
A detailed list of display readings and their associated ZS550

functionalities (devices).
PLC control unit functionality

DP bus master functionality (cyclical I/O processing)
TCP/IP COM functionality via backside (BS);
system bus communications
TCP/IP COM functionality via frontside (FS);
external communications
DP/V1 COM functions
V24 COM functionality – serial interface
(if configured)
InterBus-S functionality (ZS550-DP-IBS only)
- Configurable RSS channels 4-7

Power supply (battery monitor)
Function and/or configuration mode
When the unit is in RUN control status, the presence of messages only
cause the Select LED to illuminate. Pressing the button causes the
highest-priority message to be moved to the foreground. Releasing the
button causes the current message to disappear after 10 seconds,
extinguishing the display.
Message of a type which leads to a module are immediately switched to

the foreground with the highest-priority message.
The Select button can be pressed to “scroll through” additional active

messages.
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3.3.1.1 Control elements / Displaying PLC control unit functions
Status LEDs and control elements
Stop
Run
AS
Fix
STOP / RUN
switch
RUN Program is running, outputs are active.
Timer and counter values are being
processed.
STOP ZS is stopped, all outputs are LOW.

Remanent markers, timer and counter
values are retained.
LED: “ZS Stop“

Off ZS is in RUN mode.
On Module Stop mode caused by ZS

(detailed information appears in 7-
segment status display).
LED: „AS“ Disabling outputs:

- All outputs are set LOW
- PLC program is being processed
- I/O image is being processed
LED: „FIX“ Inputs and outputs are fixed by the PLC

utility program.
Stop mode causes
When a control unit enters Stop mode, the cause may be as follows:
● Stop command via slide switch on central processing unit

● Stop via command (from PG programming device or interface)
● Stop caused by application (HLT instruction, error, cycle time)
Stop mode causes all outputs to be deleted, and the bus master to be
switched to Clear. All other operands retain the contents they had during
the preceding (last) cycle.
While in Stop mode, the central processing unit can continue to function
as a server, processing tasks from partner units.
Upon transition from RUN to STOP mode, the error and/or information
status is updated. The status can be visualized via the WinSPS and
WinDP utility programs.
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A Stop request can be canceled only by the requesting partner. If several

request are active, all issuing partners must cancel the Stop before the
central processing unit is able to reenter RUN status.
When the control unit function reports an error, the top display always
indicates code “1”. Because messages of this type always cause a ZS-
Stop, the display is always instantaneous. It is also possible that several
codes are present at the same time, a condition which is signaled by the
Select LED, meaning that the messages can always be scrolled through
by pressing the Select LED
Explanation of status displays
Select
Dev
Select: Control unit function
Status display of control unit functions
Status
Status Explanation
display
Off Application program is “running”
Remanence error, data loss affecting application operands
Memory error, missing application program
Cycle time error (HW and SW)
Application program error

(application stack error, module task error, no active DM found)
Application program error

(parameter error, addressing error, module not found / not available)
HLT instruction in application program
Stop instruction issued via PG programming device
Stop signal issued via slide switch on front panel
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3.3.1.2 Displaying DP bus master functions
Select
Dev Select: DP bus master functions (cycl. I/O

processing)
Status
Status display for DP bus master functions
Status Explanation
display
Off OPERATE mode (fault-free operation). DP/V1 bus master engaged in
cyclical data transfer.
CLEAR mode ; sources for CLEAR are the following:
- Control unit in STOP mode
- Control unit in CLAB mode (outputs disabled)
The DP is engaged in cyclical I/O data transfer. Value 00H (outputs
cleared) is transferred for outputs.
Loading new master parameter set (MPS)
OFFLINE mode. DP is not communicating w/ PROFIBUS (OFFLINE).

No MPS or invalid MPS available.
The original initialization (subsequent to Off/On cycle) is active.
The DP is attempting to start with the available MPS.
The initialization phase is ended when:
- an error/fault (hardware, address assignment, MPS, etc.) is
present
- all slaves can be reached w/o error (neither SNE nor SKF is
present)
- the controller halt interval (PLC_Stop_Time) has expired.
At least one slave reports configuration error (SKF).
At least one slave is not reachable (SNE), or not ready for cyclical data
traffic (SNB).
At least one slave reports static diagnosis (DPS)
Bus error – Bus master is unable to access the bus (no idle level)
Possible causes:
- Short-circuit on PROFIBUS
- Terminating resistor not switched on
- Terminating resistor not powered
Fatal error in DP bus master (system error)
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3.3.1.3 Displaying TCP/IP COM functions
Frontside Backside
Select Select
Dev
Select: TCP/IP COM functions
Dev
Status
Status display of
Status
TCP/IP COM functions
Status Explanation
display
Off Channel is inactive, and/or channel processes only external tasks

(server operation).
Displayed central task is faulty.

-
At least one central task with an ID higher than 16 is faulty.
Serial channel is being used for order logging (Tracer on).
Serial channel is being used for order logging.
No IP address assigned to Ethernet channel.
Consistency check of configuration file revealed errors (rack

consistency errors).
The displays of the TCP/IP communication section also include the LEDs
of the Ethernet interface on the front panel:
L S
X
Ethernet
7
1
Function: Link / Activity:

LED: „L“
Off " No link
On " Link OK - no activity
Flashing " Link OK - plus activity
LED: „S“ Function: Speed LED:

Off " 10 Mbit/s
On " 100 Mbit/s
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3.3.1.4 Displaying DP/V1 COM functions
Select
Dev Select: DP/V1 COM functions
Status Status display of

DP/V1 COM functions
Status Explanation
display
Displayed central task is faulty (0...F corresponds to task ID 0...15)

-
At least one central task with an ID higher than 15 is faulty
The displays of the DP/V1 communication section also include the SEND
LED of the PROFIBUS interface:
Send
COMNET-DP
X
7
2
LED: „Send“ On " Active bus interface on PROFIBUS
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3.3.1.5 Power supply functions
Select
Dev Select: Power supply (battery monitor)
Status Status display for power supply

(battery monitor)
Status Explanation
display
Off Battery on power supply module OK.
Battery fault: Failed central battery on power supply module.
LOW BATTERY warning " Replace battery.
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3.3.1.6 Displaying InterBus-S functionality (ZS550-DP-IBS only)
Select
Dev Select : InterBus-S functions

Status display for InterBus-S functions
Status
Anzeige Bedeutung
Status
ACTIVE: InterBus-S in active status
USER: User error/parameterization
READY: InterBus-S in ready status
PF: Peripheral fault
DETECT: Diagnosis routine is active
Bus error – Busmaster cannot access the bus (no idle state level)
Possible causes:
- Short circuit on the field bus
- Terminating resistance not switched on
- Terminating resistance has no voltage
Error on the interface module/HW
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3.3.2 Function mode & Configuration mode

The Select pushbutton can be used to select component code ‘C’. The
‘C’ stands for the Function mode or Configuration mode which can be
accessed at this point. Actuating the STOP/RUN switch causes the
display to change to ‘C’, indicating that the Configuration mode is active.
The Select pushbutton can be used to select various menu commands,

all of which are represented by a dot in the top display. In the case of
those menu commands that do not provide options (items 1 and 2),
actuating the STOP/RUN switch causes the function to be started
directly.
The menu commands providing options (items 3, 4, 5, and 6) initially

indicate the currently selected option in the bottom display. By actuating
the STOP/RUN switch, the options can be stepped through in
succession. This is indicated by a dot. The Select pushbutton can now
be used to select an option, and repeated actuation of the STOP/RUN
switch causes the option to become enabled.
The following functions have been implemented in the Configuration

mode:
Dev Status Explanation

display display
Clears fixation
Superimpose nonremanent startup,

reset remanence error
Enable outputs
Outputs disabled
Serial interface has been assigned a BUEP protocol
Serial interface occupied by tracer (job logging)
Defined deletion of I/O configuration (MPS master parameter

set) of DP bus master segment
Delete all saved BIN data (PLC program, I/O configuration,
IP configuration) and reset controller
ZS550 software version
Version number is output via display change (effective v1.1

and up)
Reset lock flag for programming device access, e.g. if

connection between programming device and ZS550 has
been faulty
Active fixation or disabled outputs are also indicated by directly

connected LEDs.
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During active Configuration mode, a selection made via STOP/RUN

switch is effected immediately, with subsequent return to display mode. If
a selection is not made, the STOP/RUN switch can be used to toggle the
display from C. again to C, i.e., again to Display mode.
Overview of Configuration mode

Select The Select pushbutton is used to select either a specific configuration
command or an option. The STOP/RUN switch is used to confirm a
selection.
When a function has been executed, the Configuration mode is exited

completely, and the highest-priority message displayed.
Stop Display mode

Run Configuration mode
Select
Stop
Run
Delete Reset Select Select Select

remanence Reset monitor
fixation error lock-out
Version indicated
Stop via display change
(available w/ v1.1 & up)
Run
Outputs Serial port Delete
enabled disabled BUEPxx Tacer MPS all BIN
file files
In the default display mode, subsequent to scrolling through a blank

display field, the Select pushbutton can be pressed to access the ‘C’
display. The blank display field is intended to provide a defined
separation from the normal displays, and is present in any case. If there
are no active displays present, the ‘C’ display will be reached by pressing
the Select button twice.
To switch to Configuration mode while the ‘C’ is displayed, the

STOP/RUN switch must be actuated. In the event that neither Select
pushbutton nor the STOP/RUN switch is actuated within a 10-second
interval, the display will automatically change to the highest-priority
display, causing the ‘C’ to disappear.
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If this is the case, the function of the STOP/RUN switch will be limited to
acknowledging the display visible in Configuration mode; the control unit
itself will not respond to a change in the position of this switch.
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3.4 CL550 Startup
3.4.1 System start

After Power-On of the CL550 system, all hardware modules located in
the rack commence with their firmware startup routines.
The PC-based ZS550 hardware module first performs a self-test. This is

essentially a test of the dynamic RAM. At the conclusion of this test, the
boot sector is loaded.
The next program to be executed loads and starts the VxWorks operating
system. The operating system has been adapted to the available
hardware, and comprises all required hardware support functions.
During the system startup, a check is made to verify and initiate the
communications capability of the hardware module in conjunction with the
other components in the system.
In addition, a check is made whether or not an IP address was assigned

to all central processing units. If this is not the case, the module will halt
while returning an error message, and wait to be addressed by the
configuration tool.
The overall system will be enabled and the floating contact of the power
supply closed only after all hardware modules have started without fault.
3.4.2 Control section startup

The startup routine of the control section is performed after each Power-
On following the system start, and after each STOP/RUN command. The
way in which the startup is carried out depends on several internal
statuses. In essence, these are concerned with the following issues:
● Is the control unit in startup after Power-On?

● Is a PLC program available?
● Is a memory (remanence) error present?
● Does the user require operand remanence?
● Has buffer (backup) operation been selected on the power supply?
3.4.2.1 Startup preparations in Startup-STOP

Subsequent to switching on the control unit, the internal Startup-STOP
status is reached. In this status the Power-On flag goes HIGH. This flag
is mapped in special marker SM20.7 for evaluation.
As a first step, the power supply signals are examined to ascertain

whether buffered operation or operation without battery has been
selected. This differentiation is made centrally for all hardware modules in
the system by positioning the appropriate jumper on the power supply.
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As a next step, the availability of a valid application program is verified.

To this end, the system searches for the file named softsps.bin on the
FLASH Disk. If this file is not found, all operands and the data field will be
deleted. The display then indicates the memory error by showing error
code ‘2’. The control unit remains in Startup-STOP, and waits for a
program to be loaded. This status is also mapped in special marker
SM21.1, and deleted only subsequent to a new Power-ON cycle.
If a program is available on the FLASH Disk, this program will be loaded

into dynamic RAM. In this process the data modules are initially loaded in
their original form.
This is followed by checking the buffer status of the static RAM.
In the event that a buffer error is found, and batteryless operation was not
preselected via the power supply, the data field will be subject to a
defined deletion, and special marker SM20.1 set HIGH to identify the
data loss. However, if the buffer is fully functional, the data field will be
retained, and the remanent data modules copied from static RAM into
program memory.
The definition of operand remanences are derive from the OM2 through
interpretation of the remanence bit. If the bit is HIGH, all operands
upward of the defined address limits will be kept remanent. Up to these
limits, the operands are subject to defined deletion. If the bit is LOW, all
operands will be deleted. In the absence of the OM2, the default takes
effect, meaning that the upper half of the operands remains remanent.
The data field and the data modules defined in the PG programming
device are normally remanent.
In the case of defined remanences, the buffer status and the flag for
batteryless operation are checked. If batteryless operation is not selected
and the buffering is faulty, all operands will be subject to defined deletion
which is indicated in special marker SM20.1. The controller exhibits error
code "1" for remanence error, and remains in Startup-Stop mode. The
controller remains in this state until the error condition has been
specifically removed.
Error status ‘2’ can be acknowledged only by loading a new program via
the PG programming unit. By contrast, status ‘1’ is canceled either by
loading a program while deleting the remanent areas, or via direct user
intervention on the display, and selection of the “Nonremanent Startup”
menu option.
Another task of the Startup-STOP is the activation of the peripheral

driver, which also compares the nominal I/O configuration with actual
equipping. The response to possible discrepancies can be preselected in
the OM2. If an OM2 is not available, the default setting will take effect,
meaning that, in the event of a missing MPS (master parameter set), the
control unit will remain in Startup-STOP but will start if slaves are absent.
The control unit always exits the Startup-STOP status with a valid PLC
program and valid operands.
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Startup-STOP flow chart
Set Power-On flag

special marker SM20.7
Determine batteryless
Batterieloser- Betrieb aus
operation via signals
Netzteilsignalen from
ermitteln
power supply
Ermittle vorhandenes no
nein Lösche Operanden
Delete operands
Determine available
Anwender-program
Programm Lösche Datenfeld
Delete data field
application via
Sondermerker
Special markerSM21.1
SM21.1
über FLASH-Disk
FLASH disk
Load
Anwenderprogramm
application program
aus
FLASHfromladen
FLASH disk
ODetermine
peranden-P operand
ufferung
buffering via power supply
über Netzteilsignale und
signals and data
Datenmuster patterns
ermitteln
Batterieloser-
Batteryless Betrieb
operation yes
ja
oder Operanden
or -
Pufferung-Fehler
operand buffering error
Datenbausteine aus
Copy data modules Lösche
Delete data
Datenfeld
field
statischem from
RAM kopieren und
andremanente
remanent data
Datenbausteine
modules,
static RAM Setze
set special
Sondermerker
marker SM21.1.
SM21.1
ADetermine
nwender R application
emanenz
remanence
aus from OB2
OB2 ermitteln oder
or set defaults
Voreinstellung setzen
O peranden
Faulty -Pufferung
operand buffer
fehlerhaft und Anwender
and application ja
Remanenz
remanence selectedund
eingestellt
yes Lösche Operanden WaitWarte auf
for operand Wait
Warte
to load
auf
Delete operands Operanden
buffering, Pufferung
reset error. Anwender-P
application program
rogramm
and
kein Sondermerker
Special marker20.1
20.1 via PG progr. device.
Fehler rücksetzten über PG laden
noBbatteryless
atterieloser operation
Betrieb Display shows 1
Anzeige 1 Display shows
Anzeige 22
Startup
Anlauf
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3.4.2.2 Startup preparations in Module-STOP

In Module-STOP status, a new program can be loaded. If it is also
desirable to delete the remanent areas, this can be accomplished directly
in STOP. In the restart that follows, a response will be given only to the
remanence flag of an OM2 which may be present
3.4.2.3 Control unit startup

Once a Startup-STOP or Module-STOP has provided the information
necessary for a control unit startup, the following procedural sequences
are differentiated dependent on the flags:
● Startup after Power-ON – OB5

● Startup after STOP/RUN – OB7
The controller startup checks the flags for batteryless operation, operand
remanences, and Power-ON, and selects from these the startup OM and
remanence characteristics.
The determination is made through interpretation of the remanence bit in

OM2. If an OM2 is not available, the default setting is used, i.e., no
operand remanence is used. If the remanence has been preselected in
the OM2, the module will also supply the limits upward of which the
remanences apply. On the basis of these limits, the nonremanent
operands are deleted before the startup OM is processed.
The selection of the startup OM depends on the status of the Power-On

flag. If this flag is HIGH, OM5 will be started, otherwise OM7 is always
started. If none of these OMs is present, this will not cause an error
message to be returned.
As a rule, fixation is retained, and is independent of remanence settings.

It will be deleted either when “Loading with Reset of remanent operands”,
or via display manipulation on the ZS550.
Prior to the startup OM all peripheral outputs are cleared without

exception. Inputs are loaded with current values. A complete I/O state is
carried out subsequent to the startup OM. The possibly required
superimposition of fixation information is preformed automatically by the
periphery driver. Finally, the remanent status of the “Disable outputs”
command is superimposed.
The startup OM is followed by another deletion of nonremanent areas in

accordance with the current limits taken from the system area.
The startup OM is monitored only via the HW cycle time. Monitoring on

the basis of the SW cycle time is possible only during the OM1 cycle.
The startup OM does not permit time-controlled processing.
The trigger pulses for Power-On or “Program loaded” are set accordingly.
Copying of data module to data buffer is carried out as defined by the

entry in the OM2.
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Control unit startup flow chart
Startup-STOP Module-STOP
Determine application remanence

from OM2
or set defaults
No application remanence yes

or
batteryless operation and Power On
Delete Delete all operands,

nonremanent operands retaining data field and data modules
Prepare startup OM.
Delete and enable outputs,

read inputs.
Update trigger pulse (SM20).
Check and superimpose fixation
no
Power-ON flag is set.
Start OM5 Start OM7
Execute entire I/O state.

Repeated deletion of nonremanent
operators.
PLC cycle
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3.5 Remanence Characteristics & Data Backup

To provide remanence, i.e., data security subsequent to cycling the
CL550 OFF/ON, and/or in the event of a power failure, each central
processing unit features a static RAM that is backed up via the power
supply. The areas listed below apply to remanent data.
The following remanent data of the current project is managed:

• all data modules
• fixations
• FIFO buffers
as well as areas
• data field
• data buffer
• markers
• timers
• counters
3.5.1 Remanence with use of NT4 power supply

When using the NT4 power supply module, you will not be required to
take any measures other than defining remanence area limits.
This power supply module maintains the internal voltages required to

save remanent data for at least another 120 ms. In any case this interval
is sufficient to write all data required for a restart to the static RAM of the
ZS550 central processing unit.
Upon renewed Power-ON, the data is then copied from flash memory to
dynamic RAM (working memory). This is followed by updating the
remanent areas with information from static RAM.
⇒ The NT4 power supply module is the only power supply which
ensures that remanences are backed up c o m p l e t e l y and
w i t h o u t additional programming effort, and that there is no
limitation in terms of equipping.
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3.5.2 Remanence with use of NT1, NT2, NT3, and NT24 power supplies
When using the NT1, NT2, NT3, and NT24 power supply modules,
remanence cannot be fully guaranteed because after being switched off,
these power supplies fail to maintain the voltages required to save the
remanent data.
However, it is possible to utilize a user-managed remanence by taking

advantage of the available backup commands for remanent areas.
⇒ When using the backup commands for remanent areas, the data
held in static RAM always correspond to the respective last save
operation.
Example:
In the case of cyclical backup, the data is taken from the preceding
complete PLC cycle and NOT from the current PLC cycle!
⇒ Note also that the various power supplies belong to different

performance categories, and that therefore the number of central
processing units that can be powered will be limited:
NT1: max. 1 x ZS550 + 1 x CON550

NT2: max. 2 x ZS550 + 1 x CON550
NT3+NT24: max. 3 x ZS550 + 1 x CON550
3.5.2.1 Cyclical backup of remanent areas

The cyclical backup of remanent areas is carried out during each I/O
state. The specification that data is to be saved to static RAM via cyclical
backup is defined via entries in the OM2 (refer to Section 3.5.2.4,
remanence areas in the OM2)
Because the process of writing to static RAM is much slower than that of
writing to dynamic RAM, and thus causes the PLC cycle to be extended,
the remanent areas to be selected must be kept as small as possible.
3.5.2.2 Backing up remanent areas on request

The cyclical backup procedure may be replaced by PLC instructions that
perform the backup of remanent areas upon request (refer to Section
7.30 , Backing up & Loading Remanence Areas).
The remanence limit definitions must be declared also in this case

because, when copying from static into dynamic RAM, these areas must
be known already during the startup sequence. The user disables the
definition "Cyclical Backup".
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3.5.2.3 Processing times
Action Processing time Comment

Cyclical backup of: Routine is run through after
• M, C, T, DM, DF approx. 1000 µs for 4 each cycle, even if
KB operands were not written.
• DMs w/ remanence approx. 120 µs per DM Cyclical backup of operand
identifier with 512 bytes areas and remanence limits
must be marked in OM2.
Action-driven backup / The operand area specified
loading of: in the instruction is backed
• M, C, T, DM, DF approx. 1000 µs for 4 up / loaded in accordance
KB with remanence limits
• DMs w/ remanence approx. 120 µs per DM defined in OM2.
identifier with 512 bytes
Operand area sizes

M Markers 8 kbytes
T Timers 1 kbyte, 4 bytes / timer
C Counters 1 kbyte, 4 bytes / counter
DF Data field 32 kbytes
DB Data buffer 0.5 kbytes
DM Data module 0.5 kbyte per DM
Sample calculation
We shall assume that the entire marker range, the entire data field, and
20 DMs with 512 bytes each must be backed up:
Markers: 8 kbytes = 2 x 1000 µs = 2000 µs
Data field: 32 kbytes = 8 x 1000 µs = 8000 µs
20 DBs at 512 bytes = 20 x 120 µs = 2400 µs
Total: 12400 µs
The PLC cycle is extended by approx. 12.5 ms.
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3.5.2.4 Defining remanence areas in the OM2

;--------------------------------------------------------------------------
DEFW W 2#0000000100000100
; *******|*****||* *: not used
; | |+------- Check nominal cycle time
; | +-------- Remanent start if possible
; +-------------- Copy data module into data buffer

;--------------------------------------------------------------------------
;
DEFW W 2#0000000001000000
; *********||||||| *: not used
; ||||||+------ Markers \ remanent areas/ranges for
; |||||+------- Times \ cyclical backup into the
; ||||+-------- Counters \static RAM, as per
; |||+--------- Data field /defined remanence
; ||+---------- Data buffer / limits
; |+----------- Data modules /
; +------------ cyclical backup of marked areas

;-----------------------------------------------------------------------
DEFW W 128

;-----------------------------------------------------------------------
DEFW W 128

;-----------------------------------------------------------------------
; 128 = Remanence from marker byte M128/marker bit M128.0; the remanence
; 8192= No remanence
DEFW W 128

;-----------------------------------------------------------------------
DEFW W 256

;------------------------------------------------------------------------
; Limit applies only to backup into static RAM; this area
; takes precedence over the data field, the remainder of which is completely
; backed up to hard disk for remanent storage;
DEFW W 16384
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3.5.3 Remanent operation

In remanent operation, the statuses of the designated remanent

operands are retained after a change of operating mode, i.e., STOP/RUN
and shutdown.
In the absence of specific declarations in either OM2 or system area, this

affects the different backup modes as detailed below:
• Backup to FLASH Disk
remanent.
• The entire data field DF0 through DF32767 is always remanent.
• All FIFO buffers are always remanent.
• All data modules are always remanent.
• Backup to static RAM:
remanent.
• The upper half of the data field DF16384 through DF32767 is
always remanent.
• Data modules marked with remanence ID are always remanent.
The user can shift the so-called "remanence limits" as desired. To this
end, both OM2 and system area provide appropriate measures.
In remanent operation, nonremanent operand statuses cannot be

predefined in the startup OM because these will be deleted once the
startup modules have been processed.
⇒ The remanence limit for the data field affects only the backup into
static RAM, and not the backup to hard disk.
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3.5.4 Nonremanent operation

In nonremanent operation, a STOP/RUN operating mode change or

Power-Off/On cycle will be followed by clearing all of the following:
• All markers
• All timers
• All counters
This occurs even before processing any startup OM.
As a consequence, nonremanent operation permits predefining all

operands in the startup OM.
The entire data field, DF0 through DF32767, is always remanent,

regardless of the position of the remanence switch.
⇒ Data field backup into static RAM is subject to the defined

remanence limit (default, OM2, or system area).
All data modules are always remanent because they are stored on the
hard disk.
⇒ Backing up the data modules into static RAM accounts for only
those DMs that are marked with the remanence ID (E) in the symbol
file.
A standard rule applying to both the data field and remanent DMs is that
the backup into static RAM takes precedence over the backup to Flash
disk. Accordingly, in the event that a backup to Flash disk turns out to be
faulty or could not be carried out, the remanent data (a subset of all
remanent operands) in the dynamic RAM will be overwritten by those
from the static RAM at the time the PCL is restarted.
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3.5.5 Buffer failure, data backup error, RAM test
Buffer failure
The special marker SM20.1 (buffer failure) identifies a backup error when
saving remanent data into the static RAM onboard the ZS550 hardware.
The marker goes HIGH in the following cases: During the startup of the
CL550 is noted that the system was unable to effect a proper backup of
the remanent data to static RAM on Power-Off of the previous controller
cycle. The special marker is set while processing a startup OM, and is
reset once the PLC startup has concluded.
Data backup error
The special marker SM20.5 (data backup error) is set when, at the time
of shutdown, the backup of remanent data to the FLASH Disk was faulty.
The special marker is set after Power-On, and while processing the OM5
startup module, and is reset prior to the OM1 PLC startup module.
RAM test
During the controller startup sequence, a test of the static RAM is carried
out. If the test fails, special marker SM20.1 will go HIGH, and the test
results are stored in system area S116.
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3.5.6 Startup characteristics

With regard to the controller startup, the backed-up data, the statuses of
the SM20.1 “Buffer Failure" and SM20.5 “Data Backup Error" special
markers, plus the result of the RAM test, are reflected in the table below:
RAM test Backup to Backup to Backup to SM20.1 set SM20.5 set Contents of rem. Remanent startup
static RAM, static RAM, hard disk during during S116 Start w/ data from
shutdown prog. proc. startup startup (binary) up
NOK x x NOK x x 00001xx1 No
OK NOK NOK NOK x x 00001110 No
NOK x x OK x 00000xx1 Yes Hard disk
OK NOK NOK OK x 00000110 Yes Hard disk
OK NOK OK OK 00000010 Yes Hard disk
OK OK NOK OK 00000100 Yes Hard disk
OK OK OK OK 00000000 Yes Hard disk
OK NOK OK NOK x 00001010 Yes Static RAM backup,
last program
processing
OK OK NOK NOK x 00001100 Yes Static RAM backup,
shutdown
OK OK OK NOK x 00001000 Yes Static RAM backup,
shutdown
x = don’t care
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Peripheral Operation 4-1
4. Peripheral Operation
The connection with the periphery is in each case accomplished via a
field bus system. The I/O data of the PCL is held in the dynamic RAM of
the PC (PCL and/or ZS550), and is transferred to the image of the field
bus master either in the I/O state or by command. The configured I/O
modules (slaves) are serviced from there.
PC RAM I*
Bus master Config. I Peripherals
Config. O
O*
I/O image Bus master I/O modules
of PLC I/O image (slaves)
Acyclical transfer
*
PROFIBUS-DP: Config. I/O
CAN: Config. I/O
INTERBUS-S: All I/O
The bus master creates diagnostic tables on the basis of the I/O
configuration list. The error messages and error diagnostic functions
generated in this manner depend on the bus system being used, and
must be evaluated with the aid of the bus-specific software tools.
4.1 Data consistency

For its I/O image, the field bus master uses a dual-port RAM which is
used for read and write access by both the PLC and the bus master itself.
The asynchronous access from two sides may cause the PLC to load
only part of the data of a contiguous function block from the dual-port
RAM at a given time.
Example:
The bus master wants to transfer 20 bytes of data to a slave.
After 10 bytes have been transferred, the PLC writes new data into this
memory area. This causes the remaining 10 bytes, along with new
contents, to be sent to the slave. This means that the 20 transferred
bytes of data originate in different PLC cycles. They are therefore
inconsistent!
To ensure “consistent data exchange” for specific peripheral modules,

this can be declared in the project development tools indigenous to the
individual bus systems
For our case in point, this means that before the PLC will be permitted to
write new data into the memory area, the bus master transfers the entire
20 bytes of data to the slave.
As a consequence of declaring “consistent data exchange”, data

exchange procedures slow down considerably because a data transfer
that has been started must be concluded before new information can be
written into the memory area.
Examples of data consistency:

Digital I/O modules: Byte consistency
Analog I/O modules: Word consistency
CL150 (Mini-PLC) Definable consistency ranges
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4-2 Peripheral Operation
4.2 PROFIBUS-DP
I/O configuration
The I/O configuration for the PROFIBUS-DP is accomplished with the aid
of the WinDP Configuration & Diagnostic Tool.
Data exchange
The data exchange between bus master image and peripheral devices is
limited to those slaves that have been configured.
Data consistency
Data consistency is maintained only for those bus stations that have been
appropriately configured. The data width depends on the default values
taken from the device specification files.
Peripheral errors
The PROFIBUS-DP field bus features a comprehensive diagnostic
system whose messages are made available by the bus master. The
WinDP software also incorporates the corresponding diagnostic system.
When peripheral errors have been remedied, the PROFIBUS-DP field

bus restarts automatically.
Properties
● PCL: PROFIBUS-DP protocol, to EN50170
● CL550: PROFIBUS-DPV1
● Max. 124 slaves
● Max. 244 bytes each for inputs / outputs per slave
(max. 122 bytes consistent inputs or outputs)
● Max. 8kbytes (65536 bits) each for inputs and outputs
● Baud rates: 9.6 kbit/s through 12 Mbit/s selectable on PROFIBUS-DP.
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4.3 CAN Bus (CANopen, PCL only)
I/O configuration
The I/O configuration for the CAN (Control Area Network) field bus is
accomplished with the aid of the WinCAN Configuration & Diagnostic
Tool.
Data exchange
The data exchange between bus master image and peripheral devices is
limited to those slaves that have been configured. In addition to the data
exchange with peripherals, the exchange of SDO (Service Data Object)
data with the configured slaves is possible.
Data consistency
Data consistency is ensured for each slave (as per CAN specifications).
Peripheral errors
The CAN bus continues to operate with all slaves that are error-free,
whereas slaves with active peripheral errors are not served.
Properties
● CANopen protocol, to EN50235
● Max. 30 slaves
● Max. 512 bytes (4096 bits) each for inputs and outputs
● SDO (Service Data Object) data exchange
● Baud rates: 10 kbit/s through 1 Mbit/s selectable on CAN bus.
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4.4 INTERBUS-S
I/O configuration
The INTERBUS-S provides two I/O configuration options:
● Physical addressing of inputs and outputs
● Process data description via the CMD software by Phoenix Contact.
In physical addressing, all connected slaves are addressed in ascending

order.
This addressing mode has some inherent shortcomings:
● Faulty slaves are neither recognized nor addressed.
● Modifying the bus structure by adding and/or removing bus stations
will shift the addresses of the respective next slaves in the succession.
By contrast, the process data description via the CMD software by

Phoenix Contact facilitates free addressing of the bus stations.
⇒ For PCL only: When starting the WinPanel application, physical

addressing can be disabled. This is accomplished by specifying the
“/Y32” parameter. To enable the process data description, the CMD
software is then used to perform the I/O configuration, and to load
the same into the bus master.
To load the I/O configuration into the PCI-BM-IBS bus master,
release level 4.42 and higher of the Phoenix Contact CMD software
is required because only this release level provides for the selection
of the Type IBS USC/4 (4K) interface module. In addition, an
interface adapter (Bosch order no. 1070 083 813 will be required).
⇒ For CL550 only: To load the I/O configuration into the bus master
ZS550-DP-IBS release level 4.5 or higher of the Phoenix Contact
CMD software is required. Here, the CMD software can act in both
modes, physical addressing as well as process data description. As
an interface module for the CL550, Type IBS PC 104 SC-T has to be
specified in the CMD software.
Data exchange
Data exchange in the PCL for INTERBUS-S is limited to the input range of
I0 through I511, and the output range from O0 through O511. Higher
addresses can not be used!
In the CL550 it is limited to the input range of I0 through I1023, and the
output range from O0 through O1023. Max. 512 bytes inputs/outputs can
be occupied.
⇒ Please note that in the CMD software, I0 is designated as 512, I1 as

513, etc.
In this context, physical addressing applies to all connected addresses,

whereas the use of the Phoenix Contact CMD software applies only to
configured addresses.
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Data consistency
When starting WinPanel, byte consistency can be selected in the PCL
with the use of the /Y4 start parameter. Without this entry, data
consistency is selected for the entire I/O range by default.
When specifying data consistency across the entire I/O range, it is

instructive to note that the response interval of peripherals increases with
each additional connected slave.
In any case, data consistency is configurable in the CMD software as

well.
Peripheral errors
In the event of peripheral faults on the bus, an attempt to restart
INTERBUS-S operation will be made at each STOP/RUN switchover!
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4.5 Response Intervals

Using the example of the Bosch PCL Software PLC integrated in a PC
with Intel Pentium 200 MHz processor, the table below provides a side-
by-side comparison of various bus systems in terms of response time
(interval) for the same processing task. The response times for the
CL550 are similar.
The intervals shown in the table were measured directly at the input
and/or output of a B~IO 16DI/16DO Digital I/O Compact Module, and
therefore also contain the input delays for transitions from LOW " HIGH
(approx. 3.5 ms), and from HIGH " LOW (approx. 1.5 ms).
The table provides a rough overview of the varying response intervals of

individual field bus systems in different operating modes.
Task:
Input sets output HIGH

PCL system settings:
System clock = 1 ms, Windows calculation ratio = 50 %
Transition response intervals, 0 " LOW ### 1 " HIGH ###

field bus type HIGH LOW
in ms (at input) in ms (at input)
PROFIBUS-DP 12 Mbaud 4.5 – 5.5 2.0 – 3.0
500 kbaud 6.5 – 7.5 4.0 – 5.0
CANopen 1 Mbaud 5.5 – 7.0 4.0 – 6.0
INTERBUS-S Byte consistency 7.5 – 10 7.5 – 10
Overall consist. 10.0 – 13.0 5.0 – 7.0
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Programming Basics 5-1
5. Programming Basics
Programmable memory controllers process a program whose code
describes the controller task. This is accomplished with the use of special
programming languages that can be represented and printed out in
various modes.
5.1 Programming
5.2 Programming Languages and Representations
Instruction List (IL)

The IL comprises a text-based programming language in which the
controller tasks are described in assembler notation.
Structure of Controller Instructions
Controller Instruction Comment

Operation part Operand attribute Source OPD Destination
OPD
OPP OPA SRC , DEST ; Description
Examples
U I0.0
U W -Name ,A
L B O0 ,B
T D C , M12
MUL W 1234 ,D
Ladder Diagram (LD)

When using the LD representation method, the controller tasks are
described by means of standard circuit diagram symbols.
Function Block Diagram (FBD)

When using the FBD representation method, a graphical symbol display
(flow chart) illustrates the logical links.
Sequential Function Chart (SFC)

The SFC represents a graphical programming interface, which is used to
describe the sequentially processed machine tasks in the form of a
cascade sequence. Before it can be loaded into the PLC, this
representation is then translated into the executable IL programming
language.
Structured text (ST)

Structured text programming uses a text-based programming language in
accordance with IEC 61131-3. Structured text is a high-level language
which is easy to learn, and which facilitates compact formulation or
programming tasks. Examples of its strong suits are the implementation
of complex testing or regulating tasks.
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5-2 Programming Basics
5.3 Program Structure

To provide PLC programs with a clear structure and easy readability,
structured text programming is used in conjunction with the PCL and
CL550. It is used to segment programs into segments that are
functionally related. To achieve the referred structural clarity, various
types of program modules are available, each handling specific tasks.
Actual program processing occurs cyclically, either time or interrupt-
controlled.
Section 5.8.5, contains a sample program structure.
5.4 Module Types

The controller utilizes the following module types:
• Organization modules (OM)
• Program modules
• Data modules
All modules are enabled by being invoked and/or activated in the course
of program processing. This may occur unconditionally or dependent on a
condition. The condition may be the result of a linking or compare
operation or arithmetical operation.
5.4.1 Organization modules (OM)

The organization modules perform all administrative or management
functions for the controller program. Although they are programmed in the
same manner as the program modules, only the system program invokes
organization modules. All organization modules make use of the full
instruction set of the PLC. There is no limitation to module size.
Each organization module is processed only subsequent to a defined

condition; it cannot be called in the course of program processing.
Organization modules can be divided into 7 functional groups:
OM1 Program module that is cyclically called by the system program,

and that can be used as a distribution module for the overall
program.
OM2 Non-executable definition module (initialization table) containing

definitions for the controller system (remanence limits, etc.) that
are declared by modifying certain table entries.
OM5, OM7 Start-up modules that process various program sequences

during a controller power-up or restart.
OM8 Module that is called upon shutdown; here the application can be
brought to a defined state.
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OM9 Error module which processes responses to program errors or fault

conditions.
OM18-OM25 Time-controlled processing (resolution set in OM2).
OM30-OM63 reserved
The OM1 module must be concluded with either the EP (end of program)
or EM (end of module) instruction to ensure subsequent processing of the
input/output cycle (I/O state). With the exception of the OM2, all other
organization modules can be concluded with either EP or EM, depending
on the respective tasks being carried out.
5.5 Program modules

The program modules (PM) contain program segments that are
technically and functionally interrelated. From within program modules,
any number of additional program modules and data modules may be
called. In addition, all program modules have access to the entire
command set of the PLC. The modules are not subject to a size limit.
As a rule, program modules are concluded with an End of Module (EM)

instruction. When using the EP (end of program) instruction, its
processing will be followed by a program abort, and the input/output cycle
will occur. Program processing then continues by again starting with the
OM1.
Due to the option of parameterization, the program modules may be

written independently of absolute operands. During the module call-up,
the operands required for the current processing task are transferred to
the program module in the form of parameter values.
The following parameters can be declared:

• Input parameters: Operands, constants and modules
• Output parameters: Operands
• Input/output parameters: Operands
5.5.1 Data modules

The data modules (DM) serve as storage areas for all fixed and variable
values and text blocks that are used by the program. Therefore, during
PLC program processing, the user has the option of always keeping two
data modules enabled, each of which provides up to 512 bytes of
memory capacity.
The following applies to the processing of data modules:
• Before their respective data may be accessed, the data modules must
be enabled from within the program by means of module call
instructions (i.e., CM for the 1st DM, and CX for the 2nd DM).
• Within a given organization module (OM) or program module (PM),
the data modules remain current until other data modules are enabled
by the program.
• After the return to the primary module, the data modules active at the
time of the call-up of the base module are again activated.
• When the OM1 (cyclical program processing), and the start-up
modules OM5 and OM7 are called, no data module is active as yet.
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5.6 Program Processing

The application program is processed cyclically, and can be interrupted
by time-controlled instructions.
Start,
startup,
initialization
Application
program
processing
I/O state,
5.6.1 Cyclical program processing

Once the PCL has been initialized successfully, the actual program cycle
begins in OM1 with the first command of the application program. The
cycle time is measured from and until point in time.
Subsequent to program processing, the processing of inputs and outputs

and servicing of communication partners occurs before the cyclical
processing continues.
5.6.2 Error interrupt controlled processing

During cyclical program processing, the sequence may in certain
circumstances be interrupted by program errors at each instruction. If this
is the case, program processing branches into the OM9. The program
contained in this module is processed, followed by returning the controller
to a stable state prior to shutdown.
5.6.3 Time Controlled Interrupts

In the course of cyclical program processing, the program sequence can
be interrupted by elapsed times that can be defined in the time matrix. In
this process, interruption points are only module changes (calling a data
module does not rate as a module change). Program processing
branches into an OM that is directly assigned to time-controlled
processing, processes the program contained therein, and then returns to
the interruption point.
In the event that the user avails himself of program module calls from
within time OMs, he should disable any other time-controlled
processes,also see Section 5.16, Time Controlled Interrupts
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5.7 Time Monitoring

The entire program processing, i.e., the PLC cycle, is subject to time
monitoring. Two different monitoring times are available for this purpose.
The hardware watchdog is strictly a security function. By default, the time

for this monitoring function is set to 2.5 sec, and can neither be changed,
nor can the function be disabled. Once this time has elapsed, remanent
data can no longer be saved to the hard disk.
Cycle time monitoring comprises a security function that can be

individually adjusted. Appropriate selection functions are provided in the
OM2 initialization table (see also Section 5.9, Initialization Table for PLC
and CL500). If the OM2 is not linked to the controller program, this time
will have a default value of 1.5 sec.
⇒ When using the OM8 shutdown module (see also Section 5.12,
Shutdown module (PLC only)), the cycle time is disabled while the
module is processed. However, the hardware still remains active
during OM8 processing.
Remanent operands are saved to hard disk even if the hardware cycle
time in the OM8 has expired (timed out. As a prerequisite, the UPS must
be appropriately equipped.
1070 072 189 - 108 (02.09) GB

5.8 I/O state

The I/O state is always started after an EP (end of program) instruction,
and processes the image update for peripheral operation, the processing
of fixation and that of times / timers.
5.8.1 Image updating for peripheral operation

In the I/O state, which occurs between the EP instruction and the start of
the OM1, the PCL transfers the fixation masks and the output image to
the periphery task. This is where image updating takes place. With image
updating concluded, the periphery task again addresses the PCL for the
purpose of transferring the new input image.
5.8.2 Fixing inputs, outputs & markers

The fixation imposes a fixed status mask on inputs, outputs and markers.
The resulting fixation masks are placed over the I/O images and markers
in each I/O state.
The fixation data is saved to hard disk immediately on being modified,

and are again loaded from there upon start-up. All modifications to the
fixation masks are immediately stored on the hard disk.
A reset of the fixation can be accomplished with the Programming Unit

(PG) or via an interface.
The special marker SM20.4 indicates whether a fixation is active, i.e., at

least one bit is fixed.
Fixed inputs
Prior to entering the OM1 of the PLC program, the loaded status (input
image) is covered by the fixation mask. As a consequence, all input
queries return the status taken from the fixation mask.
Fixed outputs
Prior to entering the OM1 of the PLC program, the output status (output
image) is covered by the fixation mask. As a consequence, all process
outputs have the status imposed by the fixation mask. However, the
queries within the PLC program will return the fixed status only until the
program overwrites the outputs.
Fixed markers
Prior to entering the OM1 of the PLC program, the status of the markers
from the preceding PLC cycle is covered by the fixation mask. However,
the queries within the PLC program will return the fixed status only until
the program overwrites the markers.
1070 072 189 - 108 (02.09) GB

5.8.3 Updating timers

Depending on the selected matrix (resolution), the timers are updated
also during the I/O state. Accordingly, the accuracy of the timer circuits is
equal to the selected time matrix plus a maximum of one PLC cycle,
including I/O state. Therefore, to attain the highest timing accuracy, the
smallest possible time-base (resolution) should be used.
Startup modules
Two startup modules, OM5 and OM7, are available to handle the
program start. If a startup module is linked with the PLC program, it will
be automatically processed during the startup routine of the controller.
The startup is governed by the following criteria:

• OB5: Startup module following restart, always processed subsequent
to PCL Power-On (starting WinPanel). In this case, the OM5 is
processed upon changing the operating mode via a Stop/Run
command.
• OM7: Startup module subsequent to restart; is always processed after
a Stop/Run change of operating mode, provided that this is not the
first startup after Power. The restart criterion is met if the PLC program
processing has progressed to the OM1 at least once.
If "Remanent Operation" has been selected in the OM2, the remanence

of operators will be retained in both cases.
Program loading
Program loading is followed by processing the OM7. In conjunction with
the two trigger pulses, this facilitates the selection of any possible startup
option.
With regard to the instruction set, no restrictions exist in the startup

module. However, in remanent operation it is not possible to preselect
any nonremanent operands in the startup module.
A cycle time ceiling that can be software defined via OM2, DW2/DW5 has
not yet been implemented in the startup modules. This means that the
startup modules permit the starting and processing of initialization
routines that are independent of cycle time monitoring.
During startup module processing, the software cycle time monitoring

function (1.5 sec) is enabled. However, it can be disabled via OM2, DW2,
Bit1.
As a concluding instruction for the modules, the EM or EP command can

be used.
In the event that, during the processing of startup OMs, program modules
are called, the close instructions of such program modules will have the
established meaning:
EM: Return to the startup module that included the call.
EP: Cancel, continue with OM1.
1070 072 189 - 108 (02.09) GB

5.8.4 Cyclical processing

Refer to section 5.6 , Program Processing.
5.8.5 Application program structure

With the aim of providing a clear overview of the basic organization of
program management, the following diagram shows an example of the
program structure.
Program startup, one-time only

OM5 / OM7
Program
EM
Program processing, cyclical

OM1
→ FC1
↑ CM PM1
← CM 1st DM 1. DM
CM 2nd DM 2. DM
EM
→ PM2
CM PM2 → PM3
← CM PM3,2
P0 I1 A P0
P1 O1 = P1
←
CM PM3,2 EM
P0 I10
P1 O10
←
EM
→ PM4
CM PM4 → PM5
← CM PM5 → PM6
← CM PM6
EM ←
EM
PE EM
↑ I/O state
← Module nesting depth →
Level 1 2 3 4 .....n.... 63
Time-controlled program processing

Processing always commences subsequent to the change of module (not module call) that follows the
expiry of the associated time interval.
OM18-OM25
Program
EM
Shutdown, one-time only

Processing always occurs upon controller shutdown.
OM8
Program
EM
Program processing subsequent to program error, one-time only

Processing always occurs upon the occurrence of the branching flag (triggering criterion).
OM9
Program
EM
1070 072 189 - 108 (02.09) GB

5.9 OM2 Initialization Table for PCL and CL550

The OM2 initialization module comprises a system initialization table that
is linked with the PLC program as required. You will find a preconfigured
module named OM2PCL on the WinSPS path of your PG programming
unit.
A PLC program working without an OM2 utilizes preselected default

values that are sufficiently useful for many applications.
Deviations from the preselected system defaults are declared in the OM2
through manipulation of the entered values. It is essential that the user
neither removes nor adds DEFW instructions.
This may be used for example, to shift remanence limits, set cycle time
limits, etc.
The time matrix definition for the time OMs is also handled in the OM2.
The declarations and definitions stored in the OM2 are adopted by the
system upon Power-ON or in the case of a STOP/RUN command, even
before processing a startup OM that may be present; a part of the OM2 is
copied into the system area.
The following printout of an OM2 exemplifies all options of exercising

control over the system initialization:
1070 072 189 - 108 (02.09) GB

5.9.1 Printout of OM2PCL initialization table
;*************************************************************************
;*** ***
;*** I N I T I A L I Z A T I O N T A B L E ***
;*** ***
;*** 'P C L' S O F T P L C ***
;*** ***
;*************************************************************************
;*** Last modification: 25.04.00, zi ***
;*************************************************************************
;
;*************************************************************************
; OM2 : PCL - Initialization table
;*************************************************************************
;
; - Must be integrated in each application program
; that uses different default settings.
;
; - If no OM2 entry is made in the symbol file,
; default settings will be used.
;
; I M P O R T A N T N O T E , please observe in any case
; ============================================================
;
; Each change of data words (W) in forbidden address ranges
; ====
; may result in undefined PLC system performance.
;
;*************************************************************************
;
;DW 1: empty
;--------------
DEFW W 16#0000
;

;--------------------------------------------------------------------------
;
DEFW W 2#0000000000000000
; *******|***||||* *: not used
; | |||+------- Check nominal cycle time
; | ||+-------- Remanent start if possible
; | |+--------- Suppress cycle time monitoring
; | | during startup
; | +---------- Max. I/O range for MMIMADAP diagnostics
; +-------------- Copy data module to data buffer
;

;--------------------------------------------------------------------------
;
DEFW W 2#0000000000000000
; *********||||||| *: not used
||||||+------ Markers \ remanent areas/ranges
|||||+------- Timers \ for cyclical backup
||||+-------- Counters \into static RAM, as
|||+--------- Data field /per defined remanence
||+---------- Data buffer / limits
|+----------- Data modules /
+------------ Cyclical backup of marked areas/ranges.
;
1070 072 189 - 108 (02.09) GB

;DW 4: empty
;--------------
DEFW W 16#0000
;
;DW 5: Maximum cycle time (entries permitted)

;--------------------------------------------------------------------------
; Entries as multiples of time base 10 ms of 1 and 150
; (10 ms to 1500 ms) for cycle time monitoring.
; Function execution at DW2 / Bit 1 = 1.
;
DEFW W 150
;
;DW 6: Copy data module to data buffer (entries permitted)

;--------------------------------------------------------------------------
; Entry of 0 - 1023 (data module number 0 - 1023) possible.
; (Function execution at DW 2 / Bit 8 = 1).
;
DEFW W 0
;

;--------------------------------------------------------------------------
;
DEFW W 128
;

;--------------------------------------------------------------------------
;
DEFW W 128
;

;--------------------------------------------------------------------------
; 4096 = Remanence from marker byte M4096/marker bit M4096.0;
;
DEFW W 4096
;
;$P

;--------------------------------------------------------------------------
;
DEFW W 256
;
;
1070 072 189 - 108 (02.09) GB

; Definition of Timer OMs (entries permitted)

; ========================
; Entries between 1 and 65535 possible as a multiplier of the 10 ms
; basic timing.
; e.g., 0 = no timer-based processing
; 11 = 11 x 10 ms = 110 ms interval of processing time
;
;DW 11: Timer OM18
;----------------
DEFW W 0
;DW 12: Timer OM19

;----------------
DEFW W 0
;DW 13: Timer OM20

;----------------
DEFW W 0
;DW 14: Timer OM21

;----------------
DEFW W 0
;DW 15: Timer OM22

;----------------
DEFW W 0
;DW 16: Timer OM23

;----------------
DEFW W 0
;DW 17: Timer OM24

;----------------
DEFW W 0
;DW 18: Timer OM25

;----------------
DEFW W 0
;
;$P
;DW 19 - DW 32: empty

;--------------------
DEFW W 16#0000 ;DW19
DEFW W 16#0000 ;DW20
DEFW W 16#0000 ;DW21
DEFW W 16#0000 ;DW22
DEFW W 16#0000 ;DW23
DEFW W 16#0000 ;DW24
DEFW W 16#0000 ;DW25
DEFW W 16#0000 ;DW26
DEFW W 16#0000 ;DW27
DEFW W 16#0000 ;DW28
DEFW W 16#0000 ;DW29
DEFW W 16#0000 ;DW30
DEFW W 16#0000 ;DW31
DEFW W 16#0000 ;DW32
1070 072 189 - 108 (02.09) GB


;--------------------------------------------------------------
Limit applies only to backup into static RAM; this area
takes precedence over the data field, the entire remainder
of which is backed up to hard disk for remanent storage;
;
DEFW W 0
;

;--------------------
DEFW W 16#0000 ;DW34
DEFW W 16#0000 ;DW35
DEFW W 16#0000 ;DW36
DEFW W 16#0000 ;DW37
DEFW W 16#0000 ;DW38
DEFW W 16#0000 ;DW39
DEFW W 16#0000 ;DW40
DEFW W 16#0000 ;DW41
DEFW W 16#0000 ;DW42
DEFW W 16#0000 ;DW43
DEFW W 16#0000 ;DW44
DEFW W 16#0000 ;DW45
DEFW W 16#0000 ;DW46
DEFW W 16#0000 ;DW47
DEFW W 16#0000 ;DW48
DEFW W 16#0000 ;DW49
DEFW W 16#0000 ;DW50
DEFW W 16#0000 ;DW51
DEFW W 16#0000 ;DW52
DEFW W 16#0000 ;DW53
DEFW W 16#0000 ;DW54
DEFW W 16#0000 ;DW55
DEFW W 16#0000 ;DW56
DEFW W 16#0000 ;DW57
DEFW W 16#0000 ;DW58
DEFW W 16#0000 ;DW59
DEFW W 16#0000 ;DW60
DEFW W 16#0000 ;DW61
DEFW W 16#0000 ;DW62
DEFW W 16#0000 ;DW63
DEFW W 16#0000 ;DW64
DEFW W 16#0000 ;DW65
DEFW W 16#0000 ;DW66
DEFW W 16#0000 ;DW67
DEFW W 16#0000 ;DW68
DEFW W 16#0000 ;DW69
DEFW W 16#0000 ;DW70
DEFW W 16#0000 ;DW71
DEFW W 16#0000 ;DW72
DEFW W 16#0000 ;DW73
DEFW W 16#0000 ;DW74
DEFW W 16#0000 ;DW75
DEFW W 16#0000 ;DW76
DEFW W 16#0000 ;DW77
DEFW W 16#0000 ;DW78
DEFW W 16#0000 ;DW79
DEFW W 16#0000 ;DW80
DEFW W 16#0000 ;DW81
DEFW W 16#0000 ;DW82
DEFW W 16#0000 ;DW83
DEFW W 16#0000 ;DW84
DEFW W 16#0000 ;DW85
DEFW W 16#0000 ;DW86
DEFW W 16#0000 ;DW87
DEFW W 16#0000 ;DW88
1070 072 189 - 108 (02.09) GB

DEFW W 16#0000 ;DW89

DEFW W 16#0000 ;DW90
DEFW W 16#0000 ;DW91
DEFW W 16#0000 ;DW92
DEFW W 16#0000 ;DW93
DEFW W 16#0000 ;DW94
DEFW W 16#0000 ;DW95
DEFW W 16#0000 ;DW96
DEFW W 16#0000 ;DW97
DEFW W 16#0000 ;DW98
DEFW W 16#0000 ;DW99
DEFW W 16#0000 ;DW100
DEFW W 16#0000 ;DW101
;$P
;
; !!! Internal system memory data !!!
; ===========================================
;
; The following default settings must not be changed.
; ===================================================
;Default value for data words DW 102 - DW 127 = 16#0000

;----------------------------------------------------------
DEFW W 16#0000 ;DW102
DEFW W 16#0000 ;DW103
DEFW W 16#0000 ;DW104
DEFW W 16#0000 ;DW105
DEFW W 16#0000 ;DW106
DEFW W 16#0000 ;DW107
DEFW W 16#0000 ;DW108
DEFW W 16#0000 ;DW109
DEFW W 16#0000 ;DW110
DEFW W 16#0000 ;DW111
DEFW W 16#0000 ;DW112
DEFW W 16#0000 ;DW113
DEFW W 16#0000 ;DW114
DEFW W 16#0000 ;DW115
DEFW W 16#0000 ;DW116
DEFW W 16#0000 ;DW117
DEFW W 16#0000 ;DW118
DEFW W 16#0000 ;DW119
DEFW W 16#0000 ;DW120
DEFW W 16#0000 ;DW121
DEFW W 16#0000 ;DW122
DEFW W 16#0000 ;DW123
DEFW W 16#0000 ;DW124
DEFW W 16#0000 ;DW125
DEFW W 16#0000 ;DW126
DEFW W 16#0000 ;DW127
DEFW W 16#0000 ;DW128
;**************************************************************************
EM
1070 072 189 - 108 (02.09) GB

5.9.2 Printout of OM2CL550
;*************************************************************************
;*** ***
;*** I N I T I A L I Z A T I O N T A B L E ***
;*** ***
;*** 'Z S 5 5 0' ***
;*** ***
;*************************************************************************
;*** Last modification: 25.04.00, zi ***
;*************************************************************************
;
;*************************************************************************
; OM2 : ZS550 – Initialization table
;*************************************************************************
;
; - Must be integrated in each application program
; that uses different default settings.
;
; - If no OM2 entry is made in the symbol file,
; default settings will be used.
;
; I M P O R T A N T N O T E , please observe in any case
; ============================================================
;
; Each change of data words (W) in forbidden address ranges
; ====
; may result in undefined PLC system performance.
;
;*************************************************************************
;
;DW 1: empty
;--------------
DEFW W 16#0000
;
;DW 2: Initialization flag (entries permitted)

;--------------------------------------------------------------------------
;
DEFW W 2#0000000000000000
; *******|***||||* *: not used
; | |||+------- Check nominal cycle time
; | ||+-------- Remanent start if possible
; | |+--------- Suppress cycle time monitoring
; | | during startup
; | +---------- min. IO range for MMIMADAP diagnostics
; +-------------- Copy data module to data buffer
;

;--------------------------------------------------------------------------
;
DEFW W 2#0000000000000000
; *********||||||| *: not used
||||||+------ Markers \ remanent areas/ranges
|||||+------- Timers \ for cyclical backup
||||+-------- Counters \into static RAM, as
|||+--------- Data field /per defined remanence
||+---------- Data buffer / limits
|+----------- Data modules /
+------------ Cyclical backup of marked areas/ranges.
;
1070 072 189 - 108 (02.09) GB

;DW 4: Error responses (entries permitted)

;--------------------------------------------------------------------------
; Entry 0 = If error, DO NOT execute system stop.
; Entry 1 = If error, execute system stop.
;
DEFW W 2#0000000000000000
; *************||| *: not used
; ||+------ Missing device specification file
; |+------- Slave error, periphery
; +-------- Bus error
;
;DW 5: Maximum cycle time (entries permitted)

;--------------------------------------------------------------------------
; Entries as multiples of time base 10 ms of 1 and 150
; (10 ms to 1500 ms) for cycle time monitoring.
; Function execution at DW2 / Bit 1 = 1.
;
DEFW W 150
;
;DW 6: Copy data module to data buffer (entries permitted)

;--------------------------------------------------------------------------
; Entry of 0 - 1023 (data module number 0 - 1023) possible.
; (Function execution at DW 2 / Bit 8 = 1).
;
DEFW W 0
;

;--------------------------------------------------------------------------
;
DEFW W 128
;

;--------------------------------------------------------------------------
;
DEFW W 128
;

;--------------------------------------------------------------------------
; 4096 = Remanence from marker byte M4096/marker bit M4096.0;
;
DEFW W 4096
;
;$P

;--------------------------------------------------------------------------
;
DEFW W 256
;
;
1070 072 189 - 108 (02.09) GB

; Definition of Timer OMs (entries permitted)

; ========================
; Entries between 1 and 65535 possible as a multiplier of the 10 ms
; basic timing.
; e.g., 0 = no timer-based processing
; 11 = 11 x 10 ms = 110 ms interval of processing time
;
;DW 11: Timer OM18
;----------------
DEFW W 0
;DW 12: Timer OM19

;----------------
DEFW W 0
;DW 13: Timer OM20

;----------------
DEFW W 0
;DW 14: Timer OM21

;----------------
DEFW W 0
;DW 15: Timer OM22

;----------------
DEFW W 0
;DW 16: Timer OM23

;----------------
DEFW W 0
;DW 17: Timer OM24

;----------------
DEFW W 0
;DW 18: Timer OM25

;----------------
DEFW W 0
;

;--------------------
DEFW W 16#0000 ;DW19
DEFW W 16#0000 ;DW20
DEFW W 16#0000 ;DW21
DEFW W 16#0000 ;DW22
DEFW W 16#0000 ;DW23
DEFW W 16#0000 ;DW24
DEFW W 16#0000 ;DW25
DEFW W 16#0000 ;DW26
DEFW W 16#0000 ;DW27
DEFW W 16#0000 ;DW28
DEFW W 16#0000 ;DW29
DEFW W 16#0000 ;DW30
DEFW W 16#0000 ;DW31
DEFW W 16#0000 ;DW32

;--------------------------------------------------------------
Limit applies only to backup into static RAM; this area
takes precedence over the data field, the entire remainder
of which is backed up to hard disk for remanent storage;
;
DEFW W 0
1070 072 189 - 108 (02.09) GB


;--------------------
DEFW W 16#0000 ;DW34
DEFW W 16#0000 ;DW35
DEFW W 16#0000 ;DW36
DEFW W 16#0000 ;DW37
DEFW W 16#0000 ;DW38
DEFW W 16#0000 ;DW39
DEFW W 16#0000 ;DW40
DEFW W 16#0000 ;DW41
DEFW W 16#0000 ;DW42
DEFW W 16#0000 ;DW43
DEFW W 16#0000 ;DW44
DEFW W 16#0000 ;DW45
DEFW W 16#0000 ;DW46
DEFW W 16#0000 ;DW47
DEFW W 16#0000 ;DW48
DEFW W 16#0000 ;DW49
DEFW W 16#0000 ;DW50
DEFW W 16#0000 ;DW51
DEFW W 16#0000 ;DW52
DEFW W 16#0000 ;DW53
DEFW W 16#0000 ;DW54
DEFW W 16#0000 ;DW55
DEFW W 16#0000 ;DW56
DEFW W 16#0000 ;DW57
DEFW W 16#0000 ;DW58
DEFW W 16#0000 ;DW59
DEFW W 16#0000 ;DW60
DEFW W 16#0000 ;DW61
DEFW W 16#0000 ;DW62
DEFW W 16#0000 ;DW63
DEFW W 16#0000 ;DW64
DEFW W 16#0000 ;DW65
DEFW W 16#0000 ;DW66
DEFW W 16#0000 ;DW67
DEFW W 16#0000 ;DW68
DEFW W 16#0000 ;DW69
DEFW W 16#0000 ;DW70
DEFW W 16#0000 ;DW71
DEFW W 16#0000 ;DW72
DEFW W 16#0000 ;DW73
DEFW W 16#0000 ;DW74
DEFW W 16#0000 ;DW75
DEFW W 16#0000 ;DW76
DEFW W 16#0000 ;DW77
DEFW W 16#0000 ;DW78
DEFW W 16#0000 ;DW79
DEFW W 16#0000 ;DW80
DEFW W 16#0000 ;DW81
DEFW W 16#0000 ;DW82
DEFW W 16#0000 ;DW83
DEFW W 16#0000 ;DW84
DEFW W 16#0000 ;DW85
DEFW W 16#0000 ;DW86
DEFW W 16#0000 ;DW87
DEFW W 16#0000 ;DW88
DEFW W 16#0000 ;DW89
DEFW W 16#0000 ;DW90
DEFW W 16#0000 ;DW91
DEFW W 16#0000 ;DW92
DEFW W 16#0000 ;DW93
DEFW W 16#0000 ;DW94
DEFW W 16#0000 ;DW95
DEFW W 16#0000 ;DW96
DEFW W 16#0000 ;DW97
DEFW W 16#0000 ;DW98
DEFW W 16#0000 ;DW99
DEFW W 16#0000 ;DW100
DEFW W 16#0000 ;DW101
1070 072 189 - 108 (02.09) GB

; !!! Internal system memory data !!!

; ===========================================
;
; The following default settings must not be changed.
; ===================================================================
;Default value for data words DW 102 - DW 127 = 16#0000

;----------------------------------------------------------
DEFW W 16#0000 ;DW102
DEFW W 16#0000 ;DW103
DEFW W 16#0000 ;DW104
DEFW W 16#0000 ;DW105
DEFW W 16#0000 ;DW106
DEFW W 16#0000 ;DW107
DEFW W 16#0000 ;DW108
DEFW W 16#0000 ;DW109
DEFW W 16#0000 ;DW110
DEFW W 16#0000 ;DW111
DEFW W 16#0000 ;DW112
DEFW W 16#0000 ;DW113
DEFW W 16#0000 ;DW114
DEFW W 16#0000 ;DW115
DEFW W 16#0000 ;DW116
DEFW W 16#0000 ;DW117
DEFW W 16#0000 ;DW118
DEFW W 16#0000 ;DW119
DEFW W 16#0000 ;DW120
DEFW W 16#0000 ;DW121
DEFW W 16#0000 ;DW122
DEFW W 16#0000 ;DW123
DEFW W 16#0000 ;DW124
DEFW W 16#0000 ;DW125
DEFW W 16#0000 ;DW126
DEFW W 16#0000 ;DW127
DEFW W 16#0000 ;DW128
;**************************************************************************
EM
1070 072 189 - 108 (02.09) GB

5.10 Module Reference List

The module reference list comprises a Table of Contents listing the
modules integrated in the PLC program. The list contains information
about module attendance, module size and module start address.
To extract this data, special instructions are available to the user.
⇒ The instructions used to verify module attendance, module size and

module start address of OMs and PMs can be used only with the
WinSPS v3.0 and WinPanel v1.9 and higher.
5.10.1 Module attendance
Examples
; Check module attendance
;-------------------------
; Checks for the existence of modules OM8, DB8, and FC8.
; direct addressing
A OM8 ; OM8 present?
A DM8 ; DB8 present?
A FC8 ; PM8 present?
; indirect addressing
L D 8,A ; load module No. in register A
A OM[A] ; OM8 present?
A DM[A] ; DB8 present?
A PM[A] ; PM8 present?
5.10.2 Module size
Examples
; Extract module size
;---------------------
; Extracts module lengths of modules OM8, DM8, and PM8.
; direct addressing
L D OM8,A ; size of OM8 in register A
L D DM8,A ; size of DM8 in register A
L D PM8,A ; size of DM8 in register A
L D 8,A ; load module No. in register A
L D OM[A],B ; size of OM8 in register B
L D DM[A],B ; size of DM8 in register B
L D PM[A],B ; size of PM8 in register B
1070 072 189 - 108 (02.09) GB

5.10.3 Module start address
Examples
; Read module start address
;----------------------------
; Extracts module start addresses for modules OM8, DB8, and F8.
; direct addressing
L D &OM8,A ; start address for OM8 in register A
L D &DB8,A ; start address for DB8 in register A
L D &FC8,A ; start address for FC8 in register A
L D 8,A ; Baustein-Nr. in Register A laden
L D &OM[A],B ; start address for OM8 in register B
L D &DM[A],B ; start address for DB8 in register B
L D &FC[A],B ; start address for FC8 in register B
1070 072 189 - 108 (02.09) GB

5.11 Module Header

The module header contains information about the following:
• Module start address
• Module size
• Module version number, generated by the WinSPS module header
editor
• Length of module name (currently = max. 8)
• Module name in string notation
The user can employ a special instruction to evaluate this data. The
function of this instruction is explained in the following example.
⇒ The instructions used to check module headers can be used only

with the WinSPS v3.0 and WinPanel v1.9 and higher.
Example
; Write module header contents on marker
;-----------------------------------------
; 20 bytes of the FC100 module header shall be stored
; from marker M20 and up.
; Number of bytes to be read must be in register C.

L D 20,C
; Writing 20 bytes of header information onto an operand.

; Due to double-word processing, the operand start address
; must be a multiple of 4.
L D FC100,M20 ; 20 bytes save FC100 header contents, M20 & up.
; 4 bytes (M20-M23): Start address
; 4 bytes (M24-M27): Size in bytes
; 2 bytes (M28+M29): Version no. from header
; 1 Byte (M30): Length n of module name
; 8+1Byte (M31-M39): Module name string,
; concluding with`\0´.
; 2 Bytes : PXL/PXO code:
; 1 = secret
; 0 = public
The user can utilize this command sequence to read the module header
information of OMs, PMs and DMs. It should be noted that DMs do not
feature version identifiers in the module header, i.e., the respective bytes
have a content of = 0.
1070 072 189 - 108 (02.09) GB

5.12 OM8 Shutdown module (PCL only)

This module is processed once only in the event that the PCL is shut
down via WinPanel or via the shutdown signal of the UPS (uninterruptible
power supply). The shutdown signal is triggered by the Bosch BT150/155
and BT200/205 PC-based Control Terminals.
During OM8 processing, inputs can be read directly from the dual-port
RAM of the bus master, and outputs can be written to that location.
OM8 features and functions:

• The OM8 is called independently of the RUN/STOP controller status.
• Without exception, while in RUN mode, the program cycle is
concluded or the I/O state ended before the OM8 is called.
• The remanence areas defined in the OM2 and the data modules
identified with remanence identifier E in the symbol file are backed up
to the static RAM of the PCI-BMxxx. This action occurs independent of
the OM8, that is, if the OM8 is not present, it will also occur
subsequent to OM8 processing.
• Module management is active, i.e., other program and data modules
can be called.
• In the OM8, the processing of application times, cycle time monitoring
(definition in OM2 or 1.5 sec default), and the timer for invoking timed
OMs are disabled. The hardware watchdog of approx. 2.5 sec
continues to be active.
• After the OM8 has been processed, an I/O image exchange no longer
occurs.
• The READY relay contact (external control elements) is not affected. If
the PCL is in RUN mode at the time the shutdown command is
received, the contact will be opened only once the OM8 has been
processed. If it is in STOP mode, the contact will remain open during
OM8 processing.
• The PLC status can be read from the system area S76 (0 = RUN, 1 =
STOP, READY contact closed/open), facilitating possible responses.
⇒ Please note that the hardware watchdog (approx. 2.5 sec) comprises
strictly a security function, and that it will terminate the PLC
program processing with instant effect. For this reason, the user
must ascertain that the processing time of the OM8, when
processed with the use of a program loop, does not exceed this
interval length. However: Even if the hardware watchdog times out,
this is in any case followed by a backup of the remanent data.
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5.13 OM9 Error Module

This module is processed once only in the event that a program error is
noted that would normally cause an immediate stop of the central
processing control unit. To serve the intended purpose, the OM9 must be
linked with the PLC program.
The triggering criteria are defined errors that can be interpreted by setting
a special marker bit in SM14 / SM15 and in SM28 / SM29.
Upon calling the OM9, the cycle time monitoring function is restarted with
the defined value (definition in OM2 or default value of 1.5 sec). While the
module is being processed, countermeasures for possible error
occurrences can be programmed.
For example, certain data, including the special error markers, can be
moved to nonvolatile areas.
Once the OM9 error module has been processed, the PCL enters STOP
mode.
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5.14 Fixation
The PCL provides the option to fix operands.
In contrast to the "Control" programming device function, this option can

be used to fix operands permanently to specific bit statuses or values.
Operands suitable for fixation:

• Inputs
• Outputs
• Marker
Remanence of fixation
An existing fixation is retained in the following cases:
• Always after a STOP/RUN change in operating mode.
• Always after reloading.
• Always after Power-Off/On cycle.
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5.15 Parameterized Modules

When a program module is called up, up to 63 parameter values can be
transferred. The number of transferred parameters is declared with the
module start command. This is followed by the parameters, starting with
P0.
Example of parameter transfer

DEF I0.0,-Start
DEF M0,-Sollwert
DEF M2,-Istwert
DEF O0.0,-Soll_Ist
DEF O0.1,-keinErg
;
CM -SOLL_IST,5
;
; +--------------------+
P0 -Start ; | BOOL VAR_INPUT | Start of function
P1 W -Sollwert ; | WORD VAR_IN_OUT | Expected piece count
P2 W -Istwert ; | WORD VAR_INPUT | Current piece count
P3 -Soll_Ist ; | BOOL VAR_IN_OUT | Nominal value attained
P4 -keinErg ; | BOOL VAR_OUTPUT | No valid reading
; +--------------------+
Utilization of parameters in called-up module
+-----------------------------------------------------------------------+
!Parameter header
+-----------------------------------------------------------------------+
P0 BOOL Start VAR_INPUT Start of function
P1 WORD Sollwert VAR_IN_OUT Expected piece count
P2 WORD Istwert VAR_INPUT Current piece count
P3 BOOL Soll_Ist VAR_IN_OUT Nominal value attained
P4 BOOL keinErg VAR_OUTPUT No valid reading
+ ----------------------------------------------------------------------+
! Program module file
+ ----------------------------------------------------------------------+
; Compare values
A -Start P0 Start of function
JPCI keinVergleich
L W -Sollwert,A P1 Expected piece count
CPLA W -Istwert,A P2 Current piece count
A Z ; Result=0 -> values are equal
= -Soll_Ist P3 Nominal value attained
R -keinErg P4 No valid reading
keinVergleich:
; Delete compare result

AN -Start P0 Start of function
R -Soll_Ist P3 Nominal value attained
S -keinErg P4 No valid reading
EM
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5.16 Time Controlled Interrupts

The PCL provides the option of time-controlled program interrupts.
Time-controlled interrupts are supported by 8 timer OMs that interrupt the

program in accordance with predefined intervals to activate one of these
modules. The timer resolution (matrix) is defined in the OM2.
For each time the timer OM is called, the following must be true:
1. The designated time interval has expired.
2. Sequential processing has reached a change of module.
Defined module changes are an executed module call, as well as an end

of module. Neither a DM call-up nor an EP instruction is considered a
change of module.
Within the group of timer interrupts, the highest priority is given to the
interrupt that is assigned to the lowest OM number.
OM18 = highest priority, OM25 = lowest priority
⇒ Because some programs utilize the register contents across module

boundaries (e.g., MADAP with the KETTEPCL program module), the
register contents should always be backed up upon entry into a
timer OM, and again updated prior to the end of module
(PUSH/POP).
Instructions for handling time interrupts

The time-controlled interrupts (TI) are assigned an interrupt mask. This
mask can be written to and loaded with the use of the TIM and LIM
instructions, respectively. Each possible interrupt corresponds to one bit
in this mask. When a bit is HIGH, this means that the respective interrupt
has been enabled; when the bit is LOW, the interrupt is disabled.
To perform the actual enabling of the interrupts declared in the mask, the
additional instruction EAI (Enable All Interrupts) must be issued. A
general disabling of the interrupts without influencing the mask is
accomplished with the DAI (Disable All Interrupts) instruction.
Incoming interrupts cause an entry in the corresponding interrupt register

also in cases where the respective interrupts have been masked. Here
again, a bit is assigned to each interrupt.
When the interrupt is executable, i.e., enabled, calling the interrupt OM

automatically deletes the bit in the interrupt register.
When the interrupt is disabled, the bit remains in the interrupt register,
and the interrupt awaits its being enabled.
The interrupt register can be loaded with the use of the LAI (Load All
Interrupts) instruction, and active interrupts can be deleted with the RAI
(Reset All Interrupts) instruction.
A change of operating mode, i.e., STOP/RUN or Power-Off/On, deletes

all active interrupts.
By default, all time controlled interrupts are enabled.
During the startup procedure, i.e., processing of OM5 and OM7, all
interrupts remain disabled.
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5.17 Application Stack

The application stack (AST) comprises a pushdown-pop-up memory
stack with a storage depth of 256 words, using FILO (first-in-last-out)
processing.
The PUSH and POP instructions facilitate a word-by-word data transfer

between the registers and the contents of the application stack.
Example
PUSH A ;Shift contents of register A to applic. stack
PUSH B ;Shift contents of register B to applic. stack
PUSH C ;Shift contents of register C to applic. stack
PUSH D ;Shift contents of register B to applic. stack
POP D ;Load uppermost value from applic. stack into Reg. D

POP C ;Load uppermost value from applic. stack into Reg. C
POP B ;Load uppermost value from applic. stack into Reg. B
POP A ;Load uppermost value from applic. stack into Reg. A
In the event of an application stack underflow, special marker S28.4 will

be set to HIGH.
In the case of an application stack overflow, special marker S28.5 will be

set to HIGH.
Both application stack (AST) underflow and overflow conditions will cause
the central processing module to enter STOP mode, returning an error
message pointing to the cause of the error.
»The application stack is flushed after each EP
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Addressing Conventions 6-1
6. Addressing Conventions
6.1 Operand & Module Identifiers, Module List
Operand & module identifiers

Abbrev. indexed Operand Access / Data width Image update
A, B, C, D Standard arithmetical X, B, W, D, R, L
registers
I I[R] Input Image/ in I/O state
X, B, W, D, R, L
Q Q[R] Output Image/ in I/O state
X, B, W, D, R, L
M M[R] Marker X, B, W, D, R, L
SM SM[R] Special marker X, B, W, D, R, L
T T[R] Timer X (status), W (value)
C C[R] Counter X (status), W (value)
D D[R] Data word, 1st current DM X, B, W, D, R, L
DX DX[R] Data word, 1nd current DM
DB DB[R] Data buffer X, B, W, D, R, L
DF DF[R] Data field X, B, W, D, R, L
S S[R] System data range X, B, W, D, R, L
P P[R] Parameter X, B, W, D
FI FIFO max. 512 bytes
TI Time-controlled interrupt
b#www Constant X, B, W, D, R, L
DM DM[R] Data module CM DMnn ; calls 1st DM
BX DMnn ; calls 2nd DM
PM PM[R] Program module
In the above enumeration, R is replaced by X = bit, B = byte, W = word,
the register IDs A, B, C or D. D = double word, R = REAL, L = LREAL
Module list
The PCL manages the following modules:
Name Signal Comment

OM1 Cyclical program processing
OM2 Initialization table Refer to Section "Initialization Table"
OM5 Startup module after Power-ON
OM7 Startup module after STOP/RUN
OM8 Shutdown module
OM18 - OM25 Time-controlled modules Time matrix defined in OM2 or S18 - S32;
lowest module no. = highest priority.
OM42 - OM63 reserved
FC0 – FC1023 Program modules
DM0 - DM1023 Data modules
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6-2 Addressing Conventions
6.2 Assignments in Special Marker Area

The PCL features a special marker area of 16-word size, i.e., SM0
through SM30.
It contains essential system flags and PLC cycle time information.
The unused addresses are reserved for internal system functions, and
may not be changed.
Address Contents Comment

SM14 PLC program and system error messages (hex):
12 Cycle time error
16 Module stack overflow
17 Application stack overflow
18 Application stack underflow
19 DM too short
1A OpCode error
1B Parameter error
1C Parameter not found
1D Address error, access to invalid address, e.g., transfer to
constant or timer or actual counter value.
1E Nonexistent PM called
1F Nonexistent DM called
20 HALT instruction
21 Controller in STOP
22 Hardware fault
23 "C" application error
24 "C" application warning
25 Reentrant module call
26 Assignment list error
27 No PLC program
28 Error in call for peripheral driver
29 Error in peripheral driver installation
2B Nonexistent interrupt OM
2C Instruction not yet integrated
2D Error in direct jump
2E Wrong operand number
2F DM not active
30 Illegal DM size
31 Nonreproducible error
32 Undersized module stack of "C" module
33 Fixation list not found
34 Unable to allocate dynamic DM Instantiation of standard FUNs under
35 Standard FUN parameter error structured text ST
40 Server2 work task error
41 System software error
SM16
SM18
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Address Contents Comment

SM20 Bit Read-only for entire bit field
20.0 Trigger pulse upon each startup
20.1 Buffer failure =1
PCL: Fault data backup to static RAM of
PCI-BMxx card
CL550: Low Battery warning /battery fault.
20.2 Flashing marker
20.3 Outputs disabled
20.4 Fixation active
20.5 Data backup error = 1, memory error on PC hard disk
20.6 Cold start flag
20.7 Trigger pulse after Power-ON or loading
SM21 21.0 Windows (WinPanel) no longer responds
21.7 Backup of operands into static RAM not supported
by hardware version.
SM22 Actual cycle time of last complete cycle Read-only
SM24 Maximum measured cycle time
SM26 Minimum measured cycle time
SM28 Error word 1 All errors are read-only
28.0 Addressing error
28.1 Parameter error
28.2 Nonexistent module called
28.3 Module stack error
28.4 Application stack underflow
28.5 Application stack overflow
28.6
28.7
29.0
29.1 OpCode error
29.2
29.3
29.4
29.5 No DM active
29.6 Group fault message/indication For detailed information, refer to SM14.
29.7 Cycle time error
SM30 Auxiliary marker word All markers are read-only
30.0
30.1
30.2
30.3 Always 0
30.4
30.5
30.6
30.7
31.0 Logical greater flag Influenced only by CPL instruction
31.1 Always 1
31.2
31.3
31.4
31.5
31.6 Carry flag, logical less at 1 Influenced only by CPL instruction
31.7 Zero flag, logical equal at 1 Influenced only by CPL instruction
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6.3 System Area Assignment

The PCL features a system area of 512-word size, i.e., S0 through S511.
It contains the system configuration data for the respective controller.
Essential declarations made in OM2 are copied into the system area, and
can thus be read by the PLC program.
To the extent deemed useful, the system declarations may be changed

upon runtime. This also includes the time intervals of time-controlled
organization modules.
Segments of the system area are used by default function modules which
make data available that is also used by other PLC program parts.
Example: Date and time.
The unassigned addresses in the system area are reserved for internal
purposes, and may not be modified.
Addr. Contents Comment

S0 Initialization flags, e.g., OM2_DW2 Writing in OM5 / OM7 *
S2 System settings, as in OM2_DW3
S4 Error response, as in OM2_DW4 Writing in OM5 / OM7
S6 Maximum cycle time, as in OM2_DW5 Writing in OM5 / OM7
S8 DM to be copied, as in OM2_DW6 Read-only
S10 First remanent timer, as in OM2_DW7 Writing in OM5 / OM7
S12 First remanent counter, as in OM2_DW8 Writing in OM5 / OM7
S14 First remanent marker address, as in OM2_DW9 Writing in OM5 / OM7
S16 First remanent data buffer address, as in OM2_DW10 Writing in OM5 / OM7
S18 OM18 time interval, as in OM2_DW11 Transfer during startup and EP, possibly active timer
S20 OM19 time interval, as in OM2_DW12 must expire before new matrix is activated.
S22 OM20 time interval, as in OM2_DW13
S62 First remanent data field address, as in OM2_DW33

S64 Current processing time, in microseconds Program cycle time: OM1 start through I/O state end.
S66 Current processing time, in milliseconds
S68 Max. processing time, in microseconds Program cycle time: OM1 start through I/O state end.
S70 Max. processing time, in milliseconds
S72 Min. processing time, in microseconds Program cycle time: OM1 start through I/O state end.
S74 Min. processing time, in milliseconds
S76 PCL status: 0 = RUN, 1 = STOP RUN = READY contact closed
S78 Temperature CPU board in degrees centigrade Only CL550
S100 Real-time: minutes / seconds Read-only; entered by operating system

S102 day/ hours 0 = Su, 1 = Mo ... 6 = Sa
S104 year / month
S106 ----- / day of week
S114 Periphery Status See section 6.4, Periphery Status

S116 Remanence status See section 3.5.6 , Startup characteristics CL550
S120
S122 Field bus type 1: PROFIBUS-DP, 2: CAN, 3: INTERBUS S
S124 I-size I/O information
S126 O-size
S128 Hardware / software version
S140 Rack ID Only CL550

S141 ZS ID
S142 reserved
S143 Total status
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S144 Entry status module 1

:
S158

:
S174

:
S190

:
S206

:
S222

:
S238
PROFIBUS-DP Slave diagnostics Bit status:

S240 BTN 15 .............. 0 0 = Slave working OK
: 1 = Slave reports diagnostics (not reachable or error)
S255 BTN 127 ........... 112
Classified diagnosis – SNE: Slave is not reachable Bit status: see section 6.4
S256 BTN 15 .............. 0 0 = Slave working OK
: 1 = Slave reports diagnostics (or error)
S271 BTN 127 ........... 112
Classified diagnosis – SKF: Slave configuration error
S272 BTN 15 .............. 0
:
S287 BTN 127 ........... 112
Classified diagnosis – DPS: Slave reports static diagnosis
S288 BTN 15 .............. 0
:
S303 BTN 127 ........... 112
Classified diagnosis – EXD: Slave reports extended diagnosis
S304 BTN 15 .............. 0
:
S319 BTN 127 ........... 112
Classified diagnosis – SNB: Slave is not ready
S320 BTN 15 .............. 0
:
S335 BTN 127 ........... 112
Classified diagnosis – SF: Slave reports error of another type
S336 BTN 15 .............. 0
:
S351 BTN 127 ........... 112
S510
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6.4 Periphery Status

The periphery status word S114 provides an overview of the status of the
bus master; it has the following format:
Bit Explanation
0 BMF Bus master fault
1 KSD Classified slave diagnostics
2 SD Slave diagnostics / System diagnostics
3 Reserved
4 Init Init phase: Waiting until periphery is operation-ready, or until
PLC STOP time has elapsed.
5 BmClab Bus master has switched DP bus to CLEAR status: BmClab
= [SNE ∨ SKF ∨ SNB] & Error_Action_Flag = 1. The timing
for the restart after the remedy of BmClab causes can be
controlled by the PLC program.
6 PgStop Programming Unit keeps DP bus in STOP state.
7 Aktiv Active ID
8 SNE One or more slaves are not reachable on the bus.
9 SKF One or more slaves report configuration errors.
10 DPS One or more slaves report static diagnostics.
11 EXD One or more slaves report extended diagnostics.
12 SNB One or more slaves not ready for cyclical data exchange.
13 SF One or more slaves report error of another type.
14 reserved
15 reserved
The bits Init, BmClab, and PgStop are not relevant to the PLC program
because, in the RUN state of the PCL, they always have the value 0..
BMF – Bus Master Fault

This bit indicates that a bus master fault has been detected.
KSD – Classified Slave Diagnostics

The KSD bit in the DP status word represents the OR link of bits 8
through 13.
The individual error types for the KSD are indicated in bits 8 though 13 of
the DP status word.
The KSD messages for each slave are saved in the status words range
from S256 to S351.
The classified slave diagnosis differs the following error cases:
SNE Slave is not reachable

The Slave is not reachable on the bus.
Possible causes:
• Slave is not existent
• Slave is switched off
• Faulty bus installation
• Physical disturbance
SKF Slave Configuration error
The type or the I/O configuration of the slave does not correspond to
the entries in the fieldbus configuration file of the master.
DPS Slave reports static diagnosis
The slave does not deliver valid user data. The application layer of
the slave is not ready to exchange date with the master.
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EXD Slave reports extended diagnosis

The extended diagnosis is specific for each slave and is described in
the slave manual. Possible causes:
• Load voltage error (e.g. by emergency stop)
• Short circuit on output
• Overload
• Overtemperature
• Open circuit
SNB Slave is not ready

The slave is yet not ready for data exchange, because it is not
completely set to operation mode by the master (report from the
protocol layer of the slave).
SF Slave reports error of another type
⇒ Every fieldbus system forms its own fieldbus specific diagnosis

according to the fitting message of the KSD. Therefore, according to
the used fieldbus system, not all KSD messages are used.
SD – System Diagnostics as per DP standard

The DP standard differentiates between system diagnostics and slave
diagnostics. System diagnostics comprise a bit field that indicates which
slaves report diagnostics. In addition, there is a detailed diagnostic
routine for individual slaves, the slave diagnostics.
The SD bit in the DP status word represents the OR link of all system
diagnostics bits. Therefore, when SD = HIGH, at least one slave reports
diagnostics.
Active ID
This bit must always have a value of 1. If this is not the case, this
indicates a fatal error in the bus master software.
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6.5 Data Formats
Bit
HIGH word LOW word
HIGH byte LOW byte HIGH byte LOW byte
31 2523 1615 87 3 0
Byte = B
HIGH word LOW word
31 25 23 16 15 8 7 0
This addressing mode differentiates between load and transfer
instructions:
Load instruction
The source operand may be either the even-numbered (LOW) byte or the
odd-numbered (HIGH) byte. In the case of the destination operand
(register), the LOW byte is always addressed.
Examples
L B M1,A
M0
HIGH byte LOW byte
Register A
HIGH word LOW word
L B M2,A
M2
HIGH byte LOW byte
Register A
HIGH word LOW word
Transfer instruction
For the source operand, the LOW byte is addressed. The destination
operand (DEST_OPD) may be both the even-numbered (LOW) byte and
the odd-numbered (HIGH) byte.
Examples
T B A,M1
Register A
HIGH word LOW word
M0
HIGH byte LOW byte
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T B A,M2
Register A
HIGH word LOW word
M2
HIGH byte LOW byte
Word = W
HIGH word LOW word
31 25 23 16 15 8 7 0
In binary word processing, the Load or Transfer instruction always

specifies an even-numbered byte address.
Without exception, for the Load instruction, the specified byte and its
subsequent byte are loaded into the LOW word of the Register (32-bit);
the HIGH word of the Register remains unchanged.
Without exception, for the Transfer instruction, the specified byte and its
subsequent byte are loaded into the LOW word of the Register (32-bit).
Sample LOAD Instruction

L W M2,A
M2
HIGH byte LOW byte
Register A
HIGH word LOW word
Double word = D
HIGH word LOW word
31 25 23 16 15 8 7 0
For double word processing when loading or transferring, the base byte
address, which must be divisible by 4, is always specified.
Loading always requires the base byte and the following 3 bytes to be
loaded into the specified Register (32-bit).
Transferring always requires the base byte and the following 3 bytes from
the specified Register (32-bit) to be written to.
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Examples
L D M4,A
M6 M4
Register A
HIGH word LOW word
T D A,M4
Register A
HIGH word LOW word
M6 M4
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6.6 Register Structure

The controller features 4 working registers, which can be addressed in a
bit-wise, byte-wise or word-by-word fashion. In this context, it should be
noted that byte/word addressing always addresses the LOW-byte/word.
Register A, B, C, D
31 24 23 16 15 8 7 0
HIGH word LOW word
For operations that exceed the 32-bit format, the registers are combined
to form permanent register pairs.
Register pair A + B
31 24 23 16 15 8 7 0
Word 4 = HIGH word B Word 3 = LOW word B
Word 2 = HIGH word A Word 1 = LOW word A
Register pair C + D
31 24 23 16 15 8 7 0
Word 4 = HIGH word D Word 3 = LOW word D
Word 2 = HIGH word C Word 1 = LOW word C
Status bits
N O C Z
Zero
Carry
Overflow
Negative
⇒ The negative flag always corresponds to the MSB (most significant

bit) of the specified data format. Therefore, for byte operations, this
is Bit 7, for word operations, it is Bit 15, and for double-word
operations, it is bit 31.
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6.7 Representing Constants

Data Type WinSPS
Explanation Notation PLC Utility Program
UINT (unsigned integer) Binary / Dual, Word 2#00000000_00000000 through 2#11111111_11111111
Decimal, Word 0 through 65535
Double word 0 through 4294967295
Hexadecimal, Word 16#0000 through 16#FFFF
Double word 16#00000000 through 16#FFFFFFFF
INT (signed integer) Decimal, Word -32768 through +32767
Double word -2147483648 through +2147483647
Floating-Point REAL Double word 1.175494351e-38 through 3.402823466e+38
LREAL Quad word 2.2250738585072014e-308 through 1.7976931348623158e+308
Text, STRING(2) ASCII, Word 'AB'
Double word 'ABCD'
Time value TVALUE Time value (+time base r) T#10ms through T#10230s
r: 0 = 10 ms, 1 = 100 ms, T#0.r through T#1023.r
2 = 1 s, 3 = 10 s
TCPIP addresses, ISTRING Double word ‘‘1.2.3.4‘‘
6.8 Program Module Calls

WinSPS
PLC Utility Program
Program module / function call (IEC1131-3) CM PM
6.9 Jump Instructions

WinSPS
PLC Utility Program
Jump instruction JPx label
Jump destination label:
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6.10 Bit & Module Addresses

Operand Addresses [decimal]
I 0.0 through 8191.7
Q 0.0 through 8191.7
M 0.0 through 8191.7
SM 0.0 through 31.7
D 0.0 through 511.7
DX 0.0 through 511.7
DB 0.0 through 511.7
DF 0.0 through 32767.7
T-status 0 through 255
C-status 0 through 255
P 0 through 62
DM 0 through 1023
PM 0 through 1023
6.11 Byte, Word & Double Word Addresses

Operand Address [decimal] Comment
I 0 through 8191
Q 0 through 8191
T-actual val. 0 through 256 Timer range 10 ms through 1023 s;
T-status 0 through 256 Matrix: 0.01; 0.1; 1; 10 s
C-actual val. 0 through 256 Counter range: 0 through 8191
C-status 0 through 256
M 0 through 8191
S 0 through 511 Managed values:
- System clock
- Error codes
- Timers for time-controlled process.
- Versions, etc.
P 0 through 62
DF 0 through 32767
DB 0 through 511
D 0 through 511
DX 0 through 511
The even-numbered byte addresses are used as word addresses; for
double word addresses, the byte addresses must be divisible by 4.
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6.12 Addressing Modes
6.12.1 Absolute addressing operands
Reading
Byte / Word / I, O, M, T, C and P for T/C, actual values apply
Double word / REAL / LREAL K, DF, DB, D, DX, SM, S
Writing
Byte / Word / A, M, P P writing, depending on assigned operand
Double word / REAL / LREAL DF, DB, D, DX, S
6.12.2 Direct addressing of all absolute addressable operands
Register A
Register B Operand adress
Register C
Register D
Example
L B I10,B ; Loads the status of input byte I10 into the

; LOW byte of LOW word in B.
L W 100,C ; Loads the value 100 into the Low word of
; register C
6.12.3 Register-to-register addressing
Register A
Register B
Register C
Register D
Example
L W C,B ; Loads contents of LOW word from register

; C into LOW word of register B.
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6.12.4 Register indirect addressing
Register A Index address
Register B
Register C
Register D Peripherals
Example
L D 10,A ; Load index address as byte number Low

; word from A; High word is deleted
L W I[A],D ; Load status of I10 (address in A) into
; Low word of register D
6.12.5 Indirect addressing

Indirect addressing, whether word/byte or bit-oriented, is accomplished
with the use of an operand prefix containing the operand identifier
(operand ID) and operand address. This greatly facilitates the handling
and monitoring of operand addresses.
In addition, all data and program modules can be called indirectly.
The operand prefix is structured as follows:
OPD[R] OPD = Operand ID

[R] = Operand address (index addr.) in register A, B, C, D
⇒ When loading index addresses in one of the registers, double word
D must always be used as a supplement because the registers are
32 bits wide, and the HIGH word must be deleted!
Principle of indirect addressing, using the example of a block transfer via

program loop:
Task to be accomplished: Transfer of 5 input words starting at address

I10 into marker words from address M50 upward.
L D 5,A ; Loads the loop counter

L D 10,B ; Loads the byte base address I10
L D 50,C ; Loads the byte base address M50
further: ; Loop entry label
L W I[B],D ; Reads contents (operand status)
T W D,M[C] ; Writes status that was read
INC D B,2 ; Next E-word (byte address + 2)
INC D C,2 ; Next M-word
DEC D Q,1 ; Loop counter -1
JPN further ; No all words processed as yet
1070 072 189 - 108 (02.09) GB

Indirect byte addresses

OPD Identifier Byte address Instructions Examples
[decimal] ... [Reg]
I 0 through 8191 L L D 10,A
Q 0 through 8191 L, T L W OPD[A],B
T-actual value 0 through 255 L L D 10,A
T W B,OPD[A]
C-actual value 0 through 255 L
M 0 through 8191 L, T
P 0 through 62 L
S 0 through 511 L, T
SM 0 through 31 L, T
DF 0 through 32767 L, T
DB 0 through 511 L, T
D 0 through 511 L, T
DX 0 through 511 L, T
To address the next byte or next T/C, the address must be incremented
by 1. To address the next word, the address must be incremented by 2.
Indirect bit addresses

OPD Identifier Bit Address Instructions Examples
[decimal] See column 1 for
OPD
I 0 through A, AN, O, ON
65535
Q 0 through A, AN, O, ON, S, R, = L D 10,A
65535 A OPD[A]
M 0 through A, AN, O, ON, S, R, = = OPD[A]
65535
S 0 through 4095 A, AN, O, ON
SM 0 through 255 A, AN, O, ON
D 0 through 4095 A, AN, O, ON, S, R, =
DX 0 through 4095 A, AN, O, ON, S, R, =
DB 0 through 4095 A, AN, O, ON, S, R, =
DF 0 through A, AN, O, ON, S, R, =
262143
T-status 0 through 255 A, AN, O, ON
C-status 0 through 255 A, AN, O, ON
To address the next bit relative to a given starting address, this address
must be incremented by 1.
Indirect module addresses

Operand Module No. Instructions Example
... [Reg]
DM 0 through 1023 CMx L D 10,A
BXx CM DM[A]
PM 0 through 1023 CMx L D 100,A
CMx CM PM[A]
To address the next module relative to a given module number, this
number must be incremented by 1.
In the case of a range violation or if the module is not available, the

controller will enter STOP mode. In both instances, the cause of the error
can be indicated with the use of the Programming Unit (PG).
1070 072 189 - 108 (02.09) GB

6.13 Parameter Transfer

When a program module is called up, up to 63 parameter values can be
transferred. The number of transferred parameters is declared with the
module start command. This is followed by the parameters, starting with
P0. In a PM that has been called, these parameters can also be
processed independently: (L D P[R],R).
⇒ Indirect parameter processing is available only with WinSPS v3.0

and WinPanel v2.0 and higher.
The applicable operand attributes are listed below:

• D – Double word (default)
• W – Word
• B – Byte
Bit operands are programmed without the use of attributes.
⇒ Timers and counters are transferred without operand attribute to

facilitate their use as both word( i.e., timer / counter value), and as
bit (i.e., timer / counter status) in the module to be called.
Example of parameter transfer:
CM PM100,7 ; Call PM100 using 7 parameters

P0 D 43 ;Parameter P0: PM no. as constant 43
P1 D 4 ;Parameter P1: DM no. as constant K4
P2 W Q56 ;Parameter P2: Output word at byte addr. O56
P3 I7.3 ;Parameter P3: Input bit I7.3
P4 T2 ;Parameter P4: Timer T2
P5 C13 ;Parameter P5: Counter C13
P6 O10.0 ;Parameter P6: Output bit O10.0
Utilization of parameters in called-up module PM100:
L D P1,A ;Load data module no. 4

CM DM[A] ;Open DM4
BX -DB5
L D P0,A ;Load PM no. 43

CM PB[A],2 ;Use 2 parameters to call PM43
P0 W D2 ;Parameter P0: D2 of active 1st DM (DM4)
P1 W DX6 ;Parameter P1: DX6 of active 2nd DM (DM5)
L W P2,A ;Load output word O56
L W P4,B ;Load timer value from T2 to B
A P3 ;I7.3
A P4 ;Status of T2
A P5 ;Status of C13
= P6 ;O10.0
1070 072 189 - 108 (02.09) GB

6.14 Addressing Limits
Direct addressing
In direct addressing, addressing limits are determined by the operand
attribute.
Byte Address as desired

Word Address even-numbered
Double word Address divisible by 4
Real Address divisible by 4
Lreal Address divisible by 8
Example:
Operand B W D R L
M0 x x x x x
M1 x
M2 x x
M3 x
M4 x x x x
M5 x
M6 x x
M7 x
M8 x x x x x
Indirect addressing
Indirect addressing is subject to the same addressing limits as direct
addressing.
⇒ It should be noted however, that address corrections are made to

the next lower addressing limit. This correction is contingent on the
operand attribute.
Example:
L D 0,A ;Address byte 0

L D M[A],B ;Reads the status of M0+M1+M2+M3
INC D A,1 ;Address byte 1
1070 072 189 - 108 (02.09) GB

Parameterized addressing
Parameterized addressing is subject to the same addressing limits as
direct addressing.
⇒ It should be noted however, that address corrections are made to

the next lower addressing limit. This correction is contingent on the
operand attribute.
Example:
Parameter definition Parameter query Reads the following:

P0 M1 L B P0,A M1
P1 M3 L W P1,A M2 and M3
P2 M5 L D P2,A M4 through M7
P3 M7 L D P3,A M4 through M7
P1 M11 L L P1,A M8 through M15
1070 072 189 - 108 (02.09) GB

1070 072 189 - 108 (02.09) GB

Instruction List 7-1
7. Instruction List
7.1 Structure of Controller Instructions

Controller Instruction Comment
Operation part Operand attribute Source OPD Destination
OPD
OPP OPA SRC , DEST ; Description
Examples
U I0.0
U W -Name ,A
L B O0 ,B
T D C , M12
MUL W 1234 ,D
7.2 Flags
The flags are influenced by the following instruction groups:
• Bit instructions • Shift

• Compare • Rotate
• Convert • Add
• Swap • Subtract
• Increment • Multiply
• Decrement • Divide
They can be used not only in program processing instructions (jumps,

module instruction) but also in logical links (special marker queries).
Flags PG display indication JP... Flag query Explanation

CM...
CY=1 C ...C U CY Carry
CY=0 ...CN AN CY Carry Not
O=1 O ...O U O Overflow
O=0 ...ON AN O Overflow Not
Z=1 Z ...Z U Z Zero
Z=0 ...N AN Z Zero Not
N=1 N ...M U N Negative / minus
N=0 ...P AN N Positive
AG=1 ...AG No flag linking Arithmetical greater
AG=0 N∨Z ...MZ U Z Minus / Zero
O N
AN O
ON N
U O
LG=1 ...LG AN Z Logical greater
AN CY
LG=0 C∨Z ...CZ U Z Carry / Zero
O CY
1070 072 189 - 108 (02.09) GB

7-2 Instruction List
7.3 Key to Abbreviations

OPP Operation
OPA Operand attribute
B Byte
W Word
D Double word
R REAL
L LREAL
SRC Source operand
DEST Destination operand
E Input
A Output
M Marker
K Constant
SM Special marker
T Timer
Z Counter
D Data word, within data modules
DM Data buffer
DF Data field
FI FIFO
S System area
DM Data module
DX 2. 2nd active data module
PM Program module
SYM Symbolic
R.bit Register bit w/ R = A, B, C, D, and bit = 0 thru 31
OPD[R] Register indirect w/ operand prefix
TI Time interrupt, time-controlled processing
RG Program branch
A Operation permitted at RG beginning
E Operation concluding RG
Addr. Addressing mode
D Direct
R Register A, B, C, or D
[R] Register indirect w/ operand prefix
Flag
V Link result RES
CY Carry
O Overflow
Z Zero
N Negative
1070 072 189 - 108 (02.09) GB

7.4 Bit instructions

Bit instructions modify the flags CY, Z, O, and N.
Exception: Flags themselves are not changed by a binary flag query.
Links are interpreted in accordance with the Boolean AND before OR

logic principle. Parenthesized instructions are used to form logical
intermediate results.
Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
U I/O/M/SM • • • • • • U E0.0 AND link, query status 1
T/C/SYM • • • • • • U T0
R.bit • • • • • • U A.0
OPD[R] • • • • • • U M[A]
P/ • • • • • • U P0
S/D/DX/DF/DP • • • • • • • U D0.0
CY/Z/O/N • U CY
•
AN I/O/M/SM • • • • • • AN A0.0 AND link, query status 0
T/C/SYM • • • • • • AN Z0
R.bit • • • • • • AN B0.0
OPD[R] • • • • • • AN M[B]
P • • • • • • AN P1
S/D/DX/DF/DP • • • • • • • AN D0.0
CY/Z/O/N • AN CY
•
O I/O/M/SM • • • • • • O M0.0 OR link, query status 1
T/C/SYM • • • • • • O -SYMBOL
R.bit • • • • • • O C0.0
OPD[R] • • • • • • O MD[C]
P • • • • • • O P10
S/D/DX/DF/DP • • • • • • • O D0.0
CY/Z/O/N • O CY
•
ON I/O/M/SM • • • • • • ON SM31.7 OR link, query status 0
T/C/SYM • • • • • • ON -Name
R.bit • • • • • • ON D.0
OPD[R] • • • • • • ON M[D]
P • • • • • • ON P62
S/D/DX/DF/DP • • • • • • • ON D0.0
CY/Z/O/N • ON CY
•
= A/M/SYM • • • • • • = A0.0 Assign result when RES = 1
S/D/DX/DF/DP • • • • • • = D0.0
P • • • • • • = P0
OPD[R] • • • • • • = M[A]
R.bit • • • • • • = A.0
S A/M/SYM • • • • • • S M0.0 Set bit HIGH when RES = 1
S/D/DX/DF/DP • • • • • • S D0.0
P • • • • • • S P1
OPD[R] • • • • • • S M[B]
R.bit • • • • • • S B.0
R A/M/SYM • • • • • • R -SYMBOL Set bit LOW when RES = 1
S/D/DX/DF/DP • • • • • • R D0.0
P • • • • • • R P62
OPD[R] • • • • • • R M[C]
R.bit • • • • • • R C0.0
P R.bit • • • • • P A.0 Check register bit for status = 1, when
met: C = 1
PN R.bit • • • • • PN A.15 Check register bit for status = 0, when
met: C = 1
( • • • • ( AND opening bracket
) • • • • ) Closing bracket
O( • • • • O( OR opening bracket
)N • • • • )N Negation of bracket contents
1070 072 189 - 108 (02.09) GB

7.5 Timer Programming

The PCL provides 256 timer circuits, T0 through T255.
These can be utilized in the following modes:

• SP Pulse
• SPE Start pulse extended
• SR Start time as raising delay
• SF Start time as falling delay
• SRE Start time as raising delay extended
Starting the nonremanent starting timers SP, SPE, SR and SRE requires
a positive transition of the timer start condition. However, they are started
also if the start condition, at the time of first addressing (1st PLC cycle)
equals 1.
In the case of remanent timers, the flank marker is retained, i.e., whether
a 1 will start the timer at the time of first addressing (1st PLC cycle) after
startup or restart, depends on the start condition prior to STOP or Power-
OFF.
In the case of the start time as falling delay, a 0 will not start the timer
during the initial processing. Predefining the timer start condition with 1 is
possible as early as in the startup OM, provided that the information
about remanence characteristic (see Section on Remanence
Characteristics) is considered.
The timers are decremented in the I/O state. A timeout is thus recognized
only in the I/O state, and not during the program cycle!
Because a timer is decremented in the I/O state by a multiple of the

declared time matrix, it is useful to select a time matrix that is a small as
possible.
The timer starts immediately upon a positive transition of the timer start
condition.
1070 072 189 - 108 (02.09) GB

7.5.1 Timer instructions

Timer starts are activated only when the RES signal undergoes a
transition from 0↑1. In advance of the timer start, the time value is loaded
into the register being used. Reset and stop functions of timers are
always RES signal-dependent. The timer status for logical links is
instruction-dependent, and may be taken from the timer diagrams.

SP R , Tn • • SP A,T0 Pulse
, SYM • SP A,-Symbol
, T[R] • SP A,T[B]
, P • SP A,P0
SPE R , Tn • • SPE A,T0 Start pulse extended
, SYM • SPE A,-Symbol
, T[R] • SPE A,T[B]
, P • SPE A,P0
SR R , Tn • • SR A,T0 Start time as raising delay
, SYM • SR A,-Symbol
, T[R] • SR A,T[B]
, P • SR A,P0
SF R , Tn • • SF A,T0 Start time as falling delay
, SYM • SF A,-Symbol
, T[R] • SF A,T[B]
, P • SF A,P0
SRE R , Tn • • SRE A,T0 Start time as raising delay extended
, SYM • SRE A,-Symbol
, T[R] • SRE A,T[B]
, P • SRE A,P0
RT Tn • • RT T0 Set timer LOW when RES = 1
SYM • RT -Symbol
T[R] • RT T[B]
P • RT P0
TH Tn • • TH T0 Timer stop when RES = 1,
SYM • TH -Symbol
T[R] TH T[B]
Timer continues when RES = 0
•
P • TH P0
1070 072 189 - 108 (02.09) GB

7.5.2 Time format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x x x x R R W W W W W W W W W W
Time matrix Timer 1 - 1023
value:
0 0 0: 10 ms :
0 1 1: 100 ms Program entry of time constant:
1 0 2: 1 s w.r with time value w = 1 -1023
1 1 3: 10 s and time matrix r = 0 - 3
Example:
Timer T100 shall be started at 15 sec:

L W T#15s,A ;15s declaration in 1-sec time matrix
A B -start
SPE A,T100
Same function with higher matrix resolution, i.e., higher accuracy:

L W T#15000ms,A ;15s declaration in 1oo-ms time matrix
A B -start
SPE A,T100
Timer start with the assistance of the PG time matrix:

L W T#15.2,A ;15s declaration in 1-ms time matrix of PG
A B -start
SPE A,T100
Same function with higher matrix resolution, i.e., higher accuracy:

L W T#150.1,A ;15s declaration in 1oo-ms time matrix of PG
A B -start
SPE A,T100
1070 072 189 - 108 (02.09) GB

7.5.3 Timer diagrams
SP – Start time as pulse
Start condition
Reset condition
Timer status ← t → ←<t→
SPE – Start pulse extended
Start condition
Reset condition
Timer status ← t → ← t → ← t → ←<t→
SR – Start time as raising delay
Start condition
Reset condition
Timer status ← t → ←<t→
SF – Start time as falling delay
Start condition
Reset condition
Timer status ← t → ← t →
SRE – Start time as raising delay extended
Start condition
Reset condition
Timer status ← t → ← t → ← t → ←<t→
1070 072 189 - 108 (02.09) GB

7.6 Counter Instructions

The setting of counters and counting up and down occurs only at the
RES signal transition from 0 → 1.
In advance of the reset, the required counter content is loaded into the
register being used.
Counter reset functions are always RES signal-dependent.
The counter status for logical links depends on the counter content. For
counter contents > 0, the status is = 1 (HIGH); counter content = 0 will
have status = 0 (LOW).
Counting range: 0 through 8191.

SC R , Zn • • SC A,Z0 Set counter HIGH
, SYM • SC A,-Symbol
, Z[R] • SC A,Z[B]
, P • SC A,P0
CU Zn • • CU Z0 Count up
SYM • CU -Symbol
Z[R] • CU Z[B]
P • CU P0
CD Zn • • CD Z0 Count down
SYM • CD -Symbol
Z[R] • CD Z[B]
P • CD P0
RC Zn • • RC Z0 Set counter LOW when RES = 1
SYM • RC -Symbol
Z[R] • RC Z[B]
P • RC P0
1070 072 189 - 108 (02.09) GB

7.7 Digital Links

U B I/O/M/SM , R • 0 0 • • U B E0,A Digital AND link between source
W T/C/K/SYM • 0 0 • • U W T0,B
D S/DF/DP 0 0
and destination. The result is written
• • • U B S0,C
D/DX • 0 0 • • U W D0,D to destination.
R • 0 0 • • U W A,B
OPD[R] • 0 0 • • U B M[B],C
P • 0 0 U W P0,D
• •
AN B I/O/M/SM , R • 0 0 • • AN B E127,A Digital AND NOT link between
W T/C/K/SYM • 0 0 • • AN W T127,B
D S/DF/DP 0 0
source and destination. The result is
• • • AN B S511,C
D/DX • 0 0 • • AN W D510,D written to destination.
R • 0 0 • • AN W A,B
OPD[R] • 0 0 • • AN B M[B],C
P • 0 0 AN W P62,D
• •
O B I/O/M/SM , R • 0 0 • • O B E0,A Digital OR link between source and
W T/C/K/SYM • 0 0 • • O W T0,B
D S/DF/DP 0 0
destination. The result is written to
• • • O B S0,C
D/DX • 0 0 • • O W D0,D destination.
R • 0 0 • • O W A,B
OPD[R] • 0 0 • • O B M[B],C
P • 0 0 O W P0,D
• •
ON B I/O/M/SM , R • 0 0 • • ON B E127,A Digital OR NOT link between source
W T/C/K/SYM • 0 0 • • ON W T127,B
D S/DF/DP 0 0
and destination. The result is written
• • • ON B S511,C
D/DX • 0 0 • • ON W D510,D to destination.
R • 0 0 • • ON W A,B
OPD[R] • 0 0 • • ON B M[B],C
P • 0 0 ON W P62,D
• •
XO B I/O/M/SM , R • 0 0 • • XO B E0,A EXCLUSIVE OR link between
W T/C/K/SYM • 0 0 • • XO W T0,B
D S/DF/DP 0 0
• • • XO B S0,C
D/DX • 0 0 • • XO W D0,D written to destination.
R • 0 0 • • XO W A,B
OPD[R] • 0 0 • • XO B M[B],C
P • 0 0 XO W P0,D
• •
XON B I/O/M/SM , R • 0 0 • • XON B E127,A EXCLUSIVE OR NOT link between
W T/C/K/SYM • 0 0 • • XON W T127,B
D S/DP/DF/DP 0 0
• • • XON B S511,C
D/DX • 0 0 • • XON W D510,D written to destination.
R • 0 0 • • XON W A,B
OPD[R] • 0 0 • • XON B M[B],C
P • 0 0 XON W P62,D
• •
7.8 SWAP Instructions

SWAP W R • SWAP W A Change in Register High-Byte ↔ Low-Byte
D SWAP D A High-Wort ↔ Low-Wort
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7.9 COMPARE Instruction

The universally applicable CPLA (Compare Logical and Arithmetical)
instruction is available for Compare operations. This facilitates both
logical and arithmetical compare operations.
Also, for reasons of compatibility, the purely logical CPL instruction was
implemented; it is used to map binary result queries also in special
markers.
The logical compare operation regards the bytes, words, or double words
to be compared as unsigned integers, i.e., as "unsigned 8", "unsigned
16", or "unsigned 32".
The arithmetical compare operation regards the bytes, words, or double

words to be compared as signed integers, i.e., as "signed 8", "signed 16",
or "signed 32".

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z AG LG
CPLA B I/O/M/SM , R • • • • • • • CPLA W E62,A Arithmetical Compare function.
W T/C/K/SYM • • • • • • • CPLA B 255,B
D S/DF CPLA W DF510,C
The result may be used for logical
• • • • • • •
D/DX/DP • • • • • • • CPLA B D511,D and arithmetical purposes.
R • • • • • • • CPLA B B,C
OPD[R] • • • • • • • CPLA W M[C],D
P • CPLA B P62,A
• • • • • •
CPL B I/O/M/SM , R • • • • • • • CPL W E62,A Logical Compare operation. The
W T/C/K/SYM • • • • • • • CPL B 255,B
D S/DF CPL W DF510,C
result may be used for logical
• • • • • • •
D/DX/DP • • • • • • • CPL B D511,D purposes only, i.e., the values will
R • • • • • • • CPL B B,C be treated as positive integers.
OPD[R] • • • • • • • CPL W M[C],D
P • CPL B P62,A
• • • • • •
CPLA compare values:

• Logical: positive, integer
• Arithmetical: two's complement, signed integer
As a result of a compare operation, the flags or special markers provide
information about the result.
1070 072 189 - 108 (02.09) GB

Examples:
Compare DEST A with CPL B,A CPLA B,A

SRC B Logical Logical Arithmetic
Jump Flag query Jump Flag query Jump
instruction instruction instruction
Equal A=B JPZ U SM31.7 JPZ U Z JPZ
Unequal A≠B JPN AN SM31.7 JPN AN Z JPN
Less than A<B JPCY U SM31.6 JPCY U CY JPM
Less than / A≤B JPCZ AN SM31.0 JPCZ U Z JPMZ
O CY
equal
Greater than A>B JPLG U SM31.0 JPLG AN CY JPAG
AN Z
Greater than/ A≥B JPCN AN SM31.6 JPCN AN CY SPP
equal
⇒ When using the CPLA instruction, the evaluation of the compare

results must always be programmed immediately following the
compare instruction itself. The user is advised to bear in mind that
with the exception of flag queries, binary operations will cause a
modification of the flags. Therefore, a compare result can be used
only in a link. Following this, another CPLA instruction must again
be programmed.
⇒ The special markers that are influenced only by the CPL instruction
will remain unaffected until the next CPL instruction.
1070 072 189 - 108 (02.09) GB

7.10 LOAD Instructions

Load instructions are used to write statuses or values from operands into
registers. Signal statuses of inputs / outputs are loaded from the
periphery image.
In the event that the status of inputs is to be loaded directly from the dual-
port RAM of the bus master during the program cycle, this status must be
loaded into the image with the use of the load instruction LD before the
load instruction L is issued.

L B I/O/M/SM , R • L W E0,A Load contents of SRC into DEST.
W T/C/K/SYM • L B 0,B
D DF/DP • L W DF0,C
D/DX • L B D0,D
R • L B B,C
OPD[R] • L W M[C],D
P • L B P0,A
P[R] • L D P[A],B
OM, FC, DM • L DB10,A Load DB10 module size
LD E , K • LD E0,20 Load 20 bytes* of input statuses into image, starting with I0.
E[R] , [R] •
LD E0,[B] Load I-statuses into image, starting with I0; byte* count in B.
LD E[A],[B] Load I statuses into image (start address in A), byte* count in
B.
* maximum byte count = 256

Example of direct loading:
LD D I12,4 ; Load 4 bytes from bus master into I-image,
; starting with I12.
L D I12,A ; Load statuses I12 thru I15 into register A
⇒ When using the "indirect" load instruction parameter (L D

P[R],R), the WinSPS is unable to perform a syntax check because
it cannot foresee which operand parameter will actually be
addressed by the parameter. The controller may enter STOP mode.
The user is therefore advised to ensure the required syntax for this
instruction.
1070 072 189 - 108 (02.09) GB

7.11 TRANSFER Instructions

Transfer instructions (T) are used to write statuses or values from
registers into operands. Signal statuses from outputs are written into the
periphery image. During the I/O state this image is then transferred to the
outputs.
In the event that the statuses of outputs are to be sent directly to the
dual-port RAM of the bus master during the program cycle, the TD
transfer instruction will be used.

T B R , A/M/SYM • T W A,M0 Transfer contents of SRC to DEST.
W , S/DF • T B B,DF0
D , D/DX/DP • T W C,D0
, R • T W A,B
, OPD[R] • T B B,M[C]
, P • T W D,P0
TD A , K • TD O0,20 Send 20 bytes* of output statuses from image to
A[R] , [R] • outputs, starting with O0.
TD O0,[B] Send O-statuses from image to outputs, starting
with O0. Byte count* in B.
TD A[A],[B] Send O-statuses from image to outputs (start

address in A). Byte count* in B.
* max. byte count = 256
Example of direct transfer:

L D 16#1234FFFF,A ; Load hex constant into register A,
T D A,A12 ; and write into O-image.
TD D A12,4 ; Transfer 4 bytes for O12-O15 into ,
bus master.
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7.12 CONVERT Instructions

BID B R • 0 • 0 • BID W A Binary → BCD (decimal), result >
W BID B B
D 9999 sets the overflow bit.
DEB B R • 0 • 0 • DEB W C BCD (decimal) → Binary, wrong BCD
W DEB B D
D coding sets the overflow bit.
CMP B R • • • • • CMP W A Converts register contents to the two's
W CMP B B
D
complement.
N B R • 0 • 0 • N W C Negates register contents, one's
W N B D
D
complement.
Positive and negative numbers are differentiated by the status of the

MSB.
OPA Positive Range Negative Range

Double word Bit 31 = 0 0 through +2,147,483,647 Bit 31 = 1 0 through -
2,147,483,648
Word Bit 15 = 0 0 through +32,767 Bit 15 = 1 0 thru -32.768
Byte Bit 7 = 0 0 through +127 Bit 7 = 1 0 through -128
Example of the representation of positive and negative numbers
By way of illustration, a 4-bit number (nibble) is used here; the nibble data
format ("tetrade") is not supported by the controller.
0 1 1 0 positive number 6
1 0 0 1 Negation, one's complement
+ 1
1 0 1 0 Two's complement = negative number 6
1111 0000
-1 0
1110 0001
-2 +1
1101 0010
-3 +2
1100 0011
-4 +3
1011 negativ positive 0100
-5 e +4
1010 0101
-6 +5
1001 0110
-7 +6
1000 0111
-8 +7
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7.13 INCREMENT & DECREMENT Instructions

Increment / decrement the contents of source operand SRC:
• by the number n, where n = 1 through 127
• when n = 0, and when [C], by the number stored in C, max. 127.

INC B R , n • • • • • INC B A,5 Increment the contents of the SRC
W , 0 • • • • • INC W A,0
D , [C] • • • • • INC W B,[C]
DEC B R , n • • • • • DEC B A,5 Increment the contents of the SRC
W , 0 • • • • • DEC W A,0
D , [C] • • • • • DEC W B,[C]
7.14 STACK Instructions

The available stack size comprises 256 double words. In the event of
underflow, special marker S28.4 in the system area goes HIGH; overflow
sets the S28.5 to HIGH. The I/O state resets/deletes the entire
application stack.

PUSH D R • PUSH D A Saves the register contents to application
stack, and lowers the stack address.
POP D R • POP D B Raises the application stack address, and
reads the saved contents from the stack.
7.15 No Operation Instructions & CARRY Manipulations

NOP NOP No operation
SCY • SCY Unconditionally set CARRY flag HIGH.
RCY • RCY Unconditionally set CARRY flag LOW.
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7.16 SHIFT Instructions

Shift the contents of source operand SRC:
• by the number n
• when n=0, and when [C], by the number stored in C
when OPA = D, n = 1 through 31
when OPA = W, n = 1 through 15
when OPA = B, n = 1 through 7

SLR B R , n • • • • • SLR W A,7 SHIFT logical RIGHT
W , 0 • • • • • SLR B B,[C]
D , [C] • • • • •
SLL B R , n • • • • • SLL W A,7 SHIFT logical LEFT
W , 0 • • • • • SLL B B,[C]
D , [C] • • • • •
SAR B R , n • • • • • SAR W A,7 SHIFT arithmetical RIGHT
W , 0 • • • • • SAR B B,[C]
D , [C] • • • • •
Logical SHIFT
MSB LSB CY
SLR B,n
o→ o • → • → o
MSB LSB CY
SLL B,n
• ← • o ←0 o
↓ ↑
→
Arithmetical SHIFT
All bits being vacated are filled up with the contents of the MSB.
MSB LSB CY
SAR B,n
• → • → • → o
In the case of shift operations exceeding one space (n > 0), the overflow
bit is set HIGH after a "1" was shifted through CY.
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7.17 ROTATE Instructions

Shift the contents of source operand SRC:
• by the number n
• when n=0, and when [C], by the number stored in C
when OPA = D, n = 1 through 31
when OPA = W, n = 1 through 15
when OPA = B, n = 1 through 7

ROR B R , n • • • • • ROR B A,7 Rotate RIGHT
W , 0 • • • • • ROR W A,0
D , [C] • • • • • ROR W B,[C]
ROL B R , n • • • • • ROL B A,7 Rotate LEFT
W , 0 • • • • • ROL W A,0
D , [C] • • • • • ROL W B,[C]
RCR B R , n • • • • • RCR B A,7 Rotate RIGHT THROUGH CARRY
W , 0 • • • • • RCR W A,0
D , [C] • • • • • RCR W B,[C]
RCL B R , n • • • • • RCL B A,7 Rotate LEFT THROUGH CARRY
W , 0 • • • • • RCL W A,0
D , [C] • • • • • RCL W B,[C]
Rotate RIGHT
MSB LSB CY
ROR B,n o • → • o
↑ ←--- ↓ → ↑
Rotate LEFT
MSB LSB CY
ROL B,n
• ← • ο o
↓ → ↑ → ↑
Rotate RIGHT THROUGH CARRY
MSB LSB CY
RCR B,n
ο • → • → ο
↑ ←--- ↓
Rotate LEFT THROUGH CARRY
MSB LSB CY
RCL B,n
• ← • ο ← ο
↓ → ↑
In the case of a rotation by more than one space, the following applies:
• The overflow bit goes HIGH when a 1 has been rotated through CY.
• The negative bit goes HIGH when the MSB contains a 1.
MSB: Bit 7 when OPA = B
MSB: Bit 15 when OPA = W
MSB: Bit 31 when OPA = D
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7.18 Fixed Point Arithmetic
7.18.1 ADD instructions

ADD B I/O/M/SM , R • • • • • ADD W E0,A Fixed-point addition of signed integers:
W T/C/K/SYM • • • • • ADD B 0,B
D S/DF/DP ADD W DP0,C
SRC + DEST = DEST
• • • • •
D/DX • • • • • ADD B D0,D
R • • • • • ADD B B,C
OPD[R] • • • • • ADD W M[C],D
P • ADD B P0,A
• • • •
ADC B I/O/M/SM , R • • • • • ADC W E0,A Fixed-point addition of signed integers
W T/C/K/SYM • • • • • ADC B 0,B
D S/DF/DP ADC W DP0,C
allowing for CY.
• • • • •
D/DX • • • • • ADC B D0,D SRC + DEST + CY = DEST.
R • • • • • ADC B B,C
OPD[R] • • • • • ADC W M[C],D
P • ADC B P0,A
• • • •
Byte, word, and double-word addition

MSB:
• Bit 7 when OPA = B
• Bit 15 when OPA = W
• Bit 31 when OPA = D
0
ADD OPA B, A sg A
+
sg B
=
sg A
ADC OPA C, A sg A
+
sg C
+
CY
=
sg A
Quad-word addition: Value 1 + value 2

Value 1: LOW DW in B, HIGH DW in A
Value 2: LOW DW in D, HIGH DW in C
LOW DW 31 0
ADD D D, B B
+
D
=
B
HIGH DW
ADC D C, A sg A
+
sg C
+
Cy
=
sg A
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7.18.2 SUBTRACT instructions

SUB B I/O/M/SM , R • • • • • SUB W E0,A Fixed-point subtraction of signed integers:
W T/C/K/SYM • • • • • SUB B 0,B
D S/DP/DF/DP SUB W DP0,C
DEST - SRC = DEST.
• • • • •
D/DX • • • • • SUB B D0,D
R • • • • • SUB B B,C
OPD[R] • • • • • SUB W M[C],D
P • SUB B P0,A
• • • •
SBB B I/O/M/SM , R • • • • • SBB W E0,A Fixed-point subtraction of signed integers
W T/C/K/SYM • • • • • SBB B 0,B
D S/DP/DF/DP SBB W DP0,C
allowing for negative CY.
• • • • •
D/DX • • • • • SBB B D0,D DEST - SRC - CY = DEST.
R • • • • • SBB B B,C
OPD[R] • • • • • SBB W M[C],D
P • SBB B P0,A
• • • •
Byte, word, double-word subtraction

MSB:
• Bit 7 when OPA = B
• Bit 15 when OPA = W
• Bit 31 when OPA = D
0
SUB OPA B , A sg A
-
sg B
=
sg A
SBB OPA C , A sg A
-
sg C
-
CY
=
sg A
Quad-word subtraction: Value 1 – value 2

Value 1: LOW DW in B, HIGH DW in A
Value 2: LOW DW in D, HIGH DW in C
LOW DW 31 0
SUB D D, B B
-
D
=
B
HIGH DW
SBB W C, A sg A
-
sg C
-
CY
=
sg A
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7.18.3 MULTIPLY instructions

MUL B K , R • 0 0 • • MUL B 100,A Fixed-point multiplication of signed integers.
W R • 0 0 • • MUL W B,A
D MUL D B,A
In multiplication, the product always occupies the double width of the

output operands.
Byte / word multiplication

7/15 0
MUL B/W B, A ; SRC sg B
B/W
x
; DEST sg A
B/W
15/31 =
; DEST sg A
W/D
Double-word multiplication
31 0
MUL D B, A ; SRC-D sg B
x
; DEST-D sg A
=
; DEST-D A
and
; DEST-D sg B
+1
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7.18.4 IVIDE instructions

DIV B K , R • 0 • • • DIV B 100,A Fixed-point division of signed integers.
W R • 0 • • • DIV W B,A
D DIV D B,A
In division, the dividend always occupies the double width of the divisor.
Byte / word division

15/31 0
DIV B/W B, A ; DEST sg A
W/D
7/15 : 0
; SRC sg B
B/W
15/31 = 0
; DEST-D A: HIGH BY = Rest sg LOW BY = Quotient
Double-word division
63 32
DIV W C, A ; DEST-D sg B
+1
31 0
; DEST-D A
31 : 0
; SRC-D sg C
=
; DEST-D sg A: Quotient
; DEST-D B: Rest
+1
⇒ In the case of a division by 0, the division instruction is not carried

out, and the overflow bit goes HIGH. The overflow bit is also set
HIGH in the case of division overflow.
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7.19 Floating Point Arithmetic
Data formats, accuracy

The floating-point arithmetic supports the data formats specified in the
IEEE 754 and IEE 854 standards.
Two data formats, REAL and LREAL, are defined in accordance with
IEC1131.
Data format Data width Mantissa Exponent Range

REAL 32 bits 24 bits 8 bits 10±38
Short, real floating-point number, single
precision
LREAL 64 bits 53 bits 11 bits 10±308
Long, real floating-point number, double
precision
Data format L always uses the register pairs AB and CD.
When calculating with the REAL data format, inaccuracies in the decimal
range will occur sooner than with the LREAL format. If a high degree of
accuracy is required, the LREAL format should be used. The appropriate
conversion routines are available in WinSPS v2.4 with WinPanel, v1.5
and higher.
The floating-point formats do not permit the representation of all numbers

in any desired resolution. For example, if one wants to work with a unit of
measure such as µm, which is quite common in mechanical engineering,
the REAL data format permits, for each individual µm, a representation
with a limit value of 16.0 metres. If the LREAL format is chosen instead,
the representation of numbers up to 17,179,869,184.0 m becomes
possible.
Display resolution Limit value

Floating-point notation Exponential notation REAL LREAL
0
1.0 E 16,777,228.0 18,014,398,509,481,984.0
-1
0.1 E 1,048,576.0 1,125,899,906,842,624.0
-2
0.01 E 131,072.0 140,737,488,355,328.0
-3
0.001 E milli m 16,384.0 17,592,186,044,416.0
-4
0.0001 E 1,024.0 1,099,511,627,776.0
-5
0.00001 E 128.0 137,438,953,472.0
-6
0.000001 E micro µ 16.0 17,179,869,184.0
-7
0.0000001 E 1.0 1,073,741,824.0
-8
0.00000001 E 0.125 134,217,728.0
-9
0.000000001 E nano n 0.015625 16,777,216.0
-10
0.0000000001 E 0. 000976563 1,048,576.0
-11
0.00000000001 E 131,072.0
-12
0.000000000001 E pico p 16,384.0
-13
0.0000000000001 E 1,024.0
-14
0.00000000000001 E 128.0
-15
0.000000000000001 E femto f 16.0
-16
0.0000000000000001 E 1.0
-17
0.00000000000000001 E 0.125
-18
0.000000000000000001 E atto a 0.015625
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Operands
Depending on the instruction, the following may be used as floating-point
operands:
• M, S, DM, DF, D, DX
with both direct and indirect addressing.
The specified operand address must be divisible as follows: - by 4 for
REAL data format REAL
- by 8 for LREAL data format.
• K, register
• P
A PM parameter may not be used as a floating-point constant. In the
event that this is required, the constant may first be loaded into a
marker word, for example.
Instructions
The floating-point data formats and operands may be used in the
following instruction types:
• LOAD floating point value
• TRANSFER floating point value
• CONVERT
• COMPARE floating point values
• Basic arithmetic functions
• Forming absolute value
• Extracting square root
• Logarithmic functions
• Trigonometric functions
Error displays, range overlaps

Calculating errors and range violations (overlaps) are displayed on the
screen of the Programming Unit (PG) in Monitor Mode.
Exceeding the greatest possible number, and division by 0:

++++++.++++++
Shortfall of smallest possible number:

------.------
Nondisplayable number, calculating errors:

******.******
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7.19.1 LOAD floating point value

L R K , R • L R 12,321,A REAL constant → Register A
L R • L L A,C LREAL Register pair AB → CD
M, S, • L L M8,C LREAL M8 through M15 → Register pair CD
DP, DF, D, DX • L R DF16,B REAL DF16 through DF23 → Register B
P • L R P0,D REAL P0 → Register D
OPD[R] • L L D[A],C LREAL contents of operand addressed by Register A →
Register C
7.19.2 TRANSFER floating point value

T R R , M, S, • T R A,M0 REAL Register A → M0 through M3
L , DP, DF, D, DX • T L A,DF0 LREAL Register pair AB → DF0 through DF7
, P • T R D,P0 REAL Register D → P0
, OPD[R] • T L D,[A] LREAL contents of register D
to operand addressed by register A.
7.19.3 CONVERT number formats

• Converting 32-bit integer values to floating-point REAL / LREAL.
• Converting floating-point REAL / LREAL to 32-bit integer values.

ITF R R • ITF R A Converts 32-bit integer values from
L
register A to REAL floating-point format.
ITF L C Converts 32-bit integer value from
register C to LREAL floating point. .The
result is written to register pair CD.
FTI R R • FTI R A Converts REAL floating-point from
L
register A to 32-bit integer value.
FTI L C Converts LREAL floating-point from
register pair CD to 32-bit integer value. The
result is written to register C.
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7.19.4 CONVERT data formats

In the REAL data format, inaccuracies may occur in the decimal
positions. If better accuracy is required, the LREAL data format must be
used. To handle the required data format conversion, specific convert
instructions are provided.

RTL R • RTL A Converts the LREAL value of register A to a
REAL value.
Destination register pair = AB.
RTL C Converts the REAL value of register C to an
LREAL value.
Destination register pair = CD.
LTR R • LTR A Converts the LREAL value of register pair AB
to REAL value.
Destination register = A.
LTR C Converts the LREAL value of register pair
CD to a REAL value.
Destination register = C.
7.19.5 Removing decimal positions

TRC R R • TRC R A Writes the value in register A back to register
L
A, but without decimal positions.
TRC L C Writes the value in register pair CD back to
CD, but without decimal positions.
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7.19.6 COMPARE floating point values

CPLA R M/K , R • • • • • • CPLA R M4,A Compare REAL M4 thru M7 w/ register A.
L
S/DF/D/ • • • • • • CPLA L D200,C Compare LREAL D200 thru D208 w/ register
DX/DP
CD.
R • • • • • • CPLA L A,C Compare LREAL register pair AB w/ CD.
P • • • • • • CPLA R P62,A Compare REAL REAL P62 w/ register A.
OPD[R] • • • • • • CPLA L M[C],A Compare LREAL contents of operand
addressed by register C w/ register pair AB.
When comparing the REAL and LREAL data formats, the flags require
arithmetical interpretation.
Examples:
Compare DEST A with SRC B CPLA B,A

Jump instruction
Equal A=B JPZ
Unequal A≠B JPN
Less than A<B JPM
Less than / equal A≤B JPMZ
Greater than A>B JPAG
Greater than/ equal A≥B SPP
⇒ When using the CPLA instruction, the evaluation of the compare

results must always be programmed immediately following the
compare instruction itself. The user is advised to bear in mind that
binary operations will cause a modification of the flags. Therefore, a
compare result can be used only in a link. Following this, another
CPLA instruction must again be programmed.
⇒ With various resolutions (decimal positions) the compare operation

in the REAL data format returns correct results only up to specific
limit values.
Display resolution Limit value

0.001953125 256.0000
0.03125000 2048.000
0.2500000 32768.00
2.000000 262144.0
32.00000 2097152
Example:
L R 2048.00000,A
CPLA R 2048.00009,A
The difference is not found, and the numbers are recognized as being
equal, Z = 1.
For large numbers at high resolution the LREAL data format must be
used.
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7.19.7 Calculating with floating point values

For working with floating-point values, the basic arithmetic functions are
available:
Addition, subtraction, multiplication and division.
The instructions handling the four basic arithmetic functions offset the
contents of the destination register or register pair against the contents of
the SRC operand. The results are always written to the destination
register or register pair.

ADD R M/K , R • • • • • ADD R M2,A REAL M2 thru M5 plus register A contents.
SUB L S/DF/D/DX/DP • • • • • SUB L D200,C LREAL register CD minus D200 thru D208.
R • • • • • ADD L A,C LREAL register pair AB plus CD.
P • • • • • SUB R P62,A REAL register A minus P62.
OPD[R] • • • • • SUB L M[C],A LREAL contents of register pair AB minus
operand addressed by register C.
MUL R K , R • • • • • MUL R 123.456,A REAL 123.456 multiplied w/ contents of
DIV L
register A.
R • • • • • DIV L A,C LREAL register pair CD divided by register pair
AB.
7.19.8 Forming absolute value

Absolute values are always formed with the use of a register or register
pair. The ABS instruction returns the absolute value of a number.
Negative numbers are returned as positive values. If the number is 0, the
zero bit will go HIGH.

ABS R R • • ABS R A Return absolute value of REAL contents of
L
register A.
ABS L C Return absolute value of LREAL contents of
register pair CD.
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7.19.9 Extracting square root

Square root extraction always uses a register or register pair. The result
is then written to the same register or register pair.

SQRT R R • • • • • SQRT R A Extract square root of REAL contents of
L
register a.
SQRT L C Extract square root from LREAL contents of
register pair CD.
7.19.10 Exponentiation
Y
For exponentiation X , the following procedure is used:
• In REAL format, registers A and C are used, with register A holding
the base, and C the exponent. The result is written to register A.
• In LREAL format, register pairs AB and CD are used, with AB holding
the base, and CD the exponent. The result is written to register pair
AB.

POW R R R • • • • • POW R A,C Exponentiate the REAL contents of register A
L
with the REAL contents of register C. The
result is written to register A.
POW L A,C Exponentiate the LREAL contents of register
pair AB with the LREAL contents of CD. The
result is written to register pair AB.
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7.19.11 Logarithmic functions

The instructions for logarithmic functions calculate the contents of a
register or register pair. The results are always written to the destination
Realisiert sind:
• Natural logarithm
• Base-10 logarithm
• Forming exponential function from base-10 (common) logarithm

LN R R • • • • • LN R A Form natural logarithm from REAL contents of
LOG L
EXP
register A.
LOG L C Form common logarithm from LREAL contents
of register pair CD.
EXP R C Form exponential value from common
logarithm of REAL contents in register C.
7.19.12 Trigonometric functions

The instructions for trigonometric functions calculate the contents of a
register or register pair. The results are always written to the destination
Realized are:
• Sinus, with entry in radian measure
• Cosine, with entry in radian measure
• Tangent, with entry in radian measure
• Arc sine, main value
• Ant cosine, main value
• Arc tangent, main value

SIN R R • • • • • SIN R A Form sine from REAL contents of register A.
COS L
TAN COS L C Form cosine from LREAL contents of register
ASIN pair CD.
ACOS
TAN R C Form tangent from REAL contents of register
ATAN
C.
ASIN R A Form arc sine from REAL contents of register
A.
ACOS L C Form arc cosine from LREAL contents of
register pair CD.
ATAN R C Form arc tangent from REAL contents of
register C.
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7.20 Parameter Assignments

Pn B/W/D/ I/O/M/T/C/K • P0 I0.0 Parameter definition for parameterized module
R/L S/SM/SYM • P1 W S0
D/DX/DF/DP P2 W D0
calls.
•
FC/DM • P3 PM0 REAL and LREAL not as a constant.
n: 0 through 62
7.21 Local Symbol Names & Auxiliary Markers for Program Tracking

DEF I/O/M/T/C/K , SYM DEF I0.0,-Symbol Definition of symbolic names that are locally
S/SM/SYM DEF I0,-Name
D/DX/DF/DP
valid only within the module in which they have
FC/DM been entered. Essential for the creation of
library modules.
* n * 1 Definition of auxiliary flags for program
n = 0 bis 63
tracking. Processing of these flags is written
only into the marker buffer, and is interpretable
only in case of an error. The auxiliary flag has
no influence on the program.
7.22 System Variable

DEFW W K DEFW W 16#0000 Definition of function for system variable in
OM2.
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7.23 Jump Instructions

Jump operations may be executed unconditionally, and also in
dependence of a binary link and/or mathematical operation (see also
Section 7.2, ). With one exception (JP [R]), Jump instructions are
programmed symbolically, with the understanding that the entry point
may not bee located within a program branch because this would also
cause the RES at the jump origin point to be linked.

JP SYM • JP -LABEL1 Unconditional to -LABEL
[R],n* • JP [A]
destination.
Unconditional, by jump distance in
register A.
JPB SYM • • 1 JPB -LABEL2 Conditional, see flags.
JPCI SYM • • 0 JPCI -LABEL3 Conditional, see flags.
JPCY SYM • 1 JPCY -LABEL4 Conditional, see flags.
JPCN SYM • 0 JPCN -LABEL5 Conditional, see flags.
JPO SYM • 1 JPO -LABEL6 Conditional, see flags.
JPON SYM • 0 JPON -LABEL7 Conditional, see flags.
JPM SYM • 1 JPM -LABEL8 Conditional, see flags.
SPP SYM • 0 SPP -LABEL9 Conditional, see flags.
JPZ SYM • 1 JPZ -LABEL10 Conditional, see flags.
JPN SYM • 0 JPN -LABEL11 Conditional, see flags.
JPAG SYM • 1 JPAG -LABEL12 Conditional, see flags.
JPMZ SYM • 0 JPMZ -LABEL13 Conditional, see flags.
JPLG SYM • 1 JPLG -LABEL14 Conditional, see flags.
JPCZ SYM • 0 JPCZ -LABEL15 Conditional, see flags.
The JP [R] instruction causes an unconditional jump whose entry point
must always be a jump instruction. This instruction variant was created
specifically for the simple implementation of jump distributors. The
controller monitors the mnemonical code of the entry point, and enters
STOP mode if this fails to correspond to any jump instruction. In such
case, the error status of the Programming Unit (PG) provides information
about the cause of the error.
The parameter n can be specified for the purpose of jump sequence

monitoring, i.e., n can be less or equal to the jump count.
The following example denotes the application of this jump instruction.
1070 072 189 - 108 (02.09) GB

Example:
PLC program interlude
Fixed program sequence
Jump distance calculation in register A for the following jump sequence:

A may have odd-numbered values only (1, 3, 5, ...).
JP [A],n ; 1-word instruction

JP Ziel1 ; 2-word instruction
JP Ziel2 ; 2-word instruction
:
:
JP Zieln ; 2-word instruction
Ziel1: ; Program part 1
PLC program
JP End
Ziel2: ; Program part 2
PLC program
JP End
:
:
:
:
:
Zieln: ;Program part n
PLC program
JP End
:
:
End
PLC successor program
:
1070 072 189 - 108 (02.09) GB

7.24 Module Calls

Module calls may be executed unconditionally, in dependence of a binary
link, or as a result of a calculation example (see also Section 7.2, ).
The PCL uses a module nesting depth of 63 program modules.
Two data modules may be kept enabled at the same time. For this
purpose the following module calls are available:
CM, BAB, BAI DMx: enables DMx as 1st DM
BX, BXB, BXI DMy: enables DMy as 2nd DM

CM DM • CM DM0 Unconditional, direct.
BX PM • CM PM0
PM , n • CM PM1,2 Parameterized, list to follow.
P • CM P0 As parameter.
P , n • CM P0,2 As parameter; parameterized, list to follow.
PM[R] • CM PM[A] Indirect
CMC DM • • 1 CMC DM0 Conditional, see flags.
BXB PM • CMC PM0 Direct
PM , n • CMC PM1,2 Parameterized, list to follow.
P • CMC P0 As parameter.
P , n • CMC P0,2 As parameter; parameterized, list to follow.
PM[R] • CMC PM[A] Indirect
CMCI DM • • 0 CMCI DM0 Conditional, see flags.
BXI PM • CMCI PM0 Direct
PM , n • CMCI PM1,2 Parameterized, list to follow.
P • CMCI P0 As parameter.
P , n • CMCI P0,2 As parameter, parameterized. List to follow.
PM[R] • CMCI PM[A] Indirect
CMCY DM • 1 CMCY DM0 Conditional, see flags.
PM • CMCY PM0 Direct
PM , n • CMCY PM1,2 Parameterized, list to follow.
P • CMCY P0 As parameter.
P , n • CMCY P0,2 As parameter; parameterized, list to follow.
PM[R] • CMCY PM[A] Indirect
CMCN DM • 0 CMCN DM0 Conditional, see flags.
PM • CMCN PM0 Direct
PM , n • CMCN PM1,2 Parameterized, list to follow.
P • CMCN P0 As parameter.
P , n • CMCN P0,2 As parameter; parameterized, list to follow.
PM[R] • CMCN PM[A] Indirect
CMO DM • 1 CMO DM0 Conditional, see flags.
PM • CMO PM0 Direct
PM , n • CMO PM1,2 Parameterized, list to follow.
P • CMO P0 As parameter.
P , n • CMO P0,2 As parameter; parameterized, list to follow.
PM[R] • CMO PM[A] Indirect
CMON DM • 0 CMON DM0 Conditional, see flags.
PM • CMON PM0 Direct
PM , n • CMON PM1,2 Parameterized, list to follow.
P • BAPN P0 As parameter.
P , n • CMON P0,2 As parameter; parameterized, list to follow.
PM[R] • CMON PM[A] Indirect
1070 072 189 - 108 (02.09) GB


CMM DM • 1 CMM DM0 Conditional, see flags.
PM • CMM PM0 Direct
PM , n • CMM PM1,2 Parameterized, list to follow.
P • CMM P0 As parameter.
P , n • CMM P0,2 As parameter, parameterized.
[R] • CMM PM[A] Indirect
CMP DM • 0 CMP DM0 Conditional, see flags.
PM • CMP PM0 Direct
PM , n • CMP PM1,2 Parameterized, list to follow.
P • CMP P0 As parameter.
P , n • CMP P0,2 As parameter, parameterized.
[R] • CMP PM[A] Indirect
CMZ DM • 1 CMZ DM0 Conditional, see flags.
PM • CMZ PM0 Direct
PM , n • CMZ PM1,2 Parameterized, list to follow.
P • CMZ P0 As parameter.
P , n • CMZ P0,2 As parameter, parameterized.
PM[R] • CMZ PM[A] Indirect
CMN DM • 0 CMN DM0 Conditional, see flags.
PM • CMN PM0 Direct
PM , n • CMN PM1,2 Parameterized, list to follow.
P • CMN P0 As parameter.
P , n • CMN P0,2 As parameter, parameterized.
PM[R] • CMN PM[A] Indirect
DM • 1 CMAG DM0 Conditional, see flags.
CMAG PM • CMAG PM0 Direct
PM , n • CMAG PM1,2 Parameterized, list to follow.
P • CMAG P0 As parameter.
P , n • CMAG P0,2 As parameter, parameterized.
PM[R] • CMAG PM[A] Indirect
DM • 0 CMMZ DM0 Conditional, see flags.
CMMZ PM • CMMZ PM0 Direct
PM , n • CMMZ PM1,2 Parameterized, list to follow.
P • CMMZ P0 As parameter.
P , n • CMMZ P0,2 As parameter, parameterized.
PM[R] • CMMZ PM[A] Indirect
DM • 1 CMLG DM0 Conditional, see flags.
CMLG PM • CMLG PM0 Direct
PM , n • CMLG PM1,2 Parameterized, list to follow.
P • CMLG P0 As parameter.
P , n • CMLG P0,2 As parameter, parameterized.
Fc[R] • CMLG PM[A] Indirect
DM • 0 CMCZ DM0 Conditional, see flags.
CMCZ PM • CMCZ PM0 Direct
PM , n • CMCZ PM1,2 Parameterized, list to follow.
P • CMCZ P0 As parameter.
P , n • CMCZ P0,2 As parameter, parameterized.
PM[R] • CMCZ PM[A] Indirect
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7.25 End of Module Instruction

The use of End of Module instructions is possible either unconditional,
conditional by a binary link or based on the result of an arithmetical
operation (see also section 7.2).

EM EM Unconditional
EMC 1 EMC Conditional, see flags.
BEI 0 BEI Conditional, see flags.
EMCY 1 EMCY Conditional, see flags.
EMCN 0 EMCN Conditional, see flags.
EMO 1 EMO Conditional, see flags.
EMON 0 EMON Conditional, see flags.
EEM 1 EEM Conditional, see flags.
EMP 0 EMP Conditional, see flags.
EMZ 1 EMZ Conditional, see flags.
EMN 0 EMN Conditional, see flags.
EMAG 1 EMAG Conditional, see flags.
EMMZ 0 EMMZ Conditional, see flags.
EMLG 1 EMLG Conditional, see flags.
EMCZ 0 EMCZ Conditional, see flags.
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7.26 FIFO Instructions

The PCL provides four FIFO buffers, designated FI0 through FI3. Each
FIFO buffer has a size of 1024 bytes. Reading from and writing to the
FIFO buffers is accomplished with the LFI and TFI instructions.
A single instruction reads or writes 1 to 32 bytes.
The number of bytes to be handled by means of the LFI / TFI instruction

is variable, and is declared in Register C.
Exception: In the event that register contents are written to or read from
FIFO buffers, the number of bytes will be defined via the operand
attribute W/BY. Accordingly, operand attribute BY = one byte; operand
attribute W = two bytes.
When the number of bytes to be handled is variably declared in Register

C, each FIFO byte that is read or written causes the value in Register C
to be decremented.
In the case of a FIFO buffer overflow or underflow, the value stored in

Register C provides information about the number of bytes that could no
longer be read or written.
FIFO overflow or underrun will not automatically cause a ZS STOP. As

an indication of a FIFO overflow, carry bit SM31.3 goes HIGH. A FIFO
underrun causes zero bit SM31.7 to go HIGH.
The FIFO buffer is flushed with the RFI (Reset FIFO) instruction.
FIFO buffers are always remanent.
All FIFO instructions are RES-independent.

LFI B FIn , M/S/SYM • Ü:• U:• LFI B FI2,DF30 Read from FIFO buffer.
W n = 0 bis 3 , D/DX • Ü:• U:• LFI B FI3,D[A] Number of bytes in C.
D , DF/DP • Ü:• U:• LFI B FI0,A 1 Bytes from FIFO into register A
R , OPD[R] • Ü:• U:• LFI W FI0,A 2 Bytes from FIFO into register A
L , R • Ü:• U:• LFI D FI0,A 4 Bytes from FIFO into register A
TFI B M/S/SYM , FIn • Ü:• U:• TFI B DF0,FI2 Write to FIFO buffer.
W D/DX n = 0 bis 3 • Ü:• U:• TFI B D[A],FI3 Number of bytes in C.
D DF • Ü:• U:• TFI B A,FI0 1 Bytes from register A into FIFO.
R [R] • Ü:• U:• TFI W A,FI0 2 Bytes from register A into FIFO.
L R • Ü:• U:• TFI D A,FI0 4 Bytes from register A into FIFO.
RFI FIn RFI FI0 Flush FIFO bugger.
n = 0 bis 3
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7.27 Block Commands

Block commands are provided as a comfortable means of loading and
transferring, and also comparing and searching data blocks within the
PCL. The maximum size of the referred data blocks is 512 bytes/256
words/128 double words. The operand attribute indicates whether the
block size refers to byte, word, double word, REAL or LREAL size.
⇒ The following minimum release versions are a prerequisite for the

use of operands I and O in block commands:
WinSPS v3.1
PCL v2.2
CL550 v1.1.

BLT B/W/D/ M/S , M/S • BLT B M0,D0 Block transfer from source address →
R/L E/A , A • BLT W DF[B],M[A]
D/DX , D/DX destination address, block size in Register C
•
DP/DF , DP/DF •
OPD[B] OPD[A] •
CFxx B/W/D M/S , M/S • • CFZ W M0,D0 Forward/ backward Compare operation
CBxx E/A , E/A • CBN B M[B],D[C]
D/DX , D/DX
within block.
•
DP/DF , DP/DF •
OPD[B] OPD[A] •
SFxx B/W/D K , M/S • • SFZ W 50,M20 Forward/ backward Search operation within
SBxx R , E/A • SBLG B B,M[A]
, D/DX
block.
•
, DP/DF •
OPD[A] •
Block transfer
Block transfers are accomplished by shifting data block of defined size, whereby
the data block may not overlap. Block transfers use only ascending addresses
(incremental).
Example 1
CM DM10 ; 1st DM
BX DM9 ; 2nd DM
L D 50,C ; Block size = 50
BLT W D20,DX40 ; Copy 50 words, from DM9/D20 up, to DM10/D40.
Example 2
L D 50,A ; DEST address offset
L D 50,B ; SRC address offset
BLT D DF[B],M[A] ; Copy 50 double words, from DF50 up, to M50.
1070 072 189 - 108 (02.09) GB

Block COMPARE
The function compares two data blocks.
When the compare condition is met, processing is stopped, and the
number of uncompared bytes/words written to register C. When using
prefix addressing, the operand addresses too are output to registers a
and B.
The zero flag goes HIGH when the compare conditions were not met
throughout the entire range.
Block compare operations are possible in forward direction on ascending

addresses, and in backward direction on descending addresses.
By interpreting the flags, C, and M, and their respective combinations, 8

compare criteria are available.
OPP Explanation
Compare Forward operation for the following:
CFZ Equal
CFN Unequal
CFAG Arithmetical greater
CFM Arithmetical less
CFLG Logical greater
CFCY Logical less
CFCN Logical greater or equal
CFCZ Logical less or equal
Compare Backward operation for the following:
CBZ Equal
CBN Unequal
CBAG Arithmetical greater
CBM Arithmetical less
CBLG Logical greater
CBCY Logical less
CBCN Logical greater or equal
CBCZ Logical less or equal
DEST block address direct or in register A, SRC block address direct or
in register B, block size always in register C.
Example 1
CM DM10 ; 1st DM
CFLG W D20,M20 ; Compare forward 50 words f. Logical Greater,
; starting at DM10/D20 with marker from M20 up.
Example 2:
L D 50,B ; SRC address offset
CBZ D DF[B],M[A] ; Compare backward 50 double words for Equal,
; starting at DF50 with marker from M50 up.
Result evaluation of compare condition:

• Not met: Z-flag = 1
• Met: Z-flag = 0
• Register A contains the operand offset in the DEST block.
• Register B contains the operand offset in the SRC block.
• Register C contains the count of data that was not compared.
1070 072 189 - 108 (02.09) GB

Block search
The function searches for a character within a data block.
When the character is found, the number of bytes/words that were not
searched is stored in register C. With the use of prefix addressing,
register A will also contain the operand address.
If the character was not found (search condition not met) throughout the
entire range, the zero flag goes HIGH.
Through the interpretation of flags C, M, and Z, and their respective

combinations, 8 search criteria are available.
OPP Explanation
Search Forward for character:
SFZ Equal
SFN Unequal
SFAG Arithmetical greater
SFM Arithmetical less
SFLG Logical greater
SFCY Logical less
SFCN Logical greater or equal
SFCZ Logical less or equal
Search Backward for character:
SBZ Equal
SBN Unequal
SBAG Arithmetical greater
SBM Arithmetical less
SBLG Logical greater
SBCY Logical less
SBCN Logical greater or equal
SBCZ Logical less or equal
Block start address direct or in register A, search values as constants or
in register B; block size always in register C.
Example 1
SFLG B 35,M20 ; Search forward 50 bytes, starting at M20,
; for the value 35.
Example 2
CM DM10
L D 50,B ; Search value
SRZ D B,M[A] ; Search backward 10 bytes , starting at M20,
; for the value 50.
Result evaluation of Search operation (condition):

• Not met: Z-flag = 1
• Met: Z-flag and = 0
• Register A contains the operand offset in the DEST block.
• Register C contains the count of data was not searched.
1070 072 189 - 108 (02.09) GB

7.28 Interrupt Instructions

TIM R , TI • TIM A,TI Transfers interrupt mask. Writes interrupt mask
for enabling / disabling interrupts. The mask was
first loaded into a register.
LIM TI , R • LIM TI,B Loads interrupt mask, define interrupt mask.
EAI TI • EAI TI Enables interrupt group.
DAI TI • DAI TI Disables interrupt group.
LAI TI , R • LAI TI Loads interrupt register, reads statuses.
RI R , TI • RI A,TI Resets interrupts based on a mask that was first
loaded.
7.29 Program Stop & Program End

HLT HLT HALT instruction. Controller enters STOP mode,
program address is entered into error stack, and
outputs are cleared (deleted).
PE PE Program End. I/O state is initialized, and the
program cycle start again at the beginning. At
least one EP instruction must be present.
7.30 Backing Up & Loading Remanence Areas

Backing up and loading remanent data between static RAM and PLC:
• Backup: PLC " static RAM
• Loading: static RAM " PLC
Remanence areas to be backed up or loaded are:
• Only data modules as marked with remanence ID in symbol file.
• Operands as per remanence limits set in OM2.
For PCL, refer to Section PCL 2.5.3.2, "Backing up remanence areas on

request"; for CL550, see Section 3.5.2.2.
In the case of markers and the data field, specific areas of the defined
remanence area (Offset, Number in table below) can be specified for the
backup / loading procedures.

RS DMn RS DM1 Backs up DM1 to static RAM.
M, T, Z, RS M Backs up remanent area, as defined in OM2.
DF, DP RS DF
M, DF Off,Anz RS M10,50 Remanence from M10 up, backup of 50 bytes.
RL DMn RL DM1 Loads DM1 from static RAM.
M, T, Z, RL M Loads remanent area, as defined in OM2.
DF, DP RL DF
M, DF Off,Anz RL M10,50 Remanence from M10 up, loads 50 bytes.
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Processing Times 8-1
8. Processing Times
8.1 PCL Processing Intervals

The program cycle time in the PCL is dependent on the interaction
between the Microsoft Windows and VxWorks operating systems, and
on several parameters that are discussed below.
• Processor speed. The PC processor responds to the instruction

processing times in an almost linear fashion.
Example: Processing times for a 200 MHz Intel Pentium CPU:
Bit instructions approx. 55 ns
Word / double word approx. 30 ns
instructions
Data module access approx. 110 ns
Floating point instructions approx. 300 to 500 ns
• System timing. Selectable in WinPanel in increments of 1 ms, 2 ms, 5

ms and 10 ms. Especially in the case of very short PLC programs
(shorter than system timing intervals), system timing is essentially
governing PLC cycle time because the next PLC cycle is always
started only after receiving the subsequent system timing signal, refer
to example 1.
Exceptional case:
At least 25% of the system clock speed must be available to process
Windows applications, otherwise another clock will be provides for
their processing, see Example 2.
• Allocated Windows calculating time ('calc-time'). Selectable in

WinPanel as an interrelation of system clock speed and Windows
calculating time. Possible settings are 9/1, 3/1, 1/1, 1/3, and 1/9. This
speed ratio takes effect only if the PLC processing time exceeds the
currently selected system clock speed, see Examples 3 and 4.
• WinPanel startup with fixed default cycle time. The PLC cycle time can
be preset to a fixed value. This is accomplished by means of one of
the WinPanel startup parameters, i.e., WinPanel/Zn, where n is the
value in ms. In this context, care must be taken that the actual PLC
processing time is smaller than the selected value because otherwise
the preselected cycle time will be exceeded. See Example 5.
• I/O image transfer time to bus master. The image transfer time to the
bus master handling the decentralized peripherals is approx. 1 ms.
This time value is integrated in the PLC processing time in the
following sample diagrams.
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8-2 Processing Times
System clock speed vs. Windows calculating time

Selectable combinations:
10 25 50 75 90
Windows calc-time / system speed
ratio [%].
9/1 3/1 1/1 1/3 1/9 System clock / Windows clock ratio
System 1 x x x x x
clock [ms] 2 x x x
5 x
10 x x: permitted settings
⇒ Default setting:
System clock = 1 ms, share in Windows calc-time = 50 %. In normal
circumstances these values do not require user modification. Only
in the event that a specific application necessitates another setting
– because significantly more calc-time is required for Windows
applications – should these values be changed.
When using an integration of the MMI-MADAP and the PCL in the
same device, the following settings have produced good results:
System speed = 5 ms, Windows calc-time ratio = 50 %.
PLC Processing Time

Throughout the following examples, the PLC processing time denotes the
actual length of the program processing interval, which includes the
transfer of the I/O image to the bus master.
Die SPS-Zykluszeit ist als die Zeit definiert die von einem
Programmanfang bis zum nächsten vergeht.
System clock
OM1 ... ... I/O image Windows calc-time OM1 ...
PE
← PLC Processing Time →

← PLC Cycle Time →
System clock / Windows clock ratio

The system clock / Windows clock ratio will be effective only if the PLC
processing time is greater than the system clock speed.
1070 072 189 - 108 (02.09) GB

PLC processing time vs. Windows calc-time

When the PLC processing time is shorter than 75% of the system clock
speed, Windows still has free resources available for other applications,
see also Example 1. In this case the next PLC cycle starts with the next
system clock pulse.
← System clock → ← System clock → ← System clock →
  PLC
 Windows
← <75 % →  
 
Next PLC Next PLC
cycle cycle
A more critical controller behavior occurs when the PLC processing time
exceeds this 75% limit. In this case, all settings must be optimized.
Example 1
Preconditions:
• System clock = 2 ms
• System clock / Windows clock ratio = 3/1
• PLC processing time = 1.2 ms
← 2 ms →
1 2 3 4 5 6 System clock
  PLC
 Windows
    
    
Next PLC Next PLC Next PLC Next PLC Next PLC
cycle cycle cycle cycle cycle
In this situation, because the PLC processing time of 1.2 ms is shorter

than 75% of the system clock of 2 ms, the system clock / Windows clock
ratio of 1/3 does not have an effect.
The PLC program finishes in time, and Windows is given sufficient time
for processing Windows applications.
1070 072 189 - 108 (02.09) GB

Example 2
Preconditions:
← 2 ms →
  PLC
 Windows
<25%  
for  
Windo Next PLC Next PLC
ws cycle cycle
The length of the PLC processing time exceeds 75% of the system clock
rate.
In this case, a stipulation takes effect stating that >25% of the system
clock rate must be provided for Windows applications. Because this is not
the case, there remains insufficient time for processing Windows
programs, and an additional pulse for Windows is inserted. In this
example, the system clock / Windows clock ratio of 1/3 has no effect.
Example 3
Preconditions:
← 2 ms →
  PLC
 Windows
2 ms PLC 0.2 ms leftover 
processing time PLC processing 
time Next PLC cycle
← 25 % PLC → ← 75 % Windows →
The PLC program takes longer than the selected system clock speed.
Upon conclusion of the first system cycle, Windows receives 3 cycles for
processing. The remainder of the PLC program is processed during the
5th system cycle. The next PLC cycle will start only in the 6th system
cycle. In this example, the system clock / Windows clock ratio of 3/1
takes effect.
1070 072 189 - 108 (02.09) GB

Example 4
Preconditions:
← 2 ms →
  PLC
 Windows
5.6 ms PLC processing time 

Next PLC cycle
← 75 % PLC → ← 25 % Windows →
Upon conclusion of the first system cycle, Windows receives 1 cycle for
processing. The next PLC cycle will start only in the 5th system cycle. In
this example, the system clock / Windows clock ratio of 3/1 takes effect.
Example 5
Preconditions:
• Fixed predefined PLC cycle time = 20 ms, WinPanel start parameter
/Z20
• Actual PLC processing time = 3.0 ms
← 2 ms →
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 System clock
  PLC
 Windows
2 ms PLC 1 ms Windows, until predefined time has elapsed. 
processing leftover 
time PLC Next PLC
processi cycle
ng time
Upon conclusion of the first system cycle, Windows receives 1 system
cycle for processing. The remainder of the PLC program is processed
during the 3rd system cycle. At the end of this interval, Windows is able
to use the CPU performance until the 20 ms have elapsed. In this
example, the system clock / Windows clock ratio of 1/1 takes effect.
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8.2 CL550 Processing Intervals

In the CL550, the command processing times are as follows:
Bit instructions approx. 60 ns

Word / double word instructions approx. 35 ns
Data module access approx. 130 ns
Floating point instructions approx. 350 to 600 ns
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Sample Programs 9-1
9. Sample Programs
9.1 Indirect Addressing

; DM verification, checking
; a) for attendance of DM1-DM16, plus generating
; b) "attendance bits" in result DM0/D0
; c) Writing DM sizes into result DM, starting with D2
L D 1,A ; Starting with DM1

L D 0,B ; DM attendance bits in result DM in D0
L D 2,C ; DM sizes in result DM, starting with D2
L D 0,D ; DM no of result DM
CM DM[D] ; result DM indirect module call
nicht_fertig:
; Check DMs and write results
U DM[A] ; Check DM, indirect module attendance check
= D[B] ; If applicable, set attendance bit HIGH, ind. bit addressing.
PUSH D A ; Save DM no.
L D DM[A] ; Load DM size, indirect module length verification.
T W A,D[C] ; Write to size word, indirect double word addressing
POP D A ; Write back DM no.
; Increment address
INC D A,1 ; next DM
INC D B0.1 ; next DM attendance bit
INC D C0.2 ; next DM size word
; All 16 predefined DMs processed?
CPLA D 16,A
JPCZ nicht_fertig; Jump on less than or equal
EM
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9-2 Sample Programs
9.2 COMPARE Instruction

; Simulated compare value
;----------------------------
L W M0,A ; Load markers M0-M1
INC W A,1 ; Increment register
T W A,M0 ; Write value into markers M0-M1
; 1. Compare for "equal"

;-----------------------------
L W M0,A ; current M0-M1 status

CPLA W 10000,A ; value 10.000 attained?
; Interpretation via links

U Z ; value 10.000 attained!
CU Z0 ; increment counter C0 by 1
; Ínterpretation via jump instruction

JPN nicht_0
L W 0,A ; upon attaining value 10.000,
T W A,M0 ; ... delete M0-M1
nicht_0:
; 2. Range/area monitoring
;------------------------
; Check value range 4000-6000

CPLA W 4000,A
JPCY Bereich_niO ; Value must not be less than 4000
CPLA W 6000,A
JPCN Bereich_niO ; ... and not greater than 6000
; Increment marker M2 in value window 4000-6000

L D M4,B ; Read markers M4-M7
INC D B0.100 ; Increment register
T D B,M4 ; Write value to markers M4-M7
Bereich_niO:
(range NOK) ; Delete markers M0-M1 and counter C0 via trigger pulse
U -RI_Anl
JPCI kein_RI
L D 0,A ; Write value 0
T W A,M0 ; ... to markers M0-M1
SC A,Z0 ; ... and T0
T D A,M4 ; ... on markers M4-M7
kein_RI:
EM
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Sample Programs 9-3
9.3 FIFO Instructions

DEF SM31.1,-log1
DEF SM31.6,-carry
DEF SM31.7,-zero
DEF M0.0,-trouble
DEF M2.0,-nofifo
DEF M6,-rest
DEF M8.0,-RFI
;Transferring data into a FIFO buffer:
BX -db5 ; open data module
A -nofifo ; FIFO instruction locked?

JPB end ; then no transfer to FIFO
L W K30D,C ; Task is to transfer 30 bytes from 2nd active DM,

TFI B DX10,FI3 ; starting with D10, into FIFO FI3.
A -log1 ; Lock FIFO instruction to prevent repeat execution

S -nofifo
A -carry ; FIFO overflow?

O -zero ; FIFO underflow?
S -trouble
JPCI nosave
T W C,-rest ; In the case of overflow/underflow, the count of remaining data
nosave: ; that could not be transferred is written to register C.
L W C,C ; Monitor Help

end:
;Delete FIFO:
A -RFI ; Delete locked?
JPCI noreset
RFI FI3 ; Delete FIFO FI3
A B -log1
R B -RFI ; Lock delete sequence to prevent repeat execution of same.
noreset:
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9-4 Sample Programs
9.4 Bit-indirect Writing to Inputs

For simulation purposes, describing inputs via PLC program is helpful in
many situations.
This can be accomplished with the commands:
= I[R] ; Assigning an input
S I[R] ; Latching setting of inputs
R I[R] ; Latching RESET of inputs
To preset a range of inputs in a DM, proceed as follows:
; Presetting of 20 input bytes, starting with I10.0, ; from DM20,

D10.0 and up. CM DB20 ; Activate DM20
L D 160,C ; 20 bytes = 160 bits
L D 80,A ; starting with I10.0 or D20.0
Loop:
A D[A] ; Write data bit
= E[A] ; to input bit. INC A,1 ; Process next I or
D bit
DEC B,1 ; loop counter –1
JPN Loop ; until loop = 0.
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PCL and CL550

Programming and Operation

Programming and Operation

Copyright by Robert Bosch GmbH, Erbach / Germany. All rights

Discretionary charge 12.00 Euro

2. PCL System Features ............................................................................................................................2-1

3. CL550 System Features ........................................................................................................................3-1

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3.3.1.3 Displaying TCP/IP COM functions ............................................................................................. 3-9

4. Peripheral Operation ..............................................................................................................................4-1

5. Programming Basics ..............................................................................................................................5-1

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5.10.1 Module attendance .......................................................................................................................5-20

6. Addressing Conventions ........................................................................................................................6-1

7. Instruction List ........................................................................................................................................7-1

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7.14 STACK Instructions..............................................................................................................................7-15

9. Sample Programs ..................................................................................................................................9-1

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1.1 Standard Operation

This instruction manual presents a comprehensive set of instructions and

The products described hereunder

⇒ This is a Class A device. In a residential area, this device may cause

Proper transport, handling and storage, placement and installation of the

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1.2 Qualified Personnel

This instruction manual is designed for specially trained personnel. The

Weiterbildung in der Automatisierungstechnik

This instruction manual is specifically designed for professional personnel

Interventions in the hardware and software of our products not described

Unqualified interventions in the hardware or software or non-compliance

Installation and maintenance of the products described hereunder is the

Trained electricians are persons of whom the following is true:

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1.3 Safety Markings on Components

DANGER! High voltage!

DANGER! Corrosive battery acid!

CAUTION! Electrostatically sensitive devices (ESD)!

Disconnect mains power before opening!

Lug for connecting PE conductor only!

Functional earthing or low-noise earth only!

Screened conductor only!

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1.4 Safety Instructions in this Manual

DANGEROUS ELECTRICAL VOLTAGE

⇒ This symbol is used to alert the user to an item of special interest.

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1.5 Safety Instructions for the Described Product

The consequences may be severe personal injury or damage to

DANGEROUS ELECTRICAL VOLTAGE

If measuring or testing procedures must be carried out on the

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Observe the following protective measures for electrostatically sensitive

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1.6 Documentation, Software Release & Trademarks

Manuals Language Order no.

PCL, Introduction to the Software PLC, English 1070 072 431

CL550 Configuration and English 1070 072 262

CL550 Controller Manual English 1070 072 263