BASIC ELECTRONICS

 Conductivity lies between conductor and insulator.

 Forbidden energy gap 0.2-2.5eV.
 At 0K a pure semiconductor behaves as an insulator.
 Semiconductor materials show a reduction in resistance with increase in
temperature. So said to have a negative temperature coefficient.
Intrinsic Se micond uctor:
 Semiconductor refined to reduce the number of impurities to a very low
level. e.g : Semiconductor in pure form
 Group-IV elements. Si, Ge,
Extrinsic Se miconductor:
 To increase the conductivity, impurities also called dopant (Group III or V) are
added to the pure semiconductor material and is called extrinsic Semiconductor
(n-type or p-type). The process is called doping.
 N-type Semiconductor- Pentavalent (As,Sb,P) atom is added to pure
semiconductor. Diffused impurities with five valence electrons are called donor
atoms.
 P-type Semiconductor- Trivalent (Al,B,Ga) atom is added to pure
semiconductor. Diffused impurities with three valence electrons are called
acceptor atoms.
 Holes are the majority carrier in p-type semiconductor and electrons are
minority carrier. In n-type semiconductor electrons are the majority carrier and
holes are the minority carrier.

Diode:

 Solid state device created by joining the p-type and n-type material is called as
semiconductor diode.

N o B ia s ( V = 0 )

 Absence of external voltage across the p-n junction is called the unbiased diode.
Because of the density gradient electrons and holes diffuse and they combine
leaving the ions unneutralised and are called uncovered charges.
 The uncovered charges generate an electric field directed from n-side to p-side
called as barrier field which opposes the diffusion process further.
 Since the vicinity of the junction is depleted of mobile charges. Hence called a
as depletion region.
Reverse Bias (V D<0V)

 Positive polarity of the external bias V D is connected to n-type and

negative terminal is connected to p-type.
 The number of uncovered positive and negative ions will increase in
the depletion region causing widening the depletion region which
creates a
great barrier for the majority carrier to overcome, effectively reducing
the majority carrier flow to zero and hence the current due to
majority carrier Imajority=0
 The minority carriers which travels down the potential barrier remain
unaffected and give a small current called the reverse saturation
current
denoted as Is.

Forward Bias (V D>0V)

 Positive polarity of the external bias V D is connected to p-type and

negative terminal is connected to n-type.
 External bias V D exerts a force on the mobile carriers to move them towards
the junction. At the boundary they recombine with the ions and reduce the
width of the depletion region.
 The depletion region will continue to decrease in width as the voltage is
increased further and a heavy flood of electrons will move from n-side to p-side
giving the Imajority an exponential rise from p-side to n-side,
 The minority carrier flow will not be affected by this because the conduction
level is determined by the limited number of impurities in the material and the
current is
 denoted by Is.
The total current is given by

ID =I For ward+IReverse
=Imajority - Iminority (Direction opposite)

In terms of reverse saturation current, ID can be written as

eV
ID =Isexp( )-Is is called the Shockley’s equation.
KT
Where
e- Charge of an electron
K-Blotzman’s Conatant
T-Temperature in Kelvin
η- Quality factor depends upon the diode material (η=2 for Si and 1 for
Ge) V- Supplied voltage across the junction

B rea kdow n C onditio n:

(a) Zener Brea kdow n
 Too much of reverse bias across a p-n junction exert a strong
force on a bound electron to tear it out from the covalent
bond.
Thus a large number of electron and hole pair will be generated
through a direct rupture of the covalent bonds and they
increase
the reverse current and gives sharp increase in the
characteristics. It is called zener breakdown. Diode
employing the unique
portion of the characteristics of a p-n junction is called zener
diode.
 Maximum reverse voltage potential that can be applied before
entering the zener region is called the peak inverse voltage
(PIV)
or peak reverse voltage (PRV).
 (b) A vala nc he Breakdow n:
 With increasing reverse bias voltage, the electric field across
the junction of a diode increases. At a certain value of the
reverse
voltage, the electric field imparts a sufficiently high energy to
a
thermally generated carrier. The carrier on colliding with an ion
on its way disrupts a covalent bond and gives a new hole
electron pair. This process is cumulative and gives an
avalanche of carriers in a very short time. It is called avalanche
multiplication.

Diode eq ui vale nt Circuit:

 Equivalent circuit is a combination of element properly chosen to

best represent the actual terminal characteristics of a device or
system in a particular operating point.

Ideal diode in forward and reverse biased condition is as follows

Diode Resistance levels:
• According to the applied signal the resistance levels in a diode has
following type
1. DC or Static (DC signal)
2. AC or Dynamic(Small AC signal)
3. Average ac( Large AC signal)

S,.. Graphkal
T,-p< Equation Cba:raclc-ristks OclerminaU.on

Vn
DC or static RD=- Defined as a point oolbe lo
In

I
clwactcristics

Yo

f
6 Vd 26mV
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tiDe betwn.limi ts of
operation
TRANSISTOR:

1. Bipolar Junction Transistor (BJT)

2. Field Effect Transistor (FET)

Bipo lar Junct ion Transistor (BJT):

 pnp-- n-type semiconductor is sandwiched between two p-type semiconductor.

 npn-- p-type semiconductor is sandwiched between two n-type semiconductor.
 It has three terminal naming E-Emitter, B-Base and C-Collector.
 Both electron and hole responsible for the current conduction. So called bipolar
junction transistor.
 Doping wise-Emitter>Collector>Base
 Two Junctions- JEB (Junction emitter base) and JCB (Junction collector base).

Transistor Operation:

 JEB is forward biased by the battery VEE by which the depletion region will decrease and
a majority carrier flow will occur from emitter to base giving current Imajority or IE.
 JCB is reverse biased by the battery VCC by which the depletion region will increase and
a minority carrier flow will occur from base to collector giving current Iminority.
 When both the battery supplies are given simultaneously the holes in the base region due
to the battery VEE will act as minority carrier. They will cross the base region to reach
the collector giving the current IC.

So the current equations of BJT can be written as

I E= I C + I B
IC= Imajority+ Iminority
IC =α IE+ ICO
Where α is defined as the fraction of the total emitter current that represents holes which
have travelled from emitter across the base to the collector and ICO is called as
leakage current.
  Depending upon the common terminal between input and output circuit of a
transistor it may be operated in 3 modes of a BJT
(a) Common Base
(b) Common Emitter
(c) Common Collector

Field-Effect Transistors
INTROD UCTIO N

The field-effect transistor (FET) is a three-terminal device used for a variety of applications
that match, to a large extent, those of the BJT transistor. JFET transistor is a voltage-controlled
device. For the FET the current ID will be a function of the voltage VGS applied to the input
circuit. The FET is a unipolar device depending solely on either electron (n- channel) or hole (
p
-channel) conduction.
The term field effect in the name deserves some explanation. We are all familiar
with the ability of a permanent magnet to draw metal filings to itself without the need for
actual contact. The magnetic field of the permanent magnet envelopes the filings and attracts
them to the magnet along the shortest path provided by the magnetic flux lines. For the FET an
electric field is established by the charges present, which controls the conduction path of the
output circuit without the need for direct contact between the controlling and controlled
quantities.

FIG. 1
voltage-controlled amplifiers.

Comparison of some of the general characteristics of BJT with FET:

One of the most important characteristics of the FET is its high input impedance.
The variation in output current is typically a great deal more for BJTs than for FETs for the
same change in the applied voltage.
FETs are more temperature stable than BJTs, and FETs are usually smaller than BJTs, making
them particularly useful in integrated-circuit (IC) chips.
The construction characteristics of some FETs, however, can make them more sensitive
to handling than BJTs.

Type of FET:
Three types of FETs : the junction field-effect transistor (JFET), the metal–oxide–
semiconductor field-effect transistor (MOSFET), and the metal– semiconductor field-effect
transistor (MESFET). The MOSFET category is further broken down into depletion and
enhancement types. The MOSFET transistor has become one of the most important
devices used in the design and construction of integrated circuits for digital computers. Its
thermal stability and other general characteristics make it extremely popular in computer circuit
design.
CONSTRUCTION AND CHARACTERISTICS OF JFETs

JFET is a three-terminal device with one terminal capable of controlling the current between
the other two. The major part of the structure is the n-type material, which forms the channel
between the embedded layers of p-type material. In the absence of any applied potentials the
JFET has two p–n junctions under no-bias conditions. The result is a depletion region at each
junction, as shown in Fig. 2 that resembles the same region of a diode under no-bias conditions.

FIG. 2
Junction field-effect transistor (JFET).

VG = 0 V, VDS Some Positive Value

A positive voltage VDS is applied across the channel and the gate is connected directly to the
source to establish the condition VGS =0 V .Under the conditions the flow of charge is
relatively uninhibited and is limited solely by the resistance of the n-channel between drain
and source. The depletion region is wider near the top of both type materials. The current ID
will establish the voltage levels through the channel as indicated on the figure. The result is
that the upper region of the p-type material will be reverse-biased by about.

As the voltage VDS is increased from 0 V to a few volts, the current will increase as
determined by Ohm’s law and the plot of ID versus VDS. As VDS increases and approaches a
level referred to as VP , the depletion regions will widen, causing a noticeable reduction in the
channel width. The reduced path of conduction causes the resistance to increase. The more
horizontal the curve, the higher the resistance, suggesting that the resistance is approaching
“infinite” ohms in the horizontal region. If VDS is increased to a level where it appears that the
two depletion regions would touch” , a condition referred to as pinch-off will result.
 FIG 3 JFET at VGS = 0 V and VDS 7 0 V FIG 4 ID versus VDS for VGS = 0 V.

As VDS is increased beyond VP, the region of close encounter between the two depletion
regions increases in length long the channel, but the level of ID remains essentially the same. In
essence, therefore, once VDS 7 VP the JFET has the characteristics of a current source. As
shown in Fig.
5, the current is fixed at ID = IDSS, but the voltage VDS (for levels 7 VP) is determined by the
applied load.

The choice of notation IDSS is derived from the fact that it is the drain-to-source current with a
short circuit connection from gate to source.IDSS is the maximum drain current for a JFET and
is defined by the conditions VGS =0 V and
VDS>| VP |.
VGS < 0 V
The voltage from gate to source, denoted VGS, is the controlling voltage of the JFET. Curves of
ID versus VDS for various levels of VGS can be developed for the JFET. For the n-channel
device the controlling voltage VGS is made more and more negative from its VGS= 0 V
level. The effect of the applied negative-bias VGS is to establish depletion regions similar to
those obtained with VGS 0 V, but at lower levels of VDS. Therefore, the result of
applying a negative bias to the gate is to reach the saturation level at a lower level of VDS, as
shown in Fig.
6 for VGS = - 1 V. The resulting saturation level for ID has been reduced and in fact will
continue to decrease as VGS is made more and more negative. Eventually, VGS when VGS = -
VP will be sufficiently negative to establish a saturation level that is essentially 0 mA, and for
all practical purposes the device has been “turned off.” In summary:
The level of VGS that results in ID= 0 mA is defined by VGS =VP, with VP being a negative
voltage for n-channel devices and a positive voltage for p-channel JFETs.

FIG.5
FIG. 6
Application of a negative voltage to the gate of a JFET. n-

Channel JFET characteristics with IDSS = 8 mA and VP = -4

V.
DEPLETION-TYPE
MOSFET
MOSFETs are further broken down into depletion type
and enhancement type. The terms depletion and
enhancement define their basic mode of operation; the name
MOSFET stands for metal–oxide–semiconductor field-effect
transistor

Basic
Construction:
The basic construction of the n-channel depletion-type
MOSFET
is provided in Fig. A slab of p-type material is formed
from a
silicon base and is referred to as the substrate. It is the
foundation
on which the device is constructed. In some cases the
substrate is
internally connected to the source terminal. The gate is
also
connected to a metal contact surface but remains insulated
from
the n-channel by a very thin silicon dioxide (SiO2) layer.
SiO2 is a type of insulator referred to as a dielectric, which
sets up opposing (as indicated by the prefix di-) electric fields
within the dielectric when exposed to an externally applied
field.
Basic Operation:
The gate-to-source voltage is set to 0 V by the direct connection from one terminal to the
other, and a voltage VDD is applied across the drain-to-source terminals. The result is an attraction
of the free electrons of the n-channel for the positive voltage at the drain. The result is a
current similar to that flowing in the channel of the JFET. In fact, the resulting current with VGS
0 V continues to be labeled IDSS.
VGS is set at a negative voltage such as -1 V. The negative potential at the gate will tend to
pressure
electrons toward the p-type substrate (like charges repel) and attract holes from the p-type
substrate
(opposite charges
attract).
Depending on the magnitude of the negative bias established by VGS, a level of
recombination between electrons and holes will occur that will reduce the number of free electrons
in the n-channel available for conduction. The more negative the bias, the higher is the rate of
recombination. The resulting level of drain current is therefore reduced with increasing negative
bias for VGS.

ENHANCEMENT-TYPE MOSFET
The characteristics of the enhancement-type MOSFET are quite different from depletion type
MOSFET.
Basic Construction:
A slab of p-type material is formed from a silicon
base and is again referred to as the substrate. As with
the depletion-type MOSFET, the substrate is
sometimes internally connected to the source terminal,
whereas in other cases a fourth lead (labeled SS) is
made available for external control of its potential
level. The source and drain terminals are again
connected through metallic contacts to n-doped
regions, but note in Fig. the absence of a channel
between the two n-doped regions. This is the primary
difference between the construction of depletion-type
and enhancement-type MOSFETs—the absence of a
channel as a constructed component of the device. In
summary, therefore, the construction of an
enhancement-type MOSFET is quite similar to that of
the depletion-type MOSFET, except for the absence of
a channel between the drain and source terminals.

Basic Operation:
If VGS is set at 0 V and a voltage applied between the drain and
the source of the device of Fig, the absence of an n-channel (with its generous number of free
carriers) will result in a current of effectively 0 A—quite different from the depletion-
type
MOSFET and JFET, where ID = IDSS. It is not sufficient to have a large accumulation of
carriers (electrons) at the drain and the source (due to the n-doped regions) if a path fails to
exist between the two. With VDS some positive voltage, VGS at 0 V, and terminal SS
directly connected to the source, there are in fact two reverse-biased p–n junctions between the
n-doped regions and the p-substrate to oppose any significant flow between drain and source.
The level of VGS that results in the significant increase in drain
current is called the threshold voltage and is given the symbol VT. On specification sheets it
is referred to as VGS(Th), although VT is less unwieldy and will be used in the analysis to
follow. Since the channel is nonexistent with VGS 0 V and “enhanced” by the
application of a positive gate-to-source voltage, this type of MOSFET is called an
enhancement-type MOSFET.
Number System
The decimal number system (Base 10) is a familiar number system. Some other number
systems that are having equal importance are: Binary (Base 2),octal(Base 8), Hexadecimal(Base
16)

All number systems have some common characteristics:

 The digits are consecutive.
 The number of digits is equal to the size of the base.
 Zero is always the first digit.
 The base number is never a digit.
 When 1 is added to the largest digit, a sum of zero and a carry of one results.
 Numeric values determined by the have implicit positional values of the digits.

Binary Numbers

The binary number system is used to model the series of electrical signals computers use to
represent information. It is also called the “Base 2 system”.

Each digit in binary is a 0 or a 1 and is called a bit, which is an abbreviation of binary digit. 0
represents the no voltage or an off state and 1 represents the presence of voltage or an on
state

There are several common conventions for representation of numbers in binary.The most
familiar is unsigned binary. An example of a 8-bit number in this case is
7 6 0
010011112 = 0*2 + 1*2 +_ _ _+ 1*2 = 64 + 8 + 4 + 2 + 1 = 7910

The largest number which can be represented by n bits is 2n − 1. For example, with 4
bits the largest number is 11112 = 15.

The most significant bit (MSB) is the bit representing the highest power of 2, and the
Least significant bit (LSB) represents the lowest power of 2.

Example : Binary: 1110110111

MSB LSB

Table : Binary numbering scale

 Decimal Binary No.
equivalent

0 0000

1 0001

2 0010

3 0011

4 0100

5 0101

6 0110

7 0111

8 1000

9 1001

Decimal to Binary Conversion

The easiest way to convert a decimal number to its binary equivalent is to use the
repeated division of a decimal number by 2 and records the quotient and remainder.

The remainder digits (a sequence of zeros and ones) form the binary equivalent in
least significant to most significant digit sequence

Example: Convert 67 to its binary equivalent:

6710 = x2

Step 1: 67 / 2 = 33 R 1 Divide 67 by 2. Record quotient in next row

Step 2: 33 / 2 = 16 R 1 Again divide by 2; record quotient in next row

Step 3: 16 / 2 = 8 R 0 Repeat again

Step 4: 8 / 2 = 4 R 0 Repeat again Step

5: 4 / 2 = 2 R 0 Repeat again

Step 6: 2 / 2 = 1 R 0 Repeat again

 Step 7: 1 / 2 = 0 R 1 STOP when quotient equals 0

Thus (67)10= (1 0 0 0 0 1 1)2

Similarly we can convert 57 and 211 as given below

53 = 32 + 16 + 4 + 1
= 25 + 24 + 22 + 20
= 1*25 + 1*24 + 0*23 + 1*22 + 0*21 + 1*20
= 110101 in binary
= 00110101 as a full byte in binary

211= 128 + 64 + 16 + 2 + 1
= 27 + 26 + 24 + 21 + 20
= 1*27 + 1*26 + 0*25 + 1*24 + 0*23 + 0*22 +
1*21 + 1*20
= 11010011 in binary

Binary to Decimal Conversion

Multiply the binary digits by increasing powers of two, starting from the right and then find
the decimal number equivalent by summing those products.

Example:

What is 10011010 in decimal?

7 6 5 4 3
10011010 = 1*2 + 0*2 + 0*2 + 1*2 + 1*2 +
2 1 0
0*2 + 1*2 + 0*2
7 4 3 1
=2 +2 +2 +2
= 128 + 16 + 8 + 2
= 154

What is 00101001 in decimal?

7 6 5 4 3
00101001 = 0*2 + 0*2 + 1*2 + 0*2 + 1*2 +
2 1 0
0*2 + 0*2 + 1*2
5 3 0
=2 +2 +2
= 32 + 8 + 1
= 41
Representation of Negative Numbers

There are two commonly used conventions for representing negative numbers. With sign
magnitude, the MSB is used to flag a negative number. So for example with 4-bit numbers we
would have 0011 = 3 and 1011 = −3. This is simple to see, but is not good for doing arithmetic.
With 2's complement, negative numbers are designed so that the sum of a number and its 2's
complement is zero.

Using the 4-bit example , we have 0101 = 5 and its 2's complement −5 = 1011. Adding
(remember to carry) gives 10000 = 0. (The 5th bit doesn't count!)
Both addition and multiplication work as you would expect using 2's complement.
There are two methods for forming the 2's complement:
1. Make the transformation 0 ! 1 and 1!0, then add 1.
2. Add some number to −2MSB to get the number you want. For 4-bit numbers an
example of finding the 2's complement of 5 is −5 = −8 + 3 = 1000 + 0011 = 1011.

• 2’s complement
– Step 1: Find 1’s complement of the number
Binary # 11000110
1’s complement 00111001
– Step 2: Add 1 to the 1’s complement
00111001
+ 00000001
------------------
00111010
Octal Number System

Also known as the Base 8 System. Uses digits 0 – 7.It can be readily converts to binary by
grouping three (binary) digits starting from the radix point. Each octal number converts to 3
binary digits

Example:
1) Convert 42710 to its octal equivalent:

427 / 8 = 53 R3 Divide by 8; R is LSD

53 / 8 = 6 R5 Divide Q by 8; R is next digit
6 / 8 = 0 R6 Repeat until Q = 0
Thus 42710= 6538

2) Convert 6538 to binary

6 5 3
↓ ↓ ↓
110 101 011

Thus 6538= 1101010112

Hexadecimal Representation
It is very often quite useful to represent blocks of 4 bits by a single digit. Thus in base 16 there is
a convention for using one digit for the numbers 0,1,2,: : :,15 which is called hexadecimal. It
follows decimal for 0 to 9, then uses letters A to F for representing 10 to 15 respectively.

CONVERSIONS
 Convert 83010 to its hexadecimal equivalent:
830 / 16 = 51 R14
51 / 16 = 3 R3
3 / 16 = 0 R3
Thus 83010 = 33E( As 14 is represented as E)

Binary to Hexadecimal Conversion

The easiest method for converting binary to hexadecimal is to use a substitution code.Each
hex number converts to 4 binary digits as shown in the table.

Floating Point Numbers

• Real numbers must be normalized using scientific notation:

n
0.1…× 2 where n is an integer

• Note that the whole number part is always 0 and the most significant digit of the
fraction is a 1 – ALWAYS!
 • Standard Format single precision representation uses 32-bit word

• The exponent field (8 bits) can be used to represent integers from 0-255

• Because of the need for negative exponents to be represented as well, the range is
offset or biased from – 128 to + 127

• In this way, both very large and very small numbers can be represented

Logic Gates
A logic gate is a hardware implementing a Boolean function; that is, it performs a logical
operation on one or more logical inputs, and produces a single logical output. Depending on the
context, the term may refer to an ideal logic gate, one that has for instance zero rise time and
unlimited fan-out( the number of gate inputs it can feed or connect to), or it may refer to a non-
ideal physical device
Logic gates are primarily implemented using diodes or transistors acting as electronic witches,
but can also be constructed using vacuum tubes, electromagnetic relays , fluidic
ogic, pneumatic logic, optics, molecules, or even mechanical elements. With amplification, logic
gates can be cascaded in the same way that Boolean functions can be composed, allowing the
construction of a physical model of all of Boolean logic, and therefore, all of the algorithms
and mathematics that can be described with Boolean logic.
• The three basic logical operations are:
• AND
• OR
• NOT
AND gate
The AND gate is an electronic circuit that gives true output i.e output (1) only if all its inputs
are true. A dot (·) is used to show the AND operation i.e. A·B.

OR gate
The OR gate is an electronic circuit that gives a gives a true output true output (1) if one or
more one or more of its inputs are true. A plus (+) is used to show the OR operation.

NOT gate
• The NOT gate is an electronic circuit that produces an inverted version of the input at its
output.
• It is also known as an inverter.
• If the input variable is A, the inverted output is known as NOT A.
• This is also shown as A', or Ā with a bar over the top.

NAND gate
• This is a NOT-AND gate which is equal to an AND followed by a NOT gate.
• The outputs of all NAND gates are true if any of the inputs are false.
• The symbol is an AND gate with a small circle on the output. The small circle represents
inversion.

NOR gate
• This is a NOT-OR gate which is equal to an OR gate followed by a gate followed by a NOT
gate .
• The outputs of all NOR gates are false if any of the inputs are true.
• The symbol is an OR gate with a small circle on the output. The small circle represents
inversion represents inversion.

EXOR gate
• The 'Exclusive-OR' gate is a circuit which will give a true output if either, but not both, of its
two inputs are true.
• An encircled plus sign (⊕) is used to show the EXOR operation.

EXNOR gate
• The 'Exclusive-NOR' gate circuit does the opposite to the EXNOR gate.
• It will give a false output if either, but not both, of its two inputs are true.
• The symbol is an EXOR gate with a small circle on the output small circle on the output .
• The

Boolean Algebra
Invented by George Boole in 1854. It’s a convenient way and systematic way of expressing
and analyzing the operation of logic circuits.

An algebraic structure defined by a set B = {0, 1}, together with two binary operators (+ and
·) and a unary operator.

Terms going to be used-

• Variable – a symbol used to represent a logical quantity.

• Complement – the inverse of a variable and is indicated by a bar over the variable.
• Literal – a variable or the complement of a variable.

Boolean Addition
• Boolean addition is equivalent to the OR operation
• A sum term is produced by an OR operation with no AND ops involved.
• i.e. A  B, A  B , A  B  C , A  B  C  D
• A sum term is equal to 1 when one or more of the literals in the term are 1.
 • A sum term is equal to 0 only if each of the literals is 0.

Boolean Multiplication
• Boolean multiplication is equivalent to the AND operation
• A product term is produced by an A ND operation with no OR ops involved.
• i.e. AB, AB , ABC , A BCD
• A product term is equal to 1 only if each of the literals in the term is 1.
 • A product term is equal to 0 when one or more of the literals are 0.

Laws of Boolean Algebra

The basic laws of Boolean algebra:

• The commutative laws
The commutative law of addition for two variables is written as: A+B
= B+A
The commutative law of multiplication for two variables is written as: AB = BA

• The associative laws

The associative law of addition for 3 variables is written as:
A+(B+C) = (A+B)+C
The associative law of multiplication for 3 variables is written as:
A(BC) = (AB)C
• The distributive laws
The distributive law is written for 3 variables as follows: A(B+C) = AB + AC

Rules of Boolean Algebra

1.A  0  A 7.A  A  A
2.A  1  1 8.A  A  0
3.A  0  0 9.A  A
4.A 1  A 10.A  AB  A
5.A  A  A
11.A  A B  A  B
6.A  A  1 12.( A  B)( A  C )  A  BC

DeMorgan’s Theorems
• DeMorgan’s theorems provide mathematical verification of:
• the equivalency of the NAND and negative-OR gates
• the equivalency of the NOR and negative-AND gates.

• The complement of two or more ANDed variables is equivalent to the OR of the

complements of the individual variables.

XY X Y
• The complement of two or more ORed variables is equivalent to the AND of the
complements of the individual variables.

X Y XY
Constructing a Truth Table for a Logic Circuit
 • Once the Boolean expression for a given logic circuit has been determined, a truth table
that shows the output for all possible values of the input variables can be developed.
• Let’s take the example:
A(B+CD)
4
• There are four variables, hence 16 (2 ) combinations of values are possible.
• To evaluate the expression A(B+CD), first
find the values of the variables that make
the expression equal to 1 (using the rules for INPUT OUTPUT
Boolean add & mult). A B C A(B+CD)
• In this case, the expression equals 1
only if A=1 and B+CD=1 because 0 0 0 0
A(B+CD) = 1·1 = 1 0 0 0 0
• Now, determine when B+CD term equals 1.
• The term B+CD=1 if either B=1 or CD=1 0 0 1 0
or if both B and CD equal 1 because 0 0 1 0
B+CD = 1+0 = 1
B+CD = 0+1 = 1 0 1 0 0
B+CD = 1+1 = 1 0 1 0 0
• The term CD=1 only if C=1 and D=1
• Summary: 0 1 1 0
A(B+CD)=1
0 1 1 0
When A=1 and B=1 regardless of
the values of C and D 1 0 0 0
When A=1 and C=1 and D=1 regardless
1 0 0 0
of the value of B
• The expression A(B+CD)=0 for all other 1 0 1 0
value combinations of the variables.
1 0 1 1
• Putting the results in truth table format
1 1 0 1
1 1 0 1
1 1 1 1
1 1 1 1

Latches & Flip-flops

Digital circuits can be classified as
1. Combinational circuits:
In this case present output of the circuit depends on present inputs only.

2. Sequential circuits:
  Present output not only depends on present inputs but also on the previous state of output.
 It can be realized as combinational circuit with a feedback path along with a memory element.

The most basic memory element can be realized by two inverters forming a static
memory cell. Assume A=0 and B=1, then the below circuit will maintain these values
indefinitely (as long as it has power applied) . The state is defined by the value of the
memory cell

Fig: Static memory cell

S-R Latches :
 Most basic type of latch.
 It is known as set-reset latch as it has two stable output state.
• NOR gates can be used instead of inverters. The SR latch below has two inputs S and R,
which will control the outputs Q and Q’.
• Here Q and Q’ feed back into the circuit. They’re not only outputs, they’re also inputs!
• To figure out how Q and Q’ change, we have to look at not only the inputs S and R, but
also the current values of Q and Q’:
Qnext = (R + Q’current)’
Q’next = (S + Qcurrent)’

Fig : S-R latch using NOR gate

S R Q
 The state S=R=1 is invalid and not allowed
0 0 No change
Fig : Truth table S-R latch using NOR gate 0 1 0 (reset)
1 0 1 (set)
Fig: S’-R’ Latch using cross coupled NAND gate