Modeling Average Current Mode Control

Philip Cooke
cooke @ unitrode.com
Unitrode Integrated Circuits Corporation
7 Continental Boulevard, Merrimack, NH 03054-4334
Phone: (603) 429-8751, FAX: (603) 429-8564

-
Abstract An averaged small signal model is presented which 11. MODEL DEVELOPMENT
predicts some of the previously reported phenomena and offers It has been reported [5] that the following equation for
new insights with analytical expressions useful for design. the duty ratio of peak current mode control takes into
Detailed analysis is given for the buck converter topology with account time varying effects but ignores the sampling effect
the boost and buck-boost results also provided. The modulator
gain, for a first order approximation, is shown to be constant
as in voltage mode control. Guidelines are presented to
optimize the design of the current loop and control-to-output
transfer functions are given which are necessary to compensate
the voltage loop. Experimental data is provided, in the case of
&t)= -Cc (t)- R
ETS
(t)--
D2 ~ s
2
D12 Ts
611( t ) - y G 2 (t)

where ME is the external slope compensation in volts per

(1)
1
the buck converter, to develop and verify the model. second, Ts is the switching period, vc is the output of the
voltage loop error amplifier, RI is the total current sense
I. INTRODUCTION gain, iL is the inductor current, D and D' are the duty and
There is a tradeoff between complexity and ease of use complementary duty ratios respectively (D' = 1-D), and mi
for models employed in the design of average current mode and m2 are the rising and falling slopes (with units of volts
control circuits. It is desirable to have expressions that lend per second) of the sensed current waveform scaled by RI.
insight into dominant system behavior and are practical and Table I lists values for mi and m2 for the three basic
simple enough to design with. This paper will present an converter topologies in continuous conduction mode
average current mode control model for the buck converter (CCM). In this table VG is the input voltage, VO is the
topology in continuous conduction mode. Details for the output voltage and L is the power stage inductance. For the
boost and buck-boost topologies are also included in the buck-boost converter Vo < 0. The modulator gain is
tables. Experimental results from the buck converter are extracted (see [7]) from (1) as
used to develop the model and verify the accuracy of the 1
derived analytical expressions. %=-.
One average current mode control model detailed in [ 1, ETS
21 is an extension of peak current mode control and includes After using the expressions in Table I and (2), conversion of
the sampling effect [3, 41. There are feedforward terms (1) into the frequency domain yields
from the input and output voltages but it contains a non-
linear equation for the modulator gain. It was shown in [5]
that for peak current mode control these feedforward terms
are required to properly model time varying effects.
Furthermore, in [6], a model was proposed questioning the TABLE I
inclusion of the sampling term for average current mode
control. However, the model described in [6] doesn't SENSED INDUCTOR VOLTAGE SLOPES FOR
include the feedforward terms one might expect in average CURRENT MODE CONTROL IN CCM
current mode control since it is similar to peak current mode
Topology ml m2
control. The aim of this work is to extend [6] to include
these feedforward terms thus satisfying the time varying Buck vG -o' R, VO
,RI
effects for average current mode control as was done for
peak current mode control and to use the first order
approximation that the modulator gain is constant. In
addition, approximate expressions for the poles and zeroes
are provided for design purposes.
Buck- VG --vo R I
Boost i R 1 L

0-7803-5864-3/00/$10.00 0 2000 IEEE 256

where GG is the line voltage feedforward term, Go is the TABLE I1
output voltage feedforward term (these are listed in Table I1
for CCM) and the carets indicate small signal variables.
This review of peak current mode control was necessary to
now develop the model for average current mode control.
A typical circuit for average current mode control is D ~ T ~ R 0~- 2 D h p I
shown in Fig. 1. Since the current loop block is a linear Buck
2L 2L
circuit, the frequency domain representation of vcl(t) is

where
From Fig. 1 the voltage loop error amplifier transfer
function, here called the controller, is given by

1 sR,C, +1
G,-(s)=--*
R I s(sR2C1C2+ C l + C 2 )
and the current loop compensation transfer function is (7)
defined as -
- --.%I l+S/WCZI
s 1+S/wf.p1

with o c I = l/(RI(CI+CZ)), oCzl = l/(R&)) and wcpl =

( C I + C ~ ) / ( R ~ C I CEquations
~). 4 and 7 describe the portion
of Fig. 2 below and including the Vcl(s) signal node. Also
with OCLI = WRCLI(CCLI+CCLZ)),
WCLZ = I~RCLZCCLI)
and in this figure the H term is the feedback voltage divider in
OCLP = Here RI is the total
(CCLI+CCL~)/(RC~~CCL~C~~~). the voltage loop, it is calculated from
current sense gain given by RI = AcLRs where kL is the
gain of the current sense amplifier (or current transformer) H=- RB
(8)
and Rs is the current sense resistor. RB+RI
where RB is the dc bias resistor. Note that the current loop
compensator (6) and the voltage loop controller (7) also
appear as blocks in Fig. 2. It is important that the l+GcL(s)
block includes the +1 term. Previous work ignored this and
it turns out that it adds a low frequency zero to the control-
to-output transfer function. The top half of this figure, from
the qcl(s) signal node and above, resembles peak current
mode control and will now be explained.
The best way to understand the modulator and power
stage is to build a working prototype and measure the
transfer function from qcl(s) to qo(s). A UC3886 average
current mode controller was used in the prototype circuit
with the following component values: power stage MI is an
IRF3315S, D, is a 32CTQ030, L = 20pH (with a DCR of RL
= 7.5m52), C = 330pF (with an ESR of Rc = 25m52), R =
Modulator
252; current sense and current loop compensation Rs =
50m52, k L = lOV/V, RCLI= 15k52, RCLZ= 15kQ CCLI=
220pF, CcL2= 5600pF; and controller RB= m, RI = 5.1 lk52,
R2 = 24.3k52, CI = 330pF and C2 = 6800pF. The design
procedure to calculate the current loop compensation
component values is given in a later section. Note that RB
Vd wasn’t necessary since V,f = 2V which is the desired output
Fig. 1: Average Current Mode Control

257
 I 30

20
20

10 -20

0 40
-
g- -10 -60
-
j
C
3 -20 -80 c
-30 -100

-40 -120

-140

-160
10 I00 1000 10000 100000
Current Current IFrequency (biz)

1 +G,,(s) Compensation Gain As was presented in [ l , 21 the proposed non-linear

modulator gain models the non-monotonic variation in the
current loop - loop gain (simply called the current loop
gain) as the duty ratio varies from a minimum to a
maximum. This behavior seems to be a function of how
Voltage Divider much peak-to-peak ripple is on the output of the current
',,, (s)= 0 loop amplifier, vcI(t), relative to the ramp peak-to-peak
Fig 2: Average Current Mode Control Small Signal Model voltage. For low ripple conditions (9) is valid, for higher
ripple conditions (9) is an approximation.
voltage. The switching frequency, fs, was approximately The final step in justifying the average current mode
1OOkHz and VG was adjusted between 3V to 7.5V to vary control diagram in Fig. 2 is to explain the GGand Go blocks.
the duty ratio. Although desired, a lower voltage MOSFET These feedforward blocks are new and expand on the work
with a lower gate charge (less than 95nC) and k,,, (less presented in [6]. Average current mode control may be
than 82mB) was not available at the time the circuit was considered as true state feedback since the average inductor
built. current is sensed. Peak current mode control is an
approximation of this behavior and one would expect that
The ?cI(s) to Q0(s) transfer function was measured with the two small signal control diagrams would have common
an AP Instruments 102B Network Analyzer using the features. One approach is to accept Fig. 2 with GG and Go
analog signal injection method. The signal was injected into as given in peak current mode control (Table 11) and
the voltage loop for three duty ratios, D = 0.31, 0.50 and .. ....
0.75. The results are shown in Fig. 3. Both the current loop 0
and voltage loop were closed for this measurement. This
-20
looks remarkably like the transfer function for the
modulator and power stage of voltage mode control. For 4
such a case, the low frequency gain is FMVdDand in this
figure the solid lines represent the theoretical voltage mode a -
modulator and power stage transfer function which include k?
80;
the resistance of the inductor (RL)and the ESR of the
capacitor (Rc) [8]. Therefore, the modulator gain for -100
l?

average current mode control is the same as voltage mode

control and is approximately constant, given by -120

1
=- (9) -140
VPP
where Vpp, equal to 1.8V in the prototype circuit, is the -160

peak-to-peak voltage of the ramp oscillator shown in Fig. 1. ' 10 100 1000 loo00

I FregueoCY W )
This was proposed in [6], here experimental results 1 Fig 4 Current Loop - Loop Gain and Phase
strengthen the concept. I ..

258
 ..... .. .- .

-20

-40

-P
-60 =
2
-im
f

-120

-140

-160
10 I00 I000 1OOOI 10 1M
Frequency (k)

Fig. 5: Open Loop Line to Output k ( s ) Transfer Function

- _ . . . .
. -.

compare the measured transfer functions and loop gains G OG 6)

with the derived theoretical results. That is the approach
taken here and continued in the next section. -
-
RD2(1-FMR I VoTs /(~L))s(s+ ~ c i 11
p + )
a4s4+a3s3+ a 2 s 2+ a , s + a o
111. EXPERIMENTAL VERIFICATION OF MODEL
(1 1)
Current loop gain was measured by injecting a signal with o E ~ R = l/(RcC). In (11) Ts is the switching period
into the current loop with the voltage loop open. Figure 4 (l/fs) and
shows the current loop gain, measured and theoretical, for D a4= LDRC,
= 0.31, 0.54 and 0.73. The buck current loop gain may be
a3= LDRCwcLp + LD,
derived using the techniques from [7], yielding
a2 = LDocLp + DR + FMRIV&Ts(1-2D)/(2L)
+ FMRIVORCQLPOCLI/~CIA
al = DRocLp + FMRIVoRTs( 1-2D)ocLp/(2L)
+ FMRIVoRCWcLPOcLi + FMRIVOWCLPOCLI/WCLZ
and
% = FMRIVOWCLflCLI.
This is the expression for the current loop gain ignoring RL
This transfer function has four poles and three zeroes, one
and &, however the theoretical results (solid lines) in Fig. 4
zero at the origin, a second is the current loop compensator
include these parasitic effects. It isn’t difficult to include
pole and the third is the ESR zero. Equation 11 was derived
these terms while deriving the expressions, although some
neglecting the RL and Rc series resistive terms of the
get too lengthy to present here. The biggest difference
inductor and capacitor. After which the 1+S/%SR factor was
occurs at the resonant frequency (about 2kHz in this case)
where (10) would show a higher Q and a commensurate added since it appears in the transfer functions when RL and
change in phase at this frequency than what the solid lines in Rc are not neglected. However, when these parasitic
Fig. 4 depict. The results presented in Fig. 4 are parameters (RL and Rc) are included the expressions for the
denominator “a” terms get unwieldy and for a well designed
encouraging and verifies, in part, the accuracy of the
converter (1 1) is a good approximation.
proposed model.
The next step is to measure the line-to-output GOG(s) The last transfer function to be measured is the control-
transfer function (also called audio susceptibility) with the to-output transfer function, Goc(s), and is plotted in Fig. 6
voltage loop open. To do this a bipolar operational power along with the theoretical result
supply was used to provide a VG with a superimposed small
amplitude analog signal. The results are shown in Fig. 5 for G , , ( ~ ) =FM V0R@CLPWCLI (l+s/W,R
)N(s) (12)
D = 0.32 and D = 0.75 along with the theoretical results a4s4 + a3s3+ a2s2+ a,s + a,
from the derived equation for the buck converter where
1 1 S2
N(s) = 1 t (13)

259
for the buck converter at three duty ratios, D = 0.31, 0.50 maximum magnitude of the integrator gain, these are
and 0.75. Notice that (12) has the same denominator as calculated at the switching frequency (os= 27cfs) from
(1 1). The N(s) polynomial (13) also appears in the control-
to-output transfer functions of the boost and buck-boost
converters. Now that the model has been verified, a design
procedure is suggested in the next section.

IV. DESIGN GUIDELINES The first constraint is presented in [6], it avoids clipping of
Procedures to design the current loop are given in [l, 6 the current amplifier at low duty ratios or high line, thus
& 91. These are modified slightly and summarized below. avoiding switching instabilities. The second constraint,
given in [9], also avoids switching instability. In (14) the
The current loop compensator is designed using a lag
min(x, y) functional notation means the minimum of x or y
network with a high frequency pole (6). Place the pole
(ocLp) between one-third and one-half of the switching and lVol is the absolute value of Vo to address the buck-
frequency, this will attenuate switching noise. Place the boost case (V, c 0). To simplify the design an
zero (ocLz) below the power stage resonant frequency given approximation for IGc-(s)l at s =jus is R C L ~ R C LHowever,
I.
by wo = (LC)-In, a factor of one half is a good starting this approximation is only exact if the compensator pole is
actually placed beyond the switching frequency. It is more
value. As WCL;S is reduced, the midband gain increases as
does the current loop crossover frequency. accurate to use IGcL(j~s)l.Some iteration may be necessary.
The last step is to solve for RcLl in the current loop The current loop design is now complete.
Closing the voltage loop is accomplished by using the
integrator gain, oCLI. It is desirable to maximize OCLI since
it increases the current loop gain proportionally for all
control-to-output transfer function, given in general form, as
frequencies, but too much gain can cause excessive voltage
ripple at the output of the current loop amplifier. This ripple
may lead to clipping of the signal and possible switching
instability. Therefore, there exists constraints on the
TABLEI11

PARAMETER VALUES FOR AVERAGE

CURRENT MODECONTROL Gm(S) (15) IN CCM (K = ~+OCL&L;S)
Para-
meter Buck Boost Buck-Boost

Koc 1 R
-
R, I D'R
-
2R I
D'R
(1 + D)R,

1
- 2 I l+D
-

260
 transfer functions were also provided which are useful in
computer design verification programs.

APPENDIX
This appendix lists the exact expressions for the current
The dc gain Kw, the zeroes and the approximate poles are loop gain, control-to-output and line-to-output transfer
listed in Table 111. These expressions are for CCM and are functions for the boost and buck-boost converters. As was
useful .for design purposes. For the boost and buck-boost done for the buck equations, block diagram manipulation
designs (and derived variants) in CCM a low frequency and the Maple symbolic computer program were used to
RHP zero exists in the control-to-output gain. Because of derive these expressions. The current loop gain for the
this, the voltage loop - loop gain (voltage loop gain) boost converter is
crossover frequency is limited to about one tenth of the RHP
zero frequency.
The expressions for opl,op2.ooc and Qoc are
approximations. An analysis of the migration of the poles
of Goc(s) as D varies from 0 to 1 for all converter designs
(the boost and buck-boost converter equations are given in The control-to-output transfer function is
the Appendix) show some movement. The boost converter
roots migrate the least amount, the buck-boost complex pole -L
pair changes its imaginary component by a factor slightly F,V,Rw,,poc,, -s+D’ (I+do,,)
RD’
more than 10. For the buck converter, however, both the G,(s)= NW. (17)
b,s4 + b3s’ + b2s2+ b , s + bo
real and imaginary parts of the poles are sensitive and
migrate, even to the point of becoming all real, as D varies The line-to-output transfer function is
from 0 to 1. Therefore, for the buck converter the
approximations given for o p 2 , oocand Qoc are valid for
high D, under these conditions the voltage loop gain has the
smallest phase margin. The expressions in Table I11 for the
boost and buck-boost poles seem to track the actual Goc(s)
pole migration fairly well.
For the component values used in the prototype circuit a
brief description of the buck G,-,c(s) pole migration is now
given. The lowest real pole, wpl, ( = I/(RC)), stays real over
the entire D range but varies slightly. For low D, less than
about 0.3, there is one complex pole pair slightly below
wcLp and a second real root at about ocu. From a D of
about 0.3 to about 0.5 there are four real roots. Above
approximately 0.5 there is one complex pole pair between
the low frequency pole opI, ( = I/(RC)) and the higher
frequency real pole, wp2, which is now approximately WCLP.
Therefore it is wise to use (12, 17, and 20, refer to
Appendix) for computer verification over the desired range
of duty ratio, especially in the case of the buck converter
(12), after the design is complete.

V. CONCLUSIONS The current loop gain for the buck-boost converter is

A small signal model for average current mode control
in continuous conduction mode was derived and compared TI ( s )
to experimental data. It was shown that it is reasonable to - FM R I (sRC(V, - Vo ) + V, - 2VO )GcL ( S )
approximate the modulator gain as a constant. The LRCS’ + (L+ FMR ,V, D’Ts/2)s + D” R + FMR ID’3RTs(V, - V0)/(2L) ’

feedforward terms used in peak current mode control were (19)

also necessary for average current mode control - The control-to-output transfer function is
experimental data compared with theory substantiates this
approach. Approximate expressions for the buck, boost and
buck-boost converters were given which will enable the
engineer to design the control loops. Exact expressions for
the current loop gain, control-to-output and line-to-output

26 1
 VOL s + D’(V, - V,
FM R w c w ~ c L l - ) (1 + doEsR
)
RD’
Gm(s)= N(s) REFERENCES
d,s4 +d,s’+d?s’ +d,s+d,
[ I ] Wei Tang, Fred C. Lee, and Raymond B. Ridley, “Small Signal
(20) Modeling of Average Current-Mode Control”, IEEE Trans. on Power
where Vo c 0 for the buck-boost converter and the line-to- Electronics, Vol. 8, No. 2, April 1993, pp. 1 12-119.
output transfer function is [21 Wei Tang, “Average Current-Mode Control and Charge Control for
PWM Converters”, Ph.D. Dissertation, Virginia Polytechnic Institute and
State University, October 1994.
[3] R.B. Ridley, “A New, Continuous-Time Model for Current-Mode
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[4] Raymond Ridley, “A New Small Signal Model for Current Mode
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University, November 1990.
[SI David J. Perreault and George C. Verghese, “Time-Varying Effects
and Averaging Issues in Models for Current-Mode Control”, IEEE Trans.
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Average Current Control”, IEEE Applied Power Electronics Conference,
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[7] Robert W. Erickson, “Fundamentals of Power Electronics”, Chapman
& Hall, 1997.

[8] F. C. Lee and B. H. Cho, “VPEC Power Electronics Professional

Seminar Course 1 - Control Design”, Virginia Polytechnic Institute and
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[9] Lloyd H. Dixon, “Average Current Mode Control of Switching Power
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262