Msi Ms-9103-00a

A B C D E
MS-9103 VER:0A
X-BUS FOSTER FOSTER
FLASH CPU U125 CPU U126
USB
CPU BUS
4
SP
SIO
LPC J6 J2 J7 J3
0811
J8 J4 J43 J44 4
BUS
i82559 PP 417
MEMORY I/F
CSB5
Thin
CMIC
IMB
FLPY B_IMB A_IMB
IDE
IMB IMB 8 DIMMs

PCI SLOT BUS BUS
33MHz/32b
PCI BUS 0
PCI BUS 3 PCI BUS 4 PCI BUS 1 PCI BUS 2

(P2) (S2) (P1) (S1) SCSI
3
CIOBX2 CIOBX1 7899 3
PCI[X]
100MHz/64b PCI[X] PCI[X] PCI[X]
100MHz/64b 133MHz/64b 100MHz/64b
INDEX BCM5701
PAGE # DESCRIPTION PAGE # DESCRIPTION PAGE # DESCRIPTION
01. BLOCK DIAGRAM ( This Page ) 24. SDRAMCLK BUFFER 47 SWITCHING CAPs 70 VCC25 & VTT GENERATION LOGIC
02. RESET & CLOCKING SCHEME DIAGRAM 25. SDRAM_&_IMB_CLK_DELAY_LOOPS 48 HARDWARE MONITOR 71 SSTL_VREF
2 03. FOSTER_1 26. CIOBX1_PCI(X) 49 SWSB5 PCI & IDE I/F 72 MOUNTING HOLES 2
04. FOSTER_1_PWR 27. CIOBX1_IMB_PWR 50 SWSB5_IMB_GPORTS 73 I2C ADDRESS & PCIIRQ MAP
05. FOSTER_2 28. CIOBX1 STRAPPING OPTIONs 51 PCI SLOT 1 & 2 74 REVISION HISTORY
06. FOSTER_2_PWR 29. CIOBX1_PCIXP1_SLOT 52 ATI RAGE XL #1 75 CLOCKING SCHEME DIAGRAM
07. CPU_GTLREF_SMBUS_ADDR 30. SCSI 7899W 1/2(PCIXS1) 53 ATI RAGE XL #2
08. VID_CONTROL 31. SCSI 7899W 2/2 54 VGA CONNECTOR
09. ITP CONNECTOR 32. SCSI CHANNEL 1 55 i82559 ETHERNET
10. CPU_LEVEL_SHIFT/TERM 33. SCSI CHANNEL 2 56 i82559 Ethernet Conn.
11. CMIC_FOSTER_IF 34. SCSI MISC 57 SIO417/PPORT/FLPY/SPORT IF
12. CMIC_CIOB_IF 35. S1 BUS TERMINATOR 58 SIO/LPC/GPORTS
13. CMIC_MEM_IF 36. CIOBX2_PCIX 59 BIOS ROM & PORT 80h I/F
14. CMIC_PWR 37. CIOBX2_IMB_PWR 60 USB_PORTS & FREE GATES
15. CMIC STRAPPINGs 38. CIOBX2_STRAPPING_OPTION 61 Thin IMD Termination
16. DIMM CONNECTOR 1, 2 39 CIOBX1_CLK_BUFF 62 FRONT PANEL
1 17. DIMM CONNECTOR 3, 4 40 CIOBX2_CLK_BUFF 63 IPMI 1
18. DIMM CONNECTOR 5, 6 41 BCM5701 Signal Pins 64 POWER ON LOGIC

19. DIMM CONNECTOR 7, 8 42 BCM5701 Power Pins 65 RESET LOGIC Micro Star Restricted Secret
20. MEMORY TERMINATIONS - 1 43 BCM5701 Power Gen. 66 POWER CONNECTORS Title
BLOCK DIAGRAM & INDEX
Rev
21. MEMORY TERMINATIONS - 2 44 CIOBX2_PCIXP2_SLOT1 67 VRM-1 Document Number 0A
22. CLK_SYNTHESIZER 45 CIOBX2_PCIXS2_SLOT2&3 68 VRM-2 MICRO-STAR INT'L CO.,LTD. Last Revision Date:
Thursday, August 16, 2001
23. PCICLK BUFFER 46 THIN_IMB_TERMINATION 69 VDD_IMB VOLT-REG_I2C No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 1 of 75
A B C D E
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5 4 3 2 1
PCB BAT_X
D D
{Value}
{Value}
U34_X
{Value}
C C
B B
A A
Title
{Title}
Size Document Number Rev

C {Doc} {RevCode}
Date: Monday, August 20, 2001 Sheet 1 of 1

5 4 3 2 1
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1
PCIRST#
CMIC_LE
P1_PCIRST#
PCIRST1# PCI-X Slot
TTL
CIOBX2 S1_PCIRST#
7407 #1 (P1,S1) SCSI 7899W
P2_PCIRST#
CIOBX2 PCI-X Slot
S2_PCIRST#
#2 (P2,S2)
Gb BCM5701H
PCIRST2# VGA
ATI Rage XL
PCI-X Slot
LAN
Intel 82550
SIO
NS87417
PCI 33 Slots
CSB5
PCIRST3#
IDE
HW
7414 Monitor
A
D D A
DIMM_RST#
I I
......
M M
M 1 to 8 M
RESET SCHEME
RSB5
PS_PWRGD#
PLLRST PCIRST#
RESET FOR RSB POWER
t0
PCIRST# PCI BUS
PSU PWR GOOD t0+100mS
WTX
PLL RST
P1/P2_PCIRST# t0+100mS
POWER PS_PWRGD PS_PWRGD#
PLLRST POWERGOOD t0+120mS
SUPPLY RESETS FOR PCI
CONN. INVERTER PLLRST PCIRST#
PCIRST#
S1/S2_PCIRST# BUSES VRM POWERGOOD
t0+50mS
CMIC CIOB'S
PROCESSOR POWERGOOD t0+120mS
PROC_RESET#
RESET GEN POWERGOOD CPU RESET
PROCESSOR RESET
SRESET# RESETDLY# t0+120mS+1mS
RESET SWITCH Config RESET - 4
PCI RESET
ITP_RESET# BCLK delay w.r.t. t0+120mS+1mS
140mS PERIOD PROC_RESET#
CONFIG RESET
RESET Vth = 4.5V t0+120mS+1mS+4 clocks
AND
CPU_PWRGD
CPU_VRM_PWRGD
AND
Micro Star Restricted Secret

Title Rev
RESET DIAGRAM
Document Number 0A
MICRO-STAR INT'L CO.,LTD. Last Revision Date:

No. 69, Li-De St, Jung-He City,
1
www.vinafix.vn
A B C D E
P1_SM_TS_ADDR[0..1] 7
P1_SM_ADDR[0..2] 7
CPU_SDA 5,69
CPU_SCL 5,69
CPU_SMBALERT# 5
R1231 45.3_1%
45.3_1%
P1_SM_TS_ADDR1
P1_SM_TS_ADDR0
TP15 10 P1_VCCA
P1_SM_ADDR2
P1_SM_ADDR1
P1_SM_ADDR0
VCC_P
10 P1_VCCIOPLL
P1VCC_SENSE VCC3
1
R1232
10 P1_VSSA DP#[0..3] 5,11
P1GND_SENSE
180
180
TP16
P1_SM_WP
P1_TDO 5,9
P1_COMP1
P1_COMP0
4 4
1 P1_TDI 9
P1_ODTEN
R1233
R1234
P1_TCK 9
DP#3
DP#2
DP#1
DP#0
P_TRDY# 5,11
ITP_TRST# 5,9
TMS 5,9
U125A Check Which CPU is
AD29
AC29
AC28
AD28
AD16
AC15
AC18
AE29
AE28
AA28
AB28
AB29
AA29
AE17
AE19
close to ITP
AD4
AD5
AA5
AB4
AA7
AE5
D26
C24
B27
E16
E25
E24
E19
A25
Y29
F24
W6
W7
W8
A3
B5
Y6
PD#[0..63]
5,11 PD#[0..63]
COMP1
COMP0
TMS
VCCIOPLL
SM_VCC1
SM_VCC
SM_TS_A1
SM_TS_A0
SM_EP_A2
SM_EP_A1
SM_EP_A0
SM_DAT
SM_CLK
SKTOCC#
SM_ALERT
ODTEN
VSSSENSE
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
DP3#
DP2#
DP1#
DP0#
TDO
TDI
TRDY#
VSSA
VCCSENSE
VCCA
SMB_WP
TCK
TRST#
DINV#[0..3] 5,11
PD#0 Y26
PD#1 D0# DINV#3
AA27 D1# DBI3# AB9
PD#2 Y24 AE12 DINV#2
PD#3 D2# DBI2# DINV#1
AA25 D3# DBI1# AD22
PD#4 AD27 AC27 DINV#0
VCC_P PD#5 D4# DBI0#
Y23 D5#
PD#6 AA24 D6# P_VID[0..4] 5,8
PD#7 AB26 F3 P_VID0
PD#8 D7# VID0 P_VID1
1K
AB25 D8# VID1 E3

PD#9 AB23 D3 P_VID2
R1236
AA22 D10# VID3 C3

PD#11 AA21 B3 P_VID4
PD#12 D11# VID4
AB20 D12#
PD#13 AB22 F9
P1_ODTEN PD#14 D13# GTLREF3
AB19 D14# GTLREF2 F23
PD#15 AA19 W9
D15# GTLREF1 P1_GTLREF1 7
PD#16
RES_NOPOP
AE26 W23
DON'T STUFF

PD#17 AC26
PD#18 D17# DSTBP#3
R1237
3 AD25 D18# DSTBP3# Y11 3

PD#19 AE25 Y14 DSTBP#2
PD#20 D19# DSTBP2# DSTBP#1
AC24 D20# DSTBP1# Y17 DSTBP#[0..3] 5,11
PD#21 AD24 Y20 DSTBP#0
PD#22 D21# DSTBP0# DSTBN#3
AE23 D22# DSTBN3# Y12
PD#23 AC23 Y15 DSTBN#2
D23# DSTBN2# DSTBN#[0..3] 5,11
PD#24 AA18 Y18 DSTBN#1
PD#25 D24# DSTBN1# DSTBN#0
AC20 D25# DSTBN0# Y21
PD#26 AC21
PD#27 D26# BPM#2
AE22 D27# BPM0# F6 BPM#[2..5] 5,9,10
PD#28 AE20 F8 BPM#3
PD#29 D28# BPM1# BPM#2
AD21 D29# BPM2# E7
VCC3 PD#30 AD19 F5 BPM#3
AB17 D31# BPM4# E8
PD#32 AB16 E4 BPM#5
PD#33 D32# BPM5#
FOSTER
RES_NOPOP
AA16
DON'T STUFF
PD#34 D33#
R1239
AC17 D34# SLP# AE6 SLP# 5,10

PD#35 AE13 D4
D35# STPCLK# CPU_STPCLK# 5,10
PD#36 AD18 C27
D36# SMI# SMI# 5,10
PD#37 AB15 F26
D37# THERMTRIP# P1_THERMTRIP# 8
PD#38 AD13 AB7
D38# PWRGD CPU1_PWRGD 64
P1_SM_WP PD#39 AD14 B25
D39# PR0CH0T# P1_PROCHOT# 8
PD#40 AD11 D6
D40# INIT# INIT# 5,10
PD#41 AC12 G23
D41# LINIT1 LINT1 5,8,10
PD#42 AE10 B24
PD#43 AC11 E27
D43# FERR# FERR# 5,8,10
PD#44 AE9 C26
D44# IGNNE# IGNNE# 5,8,10
PD#45 AD10 F27
D45# A20M# A20M# 5,8,10
2
VCC3 PD#46 AD8 2
PD#47 D46#
AC9 D47# RESET# Y8 PROC_RESET# 5,9,10,12
PD#48 AA13
.01uF PD#49 D48# HREQ#0
AA14 D49# REQ0# B19 HREQ#[0..4] 5,11
PD#50 AC14 B21 HREQ#1
C1405 PD#51 D50# REQ1# HREQ#2
AB12 D51# REQ2# C21
PD#52 AB13 C20 HREQ#3
PD#53 D52# REQ3# HREQ#4
AA11 D53# REQ4# B22
PD#54 AA10
PD#55 D54#
AB10 D55# LOCK# A17 LOCK# 5,10,11
PD#56 AC8 D7
PD#57 D56# MCERR# MCERR# 5,10
AD7 D57#
PD#58 AE7 C6
D58# RSP# RSP# 5,11
PD#59 AC6 F21
D59# RS2# RS#2 5,11
PD#60 AC5 D22
D60# RS1# RS#1 5,11
PD#61 AA8 E21
D61# RS0# RS#0 5,11
PD#62 Y9
PD#63 D62# P1_IERR#
AB6 D63# IERR# E5 P1_IERR# 8
C23 DEFER#
DEFER# DEFER# 5,11
A23 HITM#
HITM# HITM# 5,10,11
AP#0 E10 E22 HIT#
5,11 AP#0 AP0# HIT# HIT# 5,10,11
AP#1 D9 D19 ADS#
5,11 AP#1 AP1# ADS# ADS# 5,11
F17 ADSTB#0
ADSTB0# ADSTB#0 5,11
HCLK1 Y4 F14 ADSTB#1
E18 DRDY#
22 HCLK1 ADSTB#1 5,11

F18 DBSY#
BCLK0 ADSTB1#
F11 BINIT#
BPRI#
HCLK1_N
BNR#
W5
BR0#
BR1#
BR2#
BR3#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
22 HCLK1_N BCLK1
A3#
A4#
A5#
A6#
A7#
A8#
A9#
C18
C17
D17
C15
C14
D16
D15
C12
D13
D12
C11
D20
D10
D23
A22
A20
B18
A19
A13
B16
B14
B13
A12
A10
B10
B11
E14
E13
E11
F15
F12
F20
C9
C8
A9
B8
B7
A6
A7
FOSTER
1 1
BREQ#0
BREQ#1
BREQ#2
BREQ#3
DRDY#
DBSY#
BINIT#
PA#10
PA#11
PA#14
PA#15
PA#16
PA#19
PA#20
PA#21
PA#24
PA#25
PA#26
PA#29
PA#30
PA#31
PA#34
PA#35
PA#12
PA#13
PA#17
PA#18
PA#22
PA#23
PA#27
PA#28
PA#32
PA#33
PA#4
PA#5
PA#6
PA#9
PA#3
PA#7
PA#8
DRDY# 5,11 Micro Star Restricted Secret

DBSY# 5,11
PA#[3..35] Title Rev
5,11 PA#[3..35] BINIT# 5,10,11
FOSTER_1
R1240 39.2_1% Document Number 0A
5,11 BREQ#0
R1241 39.2_1% VCC_P
5 BREQ#1
5 BREQ#2
R1242 39.2_1% MICRO-STAR INT'L CO.,LTD. Last Revision Date:
R1243 39.2_1% Monday, August 20, 2001
5 BREQ#3
5,10,11 BNR# PLACE AT PROC 1 Taipei Hsien, Taiwan Sheet
5,11 BPRI#
A B C D E
www.vinafix.vn
A B C D E
VCC_P U125B VCC_P
33
34
35
36
37
38
39
40
41
U125C VCC_P
A2 A5
A1
A4
21
22
23
24
25
26
27
28
29
30
31
32
EMI_GND1
EMI_GND2
EMI_GND3
EMI_GND4
EMI_GND5
EMI_GND6
EMI_GND7
EMI_GND8
EMI_GND9
VCC VSS C1273 C1274 C1275 C1276 C1743 C1744 C1745 C1746
A8 VCC VSS A11
A14 A21 J7 A30
MTG_GND21
MTG_GND22
MTG_GND23
MTG_GND24
MTG_GND25
MTG_GND26
MTG_GND27
MTG_GND28
MTG_GND29
MTG_GND30
MTG_GND31
MTG_GND32
RSVD1
RSVD2
VCC VSS VSS GAL_VDD1 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
A18 VCC VSS A27 J9 VSS GAL_VDD2 B4
A24 VCC VSS A29 J23 VSS GAL_VDD3 B31
A28 VCC VSS B2 J25 VSS GAL_VDD4 C30
B6 VCC VSS B9 J27 VSS GAL_VDD5 D1
B20 VCC VSS B17 K2 VSS GAL_VDD7 E30
4 B26 B23 K4 F1 4
VCC VSS VSS GAL_VDD8
B29 VCC VSS B28 K6 VSS GAL_VDD9 F31
C2 VCC VSS C7 K8 VSS GAL_VDD10 G30
C4 VCC VSS C13 K24 VSS GAL_VDD11 H1 CPU1 CORE VCC_P
C10 VCC VSS C19 K26 VSS GAL_VDD12 H31 DECOUPLING
C16 VCC VSS C25 K28 VSS GAL_VDD13 J30
C22 VCC VSS C29 L3 VSS GAL_VDD14 K1
C28 VCC VSS D2 L5 VSS GAL_VDD15 K31
1
D8 VCC VSS D5 L7 VSS GAL_VDD16 L30
D14 D11 L9 M1 + C1227 + C1228 + C1229 + C1230 + C1231 + C1232 + C1233 + C1234 + C1235 + C1236
D18 VCC VSS D21 L23 VSS GAL_VDD18 M31
D24 D27 L25 N1 560uF/4V 560uF/4V 560uF/4V 560uF/4V 560uF/4V 560uF/4V 560uF/4V 560uF/4V 560uF/4V 560uF/4V
D29 D28 L27 N31
2
E2 VCC VSS E9 L29 VSS GAL_VDD21 P30
E6 VCC VSS E15 M2 VSS GAL_VDD22 R1
E20 VCC VSS E23 M6 VSS GAL_VDD24 T30
E26 VCC VSS E29 M8 VSS GAL_VDD25 U1
E28 VCC VSS F2 M24 VSS GAL_VDD26 U31
F4 VCC VSS F7 M26 VSS GAL_VDD27 V30
F10 VCC VSS F13 M28 VSS GAL_VDD28 W1 CPU1 CORE VCC_P
F16 VCC VSS F19 N2 VSS GAL_VDD29 W31 DECOUPLING
F22 VCC VSS F25 N4 VSS GAL_VDD30 Y30
F29 VCC VSS F28 N6 VSS GAL_VDD31 AA1
G2 VCC VSS G3 N8 VSS GAL_VDD32 AA31
G4 G5 N24 AB30 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V
G6 VCC VSS G7 N26 VSS GAL_VDD34 AC31
G8 G9 N28 AD30 C1237 C1238 C1239 C1240 C1241 C1242 C1243
3 G24 VCC VSS G25 P3 VSS
3
G26 VCC VSS G27 P5 VSS GAL_VSS1 A31
G28 VCC VSS G29 P7 VSS GAL_VSS2 B30
H3 H2 P9 C1 VCC_P
VCC VSS VSS GAL_VSS3
H5 VCC VSS H4 P23 VSS GAL_VSS4 C31
H7 VCC VSS H6 P25 VSS GAL_VSS5 D30
H9 VCC VSS H8 P27 VSS GAL_VSS6 E1
H25 H26 R2 F30 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V
H27 VCC VSS H28 R4 VSS GAL_VSS9 G1
H29 J3 R6 G31 C1244 C1245 C1246 C1247 C1248 C1249 C1250
J2 VCC VSS J5 R8 VSS GAL_VSS11 H30
J4 VCC VCC W29 R24 VSS GAL_VSS12 J1
FOSTER_PWR
J6
J8
VCC FOSTER_PWR VCC Y2
Y10
R26
R28
VSS GAL_VSS13 J31
K30 VCC_P
VCC VCC VSS GAL_VSS14
J24 VCC VCC Y16 T3 VSS GAL_VSS15 L1
J26 VCC VCC Y22 T5 VSS GAL_VSS16 L31
J28 VCC VCC AA4 T7 VSS GAL_VSS17 M30
K3 VCC VCC AA6 T9 VSS GAL_VSS18 N30
K5 AA12 T23 P1 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V
K7 VCC VCC AA20 T25 VSS GAL_VSS20 P31
K9 AA26 T27 R30 C1251 C1252 C1253 C1254 C1255 C1256 C1257
K23 VCC VCC AB2 T29 VSS GAL_VSS22 T1
K25 VCC VCC AB8 U2 VSS GAL_VSS23 T31
K27 VCC VCC AB14 U4 VSS GAL_VSS24 U30
K29 AB18 U6 V1 VCC_P
L2 VCC VCC AB24 U8 VSS GAL_VSS26 V31
L4 VCC VCC AC3 U24 VSS GAL_VSS27 W30
2 L6 VCC VCC AC4 U26 VSS GAL_VSS28 Y1 2
L8 VCC VCC AC10 U28 VSS GAL_VSS29 Y31
L24 AC16 V3 AA30 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V
L26 VCC VCC AC22 V5 VSS GAL_VSS31 AB1
L28 AD2 V7 AB31 C1258 C1259 C1260 C1261 C1262 C1263 C1264
M3 VCC VCC AD6 V9 VSS GAL_VSS33 AC30
M5 VCC VCC AD12 V23 VSS GAL_VSS34 AD31
M7 VCC VCC AD20 V25 VSS
M9 AD26 V27 A15 VCC_P
VCC VCC VSS RSVD3 PLACE AROUND P1 SOCKET
M23 VCC VCC AE3 V29 VSS RSVD4 A16
M25 VCC VCC AE8 W2 VSS RSVD5 A26
M27 VCC VCC AE14 W4 VSS RSVD8 B1
M29 VCC VCC AE18 W24 VSS RSVD13 C5
N3 AE24 W26 D25 C1265 C1266 C1267 C1268 C1269 C1270 C1271 C1272
VCC VCC VSS RSVD17
N5 VCC VCC R29 W28 VSS RSVD63 W3
1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V
R1230
N7 VCC VCC T2 Y5 VSS RSVD67 Y3
N25 VCC VCC T8 Y19 VSS RSVD73 AA3
RES_NOPOP
N27 T24 Y25 AB3

DON'T
STUFF
VCC VCC VSS RSVD77

N29 VCC VCC T26 AA2 VSS RSVD80 AC1
P2 VCC VCC T28 AA9 VSS RSVD83 AD1
P4 VCC VCC U3 AA15 VSS RSVD86 AE4
P24 VCC VCC U9 AB5 VSS VSS AE27
R3 VCC VCC U27 AB27 VSS VSS AE2
1 1
R5 VCC VCC U29 AC2 VSS VSS AD23
MTG_GND10
MTG_GND11
MTG_GND12
MTG_GND13
MTG_GND14
MTG_GND15
MTG_GND16
MTG_GND17
MTG_GND18
MTG_GND19
MTG_GND20
R7 V2 VCC_P AC7 AD17

MTG_GND1
MTG_GND2
MTG_GND3
MTG_GND4
MTG_GND5
MTG_GND6
MTG_GND7
MTG_GND8
MTG_GND9
VCC VCC VSS VSS

R9 VCC VCC V4 AC13 VSS VSS AD15
R23 V6 AC19 AD9 Micro Star Restricted Secret
EMI_GND10
EMI_GND11
EMI_GND12
EMI_GND13
EMI_GND14
EMI_GND15
EMI_GND16
VCC VCC VSS VSS

R27 V24 Title Rev
VCC VCC FOSTER_1_PWR
W27 VCC VCC V26
W25 V28 Document Number 0A
VCC VCC
10
11
12
13
14
15
16
17
18
19
20
FOSTER
1
2
3
4
5
6
7
8
9

42
43
44
45
46
47
48
FOSTER Monday, August 20, 2001

A B C D E
www.vinafix.vn
A B C D E
P2_SM_TS_ADDR[0..1] 7
P2_SM_ADDR[0..2] 7
CPU_SDA 3,69
CPU_SCL 3,69
TP17 10 P2_VCCA CPU_SMBALERT# 3
P2_SM_TS_ADDR0
P2_SM_TS_ADDR1
10 P2_VCCIOPLL
P2VCC_SENSE VCC3 VCC_P
P2_SM_ADDR2
P2_SM_ADDR0
P2_SM_ADDR1
45.3_1%
45.3_1%
1
10 P2_VSSA
P2GND_SENSE
TP18 DP#[0..3] 3,11
180
180
R1223
R1224
4 1 P2_ODTEN 4
P2_SM_WP
P2_TDO 9
P1_TDO 3,9
E16 P2_COMP1
AD16 P2_COMP0
P2_TCK 9
DP#3
DP#2
DP#1
DP#0
R1225
R1226
P_TRDY# 3,11
ITP_TRST# 3,9
TMS 3,9
U126A Check Which CPU is
AD29
AC29
AC28
AD28
AC15
AC18
AE29
AE28
AA28
AB28
AB29
AA29
AE17
AE19
close to ITP
AD4
AD5
AA5
AB4
AA7
AE5
D26
C24
B27
E25
E24
E19
A25
Y29
F24
W6
W7
W8
A3
B5
Y6
PD#[0..63]
3,11 PD#[0..63]
COMP1
COMP0
VCCIOPLL
SM_VCC1
SM_VCC
SM_TS_A1
SM_TS_A0
SM_EP_A2
SM_EP_A1
SM_EP_A0
SM_DAT
SM_CLK
TMS
SM_ALERT
SKTOCC#
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TRDY#
ODTEN
DP3#
DP2#
DP1#
DP0#
TDI
VSSSENSE
TDO
VSSA
VCCSENSE
VCCA
SMB_WP
TCK
TRST#
DINV#[0..3] 3,11
PD#0 Y26
PD#1 D0# DINV#3
AA27 D1# DBI3# AB9
PD#2 Y24 AE12 DINV#2
PD#3 D2# DBI2# DINV#1
AA25 D3# DBI1# AD22
VCC_P PD#4 AD27 AC27 DINV#0
PD#5 D4# DBI0#
Y23 D5#
PD#6 AA24 D6# P_VID[0..4] 3,8
PD#7 P_VID0
R1227 RES_NOPOP
AB26 F3
DON'T STUFF

AB25 D8# VID1 E3
PD#9 AB23 D3 P_VID2
AA22 D10# VID3 C3
PD#11 AA21 B3 P_VID4
PD#12 D11# VID4
AB20 D12#
P2_ODTEN PD#13 AB22 F9
PD#14 D13# GTLREF3
AB19 D14# GTLREF2 F23
PD#15 AA19 W9
PD#16 AE26 W23
PD#17
1K
3 AC26 D17#
3
PD#19 D18# DSTBP3# DSTBP#2
AE25 D19# DSTBP2# Y14
PD#20 DSTBP#1
R1228
AC24 D20# DSTBP1# Y17 DSTBP#[0..3] 3,11

PD#22 D21# DSTBP0# DSTBN#3
AE23 D22# DSTBN3# Y12
PD#23 AC23 Y15 DSTBN#2
D23# DSTBN2# DSTBN#[0..3] 3,11
PD#24 AA18 Y18 DSTBN#1
PD#25 D24# DSTBN1# DSTBN#0
AC20 D25# DSTBN0# Y21
PD#26 AC21
PD#27 D26# BPM#2
AE22 D27# BPM0# F6 BPM#[2..5] 3,9,10
PD#28 AE20 F8 BPM#3
VCC3 PD#29 D28# BPM1# BPM#2
AD21 D29# BPM2# E7
PD#30 AD19 F5 BPM#3
AB17 D31# BPM4# E8
PD#32 BPM#5
RES_NOPOP
AB16 D32# BPM5# E4

DON'T STUFF
PD#33
FOSTER
R1229
AA16 D33#
PD#34 AC17 AE6
D34# SLP# SLP# 3,10
PD#35 AE13 D4
D35# STPCLK# CPU_STPCLK# 3,10
PD#36 AD18 C27
D36# SMI# SMI# 3,10
PD#37 AB15 F26
D37# THERMTRIP# P2_THERMTRIP# 8
P2_SM_WP PD#38 AD13 AB7
D38# PWRGD CPU2_PWRGD 64
PD#39 AD14 B25
D39# PR0CH0T# P2_PROCHOT# 8
PD#40 AD11 D6
D40# INIT# INIT# 3,10
PD#41 AC12 G23
PD#42 AE10 B24
PD#43 AC11 E27
D43# FERR# FERR# 3,8,10
PD#44 AE9 C26
D44# IGNNE# IGNNE# 3,8,10
PD#45 AD10 F27
2 D45# A20M# A20M# 3,8,10 2
PD#46 AD8
VCC3 PD#47 D46#
AC9 D47# RESET# Y8 PROC_RESET# 3,9,10,12
PD#48 AA13
PD#49 D48# HREQ#0
AA14 D49# REQ0# B19 HREQ#[0..4] 3,11
.01uF PD#50 AC14 B21 HREQ#1
AB12 D51# REQ2# C21
C1404 PD#52 AB13 C20 HREQ#3
AA11 D53# REQ4# B22
PD#54 AA10
PD#55 D54#
AB10 D55# LOCK# A17 LOCK# 3,10,11
PD#56 AC8 D7
PD#57 D56# MCERR# MCERR# 3,10
AD7 D57#
PD#58 AE7 C6
D58# RSP# RSP# 3,11
PD#59 AC6 F21
D59# RS2# RS#2 3,11
PD#60 AC5 D22
D60# RS1# RS#1 3,11
PD#61 AA8 E21
D61# RS0# RS#0 3,11
PD#62 Y9
PD#63 D62# P2_IERR#
AB6 D63# IERR# E5 P2_IERR# 8
C23 DEFER#
DEFER# DEFER# 3,11
A23 HITM#
HITM# HITM# 3,10,11
AP#0 E10 E22 HIT#
3,11 AP#0 AP0# HIT# HIT# 3,10,11
AP#1 D9 D19 ADS#
3,11 AP#1 AP1# ADS# ADS# 3,11
F17 ADSTB#0
ADSTB0# ADSTB#0 3,11
HCLK2 Y4 F14 ADSTB#1
DRDY# E18 DRDY#
22 HCLK2 ADSTB#1 3,11

DBSY# F18 DBSY#
BCLK0 ADSTB1#
F11 BINIT#
BPRI#
HCLK2_N
BNR#
W5
BR0#
BR1#
BR2#
BR3#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
22 HCLK2_N BCLK1
A3#
A4#
A5#
A6#
A7#
A8#
A9#
C18
C17
D17
C15
C14
D16
D15
C12
D13
D12
C11
D20
D10
D23
A22
A20
B18
A19
A13
B16
B14
B13
A12
A10
B10
B11
E14
E13
E11
F15
F12
F20
C9
C8
A9
B8
B7
A6
A7
1 FOSTER 1
BREQ#1
BREQ#0
BREQ#2
BREQ#3
BINIT#
BPRI#
VCC_P
BNR#
PA#10
PA#13
PA#14
PA#15
PA#18
PA#19
PA#20
PA#23
PA#24
PA#25
PA#28
PA#29
PA#30
PA#33
PA#34
PA#35
PA#11
PA#12
PA#16
PA#17
PA#21
PA#22
PA#26
PA#27
PA#31
PA#32
PA#3
PA#4
PA#5
PA#8
PA#9
PA#6
PA#7
Place these close to CPU2 Micro Star Restricted Secret

Title Rev
PA#[3..35] R1296 40.2_1% FOSTER_2
3,11 PA#[3..35]
R1297 40.2_1% Document Number 0A
3 BREQ#1
3,11 BREQ#0
3 BREQ#2 DRDY# 3,11 MICRO-STAR INT'L CO.,LTD. Last Revision Date:
Monday, August 20, 2001
3 BREQ#3 DBSY# 3,11
3,10,11 BNR# BINIT# 3,10,11
3,11 BPRI#
A B C D E
www.vinafix.vn
A B C D E
VCC_P U126B VCC_P
33
34
35
36
37
38
39
40
41
A2 A5
EMI_GND1
EMI_GND2
EMI_GND3
EMI_GND4
EMI_GND5
EMI_GND6
EMI_GND7
EMI_GND8
EMI_GND9
VCC VSS U126C VCC_P C1219 C1220 C1221 C1222 C1739 C1740 C1741 C1742
A8 VCC VSS A11
A14 A21
A1
A4
21
22
23
24
25
26
27
28
29
30
31
32
VCC VSS 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
A18 VCC VSS A27
A24 A29 J7 A30
MTG_GND21
MTG_GND22
MTG_GND23
MTG_GND24
MTG_GND25
MTG_GND26
MTG_GND27
MTG_GND28
MTG_GND29
MTG_GND30
MTG_GND31
MTG_GND32
RSVD1
RSVD2
A28 VCC VSS B2 J9 VSS GAL_VDD2 B4
B6 VCC VSS B9 J23 VSS GAL_VDD3 B31
B12 VCC VSS B15 J25 VSS GAL_VDD4 C30
4 B26 B23 J29 D31 4
B29 VCC VSS B28 K2 VSS GAL_VDD7 E30
C2 VCC VSS C7 K4 VSS GAL_VDD8 F1
C4 VCC VSS C13 K6 VSS GAL_VDD9 F31
C10 VCC VSS C19 K8 VSS GAL_VDD10 G30 CPU2 CORE VCC_P
C16 VCC VSS C25 K24 VSS GAL_VDD11 H1 DECOUPLING
C22 VCC VSS C29 K26 VSS GAL_VDD12 H31
C28 VCC VSS D2 K28 VSS GAL_VDD13 J30
D8 VCC VSS D5 L3 VSS GAL_VDD14 K1
1
D14 VCC VSS D11 L5 VSS GAL_VDD15 K31
D18 D21 L7 L30 + C1173 + C1174 + C1175 + C1176 + C1177 + C1178 + C1179 + C1180 + C1181 + C1182
D24 VCC VSS D27 L9 VSS GAL_VDD17 M1
D29 D28 L23 M31 560uF/4V 560uF/4V 560uF/4V 560uF/4V 560uF/4V 560uF/4V 560uF/4V 560uF/4V 560uF/4V 560uF/4V
E2 E9 L25 N1
2
E6 VCC VSS E15 L27 VSS GAL_VDD20 N31
E12 VCC VSS E17 L29 VSS GAL_VDD21 P30 CPU2 CORE
E20 VCC VSS E23 M2 VSS GAL_VDD22 R1 DECOUPLING
E28 F2 M6 T30 VCC_P
F4 VCC VSS F7 M8 VSS GAL_VDD25 U1
F10 VCC VSS F13 M24 VSS GAL_VDD26 U31
F16 VCC VSS F19 M26 VSS GAL_VDD27 V30
F22 F25 M28 W1 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V
F29 VCC VSS F28 N2 VSS GAL_VDD29 W31
G2 G3 N4 Y30 C1183 C1184 C1185 C1186 C1187 C1188 C1189
G8 VCC VSS G9 N24 VSS GAL_VDD33 AB30
3 G24 VCC VSS G25 N26 VSS GAL_VDD34 AC31 3
G26 G27 N28 AD30 VCC_P
G28 VCC VSS G29 P3 VSS
H3 VCC VSS H2 P5 VSS GAL_VSS1 A31
H5 VCC VSS H4 P7 VSS GAL_VSS2 B30
H7 H6 P9 C1 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V
H9 VCC VSS H8 P23 VSS GAL_VSS4 C31
H23 H24 P25 D30 C1190 C1191 C1192 C1193 C1194 C1195 C1196
H29 VCC VSS J3 R2 VSS GAL_VSS8 F30
J2 VCC VSS J5 R4 VSS GAL_VSS9 G1
J4 W29 R6 G31 VCC_P
J6
J8
VCC FOSTER_PWR VCC Y2
Y10
R8
R24
VSS GAL_VSS11 H30
J1
FOSTER_PWR
J24 VCC VCC Y16 R26 VSS GAL_VSS13 J31
J26 Y22 R28 K30 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V
J28 VCC VCC AA4 T3 VSS GAL_VSS15 L1
K3 AA6 T5 L31 C1197 C1198 C1199 C1200 C1201 C1202 C1203
K5 VCC VCC AA12 T7 VSS GAL_VSS17 M30
K7 VCC VCC AA20 T9 VSS GAL_VSS18 N30
K9 VCC VCC AA26 T23 VSS GAL_VSS19 P1
K23 VCC VCC AB2 T25 VSS GAL_VSS20 P31
K25 AB8 T27 R30 VCC_P
K27 VCC VCC AB14 T29 VSS GAL_VSS22 T1
K29 VCC VCC AB18 U2 VSS GAL_VSS23 T31
L2 VCC VCC AB24 U4 VSS GAL_VSS24 U30
L4 AC3 U6 V1 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V 22uF/10V
2 L6 VCC VCC AC4 U8 VSS GAL_VSS26 V31 2
L8 AC10 U24 W30 C1204 C1205 C1206 C1207 C1208 C1209 C1210
L28 AD2 V3 AA30 PLACE AROUND P2 SOCKET
M3 VCC VCC AD6 V5 VSS GAL_VSS31 AB1
M5 VCC VCC AD12 V7 VSS GAL_VSS32 AB31
M7 VCC VCC AD20 V9 VSS GAL_VSS33 AC30
M9 AD26 V23 AD31 VCC_P
M23 VCC VCC AE3 V25 VSS
M29 AE18 W2 A26 C1211 C1212 C1213 C1214 C1215 C1216 C1217 C1218
VCC VCC VSS RSVD5
N3 VCC VCC AE24 W4 VSS RSVD8 B1
N5 R29 W24 C5 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V
VCC VCC VSS RSVD13
N7 VCC VCC T2 W26 VSS RSVD17 D25
N9 VCC VCC T4 W28 VSS RSVD63 W3
R1222 RES_NOPOP

DON'T STUFF
N29 VCC VCC T26 Y19 VSS RSVD73 AA3

P2 VCC VCC T28 Y25 VSS RSVD77 AB3
P4 VCC VCC U3 AA2 VSS RSVD80 AC1
P6 VCC VCC U5 AA9 VSS RSVD83 AD1
1 1
R7 VCC VCC V2 AB27 VSS VSS AE2
MTG_GND10
MTG_GND11
MTG_GND12
MTG_GND13
MTG_GND14
MTG_GND15
MTG_GND16
MTG_GND17
MTG_GND18
MTG_GND19
MTG_GND20
R23 V6 AC7 AD17

EMI_GND10
EMI_GND11
EMI_GND12
EMI_GND13
EMI_GND14
EMI_GND15
EMI_GND16
MTG_GND1
MTG_GND2
MTG_GND3
MTG_GND4
MTG_GND5
MTG_GND6
MTG_GND7
MTG_GND8
MTG_GND9
VCC VCC VSS VSS

R27 V24 VCC_P AC19 AD9 Title Rev
VCC VCC VSS VSS FOSTER_2_PWR
W27 VCC VCC V26 AC25 VSS VSS AD3
W25 V28 Document Number 0A
VCC VCC
42
43
44
45
46
47
48
10
11
12
13
14
15
16
17
18
19
20
FOSTER FOSTER Monday, August 20, 2001

1
2
3
4
5
6
7
8
9

A B C D E
www.vinafix.vn
A B C D E
Z = R/W bit VCC3

VCC3
Z = R/W bit
DON'T STUFF DON'T STUFF
RES_NOPOP
RES_NOPOP
RES_NOPOP
RES_NOPOP
RES_NOPOP
R1194
R1195
R1196
CPU_0 Thermal Sensor SM Bus
R1197
R1198
P1_SM_TS_ADDR[0..1] 3 P1_SM_ADDR[0..2] 3
4 Addr._0 : 0011X00Z OR P1_SM_ADDR0 4

P1_SM_TS_ADDR0 P1_SM_ADDR1
: 1001X00Z
: 0101X00Z OR P1_SM_TS_ADDR1 P1_SM_ADDR2
1K
1K
1K
1K
1K
R1199
R1200
Addr._0 : 1010 000Z
R1203
R1201
R1202
VCC3 VCC3
DON'T STUFF
1K
1K
RES_NOPOP
RES_NOPOP
RES_NOPOP
DON'T STUFF P2_SM_TS_ADDR[0..1] 5
R1207
R1204
R1206
P2_SM_ADDR[0..2] 5
R1205
R1208
3 P2_SM_TS_ADDR0 P2_SM_ADDR0 3
P2_SM_TS_ADDR1 P2_SM_ADDR1
P2_SM_ADDR2
CPU_1 Thermal Sensor SM Bus
1K
RES_NOPOP
R1210
Addr._1 : 0011X01Z
1K
1K
RES_NOPOP
DON'T STUFF
OR Addr._1 : 1010 001Z
R1209
: 1001X01Z DON'T STUFF

: 0101X01Z OR
R1212
R1213
R1211
VCC_P
VCC_P
49.9_1%
49.9_1%
R1214
P1_GTLREF0
R1215
P1_GTLREF0 3
P1_GTLREF1
220pF
220pF
1.0uF/10V
P1_GTLREF1 3
220pF
220pF
1.0uF/10V
2 2
100
100
C1159
C1157
C1158
R1216
C1162
C1160
C1161
R1217
VCC_P
VCC_P
49.9_1%
49.9_1%
R1218
P2_GTLREF0
R1219
P2_GTLREF0 5
P2_GTLREF1
220pF
220pF
1.0uF/10V
P2_GTLREF1 5
220pF
220pF
1.0uF/10V
100
100
1 1
C1165
C1163
C1164
R1220
C1168
C1166
C1167
R1221
PLACE EACH 220pf OF Micro Star Restricted Secret

GTLREF NEAR PROC PIN Title
CPU_GTLREF_SMBUS_ADDR
Rev
Document Number 0A

A B C D E
www.vinafix.vn
A B C D E
VCC
8
7
6
5
TO OVERRIDE VIDS, REMOVE CPU JUMPERS, AND
RP1K
1K
VCC
INSTALL THE APPROPRIATE FORCE JUMPERS.
R1172
.01uF
RP439
4 4
1
2
3
4
C1399
J37
P_VID0 1 2 VRM_VID0
P_VID1 1 2 VRM_VID1
3 3 4 4
P_VID2 5 6 VRM_VID2
P_VID3 5 6 VRM_VID3
7 7 8 8
P_VID4 9 10 VRM_VID4
9 10
VCC3 CON10A
10
2
4
6
8
SW4 3,5 P_VID[0..4] RP442 RP0 J38 VRM_VID[0..4] 48,67
RP440 RP441
2
4
6
8
10
1 8 P6_CGF1 1 8 1 8 1 8
P6_CGF2 L1 R1 CON10A
2 7 2 L2 R2 7 2 7 2 7
3 6 P6_CGF3 3 6 3 6 3 6
P6_CGF4 L3 R3 VCC3
4 5 4 L4 R4 5 4 5 4 5
1
3
5
7
9
R1173 0_OHM
RP10K DIP_SW_4 RP330
PLACE THESE COMPONENTS SO THEY ARE ACCESSIBLE
1
3
5
7
9
1K
U139
R1174
U140 11 7
GND GND
2 1A 1Y 4 8 GND VDD 14
INTR 3
50 INTR 1B
3 5 2A 2Y 7 4 GTLREF DIRB-A 1 3
RSB_IGNNE# 6
50 RSB_IGNNE# 2B LINT0_3V LINT0
11 3A 3Y 9 9 B4 A4 6 LINT0 3,5,10
10 IGNNE#_3V 10 5 IGNNE#
3B A20M#_3V B3 A3 A20M# IGNNE# 3,5,10
14 4A 4Y 12 12 B2 A2 3
NMI LINT1_3V LINT1 A20M# 3,5,10
13 4B 13 B1 A1 2 LINT1 3,5,10
RESETDLY# 1 A/B
15 G GTL2005
74F157 .01uF
R1176
C1401
330
0_OHM
R1177
RESETDLY# 11
NMI 49
RSB_A20M# VCC_P
RSB_A20M# 50
VCC_P VCC3
VCC3
.01uF
49.9_1%
49.9_1%
49.9_1%
49.9_1%
49.9_1%
R1307
2 2
C1407
1K
1K
1K
1K
VCC_P GTLREF_1
R1182
R1181
R1183
R1273
U141 GTL2005
R1184
R1185
49.9_1%
49.9_1%
0.1uF
0.1uF
R1308
R1178
R1179
100_1%
C1500
C1501
3 P1_PROCHOT# 2 A1 B1 13 RSB_P1_PROCHOT# 50
3 A2 B2 12
5 P2_PROCHOT# RSB_P2_PROCHOT# 50
5 A3 B3 10
3 P1_IERR# RSB_P1_IERR# 50
5 P2_IERR# 6 A4 B4 9 RSB_P2_IERR# 50
GTLREF_1
R1186
R1187
1 DIRB-A GTLREF 4
VCC3 14 VDD GND 8
330
R1188
7 GND GND 11
.01uF
3 P1_THERMTRIP# C1406
5 P2_THERMTRIP#
VCC_P VCC3
R1274
1 VCC_P 1
R1275 330
330
RSB_FERR# 49 Micro Star Restricted Secret
3
Q16 Title Rev
49.9_1%
R1276
1
2 VID_CONTROL
PMBT2369 Document Number 0A

FERR# Monday, August 20, 2001
3,5,10 FERR# No. 69, Li-De St, Jung-He City,
A B C D E
www.vinafix.vn
A B C D E
VCC_P
VCC3
VCC_P VCC_P
40.2_1%
40.2_1%
40.2_1%
40.2_1%
40.2_1%
RES. TO BE WITHIN
DON'T STUFF
150
RES_NOPOP
1" OF ITP CONN.
1K5_1%
PLACE NEAR CPU1
R1152
RES. TO BE WITHIN
39 R1153
R1154
4 1" OF ITP CONN. 4
R1146
R1147
R1148
R1149
R1150
R1151
J36
1 1 2 2
3 4 DBA#
3 4
5 5 6 6 ITP_RESET# 64
3,5,10 BPM#2 7 7 8 8
9 10 P1_TDI
3,5,10 BPM#3 9 10
3,5,10 BPM#4 11 11 12 12 TMS 3,5
3,5,10 BPM#5 13 13 14 14 ITP_TRST# 3,5
3,5,10,12 PROC_RESET# 15 15 16 16
FBO 17 18 R1155 0_OHM TCK
17 18
19 19 20 20
22 CLK_100M_ITP0
22 CLK_100M_ITP1 21 21 22 22
23 23 24 24 P2_TDO THIS NET TO BE DAISY
Place it as
RES_NOPOP
RES_NOPOP
25 25 CHAINED ALONG PROCS.

X_CON25A close to ITP
Conn. as
CLK_100M_ITP = BCLK (to
680
possible RES. TO BE WITHIN
processors) + Length of
150
R1159
BPM# trace from ITP 1" OF ITP CONN.
Within 1" of the
R1156
R1157
R1158
connector to first CPU. last device on this
Net
3 3
Length of
P1_TCK =
P2_TCK
VCC_P
VCC_P U138
2 18 R_P1_TCK R1160 22
TCK 1A1 1Y1 R_P2_TCK P1_TCK 3
4 1A2 1Y2 16
6 14 R_FBO R1161 22
1A3 1Y3 P2_TCK 5
8 1A4 1Y4 12
11 9 R1162 22 FBO
2A1 2Y1
150
330
13 2A2 2Y2 7
15 2A3 2Y3 5
RES. TO BE WITHIN RES. TO BE WITHIN
R1165
17 2A4 2Y4 3
C1154 C1155
NOPOP
NOPOP
1" OF ITP CONN. 1" OF ITP CONN.
75
1 1G VCC 20 VCC_P
19 2G GND 10
C1156
1K
1K
1K
1K
1K
74LVCH244A
NOPOP
R1163
R1164
330
JP17
2 2
P1_TDI
1 P1_TDI 3
2 P2_TDO P1_TDO 3,5
R1166
R1167
R1168
R1169
3 P2_TDO 5
FBO = TCK (to
R1170
R1171
HEADER_3 VCC_P processors) + Length of
BPM# trace from ITP
Place this HDR next to the connector to first CPU.
CPU nearest to ITP conn. C1398
0.1uF
Look at Routing guidelines while

1
Placing components from this 1
sheet Micro Star Restricted Secret

GND GND SIGNAL Title Rev
ITP CONNECTOR
LAYOUT NOTE: Document Number 0A
BPM#[0..5], RST#, FBO, BCKN, BCKP, TCK, AND FBI
ARE CRITICAL ROUTES. MICRO-STAR INT'L CO.,LTD. Last Revision Date:
A B C D E
www.vinafix.vn
A B C D E
DON'T STUFF PLACE NEAR CPU2

PLACE NEAR CPU1
VCC_P
VCC_P VCC_P
40.2_1%
40.2_1%
40.2_1%
40.2_1%
40.2_1%
40.2_1%
40.2_1%
40.2_1%
40.2_1%
RES_NOPOP
RES_NOPOP
RES_NOPOP
40.2_1%
40.2_1%
40.2_1%
40.2_1%
4 C1140 C1141 C1142 C1143 C1144 C1145 4
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
R1114
R1115
R1118
R1116
R1126
R1117
R1119
R1120
R1121
R1122
R1123
R1124
R1127
R1128
R1129
R1130
3,5,9,12 PROC_RESET#
3,5,8 FERR#
3,5,11 BINIT#
3,5 SMI#
SMI# PLACE THE TERM CAPS NEAR THE TERMINATION
3,5,8 IGNNE# INIT# RESISTORS
3,5 INIT# CPU_STPCLK#
3,5 CPU_STPCLK#
3,5,8 LINT0
BPM#3
BPM#5
BPM#4
BPM#2
3,5,8 LINT1
3,5,8 A20M# SLP#

3,5 SLP#
3,5,9 BPM#[2..5]
VCC_P
150
39
39
39
39
39
R1131
R1132
R1133
R1134
R1135
R1136
3 3
PLACE THESE CLOSE TO CPU2

27PF VCC3
27PF
27PF
27PF
27PF
1K
C2061
C2058
C2059
C2060
C2062
R1137
BINIT#
U137A
3,5,11 BNR#
3,5,11 HIT# CPU_STPCLK#
3,5,11 HITM# LOCK# 3,5,11 50 RSB_STPCLK# 1 2
3,5 MCERR#
7407
VCC3
R1139 1K
1K
R1138
VCC3 U137B
U137C
3 4 SMI#
50,58 EXT_SMI# SLP#
2 5 6 2
50 RSB_SLP#
50,58 RSB_SMI#
7407
7407
R1140 1K
VCC25 U137D
9 8 INIT#
11,50,57 CMIC_PINIT#
11,50,57 RSB_PINIT#
7407
11,50,57 KBD_INIT# (Make small Cu Islands
for P1/P2_VCCA,
P1/P2_VSSA
Place these Close to CPU1 Place these Close to CPU2 and P1/P2_VCCIOPLL nets )
VCC_P VCC_P
L43 4.7uH L44 4.7uH

R1142 0_OHM 1 2 R1143 0_OHM 1 2
P1_VCCA 3 P2_VCCA 5
1
C1146 + C1147 C1148 +

1 33uF/6V 1.0uF/10V 33uF/6V C1149 1
1.0uF/10V
2
P1_VSSA 3 P2_VSSA 5
2
C1150 Title Rev

33uF/6V C1151 C1152 C1153 CPU_LEVEL_SHIFT_THERM
1.0uF/10V 1.0uF/10V
+ +
33uF/6V Document Number 0A
L45 4.7uH MICRO-STAR INT'L CO.,LTD. Last Revision Date:

1
R1144 0_OHM 1 2 R1145 0_OHM 1 2 Monday, August 20, 2001

P1_VCCIOPLL 3 P2_VCCIOPLL 5
L46 4.7uH Taipei Hsien, Taiwan Sheet
A B C D E
www.vinafix.vn
A B C D E
PD#[0..63]
PD#[0..63] 3,5
PA#[3..35]
3,5 PA#[3..35] U1A VCC_P
PA#3 K15 C2 PD#0

PA#4 A3# D0# PD#1
A17 A4# D1# E3
PA#5 PD#2
49.9_1%
A19 A5# D2# B3
PA#6 PD#3
R1096
B18 A6# D3# C3
4 PA#7 A18 F3 PD#4 4
PA#8 A7# D4# PD#5
B19 A8# D5# D4
PA#9 A20 A2 PD#6
PA#10 A9# D6# PD#7 GTL_VREF_CMIC
G16 A10# D7# D2
PA#11 C19 D3 PD#8
PA#12 A11# D8# PD#9
220pF
220pF
100_1%
E19 A12# D9# A3
PA#13 H17 H6 PD#10
PA#14 A13# D10# PD#11
H16 F6
1.0uF/10V
PA#15 A14# D11# PD#12
C1109
D19 A15# D12# G8
PA#16 F18 F5 PD#13
PA#17 A16# D13# PD#14
C1107
C1108
R1099
H18 A17# D14# H8
PA#18 G19 H10 PD#15
PA#19 A18# D15# PD#16
F19 A19# D16# F7
PA#20 A23 G9 PD#17
PA#21 A20# D17# PD#18
B23 A21# D18# E7
PA#22 A22 E6 PD#19
MEMOFFACK# PA#23 A22# D19# PD#20
15 MEMOFFACK# A21 A23# D20# A4
PA#24 F20 B4 PD#21
PA#25 A24# D21# PD#22
B20 A25# D22# D7
4.7K PA#26 A24 A5 PD#23
PA#27 A26# D23# PD#24
VCC25 A25 A27# D24# G10
PA#28 D20 K11 PD#25 VCC_P
R1398 PA#29 A28# D25# PD#26
B21 A29# D26# B7
PA#30 E20 C6 PD#27
PA#31 A30# D27# PD#28
B25 A31# D28# F8
PA#32 PD#29
R1032
R1033
R1034
B27 A32# D29# C7
PA#33 A26 E9 PD#30
PA#34 A33# D30# PD#31
C22 A34# D31# K12
3 PA#35 D22 D8 PD#32 3
A35# D32# PD#33
20.5_1%
249_1%
249_1%
D33# C8
ADSTB#0 D18 D9 PD#34
3,5 ADSTB#0 ADSTB0# D34#
ADSTB#1 C20 B9 PD#35
3,5 ADSTB#1 ADSTB1# D35#
E10 PD#36
ADS# D36# PD#37
3,5 ADS# F1 ADS# D37# A7
BNR# H19 A10 PD#38
3,5,10 BNR# BNR# D38#
BPRI# G2 A8 PD#39 GTL_COMP_PD
3,5 BPRI# BPRI# D39#
DBSY# K17 B12 PD#40 GTL_COMP_PU
3,5 DBSY# DBSY# D40#
DRDY# H5 A11 PD#41 GTL_RCOMP
3,5 DRDY# DRDY# D41#
HIT# C1 F12 PD#42
3,5,10 HIT# HIT# D42#
HITM# D1 A12 PD#43
3,5,10 HITM# HITM# D43#
LOCK# G3 G13 PD#44
3,5,10 LOCK# LOCK# D44#
P_TRDY# F4 F13 PD#45
3,5 P_TRDY# TRDY# D45#
DEFER# E1 K13 PD#46
3,5 DEFER# DEFER# D46#
BREQ#0 F23 H12 PD#47
3,5 BREQ#0 BREQ0# D47#
B13 PD#48
D48# PD#49
27,37,50,64 PS_PWRGD# AE25 PLLRST D49# D12
RESETDLY# AE24 A13 PD#50
8 RESETDLY# DLYRST D50#
PCIRST# AF26 E13 PD#51
27,37,65 PCIRST# PCIRST# D51#
R1255 10K WRMRST# AE26 C13 PD#52
VCC25 WRMRST# D52#
C14 PD#53
RS#0 D53# PD#54
15 WRMRST# 3,5 RS#0 B1 RS0# D54# A15
RS#1 G1 B15 PD#55
3,5 RS#1 RS1# D55#
RS#2 F2 D15 PD#56
3,5 RS#2 RS2# D56#
RSP# D24 E14 PD#57
3,5 RSP# RSP# D57#
E15 PD#58
HREQ#0 D58# PD#59
3,5 HREQ#0 E16 HREQ0# D59# H14
HREQ#1 G15 K14 PD#60
2 3,5 HREQ#1 HREQ1# D60# 2
HREQ#2 F15 C15 PD#61
3,5 HREQ#2 HREQ2# D61#
HREQ#3 C16 A16 PD#62
HREQ#4 H15 G14 PD#63
AP#0 E23 G5 DINV#0
3,5 AP#0 AP0# DINV0#
AP#1 C24 A6 DINV#1
3,5 AP#1 AP1# DINV1#
R1256 4.7K C10 DINV#2
VCC25 DINV2# DINV#[0..3] 3,5
AF27 H13 DINV#3
15,27,37,50 ALERT# ALERT# DINV3#
3,5,10 BINIT# F21 BINIT#
AF23 C26 DP#0
10,50,57 CMIC_PINIT# HINIT# DP0#
AD27 B26 DP#1
22 HCLK_CMIC BCLKP DP1#
AE27 E21 DP#2
22 HCLK_CMIC_N BCLKN DP2# DP#[0..3] 3,5
CMIC_FATAL# AG25 E25 DP#3
15,50 CMIC_FATAL# FATAL# DP3#
AG24 G6 DSTBN#0
VCC25 4.7K R1257 MEMOFFACK# AG26 MEMOFF# DSTBN0# DSTBN#1
MEMOFFACK# DSTBN1# F9
C9 DSTBN#2
DSTBN2# DSTBN#[0..3] 3,5
GTL_VREF_CMIC H9 D13 DSTBN#3
15,49 MEMOFF# GTL_VREF DSTBN3#
K18 GTL_VREF
VCC25 4.7K R1384 H7 DSTBP#0
GTL_COMP_PU G21 DSTBP0# DSTBP#1
GTL_COMP_PU DSTBP1# H11
GTL_COMP_PD F22 A9 DSTBP#2
GTL_COMP_PD DSTBP2# DSTBP#[0..3] 3,5
GTL_RCOMP H20 A14 DSTBP#3
GTL_RCOMP DSTBP3#
1 CMIC_LE 1

Title Rev
CMIC_FOSTER_IF
Document Number 0A

A B C D E
www.vinafix.vn
A B C D E
U1B
37 B_IMB_D_R[0..15]
B_IMB_D_R0 R25 L20 A_IMB_D_R0
B_IMB_D_R1 BIMBD_R0 AIMBD_R0 A_IMB_D_R1
T23 B IMBD_R1 AIMBD_R1 L17
B_IMB_D_R2 R26 L18 A_IMB_D_R2
4 B_IMB_D_R3 BIMBD_R2 AIMBD_R2 A_IMB_D_R3 4
R27 BIMBD_R3 AIMBD_R3 K20
B_IMB_D_R4 R22 J24 A_IMB_D_R4
P23 BIMBD_R5 AIMBD_R5 H23
B_IMB_D_R6 R24 H22 A_IMB_D_R6
R23 BIMBD_R7 AIMBD_R7 J22
B_IMB_D_R8 N25 H26 A_IMB_D_R8
BIMBD_R8 AIMBD_R8 A_IMB_D_R[0..15] 27
B_IMB_D_R9 N22 F27 A_IMB_D_R9
P21 BIMBD_R10 AIMBD_R10 G24
B_IMB_D_R11 N23 G27 A_IMB_D_R11
N24 BIMBD_R12 AIMBD_R12 G25
B_IMB_D_R13 P20 E27 A_IMB_D_R13
R18 BIMBD_R14 AIMBD_R14 F24
B_IMB_D_R15 R17 J20 A_IMB_D_R15
BIMBD_R15 AIMBD_R15
37 B_IMB_CON_R N20 BIMBCON_R AIMBCON_R F25 A_IMB_CON_R 27

25 B_IMB_CLK_R_P P25 BIMBCLK_R_P AIMBCLK_R_P H25 A_IMB_CLK_R_P 25
25 B_IMB_CLK_R_N P27 BIMBCLK_R_N AIMBCLK_R_N H24 A_IMB_CLK_R_N 25
N21 BMBPAR_R AIMBPAR_R F26 A_IMB_PAR_R 27
37 B_IMB_PAR_R
37 B_IMB_D_T[0..15] B_IMB_D_T0 A_IMB_D_T0

U21 BIMBD_T0 AIMBD_T0 M26
B_IMB_D_T1 U23 M25 A_IMB_D_T1
B_IMB_D_T2 BIMBD_T1 AIMBD_T1 A_IMB_D_T2
T20 BIMBD_T2 AIMBD_T2 N27
B_IMB_D_T3 U18 N18 A_IMB_D_T3 A_IMB_D_T[0..15]
B_IMB_D_T4 BIMBD_T3 AIMBD_T3 A_IMB_D_T4 A_IMB_D_T[0..15] 27
U17 BIMBD_T4 AIMBD_T4 N17
B_IMB_D_T5 V20 M24 A_IMB_D_T5
U20 BIMBD_T6 AIMBD_T6 N26
B_IMB_D_T7 T22 L27 A_IMB_D_T7
3 T21 BIMBD_T8 AIMBD_T8 M27 3
B_IMB_D_T9 R21 L21 A_IMB_D_T9
T25 BIMBD_T10 AIMBD_T10 M22
B_IMB_D_T11 U27 H27 A_IMB_D_T11
T24 BIMBD_T12 AIMBD_T12 J27
B_IMB_D_T13 U25 K27 A_IMB_D_T13
T27 BIMBD_T14 AIMBD_T14 J26
B_IMB_D_T15 T26 M21 A_IMB_D_T15
BIMBD_T15 AIMBD_T15
37 B_IMB_CON_T R20 BIMBCON_T AIMBCON_T M20 A_IMB_CON_T 27

25 B_IMB_CLK_T_P_R W26 BIMBCLK_T_P AIMBCLK_T_P L25 A_IMB_CLK_T_P_R 25
25 B_IMB_CLK_T_N_R W27 BIMBCLK_T_N AIMBCLK_T_N M23 A_IMB_CLK_T_N_R 25
37 B_IMB_PAR_T V27 BIMBDPAR_T AIMBPAR_T L23 A_IMB_PAR_T 27
T_IMB_D_R[0..3] 46,50
R_T_IMB_D_T0 Y22 Y26 T_IMB_D_R0
R_T_IMB_D_T1 AA25 T_IMBD_T0 T_IMBD_R0 T_IMB_D_R1
T_IMBD_T1 T_IMBD_R1 W24
R_T_IMB_D_T2 Y21 AA26 T_IMB_D_R2
R_T_IMB_D_T3 Y24 T_IMBD_T2 T_IMBD_R2 T_IMB_D_R3
T_IMBD_T3 T_IMBD_R3 W22
R_TIMB_CLK_TRAA24 Y27
T_IMBCLK_T T_IMBCLK_R T_IMB_CLK_R 25,46
R_TIMB_CON_T AA23 AA27
T_IMBCON_T T_IMBCON_R T_IMB_CON_R 46,50
R_TIMB_PAR_T AB25 W20
T_IMBPAR_T T_IMBPAR_R T_IMB_PAR_R 46,50
IMB_VREF_CMIC P18 C27

IMB_VREF CPURST# PROC_RESET# 3,5,9,10
SRESET# AF25 POWERGOOD_CMIC 15,64
TESTMODE# AD26
RP452 CMIC_IMB_COMP_PD D27 4.7K R1348
2 IMB_COMP_PD VCC25 2
T_IMB_PAR_T 1 RP22R 8 R_TIMB_PAR_T CMIC_IMB_COMP_PU H21 AE23
46,50 T_IMB_PAR_T T_IMB_CLK_TR 2 R_TIMB_CLK_TR CMIC_IMB_RCOMP IMB_COMP_PU SDA
25 T_IMB_CLK_TR 7 G22 IMB_RCOMP SCLK AG23
3 6 TESTMODE# 15
T_IMB_CON_T 4 5 R_TIMB_CON_T
46,50 T_IMB_CON_T
RCC_SDA 15,27,37,41,48,69
RP453 CMIC_LE RCC_SCL 15,27,37,41,48,69
46,50 T_IMB_D_T[0..3] T_IMB_D_T0 RP22R 8 R_T_IMB_D_T0
1
T_IMB_D_T3 2 7 R_T_IMB_D_T3
VDD_IMB
VDD_IMB
100_1%
R1104
R1031
R1399
R1400
IMB_VREF_CMIC
249_1%
249_1%
100_1%
220pF
220pF
100_1%
1 1
CMIC_IMB_COMP_PU
1.0uF/10V
CMIC_IMB_COMP_PD
C1112
R1106
C1110
C1111
CMIC_IMB_RCOMP Title Rev

CMIC_CIOB_IF
Document Number 0A

A B C D E
www.vinafix.vn
A B C D E
R_A_DQS0_0
R_A_DQS0_1
R_A_DQS1_0
R_A_DQS1_1
R_A_DQS2_0
R_A_DQS2_1
R_A_DQS3_0
R_A_DQS3_1
R_A_DQS4_0
R_A_DQS4_1
R_A_DQS5_0
R_A_DQS5_1
R_A_DQS6_0
R_A_DQS6_1
R_A_DQS7_0
R_A_DQS7_1
R_A_DQS8_0
R_A_DQS8_1
AG20
AG19
AC20
AD20
AC13
AB13
AE9
AF8
N10
V11
Y11
W1
U1C
N7
H4
H3
P7
Y2
T4
R_A_SD0_0 AA22 Y20 R_B_SD0_0 R_B_DQS0_[0..1]
A_DQS0_0
A_DQS0_1
A_DQS1_0
A_DQS1_1
A_DQS2_0
A_DQS2_1
A_DQS3_0
A_DQS3_1
A_DQS4_0
A_DQS4_1
A_DQS5_0
A_DQS5_1
A_DQS6_0
A_DQS6_1
A_DQS7_0
A_DQS7_1
A_DQS8_0
A_DQS8_1
20 R_A_SD0_[0..7] A_SD0_0 B_SD0_0 R_B_SD0_[0..7] 20 20 R_B_DQS0_[0..1]
R_A_SD0_1 AD22 AA21 R_B_SD0_1
R_A_SD0_2 A_SD0_1 B_SD0_1 R_B_SD0_2 R_B_DQS1_[0..1]
AC19 A_SD0_2 B_SD0_2 AA19 20 R_B_DQS1_[0..1]
R_A_SD0_3 AA18 V17 R_B_SD0_3
4 R_A_SD0_4 A_SD0_3 B_SD0_3 R_B_SD0_4 R_B_DQS2_[0..1] 4
AB23 A_SD0_4 B_SD0_4 V18 20 R_B_DQS2_[0..1]
R_A_SD0_5 AB19 Y19 R_B_SD0_5
AD19 A_SD0_6 B_SD0_6 AB20 20 R_B_DQS3_[0..1]
R_A_SD0_7 Y16 Y18 R_B_SD0_7
A_SD0_7 B_SD0_7 R_B_DQS4_[0..1]
20 R_B_DQS4_[0..1]
R_A_SD1_0 V15 AF22 R_B_SD1_0
20 R_A_SD1_[0..7] A_SD1_0 B_SD1_0 R_B_SD1_[0..7] 20
R_A_SD1_1 AG22 AE21 R_B_SD1_1 R_B_DQS5_[0..1]
A_SD1_1 B_SD1_1 20 R_B_DQS5_[0..1]
R_A_SD1_2 AB15 Y17 R_B_SD1_2
AD16 A_SD1_3 B_SD1_3 V16 20 R_B_DQS6_[0..1]
R_A_SD1_4 AG21 AE22 R_B_SD1_4
AF19 A_SD1_5 B_SD1_5 AE20 20 R_B_DQS7_[0..1]
R_A_SD1_6 AG17 AC18 R_B_SD1_6
AB16 A_SD1_7 B_SD1_7 AE18 20 R_B_DQS8_[0..1]
R_A_SD2_0 AG14 AF16 R_B_SD2_0
20 R_A_SD2_[0..7] A_SD2_0 B_SD2_0 R_B_SD2_[0..7] 20
R_A_SD2_1 Y14 AF15 R_B_SD2_1
R_A_SD2_2 A_SD2_1 B_SD2_1 R_B_SD2_2
AF13 A_SD2_2 B_SD2_2 AC15
R_A_SD2_3 AG12 AB14 R_B_SD2_3
AE14 A_SD2_4 B_SD2_4 AG16
R_A_SD2_5 V14 AG15 R_B_SD2_5 R_A_DQS0_[0..1]
R_A_SD2_6 A_SD2_5 B_SD2_5 R_B_SD2_6 20 R_A_DQS0_[0..1]
AG13 A_SD2_6 B_SD2_6 AD14
R_A_SD2_7 AE13 Y15 R_B_SD2_7 R_A_DQS1_[0..1]
A_SD2_7 B_SD2_7 20 R_A_DQS1_[0..1]
R_A_SD3_0 Y13 AA13 R_B_SD3_0 R_A_DQS2_[0..1]
20 R_A_SD3_[0..7] A_SD3_0 B_SD3_0 R_B_SD3_[0..7] 20 20 R_A_DQS2_[0..1]
R_A_SD3_1 AF9 AD13 R_B_SD3_1
R_A_SD3_2 A_SD3_1 B_SD3_1 R_B_SD3_2 R_A_DQS3_[0..1]
AE8 A_SD3_2 B_SD3_2 AC12 20 R_A_DQS3_[0..1]
R_A_SD3_3 AD10 AG9 R_B_SD3_3
AA12 A_SD3_4 B_SD3_4 V13 20 R_A_DQS4_[0..1]
3 R_A_SD3_5 AG8 AE12 R_B_SD3_5 3
AG6 A_SD3_6 B_SD3_6 AF10 20 R_A_DQS5_[0..1]
R_A_SD3_7 AG5 AG7 R_B_SD3_7
A_SD3_7 B_SD3_7 R_A_DQS6_[0..1]
R_A_SD4_0 R_B_SD4_0 20 R_A_DQS6_[0..1]
T10 A_SD4_0 B_SD4_0 AB4 R_B_SD4_[0..7] 20
20 R_A_SD4_[0..7] R_A_SD4_1 R_B_SD4_1 R_A_DQS7_[0..1]
Y4 A_SD4_1 B_SD4_1 AB2 20 R_A_DQS7_[0..1]
R_A_SD4_2 R11 AA1 R_B_SD4_2
T7 A_SD4_3 B_SD4_3 T8 20 R_A_DQS8_[0..1]
R_A_SD4_4 W5 AA3 R_B_SD4_4
Y3 A_SD4_5 B_SD4_5 AA2
R_A_SD4_6 U6 Y1 R_B_SD4_6
U1 A_SD4_7 B_SD4_7 AA5
R_A_SD5_0 T3 P8 R_B_SD5_0
20 R_A_SD5_[0..7] A_SD5_0 B_SD5_0 R_B_SD5_[0..7] 20
R_A_SD5_1 R2 R3 R_B_SD5_1
R4 A_SD5_2 B_SD5_2 P5
R_A_SD5_3 R5 J8 R_B_SD5_3
T5 A_SD5_4 B_SD5_4 P10
R_A_SD5_5 R1 N2 R_B_SD5_5
K8 A_SD5_6 B_SD5_6 N5
R_A_SD5_7 R6 N6 R_B_SD5_7
A_SD5_7 B_SD5_7
R_A_SD6_0 N3 W3 R_B_SD6_0
20 R_A_SD6_[0..7] A_SD6_0 B_SD6_0 R_B_SD6_[0..7] 20
R_A_SD6_1 N1 V1 R_B_SD6_1
M2 A_SD6_2 B_SD6_2 T2
R_A_SD6_3 M4 T1 R_B_SD6_3
N8 A_SD6_4 B_SD6_4 T6
R_A_SD6_5 N4 U4 R_B_SD6_5
2 L1 A_SD6_6 B_SD6_6 R7 2
R_A_SD6_7 M3 R8 R_B_SD6_7
A_SD6_7 B_SD6_7
R_A_SD7_0 H1 M1 R_B_SD7_0
20 R_A_SD7_[0..7] A_SD7_0 B_SD7_0 R_B_SD7_[0..7] 20
R_A_SD7_1 H2 J1 R_B_SD7_1
L6 A_SD7_2 B_SD7_2 M5
R_A_SD7_3 M10 L10 R_B_SD7_3
J5 A_SD7_4 B_SD7_4 K1
R_A_SD7_5 J3 L2 R_B_SD7_5
L8 A_SD7_6 B_SD7_6 M6
R_A_SD7_7 K10 M8 R_B_SD7_7
A_SD7_7 B_SD7_7
R_A_SD8_0 AF3 AD9 R_B_SD8_0
20 R_A_SD8_[0..7] A_SD8_0 B_SD8_0 R_B_SD8_[0..7] 20
R_A_SD8_1 AG2 AD8 R_B_SD8_1
AB10 A_SD8_2 B_SD8_2 AG4
R_A_SD8_3 AA9 AD7 R_B_SD8_3
AE6 A_SD8_4 B_SD8_4 V12
R_A_SD8_5 AF5 Y12 R_B_SD8_5
AC8 A_SD8_6 B_SD8_6 AE7
R_A_SD8_7 AB9 AG3 R_B_SD8_7
16,17,18,19,20 MA[0..14] A_SD8_7 B_SD8_7
MA0 AD5 AB1
MA1 MA0 WE# WE# 16,17,18,19,20
AE5 MA1 RAS# AC1 RAS# 16,17,18,19,20
MA2 Y10 W8
MA3 MA2 CAS# CAS# 16,17,18,19,20
AA8 MA3 A_CKE AB8 A_CKE 16,17,20
MA4 Y9 AE4
MA5 MA4 B_CKE B_CKE 18,19,20
Y7 MA5
MA6 AF1 U8 R_CS_0 39 R1519 CS_0
MA6 CS0 CS_0 16,18
MA7 AE2 U10 R_CS_1 39 R1520 CS_1
1 MA7 CS1 CS_1 16,18 1
AA20B_DQS0_0
AB21B_DQS0_1
AF20 B_DQS1_0
AE19B_DQS1_1
AE15B_DQS2_0
AD15B_DQS2_1
AG11B_DQS3_0
AG10B_DQS3_1
AA4 B_DQS4_0
Y5 B_DQS4_1
P1 B_DQS5_0
P3 B_DQS5_1
R10 B_DQS6_0
U2 B_DQS6_1
L4 B_DQS7_0
M7 B_DQS7_1
AC9 B_DQS8_0
AF6 B_DQS8_1
MA8 AD3 W7 R_CS_2 39 R1521 CS_2

MA8 CS2 CS_2 16,18
MA9 AE3 V8 R_CS_3 39 R1522 CS_3
MA9 CS3 CS_3 16,18
MA10 R_CS_4 39 R1523 CS_4
V10 MA12
AA7 MA13
AB6 MA14
AF2 MA10 CS4 AE1 CS_4 17,19

Y6 CS7
AA6 CS6
MA11 Y8 MA11 CS5 AD1 R_CS_5

R_CS_6
39
39
R1524
R1525
CS_5
CS_6
CS_5 17,19 Micro Star Restricted Secret
CS_6 17,19
R_CS_7 39 R1526 CS_7 Title Rev
CS_7 17,19
MA12 CMIC_LE Document Number
CMIC_MEM_IF
0A
R_B_DQS0_0
R_B_DQS0_1
R_B_DQS1_0
R_B_DQS1_1
R_B_DQS2_0
R_B_DQS2_1
R_B_DQS3_0
R_B_DQS3_1
R_B_DQS4_0
R_B_DQS4_1
R_B_DQS5_0
R_B_DQS5_1
R_B_DQS6_0
R_B_DQS6_1
R_B_DQS7_0
R_B_DQS7_1
R_B_DQS8_0
R_B_DQS8_1
MA13
MA14 MICRO-STAR INT'L CO.,LTD. Last Revision Date:
A B C D E
www.vinafix.vn
A B C D E
VCC25 VCC25
VCC_P
U1E VCC_P U1D R1026 L41
1 2 CMIC_AVDD
B2 VTT VDD_2.5 AB12
B8 AB11 C1649 V23 A1 0 47uH 22uF/10V
VTT VDD_2.5 0.01uF GND91 GND1 C1052 C1053
B16 VTT VDD_2.5 AB7 V25 GND92 GND2 A27
B17 AB5 W9 B5 1.0uF/10V
VTT VDD_2.5 C1650 GND93 GND3
B22 VTT VDD_2.5 AB3 W11 GND94 GND4 B6
4 B24 AC26 0.1uF W13 B10 4
VTT VDD_2.5 GND95 GND5
C4 VTT VDD_2.5 AC24 W15 GND96 GND6 B11
C5 AC22 C1651 B14
VTT VDD_2.5 0.01uF GND7
C11 VTT VDD_2.5 AC17 W19 GND98 GND8 C17
C23 VTT VDD_2.5 AC7 W25 GND102 GND11 D5
D16 VTT VDD_2.5 AC5 AA10 GND103 GND12 D6
D17 VTT VDD_2.5 AC3 AA11 GND104 GND13 D10 ANCHORs for JP35 JP36
D26 AD12 C1076 AA14 D11
E4
VTT VDD_2.5
AD11 0.1uF AB17
GND105 GND14
D14
CMIC_LE Heatsink 2 1
VTT VDD_2.5 GND106 GND15 1 2
E5 VTT VDD_2.5 AE17 AB18 GND107 GND16 D21
E8 AE16 C1077 AC2 D23 HS_ANCHOR HS_ANCHOR
VTT VDD_2.5 0.1uF GND108 GND17
E11 VTT VDD_2.5 AF24 AC4 GND109 GND18 K16
E12 VTT VDD_2.5 AF21 AC6 GND110 GND19 E2
F16 AF12 C1078 AC10 E17
VTT VDD_2.5 0.01uF GND111 GND20
F17 VTT VDD_2.5 AF11 AC11 GND112 GND21 E18
GND SIGNAL
GND_SIGNAL
GND
G4 AF4 AC21 E22 VCC25
VTT VDD_2.5 C1079 GND113 GND22
G11 VTT AC23 GND114 GND23 E24
G12 E26 0.01uF AC25 F10
VTT VDD_IMB GND115 GND24
100_1%
G20 VTT VDD_IMB G23 AD2 GND116 GND25 F11
C1080
R1028
J10 VTT VDD_IMB K19 AD4 GND117 GND26 F14
J12 K22 0.01uF AD6 G7
VTT VDD_IMB GND118 GND27
J14 VTT VDD_IMB K24 AD17 GND119 GND28 G17
J16 K26 C1081 AD18 G18
VTT VDD_IMB 0.01uF GND120 GND29 MEM_VREF_CMIC
J18 VTT VDD_IMB L22 AD21 GND121 GND30 G26
VDD_IMB L24 AD23 GND122 GND31 J2
100_1%
0.1uF
K9 L26 AD25 J4
C1059 1.0uF/10V
VDD_2.5 VDD_IMB GND123 GND32
220pF
220pF
3 K7 VDD_2.5 VDD_IMB M17 AE10 GND124 GND33 J6 3
K5 VDD_2.5 VDD_IMB M19 AE11 GND125 GND34 J9
K3 P17 VDD_IMB C1129 AF7 J11
VDD_2.5 VDD_IMB 0.1uF GND126 GND35
L15 VDD_2.5 VDD_IMB P19 AF14 GND127 GND36 J13
C1056
C1057
C1058
R1029
L13 VDD_2.5 VDD_IMB P24 AF17 GND128 GND37 J15
L11 T17 C1128 AF18 J17
VDD_2.5 VDD_IMB 0.1uF GND129 GND38
L7 VDD_2.5 VDD_IMB T19 AG1 GND130 GND39 J19
L5 U22 VCC25 AG27 J21
VDD_2.5 VDD_IMB C1127 GND131 GND40
L3 VDD_2.5 VDD_IMB U24 GND41 J23
M16 U26 0.1uF V5 J25 VCC25
VDD_2.5 VDD_IMB GND133 GND42
M14 VDD_2.5 VDD_IMB V19 V7 GND135 GND43 K2
M12 V24 C1082 R12 K4
VDD_2.5 VDD_IMB 0.1uF GND72 GND44 VCC25
M9 VDD_2.5 VDD_IMB V26 R14 GND73 GND45 K6
VCC25 N15 R16 K21
VDD_2.5 C1083 GND74 GND46
249_1%
R1030
N13 VDD_2.5 R19 GND75 GND47 K23
N11 0.1uF T11 K25
VDD_2.5 GND76 GND48 C1113 C1114 C1115
P16 VDD_2.5 T13 GND77 GND49 L9
P14 C1084 T15 L12
VDD_2.5 0.01uF GND78 GND50 1.0uF/16V 1.0uF/16V 1.0uF/16V
P12 VDD_2.5 T18 GND79 GND51 L14
P9 U3 L16 CMIC_DCOMP
VDD_2.5 C1085 GND80 GND52
P4 VDD_2.5 U5 GND81 GND53 L19
R15 AB27 CMIC_AVDD 0.01uF U7 M11
VDD_2.5 AVDD GND83 GND55
R13 VDD_2.5 GND56 M13
T16 AC27 C1086 U12 M15
VDD_2.5 AGND 0.01uF GND85 GND57
T14 VDD_2.5 U14 GND86 GND58 M18
T12 U9 U16 N9
270uF/4V/20mR/SP/OSCON
VDD_2.5 MEM_VREF MEM_VREF_CMIC C1087 GND87 GND59
T9 VDD_2.5 MEM_VREF W17 GND60 N12 VCC25
U15 0.01uF V3 N14
VDD_2.5 GND89 GND61
1
2 U13 AG18 CMIC_DCOMP V21 N16 2
VDD_2.5 DCOMP GND90 GND62 + C1422 +
C1095
U11 VDD_2.5 P6 GND65 GND63 N19
V22 C1088 P11 P2 560uF/4V
VDD_2.5 0.1uF GND66 GND64
V9 VDD_2.5 P13 GND67 GND71 R9
V6 AD24 CMIC_RSVD P15 P26
2
VDD_2.5 RSVD C1089 GND68 GND70
V4 VDD_2.5 P22 GND69 GND136 AA17
V2 U19 MEM_VREF_CMIC 0.1uF J7 D25
VDD_2.5 T_IMB_VREF GND139 GND137
W18 VDD_2.5
W16 C1090
VDD_2.5 0.01uF VCC_P VDD_IMB
W14
VDD_2.5
W12 VDD_2.5 C1091
W10
W6
VDD_2.5 0.01uF CMIC_LE
VDD_2.5
1
W4 VDD_2.5 C1098 C1423 + + +
C1092
W2 VDD_2.5
Y25 0.01uF 560uF/4V C1094
VDD_2.5 CMIC_RSVD 15 270uF/4V/20mR/SP/OSCON
Y23 VDD_2.5
AA16 C1099
2
VDD_2.5 0.01uF
AA15 VDD_2.5
AB26 VDD_2.5
AB24 C1653 VCC25 VDD_IMB
VDD_2.5 0.01uF
AB22 VDD_2.5
C1654
0.1uF C1655 C1656 C1657 C1658 C1659 C1660
CMIC_LE C1661
0.01uF
1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V
1 VDD_IMB C1662 1
0.1uF
C1652
0.1uF
C1664 C1665 C1666 C1667 C1668 C1669 C1670 C1671 C1672 VCC_P Title Rev
CMIC_PWR
0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF Document Number 0A
C1424 C1425 C1426 C1427 C1428 C1429 C1430
1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V Monday, August 20, 2001
A B C D E
www.vinafix.vn
A B C D E
VCC25
Thin IMB FREQ.
VCC25
COMPATIBILITY IMB 1 = 100 MHz 2X
0 = 200 MHz 2X
1: A_IMB is Compatibility Bus R1100
C1395
0.1uF
0: Thin IMB is Compatibility Bus 2.2K
( Default ) 14 CMIC_RSVD
CMIC_RSVD
U136 R1505
4 VCC25 CMIC_PLL_EN# 2 18 CMIC_FATAL# 4
CMIC_DEFER_EN 1A1 1Y1 WRMRST# CMIC_FATAL# 11,50 RES_NOPOP
4 1A2 1Y2 16
COMP_IMB MEMOFF# WRMRST# 11
6 1A3 1Y3 14
IOQ_DEPTH MEMOFFACK# MEMOFF# 11,49
8 1A4 1Y4 12 MEMOFFACK# 11
DETERMINISTIC_IMB 11 9 RCC_SCL
IMB_TRAINING 2A1 2Y1 RCC_SDA RCC_SCL 12,27,37,41,48,69
8.2K
R1105
13 2A2 2Y2 7 RCC_SDA 12,27,37,41,48,69

IMB_CRC_PARITY 15 5 ALERT#
JP25 2A3 2Y3 ALERT# 11,27,37,50
IMB_R_W_PTR_DLY 17 2A4 2Y4 3 TESTMODE#
TESTMODE# 12 Do not stuff
COMP_IMB
2
1 1 1G VDD 20 VCC25
12,64 POWERGOOD_CMIC 19 2G GND 10
HDR_1X2 74LVCH244A
R1107
1K
A/B_IMB CRC or PARITY

0 : PARITY is enabled for A & B IMB buses (Default )
VCC25
1 : CRC is enabled for A & B IMB buses
IMB - DETERMINISTIC/ NON ( In final version Use CRC on IMB buses )

R1102
VCC25 DETERMINISTIC 8.2K
3 VCC25 3
0 : Deterministic IMB JP37
DEFER ENABLE/DISABLE R1396
1 : Non Deterministic IMB (Default ) IMB_CRC_PARITY
8.2K 2
1
OFF: Defer Enabled ( Default )
8.2K
ON: Defer Disabled JP38 HDR_1X2

DETERMINISTIC_IMB R1103
2
R1108
JP13 1 2.2K
CMIC_DEFER_EN
2 HDR_1X2 1K
1
R1397
HDR_1X2
R1109
1K
IMB_TRAINING
VCC25
0 : IMB TRAINING Disabled
1 : IMB TRAINING Enabled ( Default )
R1094
2 2
8.2K
IMB_READ/WRITE POINTER DLY
VCC25
1 : 5 CLOCKs ( Default ) JP39
0 : 6 CLOCKs
CMIC PLL ENABLE/DISABLE 2
IMB_TRAINING
R1506
1
2.2K
1: APLL Disabled
1K
HDR_1X2
R1097
0: APLL Enabled
( Default )
VCC25 IMB_R_W_PTR_DLY
DO NOT STUFF
IOQ DEPTH
RES_NOPOP
VCC25
R1507
Do not stuff
RES_NOPOP
OFF: IOQ Depth 1

R1110
8.2K
ON: IOQ Depth

12 ( Default )
CMIC_PLL_EN#
R1111
1 1
JP14
2.2K
IOQ_DEPTH
2
1 Micro Star Restricted Secret
R1112
Title Rev
HDR_1X2 CMIC STRAPPING OPTIONS
1K
R1113
Document Number 0A

A B C D E
www.vinafix.vn
A B C D E
VCC25
13,17,18,19,20 MA[0..14]
100
116
124
132
139
145
176
160
152
100
116
124
132
139
145
176
160
152
11
18
26
34
42
50
58
66
74
81
89
93
11
18
26
34
42
50
58
66
74
81
89
93
3
3
C1358 C1359 C1360 C1361
0.01uF 0.01uF 0.01uF 0.01uF
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MA0 48 MA0 48
MA1 A0 A_SD0_0 MA1 A0 A_SD0_0
43 A1 D0 2 43 A1 D0 2
MA2 41 4 A_SD0_1 MA2 41 4 A_SD0_1
MA3 A2 D1 A_SD0_2 MA3 A2 D1 A_SD0_2
130 A3 D2 6 130 A3 D2 6
MA4 37 8 A_SD0_3 MA4 37 8 A_SD0_3
MA5 A4 D3 A_DQS0_0 MA5 A4 D3 A_DQS0_0
32 A5 DQS0 5 32 A5 DQS0 5
MA6 125 J2 97 A_DQS0_1 MA6 125 J3 97 A_DQS0_1
4 MA7 A6 DM0_DQS9 A_SD0_4 MA7 A6 DM0_DQS9 A_SD0_4 C1362 C1363 C1364 C1365 4
29 A7 D4 94 29 A7 D4 94
MA8 122 95 A_SD0_5 MA8 122 95 A_SD0_5 0.01uF 0.01uF 0.01uF 0.01uF
27 A9 D6 98 27 A9 D6 98
MA10 141 99 A_SD0_7 MA10 141 99 A_SD0_7
MA11 A10 D7 A_SD1_0 MA11 A10 D7 A_SD1_0
118 A11 D8 12 118 A11 D8 12
MA12 115 13 A_SD1_1 MA12 115 13 A_SD1_1
A12 D9 A_SD1_2 A12 D9 A_SD1_2
D10 19 D10 19
MA13 59 20 A_SD1_3 MA13 59 20 A_SD1_3
MA14 BA0 D11 A_DQS1_0 MA14 BA0 D11 A_DQS1_0 C1366 C1367 C1368 C1369
52 BA1 DQS1 14 52 BA1 DQS1 14
107 A_DQS1_1 107 A_DQS1_1 0.01uF 0.01uF 0.01uF 0.01uF
DM1_DQS10 A_SD1_4 DM1_DQS10 A_SD1_4
13,18 CS_0 157 CS0_ D12 105 13,18 CS_1 157 CS0_ D12 105
158 106 A_SD1_5 158 106 A_SD1_5
13,18 CS_2 CS1_ D13 A_SD1_6 13,18 CS_3 CS1_ D13 A_SD1_6
D14 109 D14 109
154 110 A_SD1_7 154 110 A_SD1_7
13,17,18,19,20 RAS# RAS_ D15 A_SD2_0 13,17,18,19,20 RAS# RAS_ D15 A_SD2_0
13,17,18,19,20 CAS# 65 CAS_ D16 23 13,17,18,19,20 CAS# 65 CAS_ D16 23
63 24 A_SD2_1 63 24 A_SD2_1 C1370 C1371 C1372 C1373
13,17,18,19,20 WE# WE_ D17 A_SD2_2 13,17,18,19,20 WE# WE_ D17 A_SD2_2 0.01uF 0.01uF 0.01uF 0.01uF
D18 28 D18 28
137 31 A_SD2_3 137 31 A_SD2_3
24 CLK0_P CLK0_P D19 A_DQS2_0 24 CLK1_P CLK0_P D19 A_DQS2_0
24 CLK0_N 138 CLK0_N DQS2 25 24 CLK1_N 138 CLK0_N DQS2 25
119 A_DQS2_1 119 A_DQS2_1
DM2_DQS11 A_SD2_4 A_CKE DM2_DQS11 A_SD2_4
13,17,20 A_CKE 21 CLKE0 D20 114 21 CLKE0 D20 114
111 117 A_SD2_5 111 117 A_SD2_5
CLKE1 D21 A_SD2_6 CLKE1 D21 A_SD2_6
D22 121 D22 121
167 123 A_SD2_7 167 123 A_SD2_7 C1374 C1375 C1376 C1377
FETEN D23 A_SD3_0 FETEN D23 A_SD3_0 0.01uF 0.01uF 0.01uF 0.01uF
D24 33 D24 33
1 35 A_SD3_1 SSTLREF_D1 1 35 A_SD3_1
17,71 SSTLREF_D1 VREF D25 A_SD3_2 VCC25 VREF D25 A_SD3_2
D26 39 D26 39
184 40 A_SD3_3 184 40 A_SD3_3
VCC25 VDDSPD D27 VDDSPD D27
3 82 36 A_DQS3_0 82 36 A_DQS3_0 VCC25 3
VDDID DQS3 A_DQS3_1 VDDID DQS3 A_DQS3_1
DM3_DQS12 129 DM3_DQS12 129
92 126 A_SD3_4 MEMB_SCL 92 126 A_SD3_4
17,19,24,69 MEMB_SCL SCL D28 A_SD3_5 MEMB_SDA SCL D28 A_SD3_5
91 SDA D29 127 91 SDA D29 127
17,19,24,69 MEMB_SDA
181
182
SA0 D30 131
133
A_SD3_6
A_SD3_7
R1013 330 181
182
SA0 I2C ADD. - 2 D30 131
133
A_SD3_6
A_SD3_7
C1378
0.01uF
C1379
0.01uF
R1014 SA1 D31 A_SD4_0 R1015 4.7K SA1 D31 A_SD4_0
183 SA2 D32 53 183 SA2 D32 53
330 DIMM_WP#1 90 55 A_SD4_1 DIMM_WP#2 90 55 A_SD4_1
WP D33 A_SD4_2 WP D33 A_SD4_2
10 RESET_ D34 57 VCC25 10 RESET_ D34 57
VCC25
102
I2C ADD. - 0 D35 60
56
A_SD4_3
A_DQS4_0 102
D35 60
56
A_SD4_3
A_DQS4_0
18 DIMM_WP#1 NC1 DQS4 A_DQS4_1 DIMM_RST# NC1 DQS4 A_DQS4_1
101 NC2 DM4_DQS13 149 101 NC2 DM4_DQS13 149
9 146 A_SD4_4 9 146 A_SD4_4
17,18,19,65 DIMM_RST# NC4 D36 A_SD4_5 NC4 D36 A_SD4_5
173 NC5 D37 147 173 NC5 D37 147
163 150 A_SD4_6 163 150 A_SD4_6 22uF/10V/20% 22uF/10V/20% 22uF/10V/20%
18 DIMM_WP#2 CS3_NU D38 A_SD4_7 CS3_NU D38 A_SD4_7 + C1380 + C1381 + C1382
71 CS2_NU D39 151 71 CS2_NU D39 151
75 61 A_SD5_0 75 61 A_SD5_0
4.7K R1625 CLK2_N_DU D40 A_SD5_1 CLK2_N_DU D40 A_SD5_1
76 CLK2_P_DU D41 64 76 CLK2_P_DU D41 64
DIMM_WP#1 17 68 A_SD5_2 17 68 A_SD5_2
VCC25 CLK1_N_DU D42 CLK1_N_DU D42
16 69 A_SD5_3 16 69 A_SD5_3
CLK1_P_DU D43 A_DQS5_0 CLK1_P_DU D43 A_DQS5_0
113 BA2_NU DQS5 67 113 BA2_NU DQS5 67
DIMM_WP#2 103 159 A_DQS5_1 103 159 A_DQS5_1
A13_NU DM5_DQS14 A_SD5_4 VCC25 A13_NU DM5_DQS14 A_SD5_4
D44 153 D44 153
4.7K R1626 155 A_SD5_5 155 A_SD5_5 22uF/10V/20% 22uF/10V/20% 22uF/10V/20%
D45 A_SD5_6 D45 A_SD5_6 + C1383 + C1384 + C1385
168 VDD D46 161 168 VDD D46 161
148 162 A_SD5_7 148 162 A_SD5_7
VDD D47 A_SD6_0 VDD D47 A_SD6_0
VCC25 120 VDD D48 72 120 VDD D48 72
108 73 A_SD6_1 108 73 A_SD6_1
2 85 VDD D50 79 85 VDD D50 79 2
70 80 A_SD6_3 70 80 A_SD6_3
VDD D51 A_DQS6_0 VDD D51 A_DQS6_0
46 VDD DQS6 78 46 VDD DQS6 78
38 169 A_DQS6_1 38 169 A_DQS6_1
VDD DM6_DQS15 A_SD6_4 VDD DM6_DQS15 A_SD6_4
7 VDD D52 165 7 VDD D52 165
VCC25 166 A_SD6_5 VCC25 166 A_SD6_5
D53 A_SD6_6 D53 A_SD6_6
D54 170 D54 170
136 171 A_SD6_7 136 171 A_SD6_7
VDDQ D55 A_SD7_0 VDDQ D55 A_SD7_0
180 VDDQ D56 83 180 VDDQ D56 83
156 84 A_SD7_1 156 84 A_SD7_1
112 VDDQ D58 87 112 VDDQ D58 87
164 88 A_SD7_3 164 88 A_SD7_3
VDDQ D59 A_DQS7_0 VDDQ D59 A_DQS7_0
143 VDDQ DQS7 86 143 VDDQ DQS7 86
128 177 A_DQS7_1 128 177 A_DQS7_1
VDDQ DM7_DQS16 A_SD7_4 VDDQ DM7_DQS16 A_SD7_4
104 VDDQ D60 174 104 VDDQ D60 174
96 175 A_SD7_5 96 175 A_SD7_5
172 VDDQ D62 178 172 VDDQ D62 178
77 179 A_SD7_7 77 179 A_SD7_7
62 VDDQ ECC0 44 62 VDDQ ECC0 44
54 45 A_SD8_1 54 45 A_SD8_1
VDDQ ECC1 A_SD8_2 VDDQ ECC1 A_SD8_2
22 51 A_SD8_3 22 51 A_SD8_3
VDDQ ECC3 A_DQS8_0 VDDQ ECC3 A_DQS8_0
140 A_DQS8_1 140 A_DQS8_1
ECC4 134 ECC4 134
135 A_SD8_5 135 A_SD8_5
ECC5 A_SD8_6 ECC5 A_SD8_6
ECC6 142 ECC6 142
144 A_SD8_7 144 A_SD8_7
ECC7 ECC7
1 1
17,20,21 A_DQS0_[0..1] 17,20,21 A_SD0_[0..7]

17,20,21 A_DQS1_[0..1] 17,20,21 A_SD1_[0..7] Micro Star Restricted Secret
17,20,21 A_DQS2_[0..1] 17,20,21 A_SD2_[0..7] Title Rev
17,20,21 A_DQS3_[0..1] 17,20,21 A_SD3_[0..7] DIMM_CONN_1_&_2
17,20,21 A_DQS4_[0..1] 17,20,21 A_SD4_[0..7] Document Number 0A
17,20,21 A_DQS5_[0..1] 17,20,21 A_SD5_[0..7]
17,20,21 A_DQS6_[0..1] 17,20,21 A_SD6_[0..7]
17,20,21 A_DQS7_[0..1] 17,20,21 A_SD7_[0..7] MICRO-STAR INT'L CO.,LTD. Last Revision Date:
17,20,21 A_DQS8_[0..1] 17,20,21 A_SD8_[0..7] No. 69, Li-De St, Jung-He City,
A B C D E
www.vinafix.vn
A B C D E
24 CLK3_P VCC25
13,16,18,19,20 MA[0..14] 24 CLK3_N
100
116
124
132
139
145
176
160
152
100
116
124
132
139
145
176
160
152
C1348 C1349
11
18
26
34
42
50
58
66
74
81
89
93
11
18
26
34
42
50
58
66
74
81
89
93
13,19 CS_5
3
13,19 CS_7 0.01uF 0.01uF
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MA0 48 MA0 48
MA1 A0 A_SD0_0 MA1 A0 A_SD0_0
43 A1 D0 2 43 A1 D0 2
MA2 41 4 A_SD0_1 MA2 41 4 A_SD0_1
130 A3 D2 6 130 A3 D2 6
MA4 37 8 A_SD0_3 MA4 37 8 A_SD0_3
MA5 A4 D3 A_DQS0_0 MA5 A4 D3 A_DQS0_0 C1353
32 A5 DQS0 5 32 A5 DQS0 5
MA6 125 J4 97 A_DQS0_1 MA6 125 J43 97 A_DQS0_1 C1352
MA7 A6 DM0_DQS9 A_SD0_4 MA7 A6 DM0_DQS9 A_SD0_4
29 A7 D4 94 29 A7 D4 94
4 MA8 122 95 A_SD0_5 MA8 122 95 A_SD0_5 0.01uF 0.01uF 4
27 A9 D6 98 27 A9 D6 98
MA10 141 99 A_SD0_7 MA10 141 99 A_SD0_7
MA11 A10 D7 A_SD1_0 MA11 A10 D7 A_SD1_0
118 A11 D8 12 118 A11 D8 12
MA12 115 13 A_SD1_1 MA12 115 13 A_SD1_1
A12 D9 A_SD1_2 A12 D9 A_SD1_2
D10 19 D10 19
59 20 A_SD1_3 MA13 59 20 A_SD1_3
13,16,18,19,20 MA13 BA0 D11 A_DQS1_0 MA14 BA0 D11 A_DQS1_0
52 BA1 DQS1 14 52 BA1 DQS1 14
13,16,18,19,20 MA14 A_DQS1_1 A_DQS1_1 C1351
DM1_DQS10 107 DM1_DQS10 107
157 105 A_SD1_4 CS_5 157 105 A_SD1_4 C1350
13,19 CS_4 CS0_ D12 A_SD1_5 CS_7 CS0_ D12 A_SD1_5
13,19 CS_6 158 CS1_ D13 106 158 CS1_ D13 106
109 A_SD1_6 109 A_SD1_6 0.01uF
D14 A_SD1_7 RAS# D14 A_SD1_7 0.01uF
154 RAS_ D15 110 154 RAS_ D15 110
13,16,18,19,20 RAS# A_SD2_0 CAS# A_SD2_0
13,16,18,19,20 CAS# 65 CAS_ D16 23 65 CAS_ D16 23
63 24 A_SD2_1 WE# 63 24 A_SD2_1
13,16,18,19,20 WE# WE_ D17 A_SD2_2 WE_ D17 A_SD2_2
D18 28 D18 28
137 31 A_SD2_3 CLK3_P 137 31 A_SD2_3
24 CLK2_P CLK0_P D19 A_DQS2_0 CLK3_N CLK0_P D19 A_DQS2_0 C1347
138 CLK0_N DQS2 25 138 CLK0_N DQS2 25
24 CLK2_N A_DQS2_1 A_DQS2_1 C1346
DM2_DQS11 119 DM2_DQS11 119
21 114 A_SD2_4 A_CKE 21 114 A_SD2_4
13,16,20 A_CKE CLKE0 D20 A_SD2_5 CLKE0 D20 A_SD2_5
111 CLKE1 D21 117 111 CLKE1 D21 117
121 A_SD2_6 121 A_SD2_6 0.01uF 0.01uF
D22 A_SD2_7 D22 A_SD2_7
167 FETEN D23 123 167 FETEN D23 123
33 A_SD3_0 33 A_SD3_0
D24 A_SD3_1 SSTLREF_D1 D24 A_SD3_1
16,71 SSTLREF_D1 1 VREF D25 35 1 VREF D25 35
39 A_SD3_2 39 A_SD3_2
D26 A_SD3_3 D26 A_SD3_3
VCC25 184 VDDSPD D27 40 VCC25 184 VDDSPD D27 40
82 36 A_DQS3_0 82 36 A_DQS3_0
VDDID DQS3 A_DQS3_1 VDDID DQS3 A_DQS3_1
3
DM3_DQS12 129 DM3_DQS12 129 3
92 126 A_SD3_4 MEMB_SCL 92 126 A_SD3_4
16,19,24,69 MEMB_SCL SCL D28 A_SD3_5 MEMB_SDA SCL D28 A_SD3_5
16,19,24,69 MEMB_SDA 91 SDA D29 127 91 SDA D29 127
181 131 A_SD3_6 181 131 A_SD3_6
R1011 330 SA0 D30 A_SD3_7 R1344 330 SA0 D30 A_SD3_7
182 SA1 D31 133 182 SA1 D31 133
VCC25
R1012
4.7K
183
90
SA2 I2C ADD. - 4 D32 53
55
A_SD4_0
A_SD4_1 4.7K
183
90
SA2 I2C ADD. - 6 D32 53
55
A_SD4_0
A_SD4_1
WP D33 A_SD4_2 R1345 WP D33 A_SD4_2
10 RESET_ D34 57 10 RESET_ D34 57
60 A_SD4_3 60 A_SD4_3
19 DIMM_WP#3 D35 VCC25 D35
102 56 A_DQS4_0 102 56 A_DQS4_0
NC1 DQS4 A_DQS4_1 DIMM_WP#4 NC1 DQS4 A_DQS4_1
101 NC2 DM4_DQS13 149 101 NC2 DM4_DQS13 149
9 146 A_SD4_4 9 146 A_SD4_4
NC4 D36 A_SD4_5 DIMM_RST# NC4 D36 A_SD4_5
16,18,19,65 DIMM_RST# 173 NC5 D37 147 173 NC5 D37 147
163 150 A_SD4_6 163 150 A_SD4_6
CS3_NU D38 A_SD4_7 CS3_NU D38 A_SD4_7
71 CS2_NU D39 151 71 CS2_NU D39 151
75 61 A_SD5_0 75 61 A_SD5_0
19 DIMM_WP#4 CLK2_N_DU D40 A_SD5_1 CLK2_N_DU D40 A_SD5_1
76 CLK2_P_DU D41 64 76 CLK2_P_DU D41 64
17 68 A_SD5_2 17 68 A_SD5_2
R1627 4.7K DIMM_WP#3 CLK1_N_DU D42 A_SD5_3 CLK1_N_DU D42 A_SD5_3
VCC25 16 CLK1_P_DU D43 69 16 CLK1_P_DU D43 69
113 67 A_DQS5_0 113 67 A_DQS5_0
R1628 4.7K DIMM_WP#4 BA2_NU DQS5 A_DQS5_1 BA2_NU DQS5 A_DQS5_1
103 A13_NU DM5_DQS14 159 103 A13_NU DM5_DQS14 159
153 A_SD5_4 VCC25 153 A_SD5_4
D44 A_SD5_5 D44 A_SD5_5
D45 155 D45 155
168 161 A_SD5_6 168 161 A_SD5_6
148 VDD D47 162 148 VDD D47 162
120 72 A_SD6_0 120 72 A_SD6_0
VCC25 VDD D48 VDD D48
108 73 A_SD6_1 108 73 A_SD6_1
85 VDD D50 79 85 VDD D50 79
2 70 80 A_SD6_3 70 80 A_SD6_3 2
VDD D51 A_DQS6_0 VDD D51 A_DQS6_0
46 VDD DQS6 78 46 VDD DQS6 78
38 169 A_DQS6_1 38 169 A_DQS6_1
VDD DM6_DQS15 A_SD6_4 VDD DM6_DQS15 A_SD6_4
7 VDD D52 165 7 VDD D52 165
166 A_SD6_5 VCC25 166 A_SD6_5
D53 A_SD6_6 D53 A_SD6_6
D54 170 D54 170
136 171 A_SD6_7 136 171 A_SD6_7
180 VDDQ D56 83 180 VDDQ D56 83
156 84 A_SD7_1 156 84 A_SD7_1
112 VDDQ D58 87 112 VDDQ D58 87
164 88 A_SD7_3 164 88 A_SD7_3
VDDQ D59 A_DQS7_0 VDDQ D59 A_DQS7_0
128 177 A_DQS7_1 128 177 A_DQS7_1
VDDQ DM7_DQS16 A_SD7_4 VDDQ DM7_DQS16 A_SD7_4
104 VDDQ D60 174 104 VDDQ D60 174
96 175 A_SD7_5 96 175 A_SD7_5
172 VDDQ D62 178 172 VDDQ D62 178
77 179 A_SD7_7 77 179 A_SD7_7
54 45 A_SD8_1 54 45 A_SD8_1
VDDQ ECC1 A_SD8_2 VDDQ ECC1 A_SD8_2
22 51 A_SD8_3 22 51 A_SD8_3
VDDQ ECC3 A_DQS8_0 VDDQ ECC3 A_DQS8_0
140 A_DQS8_1 140 A_DQS8_1
16,20,21 A_SD1_[0..7] ECC4 134 ECC4 134
135 A_SD8_5 135 A_SD8_5
16,20,21 A_SD0_[0..7] ECC5 A_SD8_6 ECC5 A_SD8_6
ECC6 142 ECC6 142
16,20,21 A_SD2_[0..7] A_SD8_7 A_SD8_7
ECC7 144 ECC7 144
16,20,21 A_SD3_[0..7]
16,20,21 A_SD4_[0..7]
1 16,20,21 A_SD5_[0..7] VCC25 1
16,20,21 A_SD6_[0..7]
16,20,21 A_SD7_[0..7] VCC25 VCC25
16,20,21 A_SD8_[0..7]
16,20,21 A_DQS0_[0..1] Micro Star Restricted Secret
16,20,21 A_DQS1_[0..1] 22uF/10V/20% 22uF/10V/20% 22uF/10V/20% Title Rev
16,20,21 A_DQS2_[0..1] + C1355 + C1356 + C1357 0.01uF DIMM_CONN_3_&_4
16,20,21 A_DQS3_[0..1] C1354 Document Number 0A
16,20,21 A_DQS4_[0..1] 0.01uF C1400
16,20,21 A_DQS5_[0..1]
16,20,21 A_DQS6_[0..1] MICRO-STAR INT'L CO.,LTD. Last Revision Date:
16,20,21 A_DQS7_[0..1] No. 69, Li-De St, Jung-He City,
16,20,21 A_DQS8_[0..1] Taipei Hsien, Taiwan Sheet
A B C D E
www.vinafix.vn
A B C D E
VCC25
13,16,17,19,20 MA[0..14]
100
116
124
132
139
145
176
160
152
100
116
124
132
139
145
176
160
152
11
18
26
34
42
50
58
66
74
81
89
93
11
18
26
34
42
50
58
66
74
81
89
93
3
3
C1318 C1319 C1320 C1321
0.01uF 0.01uF 0.01uF 0.01uF
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MA0 48 MA0 48
MA1 A0 B_SD0_0 MA1 A0 B_SD0_0
43 A1 D0 2 43 A1 D0 2
MA2 41 4 B_SD0_1 MA2 41 4 B_SD0_1
MA3 A2 D1 B_SD0_2 MA3 A2 D1 B_SD0_2
130 A3 D2 6 130 A3 D2 6
MA4 37 8 B_SD0_3 MA4 37 8 B_SD0_3
MA5 A4 D3 B_DQS0_0 MA5 A4 D3 B_DQS0_0
32 A5 DQS0 5 32 A5 DQS0 5
MA6 125 J6 97 B_DQS0_1 MA6 125 J7 97 B_DQS0_1
4 MA7 A6 DM0_DQS9 B_SD0_4 MA7 A6 DM0_DQS9 B_SD0_4 C1322 C1323 C1324 C1325 4
29 A7 D4 94 29 A7 D4 94
MA8 122 95 B_SD0_5 MA8 122 95 B_SD0_5 0.01uF 0.01uF 0.01uF 0.01uF
27 A9 D6 98 27 A9 D6 98
MA10 141 99 B_SD0_7 MA10 141 99 B_SD0_7
MA11 A10 D7 B_SD1_0 MA11 A10 D7 B_SD1_0
118 A11 D8 12 118 A11 D8 12
MA12 115 13 B_SD1_1 MA12 115 13 B_SD1_1
A12 D9 B_SD1_2 A12 D9 B_SD1_2
D10 19 D10 19
MA13 59 20 B_SD1_3 MA13 59 20 B_SD1_3
MA14 BA0 D11 B_DQS1_0 MA14 BA0 D11 B_DQS1_0 C1326 C1327 C1328 C1329
52 BA1 DQS1 14 52 BA1 DQS1 14
107 B_DQS1_1 107 B_DQS1_1 0.01uF 0.01uF 0.01uF 0.01uF
DM1_DQS10 B_SD1_4 DM1_DQS10 B_SD1_4
13,16 CS_0 157 CS0_ D12 105 13,16 CS_1 157 CS0_ D12 105
158 106 B_SD1_5 158 106 B_SD1_5
13,16 CS_2 CS1_ D13 B_SD1_6 13,16 CS_3 CS1_ D13 B_SD1_6
D14 109 D14 109
154 110 B_SD1_7 RAS# 154 110 B_SD1_7
13,16,17,19,20 RAS# RAS_ D15 B_SD2_0 CAS# RAS_ D15 B_SD2_0
13,16,17,19,20 CAS# 65 CAS_ D16 23 65 CAS_ D16 23
63 24 B_SD2_1 WE# 63 24 B_SD2_1 C1330 C1331 C1332 C1333
13,16,17,19,20 WE# WE_ D17 B_SD2_2 WE_ D17 B_SD2_2 0.01uF 0.01uF 0.01uF 0.01uF
D18 28 D18 28
137 31 B_SD2_3 137 31 B_SD2_3
24 CLK4_P CLK0_P D19 B_DQS2_0 24 CLK5_P CLK0_P D19 B_DQS2_0
24 CLK4_N 138 CLK0_N DQS2 25 24 CLK5_N 138 CLK0_N DQS2 25
119 B_DQS2_1 119 B_DQS2_1
DM2_DQS11 B_SD2_4 B_CKE DM2_DQS11 B_SD2_4
13,19,20 B_CKE 21 CLKE0 D20 114 21 CLKE0 D20 114
111 117 B_SD2_5 111 117 B_SD2_5
CLKE1 D21 B_SD2_6 CLKE1 D21 B_SD2_6
D22 121 D22 121
167 123 B_SD2_7 167 123 B_SD2_7 C1334 C1335 C1336 C1337
FETEN D23 B_SD3_0 FETEN D23 B_SD3_0 0.01uF 0.01uF 0.01uF 0.01uF
D24 33 D24 33
1 35 B_SD3_1 SSTLREF_D2 1 35 B_SD3_1
19,71 SSTLREF_D2 VREF D25 B_SD3_2 VREF D25 B_SD3_2
D26 39 D26 39
184 40 B_SD3_3 184 40 B_SD3_3
VCC25 VDDSPD D27 VCC25 VDDSPD D27
3 82 36 B_DQS3_0 82 36 B_DQS3_0 VCC25 3
VDDID DQS3 B_DQS3_1 VDDID DQS3 B_DQS3_1
DM3_DQS12 129 DM3_DQS12 129
92 126 B_SD3_4 MEMA_SCL 92 126 B_SD3_4
69 MEMA_SCL SCL D28 B_SD3_5 MEMA_SDA SCL D28 B_SD3_5
91 SDA D29 127 91 SDA D29 127
69 MEMA_SDA B_SD3_6 B_SD3_6 C1338 C1339
181 SA0 D30 131 VCC25 181 SA0 D30 131
R1010 182
183
SA1 I2C ADD. - 0 D31 133
53
B_SD3_7
B_SD4_0
R1007 4.7K
R1009 330
182
183
SA1 I2C ADD. - 2 D31 133
53
B_SD3_7
B_SD4_0
0.01uF 0.01uF
330 SA2 D32 B_SD4_1 SA2 D32 B_SD4_1

90 WP D33 55 90 WP D33 55
10 57 B_SD4_2 10 57 B_SD4_2
RESET_ D34 B_SD4_3 DIMM_WP#2 RESET_ D34 B_SD4_3
D35 60 D35 60
102 56 B_DQS4_0 102 56 B_DQS4_0
NC1 DQS4 B_DQS4_1 DIMM_RST# NC1 DQS4 B_DQS4_1
101 NC2 DM4_DQS13 149 101 NC2 DM4_DQS13 149
9 146 B_SD4_4 9 146 B_SD4_4
16 DIMM_WP#1 NC4 D36 B_SD4_5 NC4 D36 B_SD4_5
173 NC5 D37 147 173 NC5 D37 147
163 150 B_SD4_6 163 150 B_SD4_6
CS3_NU D38 B_SD4_7 CS3_NU D38 B_SD4_7
16,17,19,65 DIMM_RST# 71 CS2_NU D39 151 71 CS2_NU D39 151
75 61 B_SD5_0 75 61 B_SD5_0
CLK2_N_DU D40 B_SD5_1 CLK2_N_DU D40 B_SD5_1
76 CLK2_P_DU D41 64 76 CLK2_P_DU D41 64
17 68 B_SD5_2 17 68 B_SD5_2
16 DIMM_WP#2 CLK1_N_DU D42 B_SD5_3 CLK1_N_DU D42 B_SD5_3
16 CLK1_P_DU D43 69 16 CLK1_P_DU D43 69
113 67 B_DQS5_0 113 67 B_DQS5_0
BA2_NU DQS5 B_DQS5_1 BA2_NU DQS5 B_DQS5_1
103 A13_NU DM5_DQS14 159 103 A13_NU DM5_DQS14 159
VCC25 153 B_SD5_4 VCC25 153 B_SD5_4
D44 B_SD5_5 D44 B_SD5_5
D45 155 D45 155
168 161 B_SD5_6 168 161 B_SD5_6
VDD D46 B_SD5_7 VDD D46 B_SD5_7
148 VDD D47 162 148 VDD D47 162
120 72 B_SD6_0 120 72 B_SD6_0
108 VDD D49 73 108 VDD D49 73
2 85 79 B_SD6_2 85 79 B_SD6_2 2
70 VDD D51 80 70 VDD D51 80
46 78 B_DQS6_0 46 78 B_DQS6_0
VDD DQS6 B_DQS6_1 VDD DQS6 B_DQS6_1
38 VDD DM6_DQS15 169 38 VDD DM6_DQS15 169
7 165 B_SD6_4 7 165 B_SD6_4
VCC25 VDD D52 B_SD6_5 VCC25 VDD D52 B_SD6_5
D53 166 D53 166
170 B_SD6_6 170 B_SD6_6
D54 B_SD6_7 D54 B_SD6_7
136 VDDQ D55 171 136 VDDQ D55 171
180 83 B_SD7_0 180 83 B_SD7_0
VDDQ D56 B_SD7_1 VDDQ D56 B_SD7_1
156 VDDQ D57 84 156 VDDQ D57 84
112 87 B_SD7_2 112 87 B_SD7_2
164 VDDQ D59 88 164 VDDQ D59 88
143 86 B_DQS7_0 143 86 B_DQS7_0
VDDQ DQS7 B_DQS7_1 VDDQ DQS7 B_DQS7_1
128 VDDQ DM7_DQS16 177 128 VDDQ DM7_DQS16 177
104 174 B_SD7_4 104 174 B_SD7_4
96 VDDQ D61 175 96 VDDQ D61 175
172 178 B_SD7_6 172 178 B_SD7_6
77 VDDQ D63 179 77 VDDQ D63 179
62 44 B_SD8_0 62 44 B_SD8_0
VDDQ ECC0 B_SD8_1 VDDQ ECC0 B_SD8_1
30 49 B_SD8_2 30 49 B_SD8_2
VDDQ ECC2 B_SD8_3 VDDQ ECC2 B_SD8_3
15 47 B_DQS8_0 15 47 B_DQS8_0
VDDQ DQS8 B_DQS8_1 VDDQ DQS8 B_DQS8_1
DM9_DQS17 140 DM9_DQS17 140
134 B_SD8_4 134 B_SD8_4
ECC4 B_SD8_5 ECC4 B_SD8_5
ECC5 135 ECC5 135
142 B_SD8_6 142 B_SD8_6
ECC6 B_SD8_7 ECC6 B_SD8_7
ECC7 144 ECC7 144
1 1
19,20,21 B_SD0_[0..7]
19,20,21 B_SD1_[0..7] 19,20,21 B_DQS0_[0..1]
19,20,21 B_SD2_[0..7] 19,20,21 B_DQS1_[0..1] Micro Star Restricted Secret
19,20,21 B_SD3_[0..7] 19,20,21 B_DQS2_[0..1] Title Rev
19,20,21 B_SD4_[0..7] 19,20,21 B_DQS3_[0..1] DIMM_CONN_5_&_6
19,20,21 B_SD5_[0..7] 19,20,21 B_DQS4_[0..1] Document Number 0A
19,20,21 B_SD6_[0..7] 19,20,21 B_DQS5_[0..1]
19,20,21 B_SD7_[0..7] 19,20,21 B_DQS6_[0..1]
19,20,21 B_SD8_[0..7] 19,20,21 B_DQS7_[0..1] MICRO-STAR INT'L CO.,LTD. Last Revision Date:
19,20,21 B_DQS8_[0..1] No. 69, Li-De St, Jung-He City,
A B C D E
www.vinafix.vn
A B C D E
24 CLK7_P VCC25
24 CLK7_N
100
116
124
132
139
145
176
160
152
11
18
26
34
42
50
58
66
74
81
89
93
13,17 CS_7
3
C1308 C1309
13,16,17,18,20 MA[0..14] 13,17 CS_5
100
116
124
132
139
145
176
160
152
0.01uF 0.01uF
11
18
26
34
42
50
58
66
74
81
89
93
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
MA0 48
MA1 A0 B_SD0_0
43 2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MA0 MA2 A1 D0 B_SD0_1
48 A0 41 A2 D1 4
MA1 43 2 B_SD0_0 MA3 130 6 B_SD0_2
41 A2 D1 4 37 A4 D3 8
MA3 130 6 B_SD0_2 MA5 32 5 B_DQS0_0
MA4 A3 D2 B_SD0_3 MA6 A5 J44 DQS0 B_DQS0_1
37 A4 D3 8 125 A6 DM0_DQS9 97
MA5 32 5 B_DQS0_0 MA7 29 94 B_SD0_4 C1312 C1313
4 MA6 A5 J8 DQS0 B_DQS0_1 MA8 A7 D4 B_SD0_5 0.01uF 0.01uF 4
125 A6 DM0_DQS9 97 122 A8 D5 95
MA7 29 94 B_SD0_4 MA9 27 98 B_SD0_6
MA8 A7 D4 B_SD0_5 MA10 A9 D6 B_SD0_7
122 A8 D5 95 141 A10 D7 99
MA9 27 98 B_SD0_6 MA11 118 12 B_SD1_0
MA10 A9 D6 B_SD0_7 MA12 A11 D8 B_SD1_1
141 A10 D7 99 115 A12 D9 13
MA11 118 12 B_SD1_0 19 B_SD1_2
MA12 A11 D8 B_SD1_1 MA13 D10 B_SD1_3
115 A12 D9 13 59 BA0 D11 20
19 B_SD1_2 MA14 52 14 B_DQS1_0
D10 B_SD1_3 BA1 DQS1 B_DQS1_1
13,16,17,18,20 MA13 59 BA0 D11 20 DM1_DQS10 107
52 14 B_DQS1_0 CS_5 157 105 B_SD1_4
13,16,17,18,20 MA14 BA1 DQS1 B_DQS1_1 CS_7 CS0_ D12 B_SD1_5 C1306 C1307
DM1_DQS10 107 158 CS1_ D13 106
157 105 B_SD1_4 109 B_SD1_6 0.01uF 0.01uF
13,17 CS_4 CS0_ D12 B_SD1_5 RAS# D14 B_SD1_7
158 CS1_ D13 106 154 RAS_ D15 110
13,17 CS_6 B_SD1_6 CAS# B_SD2_0
D14 109 65 CAS_ D16 23
154 110 B_SD1_7 WE# 63 24 B_SD2_1
13,16,17,18,20 RAS# RAS_ D15 B_SD2_0 WE_ D17 B_SD2_2
13,16,17,18,20 CAS# 65 CAS_ D16 23 D18 28
63 24 B_SD2_1 CLK7_P 137 31 B_SD2_3
13,16,17,18,20 WE# WE_ D17 B_SD2_2 CLK7_N CLK0_P D19 B_DQS2_0
D18 28 138 CLK0_N DQS2 25
137 31 B_SD2_3 119 B_DQS2_1
24 CLK6_P CLK0_P D19 B_DQS2_0 B_CKE DM2_DQS11 B_SD2_4
24 CLK6_N 138 CLK0_N DQS2 25 21 CLKE0 D20 114
119 B_DQS2_1 111 117 B_SD2_5 C1310 C1311
DM2_DQS11 B_SD2_4 CLKE1 D21 B_SD2_6 0.01uF 0.01uF
21 CLKE0 D20 114 D22 121
13,18,20 B_CKE B_SD2_5 B_SD2_7
111 CLKE1 D21 117 167 FETEN D23 123
121 B_SD2_6 33 B_SD3_0
D22 B_SD2_7 SSTLREF_D2 D24 B_SD3_1
167 FETEN D23 123 1 VREF D25 35
33 B_SD3_0 39 B_SD3_2
18,71 SSTLREF_D2 D24 B_SD3_1 D26 B_SD3_3
1 VREF D25 35 VCC25 184 VDDSPD D27 40
39 B_SD3_2 82 36 B_DQS3_0
D26 B_SD3_3 VDDID DQS3 B_DQS3_1
3
VCC25 184 VDDSPD D27 40 DM3_DQS12 129 3
82 36 B_DQS3_0 MEMA_SCL 92 126 B_SD3_4
VDDID DQS3 B_DQS3_1 MEMA_SDA SCL D28 B_SD3_5
DM3_DQS12 129 91 SDA D29 127
16,17,24,69 MEMB_SCL
MEMA_SCL
MEMA_SDA
92
91
SCL D28 126
127
B_SD3_4
B_SD3_5 R1346
181
182
SA0 I2C ADD. - 6 D30 131
133
B_SD3_6
B_SD3_7 C1544 C1545
16,17,24,69 MEMB_SDA SDA D29 SA1 D31
R1005 330
181
182
SA0 I2C ADD. - 4 D30 131
133
B_SD3_6
B_SD3_7
330 183
90
SA2 D32 53
55
B_SD4_0
B_SD4_1
0.01uF 0.01uF
SA1 D31 VCC25 WP D33
183 53 B_SD4_0 R1347 10 57 B_SD4_2
SA2 D32 B_SD4_1 4.7K RESET_ D34 B_SD4_3
VCC25 90 WP D33 55 D35 60
R1006 4.7K 10 57 B_SD4_2 102 56 B_DQS4_0
RESET_ D34 B_SD4_3 NC1 DQS4 B_DQS4_1
D35 60 101 NC2 DM4_DQS13 149
102 56 B_DQS4_0 DIMM_WP#4 9 146 B_SD4_4
NC1 DQS4 B_DQS4_1 NC4 D36 B_SD4_5
17 DIMM_WP#3 101 NC2 DM4_DQS13 149 173 NC5 D37 147
9 146 B_SD4_4 DIMM_RST# 163 150 B_SD4_6
NC4 D36 B_SD4_5 CS3_NU D38 B_SD4_7 C1546 C1547
173 NC5 D37 147 71 CS2_NU D39 151
163 150 B_SD4_6 75 61 B_SD5_0 0.01uF 0.01uF
16,17,18,65 DIMM_RST# CS3_NU D38 B_SD4_7 CLK2_N_DU D40 B_SD5_1
71 CS2_NU D39 151 76 CLK2_P_DU D41 64
75 61 B_SD5_0 17 68 B_SD5_2
CLK2_N_DU D40 B_SD5_1 CLK1_N_DU D42 B_SD5_3
76 CLK2_P_DU D41 64 16 CLK1_P_DU D43 69
17 DIMM_WP#4 B_SD5_2 B_DQS5_0
17 CLK1_N_DU D42 68 113 BA2_NU DQS5 67
16 69 B_SD5_3 103 159 B_DQS5_1
CLK1_P_DU D43 B_DQS5_0 VCC25 A13_NU DM5_DQS14 B_SD5_4
113 BA2_NU DQS5 67 D44 153
103 159 B_DQS5_1 155 B_SD5_5
VCC25 A13_NU DM5_DQS14 B_SD5_4 D45 B_SD5_6
D44 153 168 VDD D46 161
155 B_SD5_5 148 162 B_SD5_7
D45 B_SD5_6 VDD D47 B_SD6_0
168 VDD D46 161 120 VDD D48 72
148 162 B_SD5_7 108 73 B_SD6_1
120 VDD D48 72 85 VDD D50 79
2 108 73 B_SD6_1 70 80 B_SD6_3 2
VDD D49 B_SD6_2 VDD D51 B_DQS6_0
85 VDD D50 79 46 VDD DQS6 78
70 80 B_SD6_3 38 169 B_DQS6_1
VDD D51 B_DQS6_0 VDD DM6_DQS15 B_SD6_4
46 VDD DQS6 78 7 VDD D52 165
38 169 B_DQS6_1 VCC25 166 B_SD6_5
VDD DM6_DQS15 B_SD6_4 D53 B_SD6_6
7 VDD D52 165 D54 170
VCC25 166 B_SD6_5 136 171 B_SD6_7
D53 B_SD6_6 VDDQ D55 B_SD7_0
D54 170 180 VDDQ D56 83
136 171 B_SD6_7 156 84 B_SD7_1
180 VDDQ D56 83 112 VDDQ D58 87
156 84 B_SD7_1 164 88 B_SD7_3
VDDQ D57 B_SD7_2 VDDQ D59 B_DQS7_0
112 VDDQ D58 87 143 VDDQ DQS7 86
164 88 B_SD7_3 128 177 B_DQS7_1
VDDQ D59 B_DQS7_0 VDDQ DM7_DQS16 B_SD7_4
143 VDDQ DQS7 86 104 VDDQ D60 174
128 177 B_DQS7_1 96 175 B_SD7_5
VDDQ DM7_DQS16 B_SD7_4 VDDQ D61 B_SD7_6
104 VDDQ D60 174 172 VDDQ D62 178
96 175 B_SD7_5 77 179 B_SD7_7
172 VDDQ D62 178 62 VDDQ ECC0 44
77 179 B_SD7_7 54 45 B_SD8_1
VDDQ D63 B_SD8_0 VDDQ ECC1 B_SD8_2
54 45 B_SD8_1 22 51 B_SD8_3
VDDQ ECC1 B_SD8_2 VDDQ ECC3 B_DQS8_0
30 VDDQ ECC2 49 15 VDDQ DQS8 47
22 51 B_SD8_3 140 B_DQS8_1
VDDQ ECC3 B_DQS8_0 DM9_DQS17 B_SD8_4
15 VDDQ DQS8 47 ECC4 134
140 B_DQS8_1 135 B_SD8_5
18,20,21 B_SD0_[0..7] DM9_DQS17 B_SD8_4 ECC5 B_SD8_6
ECC4 134 ECC6 142
18,20,21 B_SD1_[0..7] B_SD8_5 B_SD8_7
ECC5 135 ECC7 144
18,20,21 B_SD2_[0..7] B_SD8_6
18,20,21 B_SD3_[0..7] ECC6 142
144 B_SD8_7
1 18,20,21 B_SD4_[0..7] ECC7 VCC25 1
18,20,21 B_SD5_[0..7]
18,20,21 B_SD6_[0..7]
18,20,21 B_SD7_[0..7]
18,20,21 B_SD8_[0..7]
VCC25 VCC25
18,20,21 B_DQS0_[0..1] 22uF/10V/20% 22uF/10V/20% 22uF/10V/20% 22uF/10V/20% Title Rev
18,20,21 B_DQS1_[0..1] + + + + DIMM_CONN_7_&_8
18,20,21 B_DQS2_[0..1] C1548 C1549 Document Number 0A
18,20,21 B_DQS3_[0..1] C1314 C1550 C1315 C1316
18,20,21 B_DQS4_[0..1]
18,20,21 B_DQS5_[0..1]
0.01uF 0.01uF MICRO-STAR INT'L CO.,LTD. Last Revision Date:
18,20,21 B_DQS6_[0..1] No. 69, Li-De St, Jung-He City,
18,20,21 B_DQS7_[0..1] Taipei Hsien, Taiwan Sheet
18,20,21 B_DQS8_[0..1] http://www.msi.com.tw 19 of 75
A B C D E
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A B C D E
A_SD2_5 RP1 1 RP15R 8 R_A_SD2_5 A_SD4_0 RP42 4 5 R_A_SD4_0

A_SD2_1 2 7 R_A_SD2_1 A_SD4_4 3 6 R_A_SD4_4 B_SD1_5 8 RP5 1 R_B_SD1_5 B_SD4_0 RP46 5 4 R_B_SD4_0
A_SD2_4 3 6 R_A_SD2_4 A_SD4_1 2 7 R_A_SD4_1 B_SD1_1 7 2 R_B_SD1_1 B_SD4_4 RP15R 6 3 R_B_SD4_4
A_SD2_0 4 5 R_A_SD2_0 A_SD4_5 1 RP15R 8 R_A_SD4_5 B_SD1_4 6 3 R_B_SD1_4 B_SD4_5 7 2 R_B_SD4_5
A_SD2_7 RP3 1 RP15R 8 R_A_SD2_7 A_SD4_2 4 5 R_A_SD4_2 B_SD1_0 5 RP15R 4 R_B_SD1_0 B_SD4_1 8 1 R_B_SD4_1
A_SD2_3 2 7 R_A_SD2_3 A_SD4_6 RP44 3 6 R_A_SD4_6 B_SD1_3 8 RP7 1 R_B_SD1_3 B_SD4_2 RP48 5 4 R_B_SD4_2
A_SD2_2 4 5 R_A_SD2_2 A_SD4_7 1 8 R_A_SD4_7 B_SD1_7 6 3 R_B_SD1_7 B_SD4_7 7 2 R_B_SD4_7
A_SD1_5 RP9 1 RP15R 8 R_A_SD1_5 A_SD5_5 RP50 1 RP15R 8 R_A_SD5_5 B_SD1_6 5 4 R_B_SD1_6 B_SD4_3 8 1 R_B_SD4_3
A_SD1_4 2 7 R_A_SD1_4 A_SD5_1 2 7 R_A_SD5_1 B_SD0_1 RP13 8 RP15R 1 R_B_SD0_1
A_SD1_1 3 6 R_A_SD1_1 A_SD5_4 3 RP15R 6 R_A_SD5_4 B_SD0_5 7 2 R_B_SD0_5 B_SD6_0 RP54 5 4 R_B_SD5_0
4 A_SD1_2 RP11 1 RP15R 8 R_A_SD1_2 A_SD5_6 RP52 1 8 R_A_SD5_6 B_SD0_0 5 4 R_B_SD0_0 B_SD6_1 7 2 R_B_SD5_1 4
A_SD1_3 2 7 R_A_SD1_3 A_SD5_7 RP15R 2 7 R_A_SD5_7 B_SD0_2 RP15 5 RP15R 4 R_B_SD0_2 B_SD6_5 8 1 R_B_SD5_5
A_SD1_7 3 6 R_A_SD1_7 A_SD5_2 3 6 R_A_SD5_2 B_SD0_6 6 3 R_B_SD0_6 B_SD6_6 RP56 5 4 R_B_SD5_6
A_SD0_5 RP17 1 RP15R 8 R_A_SD0_5 A_SD6_4 RP58 1 8 R_A_SD6_4 B_SD0_3 8 1 R_B_SD0_3 B_SD6_7 7 2 R_B_SD5_7
A_SD0_1 2 7 R_A_SD0_1 A_SD6_5 RP15R 2 7 R_A_SD6_5 B_SD2_5 RP21 8 1 R_B_SD2_5 B_SD6_3 8 1 R_B_SD5_3
A_SD0_4 3 6 R_A_SD0_4 A_SD6_1 3 6 R_A_SD6_1 B_SD2_1 7 2 R_B_SD2_1
A_SD0_7 RP19 1 RP15R 8 R_A_SD0_7 A_SD6_3 RP60 1 8 R_A_SD6_3 B_SD2_4 5 RP15R 4 R_B_SD2_4 B_SD7_0 RP15R 6 3 R_B_SD7_0
A_SD0_3 2 7 R_A_SD0_3 A_SD6_7 RP15R 2 7 R_A_SD6_7 B_SD2_7 RP23 8 1 R_B_SD2_7 B_SD7_5 7 2 R_B_SD7_5
A_SD7_0 RP66 1 8 R_A_SD7_0 B_SD2_2 5 4 R_B_SD2_2 B_SD7_2 RP15R 6 3 R_B_SD7_2
A_SD3_4 4 RP25 5 R_A_SD3_4 A_SD7_1 RP15R 2 7 R_A_SD7_1 B_SD3_0 RP29 5 RP15R 4 R_B_SD3_0 B_SD7_3 7 2 R_B_SD7_3
A_SD3_5 1 RP27 8 R_A_SD3_5 A_SD7_7 RP68 1 8 R_A_SD7_7 B_SD3_5 8 1 R_B_SD3_5 B_SD5_5 7 2 R_B_SD6_5
A_SD3_3 1 RP15R 8 R_A_SD3_3 A_SD7_3 RP15R 2 7 R_A_SD7_3 B_SD3_7 8 RP31 1 R_B_SD3_7 B_SD5_4 6 RP15R 3 R_B_SD6_4
A_SD3_2 4 5 R_A_SD3_2 R_A_DQS4_0 R29 12 A_DQS4_0 B_SD3_2 5 4 R_B_SD3_2 B_SD5_6 7 2 R_B_SD6_6
A_SD8_1 RP33 1 8 R_A_SD8_1 R_A_DQS4_1 R30 12 A_DQS4_1 B_SD8_1 RP74 8 RP15R 1 R_B_SD8_1 B_SD5_3 6 3 R_B_SD6_3
A_SD8_0 RP15R 2 7 R_A_SD8_0 R_A_DQS5_0 R33 12 A_DQS5_0 B_SD8_0 7 2 R_B_SD8_0 B_SD5_2 5 4 R_B_SD6_2
A_SD8_4 3 6 R_A_SD8_4 R_A_DQS5_1 R34 12 A_DQS5_1 B_SD8_5 6 3 R_B_SD8_5 R_B_DQS4_0 R31
RP15R 12 B_DQS4_0
A_SD8_5 4 5 R_A_SD8_5 R_A_DQS7_0 R37 12 A_DQS7_0 B_SD8_4 5 4 R_B_SD8_4 R_B_DQS4_1 R32 12 B_DQS4_1
A_SD8_3 RP35 1 8 R_A_SD8_3 R_A_DQS7_1 R38 12 A_DQS7_1 B_SD8_7 RP76 8 RP15R 1 R_B_SD8_7 R_B_DQS5_0 R35 12 B_DQS6_0
A_SD8_7 RP15R 2 7 R_A_SD8_7 R_A_DQS6_0 R41 12 A_DQS6_0 B_SD8_3 7 2 R_B_SD8_3 R_B_DQS5_1 R36 12 B_DQS6_1
A_SD8_6 3 6 R_A_SD8_6 R_A_DQS6_1 R42 12 A_DQS6_1 B_SD8_6 6 3 R_B_SD8_6 R_B_DQS7_0 R39 12 B_DQS7_0
3 A_SD8_2 4 5 R_A_SD8_2 B_SD8_2 5 4 R_B_SD8_2 R_B_DQS7_1 R40 12 B_DQS7_1 3
R_A_DQS3_0 R17 12 A_DQS3_0 R_B_DQS2_0 R15 RP15R 12 B_DQS2_0 R_B_DQS6_0 R43 12 B_DQS5_0
R_A_DQS3_1 R18 12 A_DQS3_1 R_B_DQS2_1 R16 12 B_DQS2_1 R_B_DQS6_1 R44 12 B_DQS5_1
R_A_DQS1_0 R9 12 A_DQS1_0 R_B_DQS1_0 R7 12 B_DQS1_0
A_VTT
18,19,21 B_SD0_[0..7] 13 R_B_SD0_[0..7] CAS# RP200 1 RP47R 8

18,19,21 B_SD1_[0..7] 13 R_B_SD1_[0..7] WE# 2 7
18,19,21 B_SD2_[0..7] 13 R_B_SD2_[0..7] RAS# 3 6
18,19,21 B_SD3_[0..7] 13 R_B_SD3_[0..7] MA13 4 5
18,19,21 B_SD4_[0..7] 13 R_B_SD4_[0..7]
18,19,21 B_SD5_[0..7] 13 R_B_SD5_[0..7]
18,19,21 B_SD6_[0..7] 13 R_B_SD6_[0..7]
18,19,21 B_SD7_[0..7] 13 R_B_SD7_[0..7]
18,19,21 B_SD8_[0..7] 13 R_B_SD8_[0..7] MA6 RP226 1 RP47R 8
MA4 2 7
2 18,19,21 B_DQS0_[0..1] 13 R_B_DQS0_[0..1] 2
MA3 3 6
18,19,21 B_DQS1_[0..1] 13 R_B_DQS1_[0..1] MA2 4 5
18,19,21 B_DQS2_[0..1] 13 R_B_DQS2_[0..1] MA5 RP228 1 RP47R 8
18,19,21 B_DQS3_[0..1] 13 R_B_DQS3_[0..1] MA8 2 7
18,19,21 B_DQS4_[0..1] 13 R_B_DQS4_[0..1] MA7 3 6
18,19,21 B_DQS5_[0..1] 13 R_B_DQS5_[0..1] MA9 4 5
18,19,21 B_DQS6_[0..1] 13 R_B_DQS6_[0..1] A_CKE RP230 1 RP47R 8
18,19,21 B_DQS7_[0..1] 13 R_B_DQS7_[0..1] B_CKE 2 7
18,19,21 B_DQS8_[0..1] 13 R_B_DQS8_[0..1] MA12 3 6
MA11 4 5
MA14 RP232 1 RP47R 8
MA10 2 7
16,17,21 A_SD0_[0..7] 13 R_A_SD0_[0..7] MA0 3 6
16,17,21 A_SD1_[0..7] 13 R_A_SD1_[0..7] MA1 4 5
16,17,21 A_SD2_[0..7] 13 R_A_SD2_[0..7]
16,17,21 A_SD3_[0..7] 13 R_A_SD3_[0..7]
16,17,21 A_SD4_[0..7] 13 R_A_SD4_[0..7]
16,17,21 A_SD5_[0..7] 13 R_A_SD5_[0..7]
16,17,21 A_SD6_[0..7] 13 R_A_SD6_[0..7]
16,17,21 A_SD7_[0..7] 13 R_A_SD7_[0..7]
16,17,21 A_SD8_[0..7] 13 R_A_SD8_[0..7]
16,17,21 A_DQS0_[0..1] 13 R_A_DQS0_[0..1]

16,17,21 A_DQS1_[0..1] 13 R_A_DQS1_[0..1]
16,17,21 A_DQS2_[0..1] 13 R_A_DQS2_[0..1]
16,17,21 A_DQS3_[0..1] 13 R_A_DQS3_[0..1]
16,17,21 A_DQS4_[0..1] 13 R_A_DQS4_[0..1]
16,17,21 A_DQS5_[0..1] 13 R_A_DQS5_[0..1]
1 16,17,21 A_DQS6_[0..1] 13 R_A_DQS6_[0..1] 1
16,17,21 A_DQS7_[0..1] 13 R_A_DQS7_[0..1]
16,17,21 A_DQS8_[0..1] 13 R_A_DQS8_[0..1]

Title Rev
13,16,17,18,19 MA[0..14]
MEMORY_TERMINATIONS-1
13,16,17 A_CKE
Document Number 0A
13,18,19 B_CKE
13,16,17,18,19 WE# MICRO-STAR INT'L CO.,LTD. Last Revision Date:

13,16,17,18,19 RAS#
13,16,17,18,19 CAS#
A B C D E
www.vinafix.vn
A B C D E
A_VTT A_VTT 16,17,20 A_SD0_[0..7]

A_VTT 16,17,20 A_SD1_[0..7]
16,17,20 A_SD2_[0..7]
16,17,20 A_SD3_[0..7]
A_SD0_3 RP2 RP22R B_SD0_2 RP43 1 RP22R C364 0.1uF C1723 0.1uF 16,17,20 A_SD4_[0..7]
1 8 8 16,17,20 A_SD5_[0..7]
A_SD0_7 2 7 B_SD0_6 2 7
A_SD0_2 B_SD0_7 16,17,20 A_SD6_[0..7]
3 6 3 6 16,17,20 A_SD7_[0..7]
4 A_SD0_6 4 5 B_SD0_3 4 5 C366 0.1uF C1724 0.1uF 4
A_SD0_1 RP4 RP22R B_SD0_0 RP45 1 RP22R 16,17,20 A_SD8_[0..7]
1 8 8
A_SD0_5 2 7 B_SD0_4 2 7
A_SD0_4 B_SD0_5 C368 0.1uF C1725 0.1uF 16,17,20 A_DQS0_[0..1]
3 6 3 6 16,17,20 A_DQS1_[0..1]
A_SD0_0 4 5 B_SD0_1 4 5
A_SD1_6 RP6 RP22R B_SD1_2 RP47 1 RP22R 16,17,20 A_DQS2_[0..1]
1 8 8 16,17,20 A_DQS3_[0..1]
A_SD1_7 2 7 B_SD1_7 2 7 C370 0.1uF C1726 0.1uF
A_SD1_2 B_SD1_6 16,17,20 A_DQS4_[0..1]
3 6 3 6
A_SD1_3 A_SD2_4 16,17,20 A_DQS5_[0..1]
4 5 4 5 16,17,20 A_DQS6_[0..1]
A_SD1_5 RP8 1 8 RP22R B_SD1_0 RP49 1 8 RP22R C372 0.1uF C1727 0.1uF
A_SD1_4 B_SD1_4 16,17,20 A_DQS7_[0..1]
2 7 2 7 16,17,20 A_DQS8_[0..1]
A_SD1_1 3 6 B_SD1_1 3 6
A_SD1_0 4 5 B_SD1_5 4 5 C374 0.1uF C1728 0.1uF
B_SD2_5 RP10 1 8 RP22R B_SD2_4 RP51 1 8 RP22R
A_SD2_5 2 7 A_SD2_1 2 7
B_SD2_1 3 6 A_SD2_0 3 6 C376 0.1uF C1729 0.1uF
B_SD2_0 B_SD1_3 18,19,20 B_SD0_[0..7]
4 5 4 5 18,19,20 B_SD1_[0..7]
A_SD2_6 RP12 1 8 RP22R B_SD2_7 RP53 1 8 RP22R
B_SD2_2 B_SD2_3 C378 0.1uF C1730 0.1uF 18,19,20 B_SD2_[0..7]
2 7 2 7 18,19,20 B_SD3_[0..7]
A_SD2_2 3 6 A_SD2_7 3 6
B_SD2_6 A_SD2_3 18,19,20 B_SD4_[0..7]
4 5 4 5 18,19,20 B_SD5_[0..7]
A_SD3_3 RP14 1 8 RP22R A_SD3_7 RP55 1 8 RP22R C380 0.1uF C1731 0.1uF
B_SD3_3 B_SD3_7 18,19,20 B_SD6_[0..7]
2 7 2 7
A_SD3_2 B_SD3_2 18,19,20 B_SD7_[0..7]
3 6 3 6 18,19,20 B_SD8_[0..7]
B_SD3_6 4 5 A_SD3_6 4 5 C382 0.1uF C1732 0.1uF
A_SD3_5 RP16 1 8 RP22R A_SD3_1 RP57 1 8 RP22R
A_SD3_4 B_SD3_4 18,19,20 B_DQS0_[0..1]
2 7 2 7
B_SD3_0 B_SD3_1 C384 0.1uF C1733 0.1uF 18,19,20 B_DQS1_[0..1]
3 6 3 6 18,19,20 B_DQS2_[0..1]
3 A_SD3_0 4 5 B_SD3_5 4 5 3
A_SD4_5 RP18 RP22R B_SD4_0 RP59 1 RP22R 18,19,20 B_DQS3_[0..1]
1 8 8 18,19,20 B_DQS4_[0..1]
A_SD4_1 2 7 B_SD4_4 2 7 C386 0.1uF C1734 0.1uF
A_SD4_4 B_SD4_1 18,19,20 B_DQS5_[0..1]
3 6 3 6
A_SD4_0 B_SD4_5 18,19,20 B_DQS6_[0..1]
4 5 4 5
A_SD4_3 RP20 RP22R B_SD4_2 RP61 1 RP22R C388 0.1uF C1735 0.1uF 18,19,20 B_DQS7_[0..1]
1 8 8 18,19,20 B_DQS8_[0..1]
A_SD4_7 2 7 B_SD4_6 2 7
A_SD4_6 3 6 B_SD4_7 3 6
A_SD4_2 4 5 B_SD4_3 4 5 C390 0.1uF C1736 0.1uF
A_SD5_5 2 7 B_SD5_0 2 7
A_SD5_0 3 6 B_SD5_5 3 6 C392 0.1uF C1737 0.1uF
A_SD5_4 4 5 B_SD5_1 4 5
A_SD5_3 2 7 B_SD5_3 2 7 C394 0.1uF C1738 0.1uF
A_SD5_6 3 6 B_SD5_6 3 6
A_SD5_2 4 5 B_SD5_7 4 5
A_SD6_3 RP26 1 8 RP22R B_SD6_0 RP67 1 8 RP22R C396 0.1uF
A_SD6_7 2 7 B_SD6_1 2 7
A_SD6_2 3 6 B_SD6_4 3 6
A_SD6_6 4 5 B_SD6_5 4 5 C398 0.1uF
A_SD6_5 2 7 B_SD6_2 2 7
A_SD6_4 3 6 B_SD6_7 3 6 C400 0.1uF
A_SD6_0 4 5 B_SD6_3 4 5
A_SD7_0 2 7 B_SD7_7 2 7
A_SD7_5 3 6 B_SD7_2 3 6 C402 0.1uF
A_SD7_4 4 5 B_SD7_3 4 5
2 2
A_SD7_2 2 7 B_SD7_5 2 7
A_SD7_7 3 6 B_SD7_0 3 6
A_SD7_6 4 5 B_SD7_1 4 5
A_SD8_6 2 7 A_SD8_0 2 7
B_SD8_6 3 6 B_SD8_1 3 6
B_SD8_2 4 5 A_SD8_1 4 5
A_SD8_7 RP36 1 8 RP22R A_SD8_5 RP77 1 8 RP22R
A_SD8_3 2 7 B_SD8_5 2 7
B_SD8_7 3 6 A_SD8_4 3 6
B_SD8_3 4 5 B_SD8_4 4 5
R194 22 A_DQS0_1 R212 22 B_DQS0_0

R195 22 A_DQS0_0 R213 22 B_DQS0_1
R196 22 A_DQS1_1 R214 22 B_DQS1_0
R197 22 A_DQS1_0 R215 22 B_DQS1_1
R198 22 B_DQS2_0 R216 22 A_DQS2_0
R199 22 A_DQS2_1 R217 22 B_DQS2_1
R200 22 A_DQS3_0 R218 22 B_DQS3_1
R201 22 A_DQS3_1 R219 22 B_DQS3_0
R202 22 A_DQS4_0 R220 22 B_DQS4_1
R203 22 A_DQS4_1 R221 22 B_DQS4_0
R204 22 A_DQS5_0 R222 22 B_DQS5_0
R205 22 A_DQS5_1 R223 22 B_DQS5_1
1 R206 22 A_DQS6_0 R224 22 B_DQS6_0 1
R207 22 A_DQS6_1 R225 22 B_DQS6_1
R208 22 A_DQS7_0 R226 22 B_DQS7_0
R209
R210
22
22
A_DQS7_1
A_DQS8_0
R227
R228
22
22
B_DQS7_1
B_DQS8_0
R211 22 A_DQS8_1 R229 22 B_DQS8_1 Title Rev
MEMORY_TERMINATIONS-2
Document Number 0A

A B C D E
www.vinafix.vn
A B C D E
VCC3
OPEN: 133MHz
R963
SHORT: 10K
100MHz
R964 JP12
SYN_XTAL_X1 1 2 SEL
SYN_XTAL_X2
1K
Y8
DEFAULT - CLOSE
4 4
14.318MHZ
C2218 C2219
10P 10P
U134
SYN_XTAL_X1 22 7 HCLKITPRP R965 22

SYN_XTAL_X2 XTALI HCLK0 HCLKITPRN R966 22 CLK_100M_ITP0 9
23 XTALO HCLK0_bar 8 CLK_100M_ITP1 9
R967 22 R_REF_CLK_33 1 10 HCLKR2P R968 22
23 REF_CLK_33MHZ CLK33 HCLK1 HCLKR2N R969 22 HCLK2 5
HCLK1_bar 11 HCLK2_N 5
SEL 48 SEL100/133 HCLKR3P R970 22 PROBE_HDR_CLK_P
HCLK2 13
RSB_CLK_14MHZ R971 22 R_REFCLK_14 19 14 HCLKR3N R972 22 PROBE_HDR_CLK_N
50 RSB_CLK_14MHZ R2099 REFCLK HCLK2_bar
48 HWM_14.318M
22 26 16
IREF HCLK3
49 USBCLK48M HCLK3_bar 17
USBCLK48M R975 22 R_USBCLK 3
58 SIOCLK48M 48MHZ/SELA
R976 22 R_SIOCLK 4 42 HCLKCMICRP R977 22
48MHZ_/SELB HCLK4 HCLKCMICRN R978 22 HCLK_CMIC 11
HCLK4_bar 41 HCLK_CMIC_N 11
R979 MULT_SEL_0 30
475_1% MULT_SEL_1 MULTSEL0 HCLKR1P R982 22
29 MULTSEL1 HCLK5 39 HCLK1 3
3 38 HCLKR1N R983 22 3
SPREAD# HCLK5_bar HCLK1_N 3
20 SPREAD#
36 DIMMPLLRP R984 22
VCC3 FB_11_OHM_100Mhz R985 10K HCLK6 DIMMPLLRN R986 22 DIMM_PLL_P 24
VCC3 44 PWRDN# HCLK6_bar 35
DIMM_PLL_N 24
L37
1 2 CLK_SYNTH_VDD1 2 33
VDD HCLK7
6 VDD HCLK7_bar 32
12 VDD
C1034 + 4.7uF/10V/20% 18 5
C1035 C1036 C1037 C1038 C1039 C1040 C1041 VDD GND
+ C1043 0.1uF 0.1uF 0.0033uF 0.1uF 0.1uF 0.1uF 24 9
C1042 VDD GND
4.7uF/10V/20% 0.00039uF
R991
R992
R993
R994
R995
R996
R997
R998
R999
R1247
R1248
R1000
0.01uF 31 VDD GND 15
37 VDD GND 28
43 VDD GND 34
GND 40
CLK_SYNTH_VDD2
49.9_1%
49.9_1%
49.9_1%
49.9_1%
49.9_1%
49.9_1%
49.9_1%
49.9_1%
49.9_1%
49.9_1%
49.9_1%
49.9_1%
25 VDDA GND 47
VCC3 FB_11_OHM_100MHz 46 VDDA
L38 27
GNDA
1 2 21 VSS GNDA 45
C1044 C1046 C1047

0.1uF C1045 + SYSTEM_CLOCK_GENERATOR_CDC950
C1048 + C1049 0.0033uF 0.00039uF
0.01uF
4.7uF/10V/20% 4.7uF/10V/20%
2 2
JP26
PROBE_HDR_CLK_P 1 2 PROBE_HDR_CLK_N
VCC3
For Test Probe Only
R1001 R1249 1K
10K R_USBCLK
J35 R1003 1K R1250 1K
SPREAD# VCC3 R_SIOCLK
2
1
HDR_1X2
RES_NOPOP
DEFAULT - OPEN R1002 R1252 1K

MULT_SEL_0
MULT_SEL_1
1 R1004 10K R1253 1
RES_NOPOP
DO NOT STUFF Title
CLK_SYNTHESIZER
Rev
Document Number 0A

A B C D E
www.vinafix.vn
A B C D E
4 4
DO NO STUFF RESERVE C BYPASS ?

RES_NOPOP CAP_NOPOP
R962 C1031
22 REF_CLK_33MHZ
U132
80 OHM Y0 3 PCICLK_CIOB1R R948 33
PCICLK_CIOB1 27
24 CLK
VCC3 4 PCICLK_CIOB2R R949 33
FB_11_OHM_100MHz FB_PCICLK33_BUFF Y1 PCICLK_CIOB2 37
13 FBIN
3 L35 5 PCICLK_IRQ1R R950 33 3
VDD_PCICLK_BUFF_5 Y2 PCICLK_IRQ1 50
1 2 2 VCC
10 8 PCICLK_VGA R952 33
C1019 C1020 VCC Y3 PCICLK_VGA 52
14 VCC
C1018 + C1028 22 9 R_PCICLK_ETHER2 R953 33
C1021 VCC Y4 PCICLK_ETHER2 55
C1022 + C1023 C1017 0.1uF
0.1uF 0.0033uF 0.00039uF 0.1uF 1 15 D_PCICLKR1 R961 33
4.7uF/10V/20% 4.7uF/10V/20% AGND Y5 D_PCICLK1 51
0.01uF
23 16 PCICLK_IRQ0R R956 33
AVCC Y6 PCICLK_IRQ0 50
6 17 D_PCICLKR2 R2601 33
GND Y7 D_PCICLK2 51
7 GND
18 20 LPC_CLK_SIO_R R960 33
R951 0_OHM GND Y8 LPC_CLK_SIO 58
19 GND
21 PCICLK_RSBR R959 33
Y9 PCICLK_RSB 49
VCC3 11 G
FBOUT 12
R1246 4.7K FB_PCICLK33_BUFF
R1349 22
IDT2510C
2 2
1 1

Title Rev
PCICLK_BUFFER
Document Number 0A

A B C D E
www.vinafix.vn
A B C D E
4 4
RESERVE R FILTER!?
U130
22 DIMM_PLL_P
22 DIMM_PLL_N
13 CLKIN_P CLK0_P 3
25 FBOUT0_P CLK7_P 19
25 FBOUT0_N 14 CLKIN_N CLK0_N 2 CLK7_N 19
FBOUT0_P 35 5
R913 FBIN_P CLK1_P CLK6_P 19
36 FBIN_N CLK1_N 6
VCC25 16,17,19,69 MEMB_SDA 120_1% CLK6_N 19
16,17,19,69 MEMB_SCL
CLK2_P 10 CLK1_P 16
FB16 FBOUT0_N 9
MEM_CLK_PLL_VDD1 CLK2_N CLK1_N 16
1 2 37 SDA
12 SCK CLK3_N 19 CLK0_N 16
80S/0805
15
CLK3_P 20
CLK0_P 16 TO DIMMs
C999 C1000 VCC3 VDD_I2C
0.0033uF 0.1uF CLK4_P 22 CLK4_P 18
16 AVCC CLK4_N 23 CLK4_N 18
17 AGND
CLK5_P 46
CLK3_P 17
FB17 47
MEM_CLK_PLL_VDD2 CLK5_N CLK3_N 17
1 2 4 VDDQ
80S/0805 11 44
VDDQ CLK6_P CLK2_P 17
CLK6_N 43
+ C1278 + C1005 C1006 CLK2_N 17
C1002 21 VDDQ
3 C1001 0.1uF C1277 0.1uF C1003 28 39 3
C1004 C1007 VDDQ CLK7_P CLK5_P 18
0.00039uF 0.0033uF 0.00039uF 0.1uF 0.1uF 34 40
4.7uF/10V/20% 4.7uF/10V/20% VDDQ CLK7_N CLK5_N 18
38 VDDQ
45 VDDQ CLK8_P 29
CLK8_N 30
1 GND
7 27 HDR_CLK_P
GND CLK9_P HDR_CLK_N
8 GND CLK9_N 26
18 GND
24 33 R_FBOUT0_PR R927 0_OHM FBOUT0_PR
GND FBOUT_P R_FBOUT0_NR R928 0_OHM FBOUT0_NR FBOUT0_PR 25
25 GND FBOUT_N 32 FBOUT0_NR 25
VCC3 31 GND
41 GND
42 GND
48 GND
C1279
0.1uF
RCC_SPLL_CDCV850
2
HDR_CLK_N 2
HDR_CLK_P
JP10
CLK0_P & N - DIMM1 1 2
CLK1_P & N - DIMM2 Header for Logic

Analyzer clock
CLK2_P & N - DIMM3
CLK3_P & N - DIMM4
CLK4_P & N - DIMM5
CLK5_P & N - DIMM6
CLK6_P & N - DIMM7
CLK7_P & N - DIMM8
1 1

Title Rev
SDRAM_CLK_BUFFER
Document Number 0A

A B C D E
www.vinafix.vn
A B C D E
FBOUT0_PR R859 0_OHM FBOUT0PL2 R860 0_OHM FBOUT0_NR R869 0_OHM FBOUT0NL2 R870 0_OHM FBOUT0_N
24 FBOUT0_PR FBOUT0_P 24 24 FBOUT0_NR FBOUT0_N 24
CENTRE PATH TO BE SAME CENTRE PATH TO BE SAME
4 4
LENGTH AS DIMCLK LENGTH AS DIMCLK
R2629 0
12 A_IMB_CLK_T_N_R A_IMB_CLK_T_N 27
0 ohm instead of R_DLY1
R2630 0
12 T_IMB_CLK_TR T_IMB_CLK_T 46,50
R2631 0
50 T_IMB_CLK_RR T_IMB_CLK_R 12,46
R2632 0
27 A_IMB_CLK_R_P_R A_IMB_CLK_R_P 12

3 3
R2633 0
27 A_IMB_CLK_R_N_R A_IMB_CLK_R_N 12
R2634 0
12 A_IMB_CLK_T_P_R A_IMB_CLK_T_P 27
R2635 0
37 B_IMB_CLK_R_P_R B_IMB_CLK_R_P 12
R2636 0
12 B_IMB_CLK_T_P_R B_IMB_CLK_T_P 37
R2637 0
37 B_IMB_CLK_R_N_R B_IMB_CLK_R_N 12
2 2
R2638 0
12 B_IMB_CLK_T_N_R B_IMB_CLK_T_N 37
1 1

Title Rev
SDRAM_&_IMB_CLK_DELAY_LOOPS
Document Number 0A

A B C D E
www.vinafix.vn
A B C D E
VCC3 VCC3
S1_M66EN R2096 4.7K

S1_PLOCK# R2098 4.7K
R2097 X_100
U127A
29 P1_AD[0..63] U127B
P1_GNT#[0..6] 28,29 S1_GNT#[0..5] 28,29,30
P1_AD0 N23 D21 P1_GNT#0 M2 D12 S1_GNT#0
4 P1_AD1 P_AD0 P_GNT#0 P1_GNT#1 S_AD0 S_GNT#0 S1_GNT#1 4
R25 P_AD1 P_GNT#1 B18 G1 S_AD1 S_GNT#1 A12
P1_AD2 N25 A17 P1_GNT#2 L1 C13 S1_GNT#2
P1_AD3 P_AD2 P_GNT#2 P1_GNT#3 S_AD2 S_GNT#2 S1_GNT#3
U22 P_AD3 P_GNT#3 A16 G4 S_AD3 S_GNT#3 B12
P1_AD4 M22 A15 P1_GNT#4 L4 A13 S1_GNT#4
P1_AD5 P_AD4 P_GNT#4 P1_GNT#5 S_AD4 S_GNT#4 S1_GNT#5
P24 P_AD5 P_GNT#5 B14 E3 S_AD5 S_GNT#5 D13
P1_AD6 K21 A14 P1_GNT#6 K1
P1_AD7 P_AD6 P_GNT#6 S_AD6 S1_REQ#0
R22 P_AD7 E1 S_AD7 S_REQ#0 D11 S1_REQ#0 30
P1_AD8 P22 B20 P1_REQ#0 D2 D9 S1_REQ#1
P_AD8 P_REQ#0 P1_REQ#0 29 S_AD8 S_REQ#1 S1_REQ#1 35
P1_AD9 L22 A20 P1_REQ#1 K5 C11 S1_REQ#2
P1_AD10 N22 A19 P1_REQ#2 C1 E10 S1_REQ#3
P1_AD11 J22 C19 P1_REQ#3 H1 A11 S1_REQ#4
P1_AD12 M24 B22 P1_REQ#4 B1 D10 S1_REQ#5
P1_AD13 J25 A18 P1_REQ#5 H2
P_AD13 P_REQ#5 P1_REQ#5 29 S_AD13
P1_AD14 M25 D20 P1_REQ#6 C2 K4
P_AD14 P_REQ#6 P1_REQ#6 29 S_AD14 S_CBE#0
P1_AD15 H22 G3 A2
P1_AD16 P_AD15 P1_CBE#0 S_AD15 S_CBE#1
E23 P_AD16 P_CBE#0 L25 P1_CBE#[0..7] 29 A4 S_AD16 S_CBE#2 C4
P1_AD17 F24 L23 P1_CBE#1 B6 A9
P1_AD18 P_AD17 P_CBE#1 P1_CBE#2 S_AD17 S_CBE#3
D24 P_AD18 P_CBE#2 H24 G5 S_AD18 S_CBE#4 W4
P1_AD19 F25 D25 P1_CBE#3 A7 AC1
C25 P_AD20 P_CBE#4 AE21 C5 S_AD20 S_CBE#6 Y1
P1_AD21 G21 AD25 P1_CBE#5 D5 AD1
B25 P_AD22 P_CBE#6 AD20 A6 S_AD22
P1_AD23 E22 AD23 P1_CBE#7 B8 F4
P_AD23 P_CBE#7 S_AD23 S_FRAME# S1_FRAME# 30,35
P1_AD24 A23 C7 B4
P_AD24 S_AD24 S_DEVSEL# S1_DEVSEL# 30,35
P1_AD25 C24 E25 D6 A5
P_AD25 P_FRAME# P1_FRAME# 29 S_AD25 S_IRDY# S1_IRDY# 30,35
P1_AD26 A24 K22 D7 F2
P_AD26 P_DEVSEL# P1_DEVSEL# 29 S_AD26 S_TRDY# S1_TRDY# 30,35
P1_AD27 D23 H25 A10 F1
P_AD27 P_IRDY# P1_IRDY# 29 S_AD27 S_PAR S1_PAR# 30,35
P1_AD28 B23 F22 A8 D1
P_AD28 P_TRDY# P1_TRDY# 29 S_AD28 S_STOP# S1_STOP# 30,35
3 P1_AD29 C22 G23 E7 B3 3
P_AD29 P_PAR P1_PAR 29 S_AD29 S_SERR# S1_SERR# 30,35,50
P1_AD30 A21 G22 D8 A3
P_AD30 P_STOP# P1_STOP# 29 S_AD30 S_PERR# S1_PERR# 30,35,50
P1_AD31 A22 K24 B10
P_AD31 P_SERR# P1_SERR# 29,50 S_AD31
P1_AD32 T21 K25 N5 M1
P_AD32 P_PERR# P1_PERR# 29,50 S_AD32 S_REQ64# S1_REQ64# 30,35
P1_AD33 W21 J4 AC2
P_AD33 S_AD33 S_PAR64 S1_PAR64# 30,35
P1_AD34 T22 N21 N4 H4
P_AD34 P_REQ64# P1_REQ64# 29 S_AD34 S_ACK64# S1_ACK64# 30,35
P1_AD35 U25 AC22 J1 E4 S1_PLOCK#
P_AD35 P_PAR64 P1_PAR64# 29 S_AD35 S_LOCK#
P1_AD36 P25 T24 P4 R1619 4.7K
P_AD36 P_ACK64# P1_ACK64# 29 S_AD36
P1_AD37 W22 J23 J3 E13
P_AD37 P_LOCK# P1_PLOCK# 29 S_AD37 S_SOR# VCC3
P1_AD38 R23 R1620 4.7K P2 D15
P1_AD39 P_AD38 S_AD38 S_SIL# S1_M66EN
W23 P_AD39 P_SOR# D16 VCC3 K2 S_AD39 S_M66EN D3
P1_AD40 U23 C15 P1 B16
P1_AD41 P_AD40 P_SIL# S_AD40 S_SOD
W25 P_AD41 P_M66EN C17 L3 S_AD41
P1_AD42 T25 D19 P1_M66EN 29 R3 C9 S1_PCIRST#
P_AD42 P_SOD S_AD42 S_PCIRST# S1_PCIRST# 31
P1_AD43 AA22 M4
P1_AD44 P_AD43 P1_PCIRST# S_AD43
V22 P_AD44 P_PCIRST# D18 P1_PCIRST# 29 T2 S_AD44
P1_AD45 AA23 N3 E16 S1_PCIXCAP1
P1_AD46 P_AD45 P1_PCIXCAP1 S_AD45 S_PCIXCAP1 S1_PCIXCAP2
V24 P_AD46 P_PCICAP1 C21 U4 S_AD46 S_PCIXCAP2 D14
P1_AD47 AA25 E19 P1_PCIXCAP2 N1
P1_AD48 P_AD47 P_PCICAP2 S_AD47
V25 P_AD48 U1 S_AD48
P1_AD49 AB20 R4
P1_AD50 P_AD49 S_AD49
Y22 P_AD50 V2 S_AD50
P1_AD51 AC24 R1
Y24 P_AD52 W3 S_AD52
P1_AD53 AC25 T5
P1_AD55 AC21 T1
AB23 P_AD56 Y2 S_AD56
2
P1_AD57 AE24 T4 2
P1_AD58 P_AD57 S_AD57 VCC3
AB24 P_AD58 AA1 S_AD58
P1_AD59 AD22 U3
AB25 P_AD60 AB2 S_AD60
P1_AD61 AE23 V1 R803 5.1K
P1_AD62 P_AD61 S_AD61 P1_PCIXCAP2
P1_AD63 AE22 V4
P_AD63 S_AD63 R804 5.1K
P1_PCIXCAP1
CIOBX2 CIOBX2
R805 5.1K
S1_PCIXCAP2
R807 5.1K
VCC3 S1_PCIXCAP1
VCC
S1_PCIRST#
10K
U129 R2602 4.7K

R811 2K
5.1K
5.1K
3 Vin P1_PCIXCAP/ P1_M66EN/ P1_GNT#5/ P1_PCIXCAP2/ P1_PCIXCAP1/ FREQ. ( MHz ) P1_PCIRST#

R2603 4.7K
R808
R809
R810
12 GND S1_PCIXCAP S1_M66EN S1_GNT#3 S1_PCIXCAP2 S1_PCIXCAP1

6 2N
29 P1_PCIXCAP 7 2P 2Y 1 P1_PCIXCAP2 Gnd 0 X 0 0 PCI - 33
4 1N Conv. PCI
TP13
5 1P 1Y 2 P1_PCIXCAP1 Gnd 1 X 0 0 PCI - 66
8 3N
S1_PCIXCAP 9 14 S1_PCIXCAP2
1 1 3P 3Y 1
10 4N Pull Down X X 0 1 PCI-X - 66
11 13 S1_PCIXCAP1
JP8 4P 4Y
2 1
R819 10K

R818 2K
N.C. ( 1 ) X 1 1 1 PCI-X - 100

JP9 2 1 LM339A Title Rev
N.C. ( 1 ) X 0 1 1 PCI-X - 133 CIOBX1_PCI-X
ON : Force PCI Document Number 0A
Only Mode
N.C. ( 1 ) - Not Connected , Logic Value = 1 No. 69, Li-De St, Jung-He City,
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A B C D E
VDD_IMB
VCC25
R787 1K CIOBX2_IMB_RCOMP R1504 100_1% Route AVDD as two traces, One going to each pin.
CIOBX2_IMB_COMP_PD R790 249_1% VDD_IMB
CIOBX2_IMB_COMP_PU R789 249_1% Route AGND like AVDD, each pin having its own trace Connected
to GND pin of Filter Ckt.'s Cap.
VCC3
AC18
AC16
AC14
AC12
AC10
AC13
AA17
AA15
AA13
AA11
AE20
AB13
AE12
AC8
AC6
AC5
AA9
AA7
G25
U127D
A25 B24
IMBCOMP2
IMBCOMP1
IMBCOMP0
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
TESTMODE#
RSVD
RSVD
GND VCC3 12 A_IMB_D_T[0..15] U127C
A1 GND VCC3 B2
B21 C20 VCC25
GND VCC3 A_IMB_D_T0
B19 GND VCC3 C18 AE19 IMBD_ R0 IMBCLK_R_P AD16 A_IMB_CLK_T_P 25
B17 C16 A_IMB_D_T1 AE18 AE16
GND VCC3 IMBD_ R1 IMBCLK_R_N A_IMB_CLK_T_N 25
4 B15 C14 A_IMB_D_T2 AB17 AE8 R783 4
GND VCC3 IMBD_R2 IMBCLK_T_P A_IMB_CLK_R_P_R 25
B13 C12 A_IMB_D_T3 AB19 AD8
GND VCC3 IMBD_ R3 IMBCLK_T_N A_IMB_CLK_R_N_R 25
B11 C10 A_IMB_D_T4 AA19 0
GND VCC3 A_IMB_D_T5 IMBD_R4
B9 GND VCC3 C8 AB18 IMBD_R5 IMBPAR_T AC7 A_IMB_PAR_R 12
B7 C6 A_IMB_D_T6 AC19 AC17
GND VCC3 IMBD_ R6 IMBPAR_R A_IMB_PAR_T 12
B5 D22 A_IMB_D_T7 AE17 AB6 R_AVDD_CIOB1_PLL
GND VCC3 IMBD_R7 IMBCON_T A_IMB_CON_R 12
C23 D4 A_IMB_D_T8 AD18 AB14
GND VCC3 IMBD_ R8 IMBCON_R A_IMB_CON_T 12
2
C3 E20 A_IMB_D_T9 AB15
GND VCC3 A_IMB_D_T10 IMBD_R9 L33
E24 GND VCC3 E17 AE13 IMBD_ R10
E21 E15 A_IMB_D_T11 AD14 47uH
GND VCC3 A_IMB_D_T12 IMBD_R11
E18 GND VCC3 E12 AB16 IMBD_R12 AGND1 AE3
E14 E9 A_IMB_D_T13 AE15 AD4
GND VCC3 A_IMB_D_T14 IMBD_R13 AGND2
E11 GND VCC3 E6 AE14 IMBD_R14
E8 F23 A_IMB_D_T15 AC15 AE4 AVDD_CIOB1_PLL
1
GND VCC3 IMBD_R15 AVDD1
E5 GND VCC3 F21 AVDD2 AD5
E2 F5 A_IMB_D_R0 AB11
GND VCC3 A_IMB_D_R1 IMBD_ T0
G24 GND VCC3 F3 AB12 IMBD_ T1 SDA W5 RCC_SDA 12,15,37,41,48,69
G2 H23 A_IMB_D_R2 AC11 Y4
GND VCC3 IMBD_T2 SCLK RCC_SCL 12,15,37,41,48,69
H21 H3 A_IMB_D_R3 AB10 22uF/10V
GND VCC3 A_IMB_D_R4 IMBD_ T3 C964
H5 GND VCC3 J21 AE10 IMBD_T4 PCLKFB AD3 P1FBCLK 39
J24 J5 A_IMB_D_R5 AE9 AE2
GND VCC3 IMBD_ T5 SCLK_FB S1FBCLK 39
J2 K23 A_IMB_D_R6 AD10 AC4
GND VCC3 IMBD_ T6 CLKIN PCICLK_CIOB1 23
L24 K3 A_IMB_D_R7 AE11 AB3 S1CLKO_R R784 22
GND VCC3 IMBD_T7 SCLK_O S1CLKO 39
L21 M23 A_IMB_D_R8 AC9 AA4 P1CLKO_R R786 22
GND VCC3 IMBD_T8 PCLK_O P1CLKO 39
L15 M21 A_IMB_D_R9 AD6
GND VCC3 A_IMB_D_R10 IMBD_T9 PCIRST1#
L14 GND VCC3 M5 AE6 IMBD_ T10 PCIRST# D17 PCIRST1# 11,37,65
L13 M3 A_IMB_D_R11 AB9 AA3 R1706 0_OHM
GND VCC3 IMBD_T11 PLLRST PS_PWRGD# 11,37,50,64
L12 P23 A_IMB_D_R12 AE7
GND VCC3 A_IMB_D_R13 IMBD_ T12
3 L11 GND VCC3 P3 AB8 IMBD_ T13 ALERT AB5 ALERT# 11,15,37,50 3
L5 R21 A_IMB_D_R14 AB7
GND VCC3 A_IMB_D_R15 IMBD_T14 VREF_IMB_CIOB
L2 GND VCC3 R5 AA6 IMBD_ T15 VREFIMB0 AD12
M15 GND VCC3 T23
M14 GND VCC3 T3 12 A_IMB_D_R[0..15]
M13 GND VCC3 U21 CIOBX2
M12 GND VCC3 U5
M11 V23 VCC25
GND VCC3
N24 GND VCC3 V3
N15 GND VCC3 Y23
N14 GND VCC3 Y21
N13 GND VCC3 Y5
N12 Y3 VCC25 C968 C969 C970 C971
GND VCC3
N11 GND VCC3 AA20
N2 AB22 0.01uF 0.01uF 0.1uF 1.0uF/16V
GND VCC3
P21 GND VCC3 AB4
P15 AD24 C976 C977 C978 C979 C980 C981 C982 C983
GND VCC3
P14 GND VCC3 AD21
P13 AD2 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF
GND VCC3
P12 GND
P11 GND VDD25 K16
P5 K15 VCC25
GND VDD25 VDD_IMB
R24 K14
GND VDD25
VDD25 K13
R15 K12 VDD_IMB
GND VDD25
R14 GND VDD25 K11
R13 GND VDD25 K10
C1639 C1640 C1641 C1642
100_1%
C1638
R12 GND VDD25 L16
R791
2 R11 GND VDD25 L10 2

R2 M16 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V
GND VDD25
U24 GND VDD25 M10
U2 GND VDD25 N16
V21 N10 VREF_IMB_CIOB VCC3
GND VDD25
V5 GND VDD25 P16
100_1%
W24 GND VDD25 P10

220pF
220pF
W2 GND VDD25 R10

AA24 T16
1.0uF/10V
GND VDD25 C984 C985 C986 C987 VDD_IMB

AA21 GND VDD25 T15
C990
AA18 GND VDD25 T14

1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V
C988
C989
R792
AA16 GND VDD25 T13

AA14 GND VDD25 T12
AA12 T11 C1643 C1644 C1645 C1646 C1647 C1648
GND VDD25
AA10 GND VDD25 T10
AA8 R16 0.1uF 0.01uF 0.1uF 0.01uF 0.01uF 0.1uF
GND VDD25
AA5 GND
AA2 GND
AC23 VCC25
330uF/6.3V/NHG/PANASONIC
GND
AC20 GND
AC3 GND
AD19 GND
AD17 GND C972 C973 C974 C975 C966
C967
AE5 + +
GND
1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V
AD15GND
AD13GND
AD11GND
AD9 GND
AD7 GND
AE25GND
AE1 GND
CIOBX2
1 1
VCC3
Title Rev
CIOBX1_IMB_PWR
C991 C992 C993 C994 C995 C996 C997 C998 + + Document Number 0A
C1721
0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF C1722 MICRO-STAR INT'L CO.,LTD. Last Revision Date:
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A B C D E
S1_GNT#5
P1_GNT#0 : VCC3
0 = Disable Sec Hot-Plug
Do not stuff
VCC3 1: APLL Enabled ( * ) Controller (Default)
RES_NOPOP
0: APLL Disabled
2.2K
1 = Enable Sec Hot-Plug
R813
Controller
4 R793 4
P1_GNT#0 S1_GNT#5
P1_GNT#0 26,29 S1_GNT#5 26,29
2.2K
RES_NOPOP
P1_GNT#6
R815
Do not stuff
R794
0 = Disable Pri Hot-Plug

VCC3
Controller (Default)
S1_GNT#1
RES_NOPOP
Do not stuff
1 = Enable Pri
VCC3
Hot-Plug 1: Prim. PCI func. registers
R814
Controller VCC3 will be accessed at Func.#0
and Sec. PCI at Func.#2
Do not stuff
CIOB I2C Bus ID

2.2K
2.2K
R796 RES_NOPOP
R797 RES_NOPOP
ID = 1 0: Prim. PCI func. registers

P1_GNT#6
P1_GNT#6 26,29 will be accessed at Func.#2
and Sec. PCI at Func.#0
R1682
R816
2.2K
R795
P1_GNT#1
P1_GNT#1 26,29
P1_GNT#2 S1_GNT#1
Do not stuff
3 3
P1_GNT#2 26,29 S1_GNT#1 26,29
P1_GNT#3
P1_GNT#3 26,29
2.2K
2.2K
RES_NOPOP
RES_NOPOP
R1683
R798
R799
R800
S1_GNT#3
0 = PCI-X 133
P1_GNT#5 VCC3
1 = PCI-X 100
VCC3 0 = PCI-X 133 [ Refer to table Please refer to 'CMIC
8.2K
1 = PCI-X 100 on sheet #27 ]
STRAPPING OPTIONS' sheet
8.2K
R1615
[ Refer to table
on sheet #27 ]
JP27
S1_GNT#3
for following strappings in
R1616
JP28
2
1
S1_GNT#3 26,29
CIOB-x1 and CIOB-x2
P1_GNT#5 HDR_1X2
2 P1_GNT#5 26,29
1
1K
HDR_1X2
: - IMB - DETERMINISTIC/ NON
R1617
2 2
1K
DETERMINISTIC
R1618
: - IMB CRC or PARITY
: - IMB_TRAINING Enable/Disable
S1_GNT#0
VCC3
1: All bits of Func. #
VCC3
S1_GNT#2
2.2K
2.2K
used for reg. access

0: Only bit 0 of Func. #
IMB_READ/WRITE POINTER DLY
used for reg. access 1 : 5 CLOCKs ( Default )
R812
R1613
0 : 6 CLOCKs
1 S1_GNT#0 S1_GNT#2 1
Do not stuff
S1_GNT#0 26,29,30 S1_GNT#2 26,29

RES_NOPOP
RES_NOPOP

R817
R1614
Title Rev
CIOBX1_STRAPPING_OPTIONS
Document Number 0A

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A B C D E
VCC3
VCC3 VCC3
P1_M66EN R1437 4.7K
VCC VCC VCC3 VCC 3VSB
PCI_SLOT2 P1_REQ64# R1702 2.7K
-12V +12V_IO
PDOWN1 J23 R682 8.2K P1_PAR64 R1703 2.7K VCC3
R685 B1 A1 VCC
B2 A2 EC55 EC56 + P1_SL2_PRSNT#2
B3 A3 PDOWN1 EC57 EC58 + + EC54 P1_SL2_PRSNT#1
1K B4 A4 + + 100U/16V
B5 A5 1000U/6.3V 1000U/6.3V RP2K7
4 B6 A6 PCIIRQ#6
PCIIRQ#6 50
1000U/6.3V 1000U/6.3V
VCC3 1 RP311 8 4
PCIIRQ#7 B7 A7 2 7
50 PCIIRQ#7
B8 A8 3 6
P1_SL2_PRSNT#1 B9 A9 4 5
B10 A10
P1_SL2_PRSNT#2 B11 A11 3VSB VCC3 RP2K7
P1_PERR# 1 RP312 8
P1_SDONE 2 7
B14 A14 C826 C827 C828 C829 C830 P1_PLOCK# 3 6
B15 A15 P1_PCIRST# P1_STOP# 4 5
P1_PCIRST# 26 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
PCICLK_P1_SLT1 B16 A16
39 PCICLK_P1_SLT1
B17 A17 P1_GNT#0 P1_REQ#0 2.7K R1911
P1_GNT#0 26,28 26 P1_REQ#0
P1_REQ#0 B18 A18
26 P1_REQ#0
B19 A19 P1_PCI_PME# P1_REQ#1 2.7K R1912
P1_PCI_PME# 58 26 P1_REQ#1
P1_AD31 B20 A20 P1_AD30 C831 C832 C833 C834 C835
P1_AD29 B21 A21 P1_REQ#2 2.7K R1913
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 26 P1_REQ#2
B22 A22 P1_AD28
P1_AD27 P1_AD26 RP314
B23 A23
P1_AD25 B24 A24 VCC P1_REQ#5 8 1
26 P1_REQ#5
B25 A25 P1_AD24 P1_REQ#3 7 2
26 P1_REQ#3
P1_CBE#3 B26 A26 P1_IDSEL0 P1_REQ#6 6 3
R687 26 P1_REQ#6
P1_AD23 B27 A27 P1_AD18 C837 C838 C839 C840 P1_REQ#4 5 4
26 P1_REQ#4
B28 A28 P1_AD22
P1_AD21 B29 A29 P1_AD20 2K 0.01uF 0.01uF 0.01uF 0.01uF RP315 RP2K7
P1_AD19 B30 A30 P1_DEVSEL# 1 RP2K7 8
B31 A31 P1_AD18 P1_TRDY# 2 7
P1_AD17 B32 A32 P1_AD16 P1_IRDY# 3 6
P1_CBE#2 B33 A33 P1_FRAME# 4 5
3 B34 A34 P1_FRAME# 3
P1_FRAME# 26 RP2K7
P1_IRDY# B35 A35
26 P1_IRDY#
B36 A36 P1_TRDY#
P1_TRDY# 26
P1_ACK64# 1 RP316 8
P1_DEVSEL# B37 A37 P1_PAR 2 7
26 P1_DEVSEL#
P1_PCIXCAP B38 A38 P1_STOP# P1_SERR# 3 6
26 P1_PCIXCAP P1_STOP# 26
P1_PLOCK# B39 A39 P1_SBO# 4 5
26 P1_PLOCK#
P1_PERR# B40 A40 P1_SDONE
26,50 P1_PERR#
B41 A41 P1_SBO#
P1_SERR# B42 A42 VCC3
26,50 P1_SERR#
B43 A43 P1_PAR P1_PCIRST# C2192 X_104P
P1_PAR 26 26 P1_AD[0..63] RP8K2
P1_CBE#1 B44 A44 P1_AD15
P1_AD14 B45 A45 P1_AD32 1 RP317 8
B46 A46 P1_AD13 P1_AD34 2 7
P1_AD12 B47 A47 P1_AD11 P1_AD33 3 6
P1_AD10 B48 A48 P1_AD35 4 5
B49 A49 P1_AD9
P1_M66EN B50 A50 RP8K2
26 P1_M66EN
B51 A51 P1_AD36 1 RP318 8
C825 P1_AD8 B52 A52 P1_CBE#0 P1_AD37 2 7
P1_AD7 B53 A53 P1_AD38 3 6
0.01uF B54 A54 P1_AD6 P1_AD39 4 5 VCC3
P1_AD5 B55 A55 P1_AD4 RP8K2
26,28 P1_GNT#[0..6]
P1_AD3 B56 A56 P1_AD40 1 RP319 8
B57 A57 P1_AD2 P1_AD42 2 7 P1_GNT#0 RN29 1 2 8P4R-4.7K
P1_AD1 B58 A58 P1_AD0 P1_AD41 3 6 P1_GNT#1 3 4
B59 A59 P1_AD43 4 5 P1_GNT#2 5 6
P1_ACK64# B60 A60 P1_REQ64# RP8K2 P1_GNT#3 7 8
26 P1_ACK64# P1_REQ64# 26
B61 A61 P1_AD44 1 RP320 8
2 B62 A62 P1_AD45 2 7 P1_GNT#4 R2100 4.7K 2
P1_AD46 3 6
P1_AD47 4 5 P1_GNT#5 R2101 4.7K
B63 A63 RP8K2
B64 A64 P1_CBE#7 P1_AD48 1 RP321 8 P1_GNT#6 R2102 4.7K
P1_CBE#6 B65 A65 P1_CBE#5 P1_AD50 2 7 26,28,30 S1_GNT#[0..5]
P1_CBE#4 B66 A66 P1_AD49 3 6
B67 A67 P1_PAR64 P1_AD51 4 5 S1_GNT#0 RN30 1 2 8P4R-4.7K
P1_PAR64# 26 RP8K2
P1_AD63 B68 A68 P1_AD62 S1_GNT#1 3 4
P1_AD61 B69 A69 P1_AD52 1 RP322 8 S1_GNT#2 5 6
B70 A70 P1_AD60 P1_AD53 2 7 S1_GNT#3 7 8
P1_AD59 B71 A71 P1_AD58 P1_AD54 3 6
P1_AD57 B72 A72 P1_AD55 4 5 S1_GNT#4 R2103 4.7K
B73 A73 P1_AD56 RP8K2
P1_AD55 B74 A74 P1_AD54 P1_AD56 1 RP323 8 S1_GNT#5 R2104 4.7K
P1_AD53 B75 A75 P1_AD57 2 7
B76 A76 P1_AD52 P1_AD58 3 6
P1_AD51 B77 A77 P1_AD50 P1_AD59 4 5
P1_AD49 B78 A78 RP8K2
B79 A79 P1_AD48 P1_AD60 1 RP324 8
P1_AD47 B80 A80 P1_AD46 P1_AD61 2 7
P1_AD45 B81 A81 P1_AD63 3 6
B82 A82 P1_AD44 P1_AD62 4 5
26 P1_CBE#[0..7] RP8K2
P1_AD43 B83 A83 P1_AD42
P1_AD41 B84 A84 P1_CBE#4 1 RP325 8
B85 A85 P1_AD40 P1_CBE#5 2 7
P1_AD39 B86 A86 P1_AD38 P1_CBE#6 3 6
P1_AD37 B87 A87 P1_CBE#7 4 5
B88 A88 P1_AD36
1 1
P1_AD35 B89 A89 P1_AD34
P1_AD33 B90 A90 P1_CBE#0
B91 A91 P1_AD32 P1_CBE#1
B92 A92 P1_CBE#2
P1_CBE#3
B93 A93
B94 A94 P1_CBE#4 Title Rev
P1_CBE#5 CIOBX1_PCIXP1_SLOT
P1_CBE#6 Document Number 0A
CONN_PCI64_3_3V_SOCKET P1_CBE#7
26 P1_AD[0..63] MICRO-STAR INT'L CO.,LTD. Last Revision Date:
Tuesday, August 21, 2001
26 P1_CBE#[0..7] No. 69, Li-De St, Jung-He City,
A B C D E
www.vinafix.vn
8 7 6 5 4 3 2 1
U205C
U205B
E11 VCC1
AIC-7899W VCC11 D14
Y5 VIO9 AB7 E12 K25
D
39 PCICLK_S1_SLT1
PCICLK_S1_SLT1 T1 PCLK
AIC-7899W VIO8
VIO7 AB8 L22
VCC2
VCC3
VCC12
VCC13 L1 D
R3 TRST VIO6 AB11 M22 VCC4 VCC14 L26
S1_GNT#0 AE1 AB12 R5 M1
26,28,29 S1_GNT#0 GNT VIO5 VCC5 VCC15
AE4 IDSEL VIO4 AB15 R22 VCC6 VCC16 R1
PCIIRQ#8 AB3 AB16 T5 R26
50 PCIIRQ#8 PCIIRQ#9 IRQA VIO3 VCC7 VCC17
AB2 IRQB VIO2 AB19 T22 VCC8 VCC18 V26
50 PCIIRQ#9
AB4 IDDQ VIO1 AB20 W22 VCC9 VCC19 W1
T4
U4
TCK PCI PREQ AF1 S1_REQ#0
S1_REQ#0 26 Y22 VCC10 VCC20 AA1
AA26
TMS VCC21
P4 TDI TD0 R4 E15 SVCCA1 VCC22 AF6
E16 SVCCA2 VCC23 AF9
AC17 AD63 ACK64 AC15 E19 SVCCA3 VCC24 AF12
AD17 AD62 REQ64 AD15 E20 SVCCA4 VCC25 AF15
AE17 AD61 PAR64 AF16 G22 SVCCA5 VCC26 AF18
AF17 AD60 FRAME AD7 H22 SVCCA6 VCC27 AF21
AC18 AD59 IRDY AE7 E7 SVCCA7 AVCC18A A8
AD18
AE18
AD58 PAR AD9
AD8
E8
G5
SVCCA8 PWR/ AGNDE C13
C14
VCC3 AC19
AD57
AD56
DEVSEL
TRDY AC8 H5
SVCCA9
SVCCB1
GND AGNDF
AD19 AD55 STOP AE8 L5 SVCCB2
AE19 AD54 PERR AF8 M5 SVCCB3
S1_REQ#0 R1961 2.7K AC20 AC9
AD53 SERR
AD20 AD52 GND1 E5
AE20 AD51 C3 SVCC33A GND2 E6
S1_GNT#0 R1962 8.2K AF20 AE15 C23 E9
AD50 CBE7 SVCC33B GND3
AC21 AD49 CBE6 AC16 D4 SVCC33C GND4 E10
C AD21 AD48 CBE5 AD16 G26 SVCC33D GND5 E13 C
AE21 AD47 CBE4 AE16 GND6 E14
AC22 AD46 CBE3 AD4 A4 SVCC50A GND7 E17
AD22 AD45 CBE2 AC7 A16 SVCC50B GND8 E18
AE22 AD44 CBE1 AE9 D23 SVCC50C GND9 E21
AD23
AE23
AD43 MEMORY CBE0 AD12 H26
K1
SVCC50D GND10 E22
F5
AD42 SVCC50E GND11
AF23 AD41 TERMPWRA H23 A1 SVCC50F GND12 F22
AD24 AD40 TERMPWRB D12 AF2 PVCC1 GND13 J5
AF24 AD39 AF7 PVCC2 GND14 J22
AE24 AD38 ROMOE P24 AF10 PVCC3 GND15 K5
AF26 AD37 SEECS AC26 AF14 PVCC4 GND16 K22
AF25 AD36 MWE T23 AF19 PVCC5 GND17 L11
AE26 AD35 RAMCS W4 AF22 PVCC6 GND18 L12
AE25 AD34 ROMCS N23 A7 PVCC7 GND19 L13
AD26 AD33 EXTARBREQ AB25 A14 PVCC8 GND20 L14
AD25 AD32 EXTARBACK AB26 C17 PVCC9 GND21 L15
AC2 AD31 BRDWE AB24 GND22 L16
AD2 AD30 BRDOE AB23 P1 PXVCC18 GND23 M11
AE2 AD29 RAMPS V4 GND24 M12
AC3 AD28 W5 VDPCI/VIO GND25 M13
AD3 AD27 MDP T24 GND26 M14
AE3 AD26 AA2 PZV33 GND27 M15
AF3 AD25 MA15 T25 AA3 PZV33_A GND28 M16
AC4 AD24 MA14 R25 T11 GND47 GND29 N11
AF4 AD23 MA13 R24 T12 GND48 GND30 N12
B AC5 AD22 MA12 T26 T13 GND49 GND31 N13 B
AD5 AD21 MA11 P25 T14 GND50 GND32 N14
AE5 AD20 MA10 P23 T15 GND51 GND33 N15
AF5 AD19 MA9 P26 T16 GND52 GND34 N16
AC6 AD18 MA8 R23 N5 GND53 GND35 P11
AD6 AD17 MA7 U23 N22 GND54 GND36 P12
AE6 AD16 MA6 U24 P5 GND55 GND37 P13
AC10 AD15 MA5 U25 P22 GND56 GND38 P14
AD10 AD14 MA4 U26 U5 GND57 GND39 P15
AE10 AD13 MA3 V23 U22 GND58 GND40 P16
AC11 AD12 MA2 V24 V5 GND59 GND41 R11
AD11 AD11 MA1 V25 V22 GND60 GND42 R12
AE11 AD10 MA0 W23 AA5 GND61 GND43 R13
AF11 AD9 AA22 GND62 GND44 R14
AC12 AD8 AB5 GND63 GND45 R15
AE12 AD7 MD7 AA23 AB6 GND64 GND46 R16
AC13 AD6 MD6 Y26 AB17 GND69 GND65 AB9
AD13 AD5 MD5 Y25 AB18 GND70 GND66 AB10
AE13 AD4 MD4 Y24 AB21 GND71 GND67 AB13
AF13 AD3 MD3 Y23 AB22 GND72 GND68 AB14
AC14 AD2 MD2 W26
AD14 W25 7899W
AD1 MD1
AE14 AD0 MD0 W24
SEECK AC25
SEEDI AC23
SEEDO AC24
A A
7899W
POWER TRACE Title Rev
全部走20mil寬 Document Number
AIC 7899W/7902 1/2 (PCIXS1)
0A

8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
LVSCDAP15 D17 SCDAP15

AIC-7899W SCDAM15 D16 LVSCDAM15
LVSCDAP14 B16 C16 LVSCDAM14
LVSCDAP13 SCDAP14 SCDAM14 LVSCDAM13
D15 SCDAP13 SCDAM13 C15
LVSCDAP12 A15 B15 LVSCDAM12
LVSCDAP11 SCDAP12 SCDAM12 LVSCDAM11 LVSCDAM[15..0]
G24 SCDAP11 SCDAM11 G25 LVSCDAM[15..0] 32
LVSCDAP10 F23 F24 LVSCDAM10 LVSCDAP[15..0]
SCDAP10 SCDAM10 LVSCDAP[15..0] 32
LVSCDAP9 F25 F26 LVSCDAM9
E23 SCDAP8 SCDAM8 E24
LVSCDAP7 C21 D21 LVSCDAM7
LVSCDAP6 SCDAP7 SCDAM7 LVSCDAM6 LVSCDBM[15..0]
A21 SCDAP6 SCDAM6 B21 LVSCDBM[15..0] 33
LVSCDAP5 C20 D20 LVSCDAM5 LVSCDBP[15..0]
SCDAP5 SCDAM5 LVSCDBP[15..0] 33
D LVSCDAP3 SCDAP4 SCDAM4 LVSCDAM3 D
C19 SCDAP3 SCDAM3 D19
C18 SCDAP1 SCDAM1 D18
SCDAP0 SCDAM0
32 LVCSDAPHP A17 SCDAPHP SCDAPHM B17 LVCSDAPHM 32

32 LVCSDAPLP A22 SCDAPLP SCDAPLM B22 LVCSDAPLM 32
32 LVATNAP C22 ATNAP ATNAM D22 LVATNAM 32
32 LVBSYAP A23 BSYAP BSYAM B23 LVBSYAM 32
32 LVACKAP A24 ACKAP ACKAM B24 LVACKAM 32
32 LVRSTAP A26 RESETAP RESETAM A25 LVRSTAM 32
32 LVMSGAP B25 MSGAP MSGAM C24 LVMSGAM 32
32 LVSELAP C26 SELAP SELAM B26 LVSELAM 32
32 LVCDAP D26 CDAP CDAM C25 LVCDAM 32
32 LVREQAP D24
E25
REQAP SCSI REQAM D25
E26
LVREQAM 32
32 LVIOAP IOAP IOAM LVIOAM 32
LVSCDBP15 M2 M3 LVSCDBM15
LVSCDBP14 SCDBP15 SCDBM15 LVSCDBM14
M4 SCDBP14 SCDBM14 N4
LVSCDBP13 N1 N2 LVSCDBM13
N3 SCDBP12 SCDBM12 P3
LVSCDBP11 D6 C6 LVSCDBM11
B6 SCDBP10 SCDBM10 A6
LVSCDBP9 D5 C5 LVSCDBM9
B5 SCDBP8 SCDBM8 A5
LVSCDBP7 G1 G2 LVSCDBM7
C G3 SCDBP6 SCDBM6 G4 C
LVSCDBP5 H1 H2 LVSCDBM5
H3 SCDBP4 SCDBM4 H4
LVSCDBP3 J1 J2 LVSCDBM3
J3 SCDBP2 SCDBM2 J4
LVSCDBP1 K2 K3 LVSCDBM1
K4 SCDBP0 SCDBM0 L4
33 LVCSDBPHP L2 SCDBPHP SCDBPHM L3 LVCSDBPHM 33

33 LVCSDBPLP F3 SCDBPLP SCDBPLM F4 LVCSDBPLM 33
33 LVBSYBP E3 BSYBP BSYBM E4 LVBSYBM 33
33 LVACKBP E1 ACKBP ACKBM E2 LVACKBM 33
33 LVATNBP F1 ATNBP ATNBM F2 LVATNBM 33
33 LVRSTBP D2 RESETBP RESETBM D3 LVRSTBM 33
33 LVMSGBP C2 MSGBP MSGBM D1 LVMSGBM 33
33 LVSELBP B1 SELBP SELBM C1 LVSELBM 33
33 LVCDBP B2 CDBP CDBM A2 LVCDBM 33
33 LVREQBP B3 REQBP REQBM A3 LVREQBM 33
33 LVIOBP C4 IOBP IOBM B4 LVIOBM 33
32 DIFFSENSEA
R1965 0 H25 DIFFSENSEA LVREXT1 C9 4.99KRST R1966 KEEP TRACE SHORT
R1967 0 D9 B9
33 DIFFSENSEB DIFFSENSEB LVREXT2
7899W=0 Ohm EXREXT1 B13 6.19KRST R1968 7899W=6.19K
7902 =10K EXREXT2 B12 20 MIL 7902 =Open
S1_PCIRST# AD1 N26
26 S1_PCIRST# PCIRST PCIRSTOUT
LEDA K26 SCSILED1 65
B MISC LEDB L25 SCSILED2 65 B
J25 EXTXCVRA STPWCTLA J26 STPWCTLA 32

S1_PCIRST# C2193 X_104P K23 L24
EXTXCVRB STPWCTLB STPWCTLB 33
J24 EXPACTA WIDEPSA J23 0 R1969
K24 L23 VCC3
EXPACTB WIDEPSB
M26 IDDATA R19700
M24 AA4 R1971 4.7K
IDDATB TESTMODE
H24 SCLKIN LDALTIDA M25 R1973 7899W=0 Ohm
0 R1972 B11 M23 R1974 4.7K 0
34 AIC_CLKINP
B10
SCLKINP LDALTIDB 7902 =Open
34 AIC_CLKINM SCLKINM
D8 SRAGARDV STAGARDV C8
B8 AVCC33A AVCC33C A10
A9 AVCC33B AVCC33D A11
AC1 PAGARDV AVCC33E A12
T2 PCAVCC33A AGNDC C11
T3 PCAVCC33B AGNDD C12
U1 PXAVCC33A STAGARDG C10
U2 PXAVCC33B PXAVCC18 Y1
V1 PCAGNDA AVCC18A B7
Note : V2 C7
PCAGNDB AVCC18B
W2 PXAGNDA AVCC18D D7
THE CHIP WILL LOAD 6-BYTE OF ID DATA FROM AB1 PAGARDG PXAGNDB Y2
A13 AGNDA
DIFFERENT LOCATION OF THE SEEPROM BASED ON B14 AGNDB
THE LOGIC LEVEL AT D10 STAGARD 7899W
A A
THE SIGNAL LDALTIDA OF CHANNEL A AND THE U205A
SIGNAL IDALTIDB OF CHANNEL B. Micro Star Restricted Secret
Title Rev
DEPENDING ON THE LADLTIDA AND LADLTIDB AIC 7899W/7902 2/2
STATUS, ONE OF THE TWO POSSIBLE ID VALUES Document Number 0A
FROM THE PREDETERMINED LOCATION OF THE
SEEPROM WILL BE EXTRACTED. MICRO-STAR INT'L CO.,LTD. Last Revision Date:
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
LVTRMPWR_A
50MIL
+ LVSCDAM[15..0]
LVSCDAM[15..0] 31
LVSCDAP[15..0]
LVSCDAP[15..0] 31
EC21 C2094
10U/16V/S 104P
U206
16 D_SNS TPWR 28
D D
TPWR1 27
LVSCDAP11 2 3 LVSCDAM11
LVSCDAP10 +R1 -R1 LVSCDAM10 VCC
4 +R2 -R2 5
LVSCDAP8 +R3 -R3 LVSCDAM8
9 +R4 -R4 10
1
LVIOAP 11 12 LVIOAM
31 LVIOAP +R5 -R5 LVIOAM 31
LVREQAP 18 19 LVREQAM D60
31 LVREQAP +R6 -R6 LVREQAM 31 LVTRMPWR_A
LVCDAP 20 21 LVCDAM
31 LVCDAP +R7 -R7 LVCDAM 31 YDIMBRS340T3S
LVSELAP 23 24 LVSELAM
31 LVSELAP +R8 -R8 LVSELAM 31
LVMSGAP 25 26 LVMSGAM F1
31 LVMSGAP +R9 -R9 LVMSGAM 31
LVTRMPWR_A
2
17 13 D08-040020X-R02 50MIL
DIFF_CAP ISO
M_S 15
VREF 1
22 SCSI1
HSGND2 LVSCDAP12 LVSCDAM12
6 HSGND1 1 35
R1976 14 LVSCDAP13 LVSCDAM13
20K GND C2095 C2096 LVSCDAP14 2 36 LVSCDAM14
DIFFSENSEA 104P 475P/0805 LVSCDAP15 3 37 LVSCDAM15
31 DIFFSENSEA 4 38
DS2119M LVSCDAPHP LVSCDAPHM
220K not call out in Dallas LVSCDAP0 5 39 LVSCDAM0
C 6 40 C
datasheets. It's use for setting R1975 LVSCDAP1 LVSCDAM1
221K U207 LVSCDAP2 7 41 LVSCDAM2
initial state of the terminators 8 42
16 28 LVSCDAP3 LVSCDAM3
D_SNS TPWR LVSCDAP4 9 43 LVSCDAM4
TPWR1 27 10 44
LVBSYAP 2 3 LVBSYAM LVSCDAP5 LVSCDAM5
31 LVBSYAP +R1 -R1 LVBSYAM 31 11 45
LVATNAP 4 5 LVATNAM LVSCDAP6 LVSCDAM6
31 LVATNAP +R2 -R2 LVATNAM 31 12 46
LVACKAP 7 8 LVACKAM LVSCDAP7 LVSCDAM7
31 LVACKAP +R3 -R3 LVACKAM 31 13 47
LVRSTAP 9 10 LVRSTAM LVSCDAPLP LVSCDAPLM
31 LVRSTAP +R4 -R4 LVRSTAM 31 14 48
LVSCDAPLP 11 12 LVSCDAPLM
31 LVCSDAPLP +R5 -R5 LVCSDAPLM 31 15 49
LVSCDAP7 18 19 LVSCDAM7 DIFFSENSEA
LVSCDAP6 +R6 -R6 LVSCDAM6 16 50
20 +R7 -R7 21 17 51
LVSCDAP4 +R8 -R8 LVSCDAM4 18 52
25 +R9 -R9 26 19 53
LVATNAP 20 54 LVATNAM
21 55
17 DIFF_CAP ISO 13 22 56
15 R1977 4.7K LVBSYAP LVBSYAM
M_S LVACKAP 23 57 LVACKAM
VREF 1 24 58
LVRSTAP LVRSTAM
LVMSGAP 25 59 LVMSGAM
31 STPWCTLA 1 2 26 60
22 LVSELAP LVSELAM
HSGND2 LVCDAP 27 61 LVCDAM
1N4148S 6 HSGND1 28 62
14 LVREQAP LVREQAM
D61 GND 29 63
B R1978 C2097 C2098 LVIOAP LVIOAM B
10K 104P 475P/0805 LVSCDAP8 30 64 LVSCDAM8
DS2119M LVSCDAP9 31 65 LVSCDAM9
U208 34 68
16 28 YSCSI68-P
D_SNS TPWR
TPWR1 27
4 +R2 -R2 5
9 +R4 -R4 10
LVSCDAPHP 11 12 LVSCDAPHM
31 LVCSDAPHP +R5 -R5 LVCSDAPHM 31
20 +R7 -R7 21
POWER TRACE
25 +R9 -R9 26
17 DIFF_CAP ISO 13
全部走20mil寬
M_S 15
VREF 1
A 22 A
HSGND2
C2099
104P
6 HSGND1 Micro Star Restricted Secret
14 GND C2100 C2101 Title Rev
104P 475P/0805 SCSI CHANNEL 1
DS2119M Document Number 0A

8 7 6 5 4 3 2 1
www.vinafix.vn
8 7 6 5 4 3 2 1
LVTRMPWR_B
50MIL
+
LVSCDBM[15..0]
LVSCDBM[15..0] 31
EC22 C2102 LVSCDBP[15..0]
LVSCDBP[15..0] 31
10U/16V/S 104P
U223
16 D_SNS TPWR 28
D D
TPWR1 27
LVSCDBP11 2 3 LVSCDBM11
LVSCDBP10 +R1 -R1 LVSCDBM10 VCC
4 +R2 -R2 5
LVSCDBP8 +R3 -R3 LVSCDBM8
9 +R4 -R4 10
1
LVIOBP 11 12 LVIOBM
31 LVIOBP +R5 -R5 LVIOBM 31
LVREQBP 18 19 LVREQBM D62
31 LVREQBP +R6 -R6 LVREQBM 31 LVTRMPWR_B
LVCDBP 20 21 LVCDBM
31 LVCDBP +R7 -R7 LVCDBM 31 YDIMBRS340T3S
LVSELBP 23 24 LVSELBM
31 LVSELBP +R8 -R8 LVSELBM 31
LVMSGBP 25 26 LVMSGBM F2
31 LVMSGBP +R9 -R9 LVMSGBM 31
LVTRMPWR_B
2
17 13 D08-040020X-R02 50MIL
DIFF_CAP ISO
M_S 15
VREF 1
22 SCSI2
HSGND2 LVSCDBP12 LVSCDBM12
6 HSGND1 1 35
R1980 14 LVSCDBP13 LVSCDBM13
20K GND C2103 C2104 LVSCDBP14 2 36 LVSCDBM14
DIFFSENSEB 104P 475P/0805 LVSCDBP15 3 37 LVSCDBM15
31 DIFFSENSEB DS2119M LVSCDBPHP 4 38 LVSCDBPHM
220K not call out in Dallas LVSCDBP0 5 39 LVSCDBM0
C 6 40 C
datasheets. It's use for setting R1979 LVSCDBP1 LVSCDBM1
221K U224 LVSCDBP2 7 41 LVSCDBM2
initial state of the terminators 8 42
16 28 LVSCDBP3 LVSCDBM3
D_SNS TPWR LVSCDBP4 9 43 LVSCDBM4
TPWR1 27 10 44
LVBSYBP 2 3 LVBSYBM LVSCDBP5 LVSCDBM5
31 LVBSYBP +R1 -R1 LVBSYBM 31 11 45
LVATNBP 4 5 LVATNBM LVSCDBP6 LVSCDBM6
31 LVATNBP +R2 -R2 LVATNBM 31 12 46
LVACKBP 7 8 LVACKBM LVSCDBP7 LVSCDBM7
31 LVACKBP +R3 -R3 LVACKBM 31 13 47
LVRSTBP 9 10 LVRSTBM LVSCDBPLP LVSCDBPLM
31 LVRSTBP +R4 -R4 LVRSTBM 31 14 48
LVSCDBPLP 11 12 LVSCDBPLM
31 LVCSDBPLP +R5 -R5 LVCSDBPLM 31 15 49
LVSCDBP7 18 19 LVSCDBM7 DIFFSENSEB
LVSCDBP6 +R6 -R6 LVSCDBM6 16 50
20 +R7 -R7 21 17 51
LVSCDBP4 +R8 -R8 LVSCDBM4 18 52
25 +R9 -R9 26 19 53
LVATNBP 20 54 LVATNBM
21 55
17 DIFF_CAP ISO 13 22 56
15 R1981 4.7K LVBSYBP LVBSYBM
M_S LVACKBP 23 57 LVACKBM
VREF 1 24 58
LVRSTBP LVRSTBM
LVMSGBP 25 59 LVMSGBM
31 STPWCTLB 1 2 26 60
22 LVSELBP LVSELBM
HSGND2 LVCDBP 27 61 LVCDBM
1N4148S 6 HSGND1 28 62
14 LVREQBP LVREQBM
D63 R1982 GND C2105 C2106 LVIOBP 29 63 LVIOBM
B B
10K 104P 475P/0805 LVSCDBP8 30 64 LVSCDBM8
DS2119M LVSCDBP9 31 65 LVSCDBM9
U225 34 68
16 28 YSCSI68-P-90
D_SNS TPWR
TPWR1 27
4 +R2 -R2 5
9 +R4 -R4 10
LVSCDBPHP 11 12 LVSCDBPHM
31 LVCSDBPHP +R5 -R5 LVCSDBPHM 31
20 +R7 -R7 21
POWER TRACE
25 +R9 -R9 26
17 DIFF_CAP ISO 13
全部走20mil寬
M_S 15
VREF 1
A 22 A
HSGND2
C2107
104P
6 HSGND1 Micro Star Restricted Secret
14 GND C2108 C2109 Title Rev
104P 475P/0805 SCSI CHANNEL 2
DS2119M Document Number 0A

8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
D D
C C
B B
VCC3
8 5 R1991 22
VCC OUT+ AIC_CLKINP 31
4 GND OUT- 1 AIC_CLKINM 31

C2120
103P 7899W=Reserved
OSC1 40MHZ
7902 =SCLKINM
80 Mhz OSC for 7902 (Differential)
40 Mhz OSC for 7899W
A
POWER TRACE A
全部走20mil寬 Title
Rev
SCSI MISE.
Document Number 0A

8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
VCC3
S1_REQ64# 2 1
26,30 S1_REQ64#
S1_PAR64 4 3
26,30 S1_PAR64#
S1_ACK64# 6 5
26,30 S1_ACK64#
S1_REQ#1 8 7
26 S1_REQ#1
RN1
8P4R-2.7K
D S1_REQ#3 D
26 S1_REQ#3 2 1
S1_REQ#5 4 3
26 S1_REQ#5
S1_REQ#2 6 5
26 S1_REQ#2
S1_REQ#4 8 7
26 S1_REQ#4
RN2
8P4R-2.7K
S1_FRAME# 2 1
26,30 S1_FRAME#
S1_IRDY# 4 3
26,30 S1_IRDY#
S1_TRDY# 6 5
26,30 S1_TRDY#
S1_DEVSEL# 8 7
26,30 S1_DEVSEL#
RN3
8P4R-2.7K
S1_STOP# 2 1
26,30 S1_STOP#
S1_PERR# 4 3
26,30,50 S1_PERR#
S1_SERR# 6 5
26,30,50 S1_SERR#
S1_PAR 8 7
26,30 S1_PAR#
RN4
8P4R-2.7K
C C
B B
A A

Title Rev
S1 BUS TERMINATOR
Document Number 0A

8 7 6 5 4 3 2 1
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A B C D E
S2_AD[0..63]
45 S2_AD[0..63]
U100B
U100A
P2_AD[0..63]
41,44 P2_AD[0..63] S2_GNT#[0..5] 38,44,45
S2_AD0 M2 D12 S2_GNT#0
S2_AD1 S_AD0 S_GNT#0 S2_GNT#1
P2_GNT#[0..6] 38,41,44 G1 S_AD1 S_GNT#1 A12
P2_AD0 N23 D21 P2_GNT#0 S2_AD2 L1 C13 S2_GNT#2
P2_AD1 P_AD0 P_GNT#0 P2_GNT#1 S2_AD3 S_AD2 S_GNT#2 S2_GNT#3
R25 P_AD1 P_GNT#1 B18 G4 S_AD3 S_GNT#3 B12
P2_AD2 N25 A17 P2_GNT#2 S2_AD4 L4 A13 S2_GNT#4
P2_AD3 P_AD2 P_GNT#2 P2_GNT#3 S2_AD5 S_AD4 S_GNT#4 S2_GNT#5
U22 P_AD3 P_GNT#3 A16 E3 S_AD5 S_GNT#5 D13
4 P2_AD4 M22 A15 P2_GNT#4 S2_AD6 K1 4
P2_AD5 P_AD4 P_GNT#4 P2_GNT#5 S2_AD7 S_AD6 S2_REQ#0
P24 P_AD5 P_GNT#5 B14 E1 S_AD7 S_REQ#0 D11 S2_REQ#0 45
P2_AD6 K21 A14 P2_GNT#6 S2_AD8 D2 D9 S2_REQ#1
P_AD6 P_GNT#6 S_AD8 S_REQ#1 S2_REQ#1 45
P2_AD7 R22 S2_AD9 K5 C11 S2_REQ#2
P_AD7 P2_REQ#[0..6] 41,44 S_AD9 S_REQ#2 S2_REQ#2 45
P2_AD8 P22 B20 P2_REQ#0 S2_AD10 C1 E10 S2_REQ#3
P_AD8 P_REQ#0 S_AD10 S_REQ#3 S2_REQ#3 45
P2_AD9 L22 A20 P2_REQ#1 S2_AD11 H1 A11 S2_REQ#4
P2_AD10 N22 A19 P2_REQ#2 S2_AD12 B1 D10 S2_REQ#5
P2_AD11 J22 C19 P2_REQ#3 S2_AD13 H2
P2_AD12 P_AD11 P_REQ#3 P2_REQ#4 S2_AD14 S_AD13 S2_CBE#0
M24 P_AD12 P_REQ#4 B22 C2 S_AD14 S_CBE#0 K4 S2_CBE#[0..7] 45
P2_AD13 J25 A18 P2_REQ#5 S2_AD15 G3 A2 S2_CBE#1
P2_AD14 P_AD13 P_REQ#5 P2_REQ#6 S2_AD16 S_AD15 S_CBE#1 S2_CBE#2
M25 P_AD14 P_REQ#6 D20 A4 S_AD16 S_CBE#2 C4
P2_AD15 H22 S2_AD17 B6 A9 S2_CBE#3
P2_AD16 P_AD15 P2_CBE#0 S2_AD18 S_AD17 S_CBE#3 S2_CBE#4
E23 P_AD16 P_CBE#0 L25 P2_CBE#[0..7] 41,44 G5 S_AD18 S_CBE#4 W4
P2_AD17 F24 L23 P2_CBE#1 S2_AD19 A7 AC1 S2_CBE#5
P2_AD18 P_AD17 P_CBE#1 P2_CBE#2 S2_AD20 S_AD19 S_CBE#5 S2_CBE#6
D24 P_AD18 P_CBE#2 H24 C5 S_AD20 S_CBE#6 Y1
P2_AD19 F25 D25 P2_CBE#3 S2_AD21 D5 AD1 S2_CBE#7
P2_AD20 P_AD19 P_CBE#3 P2_CBE#4 S2_AD22 S_AD21 S_CBE#7
C25 P_AD20 P_CBE#4 AE21 A6 S_AD22
P2_AD21 G21 AD25 P2_CBE#5 S2_AD23 B8 F4
P_AD21 P_CBE#5 S_AD23 S_FRAME# S2_FRAME# 45
P2_AD22 B25 AD20 P2_CBE#6 S2_AD24 C7 B4
P_AD22 P_CBE#6 S_AD24 S_DEVSEL# S2_DEVSEL# 45
P2_AD23 E22 AD23 P2_CBE#7 S2_AD25 D6 A5
P_AD23 P_CBE#7 S_AD25 S_IRDY# S2_IRDY# 45
P2_AD24 A23 S2_AD26 D7 F2
P_AD24 S_AD26 S_TRDY# S2_TRDY# 45
P2_AD25 C24 E25 S2_AD27 A10 F1
P_AD25 P_FRAME# P2_FRAME# 41,44 S_AD27 S_PAR S2_PAR# 45
P2_AD26 A24 K22 S2_AD28 A8 D1
P_AD26 P_DEVSEL# P2_DEVSEL# 41,44 S_AD28 S_STOP# S2_STOP# 45
P2_AD27 D23 H25 S2_AD29 E7 B3
P_AD27 P_IRDY# P2_IRDY# 41,44 S_AD29 S_SERR# S2_SERR# 45,50
P2_AD28 B23 F22 S2_AD30 D8 A3
P_AD28 P_TRDY# P2_TRDY# 41,44 S_AD30 S_PERR# S2_PERR# 45,50
P2_AD29 C22 G23 S2_AD31 B10
P_AD29 P_PAR P2_PAR 41,44 S_AD31
P2_AD30 A21 G22 S2_AD32 N5 M1
P_AD30 P_STOP# P2_STOP# 41,44 S_AD32 S_REQ64# S2_REQ64# 45
P2_AD31 A22 K24 S2_AD33 J4 AC2
P_AD31 P_SERR# P2_SERR# 41,44,50 S_AD33 S_PAR64 S2_PAR64# 45
3 P2_AD32 T21 K25 S2_AD34 N4 H4 3
P_AD32 P_PERR# P2_PERR# 41,44,50 S_AD34 S_ACK64# S2_ACK64# 45
P2_AD33 W21 S2_AD35 J1 E4
P_AD33 S_AD35 S_LOCK# S2_PLOCK# 45
P2_AD34 T22 N21 S2_AD36 P4 R1393 4.7K
P_AD34 P_REQ64# P2_REQ64# 41,44 S_AD36
P2_AD35 U25 AC22 S2_AD37 J3 E13
P_AD35 P_PAR64 P2_PAR64 41,44 S_AD37 S_SOR# VCC3
P2_AD36 P25 T24 S2_AD38 P2 D15
P_AD36 P_ACK64# P2_ACK64# 44 S_AD38 S_SIL#
P2_AD37 W22 J23 S2_AD39 K2 D3
P_AD37 P_LOCK# P2_PLOCK# 44 S_AD39 S_M66EN S2_M66EN 45
P2_AD38 R23 S2_AD40 P1 B16
P2_AD39 P_AD38 S_AD40 S_SOD
W23 P_AD39 P_SOR# D16 R1392 4.7K
VCC3
S2_AD41 L3 S_AD41
P2_AD40 U23 C15 S2_AD42 R3 C9 S2_PCIRST#
P_AD40 P_SIL# S_AD42 S_PCIRST# S2_PCIRST# 45
P2_AD41 W25 C17 S2_AD43 M4
P_AD41 P_M66EN P2_M66EN 41,44 S_AD43
P2_AD42 T25 D19 S2_AD44 T2
P2_AD43 P_AD42 P_SOD S2_AD45 S_AD44 S2_PCIXCAP1
AA22 P_AD43 N3 S_AD45 S_PCIXCAP1 E16
P2_AD44 V22 D18 P2_PCIRST# S2_AD46 U4 D14 S2_PCIXCAP2
P_AD44 P_PCIRST# P2_PCIRST# 41,44 S_AD46 S_PCIXCAP2
P2_AD45 AA23 S2_AD47 N1
P2_AD46 P_AD45 P2_PCIXCAP1 S2_AD48 S_AD47
V24 P_AD46 P_PCICAP1 C21 U1 S_AD48
P2_AD47 AA25 E19 P2_PCIXCAP2 S2_AD49 R4
P2_AD48 P_AD47 P_PCICAP2 S2_AD50 S_AD49
V25 P_AD48 V2 S_AD50
P2_AD49 AB20 S2_AD51 R1
P2_AD50 P_AD49 S2_AD52 S_AD51
P2_AD51 AC24 S2_AD53 T5
P2_AD53 AC25 S2_AD55 T1
Y25 P_AD54 Y2 S_AD56
P2_AD55 AC21 S2_AD57 T4
AB23 P_AD56 AA1 S_AD58
P2_AD57 AE24 S2_AD59 U3
P2_AD59 AD22 S2_AD61 V1
2 AB25 P_AD60 AB1 S_AD62 2
P2_AD61 AE23 S2_AD63 V4
AB21 P_AD62
P2_AD63 AE22 P_AD63
CIOBX2
CIOBX2 VCC3
R766 5.1K
VCC P2_PCIXCAP2
R767 5.1K
VCC3 C1394 P2_PCIXCAP1
0.1uF
VCC R769 5.1K

S2_PCIXCAP2
U101
10K
R770 5.1K
2K
5.1K
5.1K
S2_PCIXCAP1
3 Vin P2_PCIXCAP/ P2_M66EN/ P2_GNT#5/ P2_PCIXCAP2/ P2_PCIXCAP1/ FREQ. ( MHz )
R771
R772
R773
R774
12 GND S2_PCIXCAP S2_M66EN S2_GNT#3 S2_PCIXCAP2 S2_PCIXCAP1 P2_PCIRST#

6 R2604 4.7K
2N
44 P2_PCIXCAP 7 2P 2Y 1 P2_PCIXCAP2 Gnd 0 X 0 0 PCI - 33
4 1N Conv. PCI S2_PCIRST#
5 1P 1Y 2 P2_PCIXCAP1 Gnd 1 X 0 0 PCI - 66 R2605 4.7K
8 3N
9 14 S2_PCIXCAP2
45 S2_PCIXCAP 3P 3Y
1
10 4N Pull Down X X 0 1 PCI-X - 66 1
11 13 S2_PCIXCAP1
JP5 4P 4Y
2 1
10K
2K
JP6
N.C. ( 1 ) X 1 1 1 PCI-X - 100 Micro Star Restricted Secret
2 1 LM339A
N.C. ( 1 ) X 0 1 1 PCI-X - 133 Title Rev
R781
R782
ON : Force PCI-X CIOBX2_PCIX

Document Number 0A
incapable
N.C. ( 1 ) - Not Connected , Logic Value = 1 Monday, August 20, 2001
A B C D E
www.vinafix.vn
A B C D E
R1491 249_1% CIOB2_COMP_PD

VDD_IMB
Route AVDD as two traces, One going to each pin.
VDD_IMB R1493 1K CIOB2_RCOMP R1490 100_1% CIOB2_RCOMP
VCC25
CIOB2_COMP_PD Route AGND like AVDD, each pin having its own trace Connected
CIOB2_COMP_PU R1492 249_1% CIOB2_COMP_PU
to GND pin of Filter Ckt.'s Cap.
U100D VCC3
AC18
AC16
AC14
AC12
AC10
AC13
AA17
AA15
AA13
AA11
AE20
AB13
AE12
AC8
AC6
AC5
AA9
AA7
G25
VCC25
U100C
A25 B24
IMBCOMP2
IMBCOMP1
IMBCOMP0
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
VDD1.5
TESTMODE#
RSVD
RSVD
GND VCC3 12 B_IMB_D_T[0..15]
A1 GND VCC3 B2
B21 C20 B_IMB_D_T0 AE19 AD16
GND VCC3 IMBD_ R0 IMBCLK_R_P B_IMB_CLK_T_P 25
4 B19 C18 B_IMB_D_T1 AE18 AE16 R746 4
GND VCC3 IMBD_ R1 IMBCLK_R_N B_IMB_CLK_T_N 25
B17 C16 B_IMB_D_T2 AB17 AE8 0
GND VCC3 IMBD_R2 IMBCLK_T_P B_IMB_CLK_R_P_R 25
B15 C14 B_IMB_D_T3 AB19 AD8
GND VCC3 IMBD_ R3 IMBCLK_T_N B_IMB_CLK_R_N_R 25
B13 C12 B_IMB_D_T4 AA19
GND VCC3 B_IMB_D_T5 IMBD_R4 R_AVDD_CIOB2_PLL
B11 GND VCC3 C10 AB18 IMBD_R5 IMBPAR_T AC7 B_IMB_PAR_R 12
2
B9 C8 B_IMB_D_T6 AC19 AC17
GND VCC3 IMBD_ R6 IMBPAR_R B_IMB_PAR_T 12
B7 C6 B_IMB_D_T7 AE17 AB6 L31
GND VCC3 IMBD_R7 IMBCON_T B_IMB_CON_R 12
B5 D22 B_IMB_D_T8 AD18 AB14 47uH
GND VCC3 IMBD_ R8 IMBCON_R B_IMB_CON_T 12
C23 D4 B_IMB_D_T9 AB15
GND VCC3 B_IMB_D_T10 IMBD_R9
C3 GND VCC3 E20 AE13 IMBD_ R10
E24 E17 B_IMB_D_T11 AD14
GND VCC3 B_IMB_D_T12 IMBD_R11
E21 E15 AB16 AE3
1
GND VCC3 B_IMB_D_T13 IMBD_R12 AGND1
E18 GND VCC3 E12 AE15 IMBD_R13 AGND2 AD4
E14 E9 B_IMB_D_T14 AE14 22uF/10V
GND VCC3 B_IMB_D_T15 IMBD_R14 AVDD_CIOB2_PLL C932
E11 GND VCC3 E6 AC15 IMBD_R15 AVDD1 AE4
E8 GND VCC3 F23 12 B_IMB_D_R[0..15] AVDD2 AD5
E5 F21 B_IMB_D_R0 AB11
GND VCC3 B_IMB_D_R1 IMBD_ T0
E2 GND VCC3 F5 AB12 IMBD_ T1 SDA W5 RCC_SDA 12,15,27,41,48,69
G24 F3 B_IMB_D_R2 AC11 Y4
GND VCC3 IMBD_T2 SCLK RCC_SCL 12,15,27,41,48,69
G2 H23 B_IMB_D_R3 AB10
GND VCC3 B_IMB_D_R4 IMBD_ T3
H21 GND VCC3 H3 AE10 IMBD_T4 PCLKFB AD3 P2FBCLK 40
H5 J21 B_IMB_D_R5 AE9 AE2
GND VCC3 IMBD_ T5 SCLK_FB S2FBCLK 40
J24 J5 B_IMB_D_R6 AD10 AC4
GND VCC3 IMBD_ T6 CLKIN PCICLK_CIOB2 23
J2 K23 B_IMB_D_R7 AE11 AB3 S2CLKO_R R749 22
GND VCC3 IMBD_T7 SCLK_O S2CLKO 40
L24 K3 B_IMB_D_R8 AC9 AA4 P2CLKO_R R750 22
GND VCC3 IMBD_T8 PCLK_O P2CLKO 40
L21 M23 B_IMB_D_R9 AD6
GND VCC3 B_IMB_D_R10 IMBD_T9
L15 GND VCC3 M21 AE6 IMBD_ T10 PCIRST# D17
L14 M5 B_IMB_D_R11 AB9 AA3
GND VCC3 B_IMB_D_R12 IMBD_T11 PLLRST
3 L13 GND VCC3 M3 AE7 IMBD_ T12
3
L12 P23 B_IMB_D_R13 AB8 AB5
GND VCC3 IMBD_ T13 ALERT ALERT# 11,15,27,50
L11 P3 B_IMB_D_R14 AB7
GND VCC3 B_IMB_D_R15 IMBD_T14 VREF_IMB_CIOB2
L5 GND VCC3 R21 AA6 IMBD_ T15 VREFIMB0 AD12
L2 GND VCC3 R5
M15 GND VCC3 T23
M14 GND VCC3 T3
M13 U21 CIOBX2
GND VCC3
M12 GND VCC3 U5
M11 V23 PS_PWRGD# R1931 0
GND VCC3 11,27,50,64 PS_PWRGD#
N24 GND VCC3 V3
N15 Y23 PCIRST1#
GND VCC3 11,27,65 PCIRST1#
N14 GND VCC3 Y21
N13 Y5 VDD_IMB
GND VCC3
N12 GND VCC3 Y3
N11 AA20 VDD_IMB
GND VCC3
N2 GND VCC3 AB22
P21 GND VCC3 AB4
P15 AD24 C1620 C1621 C1622 C1623
GND VCC3 C1624 C1625 C1626 C1627 C1628 C1629 C1630 C1631 C1632 C1633 C1634
P14 GND VCC3 AD21
P13 AD2 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V
GND VCC3 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
P12 GND
P11 GND VDD25 K16
P5 K15 VCC25
GND VDD25
R24 K14
GND VDD25 VCC25
K13
VDD25 VDD_IMB
R15 GND VDD25 K12
R14 K11 VDD_IMB
GND VDD25 VCC3
2 R13 GND VDD25 K10 2
R12 L16
GND VDD25 C948 C949 C950 C951 C1719
C947
C946
100_1%
R11 L10 + +
GND VDD25 +
R1317
R2 GND VDD25 M16

U24 M10 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V
GND VDD25 C934 C935 C936 C937
U2 GND VDD25 N16
V21 GND VDD25 N10
V5 P16 VREF_IMB_CIOB2 1.0uF/16V 1.0uF/16V 1.0uF/16V 1.0uF/16V
GND VDD25
W24 GND VDD25 P10
100_1%
W2 GND VDD25 R10

220pF
220pF
AA24 GND VDD25 T16

AA21 T15
1.0uF/10V
GND VDD25 VCC25 VCC25

AA18 GND VDD25 T14
C1507
AA16 GND VDD25 T13

C1505
C1506
R1318
AA14 GND VDD25 T12

AA12 GND VDD25 T11
AA10 GND VDD25 T10
AA8 R16 C956 C957 C958 C959 C960 C961 C962 C963 C952 C953 C954 C955
GND VDD25
AA5 GND
AA2 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.1uF 1.0uF/16V
GND
AC23 GND
AC20 GND
AC3 GND
AD19 GND
AD17 GND
AE5 GND
AD15GND
AD13GND
AD11GND
AD9 GND
AD7 GND
AE25GND
AE1 GND
1 VCC3 1
C938 C939 C940 C941 C942 C943 C944 C945 + C1720 + C1637
Title Rev
CIOBX2 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF CIOBX2_IMB_PWR
Document Number 0A

A B C D E
www.vinafix.vn
A B C D E
VCC3
P2_GNT#6 S2_GNT#5
VCC3
0 = Disable Pri Hot-Plug
0 = Disable Sec Hot-Plug
Do not stuff
VCC3
P2_GNT#0
Do not stuff
RES_NOPOP
1 = Enable Pri
RES_NOPOP
1: APLL Enabled ( * ) 1 = Enable Sec Hot-Plug
2.2K
R775
Hot-Plug
R776
0: APLL Disabled Controller Controller
R756
4 4
P2_GNT#0 P2_GNT#6
Do not stuff
P2_GNT#0 36,44 P2_GNT#6 36,44

S2_GNT#5
S2_GNT#5 36,44
RES_NOPOP
R757
R778
2.2K
R779
2.2K
VCC3
Do not stuff
CIOB ID For I2C Bus
RES_NOPOP
2.2K
RES_NOPOP
GNT1=LOW, S2_GNT#3
R758
3 3
GNT2=HIGH,
GNT3=LOW,
P2_GNT#5 0 = PCI-X 133
VCC3
ID=2 1 = PCI-X 100
VCC3 0 = PCI-X 133
1 = PCI-X 100
[ Refer to table
R759
R760
8.2K
8.2K
on sheet #30 ]
[ Refer to table
P2_GNT#1
R1350
P2_GNT#2
P2_GNT#1 36,41,44
R1394 on sheet #30 ]
P2_GNT#2 36,44 JP29
P2_GNT#3
P2_GNT#3 36,44 JP30 S2_GNT#3
Please refer to 'CMIC
2.2K
2 S2_GNT#3 36,44
P2_GNT#5
R762NOPOP
2.2K
2 P2_GNT#5 36,44 1
R761
1 HDR_1X2 STRAPPING OPTIONS' sheet

HDR_1X2
R763
for following strappings
1K
1K
in CIOB-x2
R1351
Do not stuff
R1395
IMB - DETERMINISTIC/ NON

: - DETERMINISTIC
2
: - IMB CRC or PARITY 2
: - IMB_TRAINING Enable/Disable
S2_GNT#1
1: Prim. PCI func. registers
S2_GNT#0
VCC3 will be accessed at Func.#0
and Sec. PCI at Func.#2 VCC3 1: All bits of Func. # VCC3
S2_GNT#2
2.2K
0: Prim. PCI func. registers used for reg. access

2.2K
will be accessed at Func.#2 0: Only bit 0 of Func. # IMB_READ/WRITE POINTER DLY

and Sec. PCI at Func.#0 used for reg. access
R1844
2.2K
1 : 5 CLOCKs ( Default )
R1352
0 : 6 CLOCKs
R777
S2_GNT#1
S2_GNT#1 36,44,45
S2_GNT#0 S2_GNT#2
1 S2_GNT#0 36,44,45 S2_GNT#2 36,44 1
R1845
RES_NOPOP
Do not stuff
RES_NOPOP

R1353
RES_NOPOP
R780
Title Rev
CIOBX2_STRAPPING_OPTIONS
Document Number 0A

A B C D E
www.vinafix.vn
A B C D E
4 P1CLKO 4
27 P1CLKO
VCC3 U98
1 3 P1FBCLKR R730 22 P1FBCLK
CLKIN 1Y0 P1FBCLK 27
R729 1K
FB_11_OHM_100MHz 2 5 P1SL1CLKR R731 22 PCICLK_P1_SLT1
VCC3 OE 1Y1 PCICLK_P1_SLT1 29
L29
1 2 PCICLK_BUFF1_VDD 6 7 P1SL2CLKR R732 100
VCC3 1Y2
4 GND 1Y3 8
C920 + C921 C915
0.1uF
4.7uF/10V/20% 0.01uF CDCV304
100
R735
3 3
S1CLKO
27 S1CLKO
U99
1 3 S1FBCLKR R739 22 S1FBCLK
VCC3 CLKIN 1Y0 S1FBCLK 27
2
R738 1K 2
FB_11_OHM_100MHz 2 5 S1SL1CLKR R740 22 PCICLK_S1_SLT1
VCC3 OE 1Y1 PCICLK_S1_SLT1 30
L30
1 2 PCICLK_BUFF2_VDD 6 7 S1SL2CLKR R741 22
VCC3 1Y2
4 GND 1Y3 8
C925
C929 + C931 0.1uF
0.01uF CDCV304
4.7uF/10V/20%
100
R744
1 1

Title Rev
CIOBX1_CLK_BUFF
Document Number 0A

A B C D E
www.vinafix.vn
A B C D E
U96 R716 22
4 P2CLKO 1 3 P2CLKFBR P2FBCLK 4
37 P2CLKO CLKIN 1Y0 P2FBCLK 37
R715 1K
2 5 P2SL1CLKR R717 22 PCICLK_P2_SLT1
VCC3 OE 1Y1 PCICLK_P2_SLT1 44
VCC3 6 7 BCMCLKR BCM5701_PCICLK
VCC3 1Y2 BCM5701_PCICLK 41
FB_11_OHM_100MHz 4 8 R718 22
GND 1Y3
L27
1 2 PCICLK_BUFF3_VDD
CDCV304
C901
0.1uF
C906 + C907
0.01uF
4.7uF/10V/20% R721
100
3 3
U97 R723 22
S2CLKO 1 3 S2FBCLKR S2FBCLK
37 S2CLKO CLKIN 1Y0 S2FBCLK 37
R722 1K
2 5 S2SL1CLKR R724 22 PCICLK_S2_SLT1
VCC3 OE 1Y1 PCICLK_S2_SLT1 45
6 7 S2SL2CLKR PCICLK_S2_SLT2
VCC3 VCC3 1Y2 PCICLK_S2_SLT2 45
2
FB_11_OHM_100MHz 2
L28 4 8 R725 22
PCICLK_BUFF4_VDD GND 1Y3
1 2
CDCV304
C912 C908
+ C914 0.1uF
4.7uF/10V/20% 0.01uF
R728
100
1 1

Title Rev
CIOBX2_CLK_BUFF
Document Number 0A

A B C D E
www.vinafix.vn
5 4 3 2 1
VCC25
36,44 P2_AD[0..63] RESs place next to BCM5701 Pins
P2_AD0
P2_AD1
P2_AD2
P2_AD3
P2_AD4
P2_AD5
P2_AD6
P2_AD7
P2_AD8
P2_AD9
P2_AD10
P2_AD11
P2_AD12
P2_AD13
P2_AD14
P2_AD15
P2_AD16
P2_AD17
P2_AD18
P2_AD19
P2_AD20
P2_AD21
P2_AD23
P2_AD24
P2_AD25
P2_AD26
P2_AD27
P2_AD28
P2_AD29
P2_AD30
P2_AD31
P2_AD32
P2_AD34
P2_AD35
P2_AD36
P2_AD37
P2_AD38
P2_AD39
P2_AD40
P2_AD41
P2_AD42
P2_AD43
P2_AD44
P2_AD45
P2_AD46
P2_AD47
P2_AD48
P2_AD49
P2_AD50
P2_AD51
P2_AD52
P2_AD53
P2_AD54
P2_AD55
P2_AD56
P2_AD57
P2_AD58
P2_AD59
P2_AD60
P2_AD61
P2_AD62
P2_AD63
P2_AD22
P2_AD33
CTD
U10
T10
W9
W7
W3
W4
W1
R1862 R1863 R1864 R1865 R1866 R1867 R1868 R1869 X_RJ45_SMT
M4
M2
M1
G1
N2
R2
R1
N3
N1
H1
H4
D4
D3
D5
U9
U8
U7
U6
U5
U4
R5
R4
U3
R3
K3
A2
E2
A1
B2
E4
E5
B5
A4
V9
V4
V2
Y8
Y6
Y5
Y3
Y4
Y2
Y1
F3
F2
F4
F5
T6
T5
T4
T3
T2
L5
L3
L4
L2
J5
U197A 49.9 49.9 49.9 49.9 49.9 49.9 49.9 T1
49.9
11
12
1 24 CTL3 J52
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AD39
AD40
AD41
AD42
AD43
AD44
AD45
AD46
AD47
AD48
AD49
AD50
AD51
AD52
AD53
AD54
AD55
AD56
AD57
AD58
AD59
AD60
AD61
AD62
AD63
TRD3- CTD3 CTL3 TRLM3
D
2 TRD3- TRL3- 23 8 D
3 22 TRLP3 7
TRD3+ TRL3+ CTL2
V16 RXD9 4 CTD2 CTL2 21 6
Y18 A13 5 20 TRLM2 5
RXD8 TRD3N TRD3+ TRD2- TRL2- TRLP2
Y20 RXD7 TRD3P A12 6 TRD2+ TRL2+ 19 4
V17 B12 TRD2- 7 18 CTL1 3
RXD6 TRD2N TRD2+ CTD1 CTL1 TRLM1
W20 RXD5 TRD2P B13 8 TRD1- TRL1- 17 2
U16 A15 TRD1- 9 16 TRLP1 1
RXD4 TRD1N TRD1+ TRD1+ TRL1+ CTL0
W19 RXD3 TRD1P A14 10 CTD0 CTL0 15
V18 B14 TRD0- 11 14 TRLM0
RXD2 TRD0N TRD0- TRL0-
10
B15 TRD0+ 12 13 TRLP0
9
TRD0P TRD0+ TRL0+
H5007
Y16 RXD0 CAPS place next
LINK
R1870
R1871
R1872
R1873
V15 RXD1 Link_Led_B B10 to CT pins
Y17 RXCLK0
U14 BCM5701_300H2BGA E9 LINK1000
RXCLK1 Spd1000ledb C2027 C2028 C2029 C2030
P18 CRS
P17 E11 LINK100
COL Spd100ledb 1000pF 75 75 75 75
D10 TRAFFIC 1000pF 1000pF 1000pF
Trafficledb
T14 TXD9
W13 TXD8
Y13 J18 C2031
TXD7 regpnp_sense_I_1_3v Layout Require at least 1 Square inch of X_1000PF_3KV
V12 TXD6
W12 J20 Copper at Pin 2 and 4 for heat dissipation.
TXD5 regpnp_cnt_I_1_3v
V11 TXD4
T12 TXD3 regpnp_supply_I_1_3v J19
W11 V18_1
TXD2
C DPAK SIZE C
Y14 H18 1_8V OUT

TX_CLKIN regpnp_sense_I_1_8v
Y15 TX_CLKOUT
T13 H19 REGCTL18 C4 +
C2036 C2037
TXD0 regpnp_cnt_I_1_8v
V13 TXD1
MJD45H11_CASE369A-13 1 Q33 V33_1
E1 H17 B 3 10UF .01uF
NC1 regpnp_supply_I_1_8v E
N17 +
C2038 C2039
MDIO
P20 MDC
J2 10UF .01uF
NC2
P19 LINKRDY regpnp_sense_I_2_5v B11
regpnp_cnt_I_2_5v D11
XTALI K17
R1941 XTALI
regpnp_supply_I_2_5v C11
XTALO 200 XTALOR K18 XTALO
Place all LEDs at the edge of NIC card
R20 SMB_DATA
D15
PCI_RST#
U15 SMB_CLK
H16 EE_DATA
DEVSEL#
RDAC
PCI_CLK
FRAME#
G16 EE_CLK
REQ64#
C_BE_0
C_BE_1
C_BE_2
C_BE_3
C_BE_4
C_BE_5
C_BE_6
C_BE_7
ACK64#
F20 MODE0
G19 MODE1
F17 MODE2
F19 MODE3
PERR#
SERR#
M66EN
STOP#
TRDY#
PAR64
TRST#
D20 GPIO0
G18 GPIO1
G17 GPIO2
IRDY#
IDSEL
INTA#
PME#
REQ#
GNT#
TCLK
TMS
TDO
PAR
C2042 15PF V33_1
TDI
1
LINK1000 R1886 150 LED1000
E10
1 2
G4
G5
C8
C5
C6
H3
C1
H5
D1
U1
C9
D8
D9
K1
K4
B1
E3
V1
P3
P2
P5
E7
B4
E6
K5
P4
E8
F1
T1
J4
J3
Y4 LINK1000 D49
R1887 R1888
B B
330K LINK100 R1889 150 LED100 1 2
1.24K_1% JTRST#
LINK100 D50
JTCLK
JTDO
JTMS
JTDI
C2045 15PF
2
MODE1
25MHZ_CRYSTAL LINK R1936 150 LEDLINK 1 2

Place Y1 close to V33_1 LINK10 D57
4.7K
4.7K
4.7K
4.7K
BCM5701
0 0 TRAFFIC R1893 150 LEDTRAFFIC 1 2
BCM5701_PCICLK
BCM5701_GPIO0
BCM5701_GPIO1
BCM5701_GPIO2
TRAFFIC LED D52
BCM5701_PME#
R1890
R1891
P2_CBE#0
P2_CBE#1
P2_CBE#2
P2_CBE#3
P2_CBE#4
P2_CBE#5
P2_CBE#6
P2_CBE#7
R1894 R1899 U199

P2_DEVSEL#
P2_PCIRST#
P2_FRAME#
P2_REQ64#
P2_ACK64#
8 1 ESD1,ESD2 are optional protection diodes for cable ESD

P2_TRDY#
P2_PAR64
P2_M66EN
P2_REQ#1
P2_PERR#
P2_SERR#
P2_GNT#1
P2_STOP#
VCC A0
P2_IRDY#
PCIIRQ#0
P2_CBE#[0..7] 36,44 7 WP A1 2
P2_PAR
1K V33_1
GB_EN
C2046
R1896
R1898
6 SCL A2 3
P2_CBE#0 1K D53
R1895
R1897
5 SDA GND 4
P2_CBE#1 TRD1-
P2_CBE#2 .01uF AT24C512 ESD1
P2_CBE#3 TRD1+
P2_CBE#4 POP Value: BAV70
P2_CBE#5 X_BAV70_NOPOP
P2_CBE#6 BCM_EE_SCL D54
P2_CBE#7 TRD0-
BCM_EE_SDA ESD2
TRD0+
BCM5701_PME# 43 BCM5701_GPIO0
BCM5701_PME# 58 43 BCM5701_GPIO2
P2_M66EN X_BAV70_NOPOP
P2_M66EN 36,44
P2_PCIRST#
P2_PCIRST# 36,44 RCC_SDA 12,15,27,37,48,69
P2_FRAME# VCC3 BCM5701_GPIO1 TP11
P2_FRAME# 36,44 1 RCC_SCL 12,15,27,37,48,69
P2_DEVSEL#
P2_DEVSEL# 36,44
P2_IRDY# PCIIRQ#0 JTDO TP12
P2_IRDY# 36,44 PCIIRQ#0 50 1
P2_PERR#
P2_PERR# 36,44,50
A P2_TRDY# P2_REQ#1 A
P2_TRDY# 36,44 P2_REQ#1 36,44
P2_SERR# 2.7K R1992 P2_PCIRST# C2194 X_104P
P2_SERR# 36,44,50
P2_PAR P2_GNT#1
P2_PAR 36,44 P2_GNT#1 36,38,44
P2_STOP# 8.2K R1993
P2_STOP# 36,44
P2_REQ64#
P2_PAR64
P2_REQ64# 36,44
C2121 X_10P BCM5701_PCICLK
BCM5701_PCICLK 40 JGB1 Micro Star Restricted Secret
P2_PAR64 36,44
P2_ACK64# P2_AD19 Title Rev
P2_ACK64# 36,44 1
GB_EN R1900 2K BCM5701 SIGNAL PINS
2 Document Number 0A
3
JGb_1-2 MICRO-STAR INT'L CO.,LTD. Last Revision Date:
YJ103 Tuesday, August 21, 2001
YJUMPER-MG No. 69, Li-De St, Jung-He City,
5 4 3 2 1
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5 4 3 2 1
VCC25
Place CAP close to BIASVDD pin
R1859 0
3V_STBY
C1962
.1uF V18_1 VCC3 V33_1
AVDD25
VCC3 AVDD18
R1930
D D
V18_PLL
D7 4.7K
V13_1
W14
W15
W16
W18
M20
G20
D14
C13
C14
D12
D13
C10
H20
N18
U13
E13
E14
A16
A17
A11
E12
A10
E20
Y12
Y19
Y10
Y11
L16
L17
L18
L19
J16
W2
W5
W6
W8
M5
M3
G2
G3
D6
N5
C2
C3
D2
H2
N4
U2
B6
A6
A8
B9
K2
V6
V7
V8
A3
A5
B3
P1
V3
V5
A9
Y7
Y9
T7
T8
T9
L1
J1
U197B
VESD1
VESD2
VESD3
AVDD25_1
AVDD25_2
AVDD25_3
AVDD18_1
AVDD18_2
AVDD18_3
AVDD18_4
AVDD18_5
BIASVDD
PCIVDDIO1
PCIVDDIO2
PCIVDDIO3
PCIVDDIO4
PCIVDDIO5
PCIVDDIO6
PCIVDDIO7
PCIVDDIO8
PCIVDDIO9
PCIVDDIO10
PCIVDDIO11
PCIVDDIO12
PCIVDDIO13
PCIVDDIO14
PCIVDDIO15
PCIVDDIO16
PCIVDDIO17
PCIVDDIO18
PCIVDDIO19
PCIVDDIO20
PCIVDDIO21
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
Vaux_Prsnt
VDDCORE1
VDDCORE2
VDDCORE3
VDDCORE4
VDDCORE5
VDDCORE6
VDDCORE7
VDDCORE8
VDDCORE9
VDDCORE10
VDDCORE11
VDDCORE12
VDDCORE13
VDDCORE14
VDDCORE15
VDDCORE16
VDDCORE17
VDDCORE18
VDDCORE19
VDDCPRE20
VDDCPRE21
VDDCPRE22
M16 LVDD1
M17 LVDD2 GMAC_AVDD_PLLVDD3 V10
M18 LVDD3
M19 VCC3
LVDD4
N16 LVDD5 GPHY_PLLVDD2 K20
N19 BCM5701_300H2BGA
LVDD6
N20 LVDD7 V18_1
U12 LVDD8 PCIPLL_AVDD_PLLVDD1 B8
U11 LVDD9
V14 LVDD10
W17 B7
PCIPLL_AGND_1
LVDD11 PCIPLL_A3VDD
W10 GMAC_AGND_1
J17 GPHY_PLLGND
PCIPLL_TVCOI
T11 GMAC_TVCOI
K19 GPHY_TVCOI
L20
K16 XTALGND
C15 BIASGND
XTALVDD_VDDC
C C
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
Place these CAPs and L2 close to

V18_1 power pins of BCM5701
C12
C16
C17
C18
C19
C20
D16
D17
D18
D19
R16
R17
R18
R19
U17
U18
U19
U20
A18
A19
A20
B16
B17
B18
B19
B20
E15
E16
E17
E18
E19
P16
V19
V20
F16
F18
T15
T16
T17
T18
T19
T20
C4
C7
A7
R1858 0
V18_PLL
L62
1 2
C1964 C1965 600Ohm_100Mhz

C1963
3V_STBY 100PF
1000pF 1000pF
C2217 V18_1
103P
R1860 0 Place these CAPs and L3 close
V18_1 AVDD18 to power pins of BCM5701
V13_1 L63
1 2
B C1971 C1972 C1967 C1968 600Ohm_100Mhz B

C1973 C1974 C1975 C1976 C1977 C1978 C1979 C1980 C1981 C1982 C1984 C1985 C1986 C1987 C1966
+ EC59
100PF 100PF 100PF .1uF .1uF .1uF .1uF .1uF .1uF .1uF 47U/10V/S .1uF .1uF .1uF .1uF 100PF
1000pF 1000pF 1000pF 1000pF
Place these CAPs close

Place these CAPs close V33_1 to power pins of VCC25
Place these CAPs close to power pins of BCM5701
to power pins of BCM5701 R1861 0
Place these CAPs and L4 close
BCM5701 to power pins of BCM5701
C1994 C1995 C1996 C1997 C1998 C1999 C2000 C2001 C2002 C2003 C2004 C2005 AVDD25 L64
+ EC60 1 2
100PF 100PF 100PF .01uF .1uF .1uF .1uF .1uF .1uF .1uF .1uF .1uF 47U/10V/S
C1970 600Ohm_100Mhz
+
C1969
2_2UF
1000pF
Place these CAPs close VCC3

A
to power pins of A
BCM5701
C2013 C2014 C2015 C2016 C2017 C2018 C2019 C2020 C2021 C2022 C2023 C2024 C2025
C2008 C2009 C2010 C2011 C2012 Title Rev
+ EC61 BCM5701 POWER PINS
.1uF .1uF .1uF .1uF .1uF .01uF .01uF .01uF .01uF .01uF .01uF .01uF .01uF .01uF .01uF .01uF .01uF .01uF 47U/10V/S Document Number 0A

5 4 3 2 1
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5 4 3 2 1
VCC3
Q25 V33_1
8 D S 1
7 2
6 3
5
D D
R1848 G SI4465
R1849
4
4.7K
D 3
Q27
1 2 2N7002 4.7K
41 BCM5701_GPIO2 G S
R1850
100K
Q28A Q28B
3V_STBY 1 S
7VAUXM 5 3
8 6 S
D D
R1853
C1961 G G 4.7K
+
C1960 SI4965DY
4
R1855
2_2UF 4.7K
1000pF
VAUXIN_EN*
C C
D 3 VCC3
Q29
41 BCM5701_GPIO0 1 22N7002
G S
R1856
D 3
Q30
1 22N7002
G S 4.7K
VAUX18_EN*
R1857
10K
V18_1
D 3
Q31 MOSF1N02
1 2
G S
B Option for WOL Circuit B
Need to use an External Voltage Regulator only for Pass1 of BCM5701, attached items can be removed on the next pass.
V13_1
VCC25
50Ohm_100Mhz
U201 L65
8 1 V13_OUT 1 2
IN OUT V13_ADJ 75RST R1934
5 SHDN_N SENSE/ADJ 2
C2054 C2055 7 6
+ GND0 GND2
4 3 C2056 C2057
0.01uF NC GND1 R1935 +
10UF LT1963ES8
1K _1% 10UF
1000pF
A A

Title Rev
VOUT=1.21(1+R2/R1)+(IADJ)(R2) BCM5701 POWER GEN
IADJ=3 UA at 25 Document Number 0A

5 4 3 2 1
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A B C D E
VCC3 VCC3
VCC VCC VCC3
-12V PCI SLOT6 +12V_IO 36,41 P2_REQ#[0..6]
PDOWN0 J27 R697 8.2K P2_REQ#0 P2_REQ#1 2K7 R1902
R698 B1 A1 P2_REQ#1 P2_REQ#2 2K7 R1903
VCC 2K7 R696
B2 A2 P2_REQ#2 P2_M66EN
B3 A3 PDOWN0 P2_REQ#4 R1842
1K B4 A4 P2_REQ#6 P2_PAR64 2K7
B5 A5 P2_REQ#3 RP2K7
B6 A6 PCIIRQ#10
PCIIRQ#10 50
P2_REQ#5 P2_REQ#0 1 RP341 8
PCIIRQ#11 B7 A7 2 7
50 PCIIRQ#11
4 B8 A8 P2_SL1_PRSNT#2 3 6 4
P2_SL1_PRSNT#1 B9 A9 P2_SL1_PRSNT#1 4 5
B10 A10
P2_SL1_PRSNT#2 B11 A11 3VSB VCC3 VCC RP2K7
1 RP342 8
2 7
B14 A14 P2_REQ64# 3 6
B15 A15 P2_PCIRST# P2_ACK64# 4 5
P2_PCIRST# 36,41
PCICLK_P2_SLT1 B16 A16 EC62
40 PCICLK_P2_SLT1 + RP2K7
B17 A17 P2_GNT#0 EC63 EC64
P2_GNT#0 36,38
P2_REQ#0 B18 A18 + + 1 RP343 8
B19 A19 P2_PCI_PME# 1000U/6.3V P2_PAR 2 7
P2_PCI_PME# 58
P2_AD31 B20 A20 P2_AD30 1000U/6.3V 1000U/6.3V P2_SERR# 3 6
P2_AD29 B21 A21 P2_SBO# 4 5
B22 A22 P2_AD28
P2_AD27 B23 A23 P2_AD26 RP2K7
P2_AD25 B24 A24 P2_REQ#4 1 RP344 8
B25 A25 P2_AD24 P2_REQ#6 2 7
P2_CBE#3 B26 A26 P2_IDSEL0 P2_REQ#3 3 6
P2_AD23 B27 A27 R699 P2_AD18 P2_REQ#5 4 5
B28 A28 P2_AD22
P2_AD21 B29 A29 P2_AD20 2K RP2K7
P2_AD19 B30 A30 VCC3 P2_DEVSEL# 1 RP345 8
B31 A31 P2_AD18 P2_TRDY# 2 7
P2_AD17 B32 A32 P2_AD16 P2_IRDY# 3 6
P2_CBE#2 B33 A33 P2_FRAME# 4 5
B34 A34 P2_FRAME# C870 C871 C872 C873 C874
P2_FRAME# 36,41 RP2K7
P2_IRDY# B35 A35
36,41 P2_IRDY#
3 B36 A36 P2_TRDY#
P2_TRDY# 36,41
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF P2_SDONE 1 RP346 8 3
P2_DEVSEL# B37 A37 P2_PERR# 2 7
36,41 P2_DEVSEL#
P2_PCIXCAP B38 A38 P2_STOP# P2_PLOCK# 3 6
36 P2_PCIXCAP P2_STOP# 36,41
P2_PLOCK# B39 A39 P2_STOP# 4 5
36 P2_PLOCK#
P2_PERR# B40 A40 P2_SDONE C875 C876 C877 C878 C879
36,41,50 P2_PERR#
B41 A41 P2_SBO#
P2_SERR# B42 A42 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF RP8K2
36,41,50 P2_SERR#
B43 A43 P2_PAR
P2_PAR 36,41
P2_AD35 1 RP347 8
P2_CBE#1 B44 A44 P2_AD15 VCC P2_AD33 2 7
P2_AD14 B45 A45 P2_AD34 3 6
B46 A46 P2_AD13 P2_AD32 4 5
P2_AD12 B47 A47 P2_AD11 C880 C881 C882 C883 C884
P2_AD10 B48 A48 RP8K2
B49 A49 P2_AD9 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF P2_AD37 1 RP348 8
P2_M66EN B50 A50 P2_AD36 2 7
36,41 P2_M66EN
B51 A51 P2_AD38 3 6
C868 P2_AD8 B52 A52 P2_CBE#0 P2_AD39 4 5
P2_AD7 B53 A53 RP8K2
0.01uF B54 A54 P2_AD6 P2_AD40 1 RP349 8
P2_AD5 B55 A55 P2_AD4 P2_AD42 2 7
P2_AD3 B56 A56 P2_CBE#0 P2_AD41 3 6
B57 A57 P2_AD2 P2_CBE#1 P2_AD43 4 5
P2_AD1 B58 A58 P2_AD0 P2_CBE#2 RP8K2
B59 A59 P2_CBE#3 P2_AD44 1 RP350 8
P2_ACK64# B60 A60 P2_REQ64# P2_CBE#4 P2_AD45 2 7
36 P2_ACK64# P2_REQ64# 36,41
B61 A61 P2_CBE#5 P2_AD46 3 6
B62 A62 P2_CBE#6 P2_AD47 4 5
P2_CBE#7 RP8K2
2
P2_AD48 1 RP351 8 2
B63 A63 P2_AD50 2 7
B64 A64 P2_CBE#7 P2_AD49 3 6
P2_CBE#6 P2_CBE#5 36,41 P2_CBE#[0..7] P2_AD51
B65 A65 4 5
P2_CBE#4 B66 A66 RP8K2
B67 A67 P2_PAR64
P2_PAR64 36,41
P2_AD52 1 RP352 8
P2_AD63 B68 A68 P2_AD62 P2_AD53 2 7
P2_AD61 B69 A69 VCC3 P2_AD54 3 6
B70 A70 P2_AD60 P2_AD55 4 5
36,38,41 P2_GNT#[0..6] RP8K2
P2_AD59 B71 A71 P2_AD58
P2_AD57 B72 A72 P2_GNT#0 RN31 1 2 8P4R-4.7K P2_AD56 1 RP353 8
B73 A73 P2_AD56 P2_GNT#2 3 4 P2_AD57 2 7
P2_AD55 B74 A74 P2_AD54 P2_GNT#3 5 6 P2_AD58 3 6
P2_AD53 B75 A75 P2_GNT#1 7 8 P2_AD59 4 5
B76 A76 P2_AD52 RP8K2
P2_AD51 B77 A77 P2_AD50 P2_GNT#4 R2105 4.7K P2_AD60 1 RP354 8
P2_AD49 B78 A78 P2_AD61 2 7
B79 A79 P2_AD48 P2_GNT#5 R2106 4.7K P2_AD63 3 6
P2_AD47 B80 A80 P2_AD46 P2_AD62 4 5
P2_AD45 B81 A81 P2_GNT#6 R2107 4.7K RP8K2
B82 A82 P2_AD44 P2_CBE#4 1 RP355 8
36,38,45 S2_GNT#[0..5] P2_CBE#5
P2_AD43 B83 A83 P2_AD42 2 7
P2_AD41 B84 A84 S2_GNT#2 RN32 1 2 8P4R-4.7K P2_CBE#6 3 6
B85 A85 P2_AD40 S2_GNT#3 3 4 P2_CBE#7 4 5
P2_AD39 B86 A86 P2_AD38 S2_GNT#1 5 6
P2_AD37 B87 A87 S2_GNT#0 7 8
B88 A88 P2_AD36
P2_AD35 B89 A89 P2_AD34 S2_GNT#4 R2108 4.7K
P2_AD33 B90 A90
1 S2_GNT#5 R2109 4.7K 1
B91 A91 P2_AD32
B92 A92
B93 A93
B94 A94 Micro Star Restricted Secret
Title Rev
CONN_PCI64_3_3V_SOCKET CIOBX2_PCIXP2_SLOT1
Document Number 0A
36,41 P2_AD[0..63]
A B C D E
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A B C D E
VCC3 VCC3
VCC VCC
PDOWN4 -12V PCI SLOT5 +12V_IO
VCC3 VCC3 J26 R1769 8.2K
VCC VCC R1770 B1 A1 VCC3
VCC
PDOWN3 -12V PCI SLOT4 +12V_IO B2 A2
J25 R690 8.2K B3 A3 PDOWN4
R692 B1 A1 VCC 1K B4 A4
B2 A2 B5 A5 S2_M66EN R689 2K7
B3 A3 PDOWN3 B6 A6 PCIIRQ#12 S2_PAR64 R1843 2K7
PCIIRQ#12 50
1K B4 A4 PCIIRQ#13 B7 A7
50 PCIIRQ#13 RP2K7
B5 A5 B8 A8
B6 A6 PCIIRQ#14
PCIIRQ#14 50
S2_SL2_PRSNT#1 B9 A9 S2_SL1_PRSNT#2 1 RP326 8
4 PCIIRQ#15 B7 A7 B10 A10 3VSB S2_SL2_PRSNT#2 2 7 4
50 PCIIRQ#15
B8 A8 S2_SL2_PRSNT#2 B11 A11 S2_SL2_PRSNT#1 3 6
S2_SL1_PRSNT#1 B9 A9 S2_SL1_PRSNT#1 4 5
B10 A10
S2_SL1_PRSNT#2 B11 A11 3VSB B14 A14
B15 A15 S2_PCIRST# S2_ACK64# R1904 2K7
PCICLK_S2_SLT2 B16 A16 S2_REQ64# R1905 2K7
40 PCICLK_S2_SLT2 2K7
B14 A14 B17 A17 S2_GNT#1 S2_SBO# R1906
S2_GNT#1 36,38,44 2K7
B15 A15 S2_PCIRST# S2_REQ#1 B18 A18 S2_SDONE R1910
S2_PCIRST# 36 36 S2_REQ#1
PCICLK_S2_SLT1 B16 A16 B19 A19 S2_PCI_PME#
40 PCICLK_S2_SLT1
B17 A17 S2_GNT#0 S2_AD31 B20 A20 S2_AD30
S2_GNT#0 36,38,44 2K7
S2_REQ#0 B18 A18 S2_AD29 B21 A21 S2_FRAME# R1907
36 S2_REQ#0 2K7
B19 A19 S2_PCI_PME# B22 A22 S2_AD28 S2_REQ#1 R1908
S2_PCI_PME# 58 2K7
S2_AD31 B20 A20 S2_AD30 S2_AD27 B23 A23 S2_AD26 S2_REQ#0 R1909
S2_AD29 B21 A21 S2_AD25 B24 A24
B22 A22 S2_AD28 B25 A25 S2_AD24 2K
S2_AD27 B23 A23 S2_AD26 S2_CBE#3 B26 A26 S2_IDSEL1 R1771 S2_AD19 RP2K7
S2_AD25 B24 A24 S2_AD23 B27 A27 36 S2_REQ#5
S2_REQ#4 1 RP329 8
B25 A25 S2_AD24 B28 A28 S2_AD22 S2_REQ#2 2 7
36 S2_REQ#2
S2_CBE#3 B26 A26 S2_IDSEL0 S2_AD21 B29 A29 S2_AD20 S2_REQ#5 3 6
36 S2_REQ#4
S2_AD23 B27 A27 R1772 S2_AD18 S2_AD19 B30 A30 S2_REQ#3 4 5
36 S2_REQ#3
B28 A28 S2_AD22 B31 A31 S2_AD18
S2_AD21 B29 A29 S2_AD20 2K S2_AD17 B32 A32 S2_AD16 RP2K7
S2_AD19 B30 A30 S2_CBE#2 B33 A33 S2_STOP# 1 RP330 8
B31 A31 S2_AD18 B34 A34 S2_FRAME# S2_DEVSEL# 2 7
S2_AD17 B32 A32 S2_AD16 S2_IRDY# B35 A35 S2_TRDY# 3 6
S2_CBE#2 B33 A33 B36 A36 S2_TRDY# S2_IRDY# 4 5
B34 A34 S2_FRAME# S2_DEVSEL# B37 A37
S2_FRAME# 36 RP2K7
3 S2_IRDY# B35 A35 S2_PCIXCAP B38 A38 S2_STOP# 3
36 S2_IRDY#
B36 A36 S2_TRDY#
S2_TRDY# 36
S2_PLOCK# B39 A39 S2_PAR 1 RP331 8
S2_DEVSEL# B37 A37 S2_PERR# B40 A40 S2_SDONE S2_SERR# 2 7
36 S2_DEVSEL#
B38 A38 S2_STOP# B41 A41 S2_SBO# S2_PERR# 3 6
36 S2_PCIXCAP S2_STOP# 36
S2_PLOCK# B39 A39 S2_SERR# B42 A42 S2_PLOCK# 4 5
36 S2_PLOCK#
S2_PERR# B40 A40 S2_SDONE B43 A43 S2_PAR
36,50 S2_PERR#
B41 A41 S2_SBO# S2_CBE#1 B44 A44 S2_AD15
S2_SERR# B42 A42 S2_AD14 B45 A45 RP8K2
36,50 S2_SERR#
B43 A43 S2_PAR
S2_PAR# 36 B46 A46 S2_AD13 S2_AD32 1 RP332 8
S2_CBE#1 B44 A44 S2_AD15 S2_AD12 B47 A47 S2_AD11 S2_AD34 2 7
S2_AD14 B45 A45 S2_AD10 B48 A48 S2_AD33 3 6
B46 A46 S2_AD13 B49 A49 S2_AD9 S2_AD35 4 5
S2_AD12 B47 A47 S2_AD11 S2_M66EN B50 A50
S2_AD10 B48 A48 B51 A51 RP8K2
B49 A49 S2_AD9 C1946 S2_AD8 B52 A52 S2_CBE#0 S2_AD36 1 RP333 8
S2_M66EN B50 A50 S2_AD7 B53 A53 S2_AD37 2 7
36 S2_M66EN 0.01uF
B51 A51 B54 A54 S2_AD6 S2_AD38 3 6
C847 S2_AD8 B52 A52 S2_CBE#0 S2_AD5 B55 A55 S2_AD4 S2_AD39 4 5
S2_AD7 B53 A53 S2_AD3 B56 A56 RP8K2
0.01uF B54 A54 S2_AD6 B57 A57 S2_AD2 S2_AD40 1 RP334 8
S2_AD5 B55 A55 S2_AD4 S2_AD1 B58 A58 S2_AD0 S2_AD42 2 7
S2_AD3 B56 A56 B59 A59 S2_AD41 3 6
B57 A57 S2_AD2 S2_ACK64# B60 A60 S2_REQ64# S2_AD43 4 5
S2_AD1 B58 A58 S2_AD0 B61 A61 RP8K2
B59 A59 B62 A62 S2_AD44 1 RP335 8
S2_ACK64# B60 A60 S2_REQ64# S2_AD45 2 7
36 S2_ACK64# S2_REQ64# 36
B61 A61 S2_AD46 3 6
B62 A62 B63 A63 S2_AD47 4 5
B64 A64 S2_CBE#7 RP8K2
2 2
S2_CBE#6 B65 A65 S2_CBE#5 S2_AD48 1 RP336 8
B63 A63 S2_CBE#4 B66 A66 S2_AD50 2 7
B64 A64 S2_CBE#7 B67 A67 S2_PAR64 S2_AD49 3 6
S2_CBE#6 B65 A65 S2_CBE#5 S2_AD63 B68 A68 S2_AD62 S2_AD51 4 5
S2_CBE#4 B66 A66 VCC3 S2_AD61 B69 A69 RP8K2
B67 A67 S2_PAR64
S2_PAR64# 36 B70 A70 S2_AD60 S2_AD52 1 RP337 8
S2_AD61 B69 A69 S2_AD57 B72 A72 S2_AD54 3 6
B70 A70 S2_AD60 C848 C849 C850 C851 C852 B73 A73 S2_AD56 S2_AD55 4 5
S2_AD59 B71 A71 S2_AD58 S2_AD55 B74 A74 S2_AD54 RP8K2
S2_AD57 B72 A72 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF S2_AD53 B75 A75 S2_AD56 1 RP338 8
B73 A73 S2_AD56 B76 A76 S2_AD52 S2_AD57 2 7
S2_AD53 B75 A75 S2_AD49 B78 A78 S2_AD59 4 5
B76 A76 S2_AD52 C854 C855 C856 C857 B79 A79 S2_AD48 RP8K2
S2_AD51 B77 A77 S2_AD50 S2_AD47 B80 A80 S2_AD46 S2_AD60 1 RP339 8
S2_AD49 B78 A78 0.01uF 0.01uF 0.01uF 0.01uF S2_AD45 B81 A81 S2_AD61 2 7
B79 A79 S2_AD48 B82 A82 S2_AD44 S2_AD63 3 6
S2_AD47 B80 A80 S2_AD46 VCC S2_AD43 B83 A83 S2_AD42 S2_AD62 4 5
S2_AD45 B81 A81 S2_AD41 B84 A84 RP8K2
B82 A82 S2_AD44 B85 A85 S2_AD40 S2_CBE#4 1 RP340 8
S2_AD43 B83 A83 S2_AD42 C858 C859 C860 C861 C862 S2_AD39 B86 A86 S2_AD38 S2_CBE#5 2 7
S2_AD41 B84 A84 S2_AD37 B87 A87 S2_CBE#6 3 6
B85 A85 S2_AD40 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF B88 A88 S2_AD36 S2_CBE#7 4 5
S2_AD39 B86 A86 S2_AD38 S2_AD35 B89 A89 S2_AD34
S2_AD37 B87 A87 S2_AD33 B90 A90
B88 A88 S2_AD36 B91 A91 S2_AD32
S2_AD35 B89 A89 S2_AD34 B92 A92
1 S2_CBE#0 VCC3 1
S2_AD33 B90 A90 B93 A93
B91 A91 S2_AD32 S2_CBE#1 VCC 3VSB B94 A94
B92 A92 S2_CBE#2
B93 A93 S2_CBE#3
S2_CBE#4 CONN_PCI64_3_3V_SOCKET
B94 A94
S2_CBE#5 EC65 Title Rev
S2_CBE#6 EC67 EC68 + + CIOBX2_PCIXP2_SLOT2&3
CONN_PCI64_3_3V_SOCKET S2_CBE#7 + + EC66 S2_PCIRST# C2195 X_104P Document Number 0A
1000U/6.3V 100U/16V
36 S2_AD[0..63]
1000U/6.3V 1000U/6.3V MICRO-STAR INT'L CO.,LTD. Last Revision Date:
36 S2_CBE#[0..7]
A B C D E
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A B C D E
4 4
PLACE THESE CLOSE TO CMIC
VCC25
VCC25 VCC3
RP356 8 1 T_IMB_D_R0 RP443 8 1
7 2 T_IMB_D_R2 7 2
6 3 T_IMB_D_R1 6 3
5 4 T_IMB_D_R3 5 RP444 4
8 1 T_IMB_PAR_R 8 1
RP357 7 2 T_IMB_CLK_R 7 2 C892 C894
6 RP100R 3 T_IMB_CON_R 6 RP100R 3 0.1uF 0.1uF
5 4 5 4
RP100R
3 RP100R 3
T_IMB_D_R[0..3] 12,50
T_IMB_D_R0
T_IMB_D_R2
T_IMB_D_R1
T_IMB_D_R3
PLACE THESE CLOSE TO CSB5
T_IMB_PAR_R
T_IMB_PAR_R 12,50
T_IMB_CLK_R VCC3
T_IMB_CLK_R 12,25
T_IMB_CON_R
T_IMB_CON_R 12,50
RP358 1 8 RP100R RP445 1 8 RP100R

2 7 T_IMB_D_T1 2 7
T_IMB_D_T[0..3] 12,50
3 6 T_IMB_D_T3 3 6
T_IMB_D_T0 4 5 T_IMB_D_T2 4 5
T_IMB_D_T1 RP359 1 8 RP100R T_IMB_PAR_T RP446 1 8 RP100R
T_IMB_D_T3 2 7 T_IMB_D_T0 2 7
T_IMB_D_T2 3 6 T_IMB_CLK_T 3 6
4 5 T_IMB_CON_T 4 5
T_IMB_PAR_T
T_IMB_PAR_T 12,50
T_IMB_CLK_T
T_IMB_CLK_T 25,50
T_IMB_CON_T
T_IMB_CON_T 12,50
2 2
1 1

Title Rev
THIN_IMB_TERMINATION
Document Number 0A

A B C D E
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A B C D E
VCC3
VCC25
C1864 C1541 C1542 C1543
C1508 C1509 C1510 C1511 C1512 C1513 C1514 0.01uF 0.01uF 0.01uF 0.01uF
4 4
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
V33_1
VCC_P
VCC3 VCC25
3 3
C1515 C1516 C1517 C1518 C1519 C1521 C1522

C1525 C1526 C1527 C1530
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
0.01uF 0.01uF 0.01uF 0.01uF
VDD_IMB VDD_IMB
2 2
VCC25
VCC3
C1538 C1523 C1524 C1865 C1866 C1867 C1868 C1869
C1533 C1535 C1536 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
0.01uF 0.01uF 0.01uF
VCC3
VCC_P
1 1

Title Rev
SWITCHING CAPs
Document Number 0A

A B C D E
www.vinafix.vn
8 7 6 5 4 3 2 1
Winbond W782D Hardware Monitor

VRM_VID[0..4]
8,67 VRM_VID[0..4] VCC
R1994
4.7K
ALARM 62
R1995 10K VCCP1D VCC
VCC_P L71 ACTICE HIGH
D R1996 10K VCC1_5D 80S/0805 C D
VCC25 C2122 BEEP/GPO# B
R1998 10K VCC3_3D 104P VCCP1D R1997 510 E Q34
VCC3
VCC1_5D 2N3904S
R1999 10K VCCP2D GNDA VCC3_3D
VDD_IMB
L72 VCCP2D
80S/0805 -12VIN
VBATDD
R2000 R322 VREF782 5VSBD
-12V
232KRST 56KRST -5VIN
-12VIN GNDA
BEEP/GPO#
R2001 10K VBATDD VRM_VID3
RTCVCC
U213
36
35
34
33
32
31
30
29
28
27
26
25
R2002 R2003 GNDA VREF782 R2004 RT2 GNDA
5VSB
5.1KRST 7.5KRST 10KRST YT103S-1N
+3.3VIN
VINR0
+5VIN
+12VIN
-12VIN
VBAT
-5VIN
VCOREA
5VSB
GNDA
GPO#/BBEP
VID3
5VSBD T1
TP14
R2005 R2006 VREF782 SYSTEM
1 120KRST 56KRST
-5VIN VREF782 37 24 VRM_VID2
T3 VREF VID2 PWMOUT1
38 VTIN3/PIITD3 PWMOUT1 23
T2 39 22 RCC_SDA VREF782 R2007 RT3 GNDA
VTIN2/PIITD2 SDA RCC_SDA 12,15,27,37,41,69
T1 40 21 RCC_SCL 30KRST YT103S-1N
VTIN1/PIITD1 SCL RCC_SCL 12,15,27,37,41,69
VRM_VID0 41 20 FAN1IN
R2008 X_0 VID0 FAN1 FAN2IN T2
C
50 SM_SMI_OUT# 42 OVT# FAN2 19 C
43 18 FAN3IN
R2009 X_0 ARDMSEL FAN3/PWMOUT2 VRM_VID4
50 SM_TEMP_ALERT# 44 SMI# VID4 17
45 16 CASEOPEN R2011 10M
SA2/IA2 CASEOPEN RTCVCC
R2012 4.7K 46 15
SA1/IA1 MR RSTDRV 65
R2014 47 14
R2013 4.7K SA0/IA0 GNDD
48 13 VCC
D1/PWMOUT4
D0/PWMOUT3
VCC3 VCC CS# VCC
4.7K
C2124
CLKIN
104P
IOW#
IOR#
VID1
SM Bus Slave Address =
D7
D6
D5
D4
D3
D2
J53
00101A2A1A0 = 00101101b VREF782 R2090 RT1 GNDA
10
11
12
CASEOPEN 82WI782D 10KRST YT103S-1N
1
2
3
4
5
6
7
8
9
1 VCC T3
2
YJ102 R2015 4.7K VRM_VID1 SYSTEM
PWMOUT2
22 HWM_14.318M
PWMOUT3
+12V
R2016 4.7K
+12V
B B
1K R2018 4.7K
R2019 D64 R2017
4.7K Q35 Q37
1N4148S
D
SI2303DS-S-SOT23 YFET-NDS7002AS
1K
R2021
FAN1IN G PWMOUT1 R2022 D65 R2020
3 + EC42 R2091 470 Q36 Q38
2 4.7K 1N4148S
D
27K X_10U/16V SI2303DS-S-SOT23 YFET-NDS7002AS
S
1
R2024
R2023 CPUFAN1 FAN3IN G PWMOUT3
YJ103-BO 3 + EC43 R2092 470
10K 27K 2 X_10U/16V
S
1
+12V R2025 CPUFAN2
YJ103-BO
R2026 4.7K 10K
1K
R2028 D66 R2027
4.7K Q39 Q40
1N4148S
D
SI2303DS-S-SOT23 YFET-NDS7002AS
R2029
FAN2IN G PWMOUT2
3 + EC44 R2093 470
A
27K 2 X_10U/16V A
S
1
R2030 CPUFAN3
YJ103-BO
10K Title Rev
HARDWARE MONITOR
Document Number 0A

8 7 6 5 4 3 2 1
www.vinafix.vn
A B C D E
VCC3
DO NOT STUFF
RES_NOPOP
D_AD[0..31] 51,52,55
R599 R601 PIDE_D[0..15]
8.2K R600 8.2K J18

PCIRST3# 1 1 2 2
D_GNT#0 U63A PIDE_D7 3 4 PIDE_D8
D_GNT#1 3 4
PIDE_D6 5 5 6 6 PIDE_D9
D_GNT#2 D_AD0 T4 F18 PIDE_DR0 R_PIDE_IOR# 1 8 PIDE_IOR# PIDE_D5 7 8 PIDE_D10
4 D_AD1 PCIAD0 DD_P(0) PIDE_DR1 R_PIDE_A2 RP279 7 8 4
V1 PCIAD1 DD_P(1) E19 2 7 PIDE_A2 PIDE_D4 9 9 10 10 PIDE_D11
D_AD2 PIDE_DR2 R_PIDE_A0 RP33R
RES_NOPOP
RES_NOPOP
U2 PCIAD2 DD_P(2) D20 3 6 PIDE_A0 PIDE_D3 11 11 12 12 PIDE_D12

D_AD3 T3 E18 PIDE_DR3 4 5 PIDE_D2 13 14 PIDE_D13
PCIAD3 DD_P(3) 13 14
R602 R603 DO NOT STUFF D_AD4 PIDE_DR4 PIDE_DR0 PIDE_D0
R604
U1 PCIAD4 DD_P(4) G18 1 8 PIDE_D1 15 15 16 16 PIDE_D14

D_AD5 T2 C20 PIDE_DR5 R_PIDE_CS1# 2 RP280 7 PIDE_CS1# PIDE_D0 17 18 PIDE_D15
1K D_AD6 PCIAD5 DD_P(5) PIDE_DR6 PIDE_DR3 RP33R PIDE_D3 17 18
P4 PCIAD6 DD_P(6) E17 3 6 19 19 20 20
D_AD7 T1 D18 PIDE_DR7 PIDE_DR1 4 5 PIDE_D1 R_IDE_DRQ_P 21 22
D_AD8 PCIAD7 DD_P(7) PIDE_DR8 PIDE_DR6 PIDE_D6 PIDE_IOW# 21 22
P3 PCIAD8 DD_P(8) C18 1 8 23 23 24 24
D_AD9 R1 B19 PIDE_DR9 PIDE_DR7 2 RP281 7 PIDE_D7 PIDE_IOR# 25 26
D_AD10 PCIAD9 DD_P(9) PIDE_DR10 PIDE_DR8 RP33R PIDE_D8 R_IDE_CHRDY_P 25 26 R605 150
P2 PCIAD10 DD_P(10) A20 3 6 27 27 28 28
STRAPPING OPTION D_AD11 P1 A19 PIDE_DR11 PIDE_DR9 4 5 PIDE_D9 PIDE_DACK# 29 30
D_AD12 PCIAD11 DD_P(11) PIDE_DR12 PIDE_DR14 PIDE_D14 29 30
N3 PCIAD12 DD_P(12) B18 1 8 R_IRQ_P 31 31 32 32
* = Used in this design D_AD13 N2 PCIAD13 DD_P(13) B17 PIDE_DR13 PIDE_DR12 2 RP282 7 PIDE_D12 PIDE_A1 33 33 34 34
D_AD14 N1 C17 PIDE_DR14 PIDE_DR13 3 RP33R 6 PIDE_D13 PIDE_A0 35 36 PIDE_A2
PCIAD14 DD_P(14) 35 36
D_PCIGNT# 0 = Enable External Arbiter D_AD15 M4 PCIAD15 DD_P(15) D16 PIDE_DR15 PIDE_DR15 4 5 PIDE_D15 PIDE_CS0# 37 37 38 38 PIDE_CS1#
D_AD16 J2 39 40
(Disable internal Arbiter) D_AD17 PCIAD16 SIDE_DR0 SIDE_DR0 RP283 RP33R SIDE_D0 39 40
J3 PCIAD17 DD_S(0) C13 1 8
1 = Disable External Arbiter D_AD18 H1 PCIAD18 DD_S(1) B13 SIDE_DR1 R_SIDE_IOR# 2 7 SIDE_IOR# HEADER_2X20_PIN
D_AD19 H2 A13 SIDE_DR2 R_SIDE_IOW# 3 6 SIDE_IOW#
(Enable internal Arbiter)* PCIAD19 DD_S(2)
D_AD20 H3 D12 SIDE_DR3 SIDE_DR1 4 5 SIDE_D1
D_AD21 PCIAD20 DD_S(3) SIDE_DR4 SIDE_DR6 RP284 RP33R SIDE_D6
G1 PCIAD21 DD_S(4) C12 1 8
CSB_PGNT#1 0 = Enable X-Bus Logic * D_AD22 G2 PCIAD22 DD_S(5) B12 SIDE_DR5 SIDE_DR7 2 7 SIDE_D7
D_AD23 G3 B11 SIDE_DR6 SIDE_DR3 3 6 SIDE_D3
PCIAD23 DD_S(6)
1 = Disable X-Bus Logic D_AD24 F2 PCIAD24 DD_S(7) C11 SIDE_DR7 SIDE_DR11 4 5 SIDE_D11
D_AD25 G4 A11 SIDE_DR8 SIDE_DR9 1 RP285 8 RP33R SIDE_D9 SIDE_D[0..15]
D_AD26 PCIAD25 DD_S(8) SIDE_DR9 SIDE_DR10 SIDE_D10
F3 PCIAD26 DD_S(9) A10 2 7
CSB_PGNT#2 1 = Enable IMB Logic * D_AD27 E3 PCIAD27 DD_S(10) B10 SIDE_DR10 SIDE_DR13 3 6 SIDE_D13
D_AD28 D1 C10 SIDE_DR11 SIDE_DR12 4 5 SIDE_D12 J19
PCIAD28 DD_S(11) RP33R SIDE_D14
3 0 = Disable IMB Logic D_AD29 C1 PCIAD29 DD_S(12) D10 SIDE_DR12 SIDE_DR14 1 RP286 8 PCIRST3# 1 1 2 2 3
D_AD30 E4 A9 SIDE_DR13 R_SIDE_CS0# 2 7 SIDE_CS0# SIDE_D7 3 4 SIDE_D8
D_AD31 PCIAD30 DD_S(13) SIDE_DR14 R_SIDE_CS1# SIDE_CS1# 3 4
D3 PCIAD31 DD_S(14) C9 3 6 SIDE_D6 5 5 6 6 SIDE_D9
D9 SIDE_DR15 SIDE_DR15 4 5 SIDE_D15 SIDE_D5 7 8 SIDE_D10
D_CBE#0 DD_S(15) 7 8
R3 CBE#(0)
SIDE_D4 9 9 10 10 SIDE_D11
D_CBE#1 M2 D14 R_PIDE_DACK# R606 33 PIDE_DACK# SIDE_D3 11 12 SIDE_D12
D_CBE#2 CBE#[1] IDEDAKP# 11 12
51,52,55 D_CBE#[0..3] J1 CBE#[2] IDEDRQ_P A17 PIDE_DRQ SIDE_D2 13 13 14 14 SIDE_D13
D_CBE#3 F1 SIDE_D1 15 16 SIDE_D14
CBE#[3] PIDE_DR11 PIDE_D11 15 16
P_IDE_IOR E20 R_PIDE_IOR# 1 8 SIDE_D0 17 17 18 18 SIDE_D15
M1 G17 R_PIDE_IOW# PIDE_DR10 2 7 PIDE_D10 19 20
51,52,55 D_FRAME# FRAME# P_IDE_IOW 19 20
K1 H18 R_PIDE_CS0# PIDE_DR5 3 6 PIDE_D5 R_IDE_DRQ_S 21 22
51,52,55 D_DEVSEL# DEVSEL# P_IDECS#(0) 21 22
L4 F19 R_PIDE_CS1# PIDE_DR2 4 5 PIDE_D2 SIDE_IOW# 23 24
51,52,55 D_IRDY# IRDY# P_IDECS01 RP33R 23 24
L3 RP287 SIDE_IOR# 25 26
51,52,55 D_TRDY# TRDY# 33 25 26
J4 B15 R_SIDE_DACK# R607 SIDE_DACK# R_IDE_CHRDY_S 27 28 R608 150
51,52,55 D_PAR PAR IDEDAKS# 27 28
K3 C14 SIDE_DRQ SIDE_DRQ SIDE_DACK# 29 30
51,52,55 D_STOP# STOP# IDEDRQ_S 29 30
50,51,55 D_SERR# L1 SERR#
R_IRQ_S 31 31 32 32
L2 B14 R_SIDE_IOR# SIDE_DR2 1 RP288 8 SIDE_D2 PIDE_A1 33 34
50,51,55 D_PERR# PERR# S_IDE_IOR 33 34
V7 A14 R_SIDE_IOW# SIDE_DR5 2 7 SIDE_D5 PIDE_A0 35 36 PIDE_A2
8 RSB_FERR# FERR S_IDE_IOW 35 36
51 D_PLOCK# C2 PCILOCK# S_IDECS00 B8 R_SIDE_CS0# SIDE_DR4 3 RP33R 6 SIDE_D4 SIDE_CS0# 37 37 38 38 SIDE_CS1#
C8 R_SIDE_CS1# SIDE_DR8 4 5 SIDE_D8 39 40
PCIRST3# S_IDECS10 39 40
65 PCIRST3# Y6 PCIRST#
V9 G20 R_PIDE_A0 R_PIDE_CS0# 1 RP289 8 PIDE_CS0#
23 PCICLK_RSB PCICLK IDE_DA(0) RP33R
G19 R_PIDE_A1 R_PIDE_IOW# 2 7 PIDE_IOW# HEADER_2X20_PIN
D_GNT#0 IDE_DA(1) PIDE_DR4 PIDE_D4
51 D_GNT#0 V4 PGNT#[0]/XARB_STRAP IDE_DA(2) F20 R_PIDE_A2 3 6
D_GNT#1 U5 R_PIDE_A1 4 5 PIDE_A1
51 D_GNT#1 PGNT#[1]/XROM_STRAP
D_GNT#2 Y3 A8 IDE_CHRDY_S
55 D_GNT#2 PGNT#[2]/IMB_STRAP IN_IORDY_S
A18 IDE_CHRDY_P
D_REQ#0 IN_IORDY_P
51 D_REQ#0 W5 PCIREQ#[0]/IDE_GNT#
D_REQ#1 Y5 W12
2 51 D_REQ#1 PCIREQ#[1]/IDE_REQ# USBCLK USBCLK48M 22 IDE_LED 62,65 2
VCC3 D_REQ#2 V6
55 D_REQ#2 PCIREQ#[2]
58 SER_ISA_IRQ0_15 A6 SERIRQ
R1517 4.7K C7 V13
50 SER_PCI_IRQ0_15 PIRQ0 USBP2P USBP2P 60
B6 PIRQ1 USBP2N Y14 USBP2N 60 Place these components
R1329 0_OHM C16 Y13
R610 4.7K
50 PIRQ_LTCH PIRQ_LATCH USBP3P
W13
USBP3P 60 close to OSB
USBP3N USBP3N 60
IRQ14 B4
IRQ15 P_IDEIRQ
A3 S_IDEIRQ USBP1N W15 USBP1N 60
V14 VCC3
USBP1P USBP1P 60
R1244 10K Y15
VCC25 USBPON USBP0N 60
R611 4.7K Y18 W14 IRQ14 R612 80 R_IRQ_P
11,15 MEMOFF# MEMOFF#/APICCLK USBPOP USBP0P 60
PWREN W18 USB_PWREN PIDE_D7
W17 R613 2.2K IDE_CHRDY_P R614 80 R_IDE_CHRDY_P SIDE_D7
USB_IN_EN R615 2.2K
Y10 NMI USB_OVRCUR V18
PIDE_DRQ R616 80
10K
10K
R_IDE_DRQ_P
R620 4.7K IRQ15 R619 80 R_IRQ_S
R617
R618
VCC3
ROSB5 IDE_CHRDY_S R621 80 R_IDE_CHRDY_S
VCC3 PCIRST3# SIDE_DRQ R622 80 R_IDE_DRQ_S

PCIRST3# 65
NMI 8
USB_PWREN
R2031 1K
1 VCC3 1
R626 5.6K
R623 R624 R_IDE_DRQ_P
VCC 4.7K 4.7K R_IDE_DRQ_S Micro Star Restricted Secret

R_IDE_CHRDY_P R625 5.6K Title Rev
R_IDE_CHRDY_S SWSB5_PCI_&_IDE_INTERFACE
C1393 Document Number 0A
0.1uF
Place these components MICRO-STAR INT'L CO.,LTD. Last Revision Date:

close to CSB No. 69, Li-De St, Jung-He City,
A B C D E
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A B C D E
CMIC_FATAL# R564 0_OHM

11,15 CMIC_FATAL#
ROM_CS# S1_SERR#
59 ROM_CS# 26,30,35 S1_SERR#
R1417 0_OHM S1_PERR#
11,15,27,37 ALERT# 26,30,35 S1_PERR#
22 RSB_CLK_14MHZ
S2_SERR# VCC3
36,45 S2_SERR#
P1_SERR# S2_PERR#
26,29 P1_SERR# 36,45 S2_PERR#
P1_PERR# PCIIRQ#3 8 RP263 1
26,29 P1_PERR# 51 PCIIRQ#3
D_PERR# P2_SERR# PCIIRQ#2 7 2
49,51,55 D_PERR# 36,41,44 P2_SERR# 51 PCIIRQ#2
D_SERR# U63B P2_PERR# PCIIRQ#1 6 3
49,51,55 D_SERR# 36,41,44 P2_PERR# 55 PCIIRQ#1
V3 PCIIRQ#0 5 RP2K7 4
8 RSB_P2_PROCHOT# GEVENT_0 41 PCIIRQ#0
W1 GEVENT_1 OSC W8
P2_PERR# W2 GEVENT_2 52 PCIIRQ#4
PCIIRQ#4 1 RP264 8
W3 Y8 D_GNT#4 PCIIRQ#5 2 7
GEVENT_3 PCIGNT#4 D_GNT#4 52 51 PCIIRQ#5
4 P2_SERR# W4 U9 D_REQ#4 PCIIRQ#6 3 6 4
48 SM_SMI_OUT# GEVENT_4 PCIREQ#4 D_REQ#4 52 29 PCIIRQ#6
S2_PERR# Y4 PCIIRQ#7 4 5
GEVENT_5 29 PCIIRQ#7
R1919 2.7K P1_SERR# Y1 C19 RP2K7
GEVENT_6 SIO_WAKEUP SIO_WAKEUP 58
R1920 2.7K S2_SERR# Y2 PCIIRQ#11 8 RP266 1
VCC3 GEVENT_7 44 PCIIRQ#11
P1_PERR# Y19 D2 PCIIRQ#10 7 2
GPCS0L/GEVENT_8 SLPBTTNX SLP_BTN# 62 44 PCIIRQ#10
SM_SMI_OUT# V17 B1 PCIIRQ#9 6 3
GPCS1L/GEVENT_9 SLPX# RSB_SLP# 10 30 PCIIRQ#9
PORT_80_CS# U16 R19 R569 1K PCIIRQ#8 5 RP2K7 4
GPCS2L/GEVENT_10 SLP_S1 VCC3 30 PCIIRQ#8
R1339 4.7K V15 B16 R570 1K
GPM0/GEVENT_11 SLP_S3#
8 RSB_P1_PROCHOT# T20 GPM1/GEVENT_12 SLP_S5# R18 SOFF#
SOFF# 62,64 45 PCIIRQ#12
PCIIRQ#12 1 RP269 8
T19 PCIIRQ#13 2 7
8 RSB_P1_IERR# GPM2/GEVENT_13 45 PCIIRQ#13
DPLL ENABLE CMOS_CLR# T18 GPM3/GEVENT_14 PLLRST B20 R1708 0_OHM
PS_PWRGD# 11,27,37,64 45 PCIIRQ#14
PCIIRQ#14 3 6
STRAPPING S1_SERR# U18 GPOC3/GEVENT_15 AGND V10 45 PCIIRQ#15
PCIIRQ#15 4 5
D_PERR# Y16 W10 AVDD_RSB_PLL R577 4.7K RP2K7
8 RSB_P2_IERR# GEVENT(16) AVDD
S1_PERR# V12
48 SM_TEMP_ALERT# USBTO1/GEVENT_17 R2692
VCC3 U12 P20 R572 4.7K
USBIRQ/GEVENT_18 INTR INTR 8 VCC3
SM_TEMP_ALERT# V19 V8 R573 150 SOFF#
RP272 RP2K7 8 GEVENT_19/PICD0 EXTEVENT
1 W20 GEVENT_20/PICD1 IGNNE# Y9 RSB_IGNNE# 8
2 7 U14 FRWP#/GEVENT_21 SMI# V16 RSB_SMI# 10,58
R574 3 6 ROM_CS# Y20 4.7K
4.7K D_SERR# ROM_CS#/GEVENT_22 R575 8.2K VCC3 VCC3
4 5 U19 GEVENT_23 CPUGNT# U3 VCC3
M3 R571 2.7K
CPUREQ# VCC3
RSB_SCL R1943 0 U20 R576 8.2K
69 RSB_SCL GPOC0
RSB_SDA R1944 0 V20 A1 C1389
69 RSB_SDA GPOC1 VDDIO_1 R1516
0.1uF
0.1uF
C1390
T17 GPOC2 VDDIO_2 A12
A16 2.7K
12,46 T_IMB_D_T[0..3] VDDIO_3
T_IMB_D_T0 L18 A5
T_IMB_D_T1 I_DATA(0) VDDIO_4 AVDD_RSB_PLL
12,46 T_IMB_CON_T M20 I_DATA(1) VDDIO_5 B9
T_IMB_D_T2 M19 D19 U64 VCC3
12,46 T_IMB_PAR_T I_DATA(2) VDDIO_6
3 T_IMB_D_T3 M18 E2 10 3
T_IMB_D_R[0..3] I_DATA(3) VDDIO_7 PCIIRQ#15 SER
12,46 T_IMB_D_R[0..3] VDDIO_8 J19 11 A VCC 16
K20 N19 C1490 22UF_10V PCIIRQ#14 12
I_CONTRO# VDDIO_9 PCIIRQ#13 B
L20 I_PARITY 13 C GND 8
W11 PCIIRQ#12 14
T_IMB_D_R1 VDDIO_11 D
1 RP277 8 TIMB_DRR1 TIMB_DRR0 J17 O_DATA(0) VDDIO_12 W16 PCIIRQ#11 3 E
T_IMB_D_R3 2 RP39R 7 TIMB_DRR3 TIMB_DRR1 K19 W19 VCC3 PCIIRQ#10 4
T_IMB_D_R0 TIMB_DRR0 TIMB_DRR2 O_DATA(1) VDDIO_13 L51 47UH PCIIRQ#9 F
3 6 K17 O_DATA(2) VDDIO_14 W7 5 G
T_IMB_D_R2 4 5 TIMB_DRR2 TIMB_DRR3 K18 K2 R1306 0 1 2 PCIIRQ#8 6 9
O_DATA(3) VDDIO_15 H QH
VDDIO_16 R2
TIMB_CONRR H19 2 7
12,46 T_IMB_CON_R O_CONTROL 23 PCICLK_IRQ0 CLK QH
R578 39 TIMB_PARRR H20 D11 15
12,46 T_IMB_PAR_R O_PARITY VDD25_1 INH
R579 39 D15 1
VDD25_2 49 PIRQ_LTCH SH/LD
25,46 T_IMB_CLK_T L19 I_CLOCK VDD25_3 D6
T_IMB_CLK_RR TIMB_CLKRR J18 F17 74LV165
25 T_IMB_CLK_RR O_CLOCK VDD25_4
F4 C742 RES_NOPOP
R580 39 VDD25_5
VDD25_6 K4
U11 L17 R581
10 RSB_STPCLK# STPCLK#/SCKREQ# VDD25_7
R4 CAP_NOPOP
VDD25_8
58,63 LPC_AD[0..3] VDD25_9 U10
VDD25_10 U15 VCC25
LPC_AD0 P17 LAD00X VDD25_11 U6 DO NOT STUFF VCC3
R582 10K LPC_AD1 P19 R17 U66
LPC_AD2 LAD(1) VDD25_12
VCC3 R20 LAD02X 10 SER
LPC_AD3 P18 V5 PCIIRQ#7 11 16
LAD03X VDD5_1 VCC A VCC
N20 E1 PCIIRQ#6 12
58 LPC_DRQ# LDRQ0 VDD5_2 B
R583 10K M17 PCIIRQ#5 13 8
LDRQ1 VREF_T_IMB PCIIRQ#4 C GND
58,63 LPC_FRAME# N18 LFRAME# IMB_VREF J20 14 D
R584 10K PCIIRQ#3 3
2 VCC3 E 2
V2 D4 PCIIRQ#2 4
R585 10K FLUSHREQ# GND1 PCIIRQ#1 F
W6 MEMACK# GND2 D8 5 G
Y17 D13 PCIIRQ#0 6 9
57 KBD_A20M# KBD_A20# GND3 H QH SER_PCI_IRQ0_15 49
62 SPKR W9 SPKR GND4 D17
10,11,57 RSB_PINIT# C15 INIT GND5 H4 23 PCICLK_IRQ1 2 CLK QH 7
RSB_A20M# A15 H17 15
8 RSB_A20M# A20M# GND6 INH
N4 PIRQ_LTCH 1
VCC3 GND7 SH/LD
59 XALAT#[0..2] GND8 N17
XALAT#0 U7 U4 74LV165
XALAT#1 XALAT#[0] GND9
Y7 XALAT#[1] GND10 U8
XALAT#2 Y11 U13 C743 RES_NOPOP
59 XAD[0..7] XALAT#[2] GND11
XAD0 A7 U17
XAD1 XAD[0] GND12 R587
B7 XAD[1] GND13 J9
R588 4.7K RSB_A20M# XAD2 D5 J10 CAP_NOPOP
XAD3 XAD[2] GND14
C4 XAD[3] GND15 J11
XAD4 B3 J12
XAD[4] GND16
VCC3
XAD5 B2 XAD[5] GND17 K9 DO NOT STUFF
XAD6 A2 K10
XAD7 XAD[6] GND18
C3 XAD[7] GND19 K11
XWC# Y12 K12
GND25
GND26
GND27
GND28
GND21
GND22
GND23
GND24
59 XWC#
NC_R1
NC_R2
NC_R3
NC_R4
NC_R5
XRC# XWC# GND20

59 XRC# V11
FID1
FID2
R1281 4.7K XRC# VCC25

M10
M11
M12
JP23 BER_1X2
257
258
L10
L11
L12
M9
D7
C6
C5
B5
A4
L9
CMOS_CLR# ROSB5
100_1%
VCC3
R589
R1282
R593 RES_NOPOP
1 33 R594 RES_NOPOP 1
R595 RES_NOPOP VREF_T_IMB VCC25
R596 RES_NOPOP VCC3
VCC3 Don't Populate R598 RES_NOPOP VCC25
100_1%
1.0uF/10V C746
0.1uFC747
220pF
C1442 C1443 C1444 C1499 Title Rev

+ + + + SWSB5_IMB_GPORTS
Document Number 0A
0.1uF
0.1uF
0.1uF
0.1uF
C1433
C1434
C1435
C1436
C1437
C1438
C1439
C1440
C1441
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
R597
C745
0.1uF
0.1uF
0.1uF
C1491
C1492
C1493
C1494
C1495
C1496
C1497
0.01uF
0.01uF
0.01uF
0.01uF
22uF/10V/20% 22uF/10V/20% 22uF/10V/20% 22uF/10V/20% MICRO-STAR INT'L CO.,LTD. Last Revision Date:
A B C D E
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A B C D E
VCC3 VCC3
VCC3 VCC3
VCC VCC +12V VCC

VCC VCC +12V VCC
-12V
PCI32_1 -12V
B1 A1 R2606 PCI32_2
-12V TRST# 5.6K R2607
B2 TCK +12V A2 B1 -12V TRST# A1
4 B3 A3 B2 A2 5.6K 4
GND TMS TCK +12V
B4 TDO TDI A4 B3 GND TMS A3
B5 +5V +5V A5 B4 TDO TDI A4
B6 A6 PCIIRQ#2 B5 A5
+5V INTA# PCIIRQ#2 50 +5V +5V
PCIIRQ#3 B7 A7 B6 A6 PCIIRQ#5
50 PCIIRQ#3 INTB# INTC# +5V INTA#
B8 A8 PCIIRQ#5 B7 A7 PCIIRQ#5
INTD# +5V 50 PCIIRQ#5 INTB# INTC#
B9 A9 PCIIRQ#5 B8 A8
PRSNT1# RSVD1 3VSB INTD# +5V
B10 RSVD2 +5V A10 B9 PRSNT1# RSVD1 A9
B11 A11 B10 A10 3VSB
PRSNT2# RSVD3 RSVD2 +5V
B12 GND GND A12 B11 PRSNT2# RSVD3 A11
B13 GND GND A13 B12 GND GND A12
B14 RSVD5 RSVD4 A14 B13 GND GND A13
B15 A15 PCIRST2# B14 A14
GND RST# PCIRST2# 52,55,58,65 RSVD5 RSVD4
D_PCICLK1 B16 A16 B15 A15 PCIRST2#
23 D_PCICLK1 CLK +5V GND RST# PCIRST2# 52,55,58,65
B17 A17 D_GNT#0 D_PCICLK2 B16 A16
GND GNT# D_GNT#0 49 23 D_PCICLK2 CLK +5V
D_REQ#0 B18 A18 B17 A17 D_PCIGNT#
49 D_REQ#0 REQ# GND GND GNT# D_GNT#1 49
B19 A19 IO_PCIPME# D_REQ#1 B18 A18
+5V RSVD6 IO_PCIPME# 58 49 D_REQ#1 REQ# GND
D_AD31 B20 A20 D_AD30 B19 A19 IO_PCIPME#
D_AD29 AD31 AD30 D_AD31 +5V RSVD6 D_AD30
B21 AD29 +3.3V A21 B20 AD31 AD30 A20
B22 A22 D_AD28 D_AD29 B21 A21
D_AD27 GND AD28 D_AD26 AD29 +3.3V D_AD28
B23 AD27 AD26 A23 B22 GND AD28 A22
D_AD25 B24 A24 D_AD27 B23 A23 D_AD26
AD25 GND D_AD24 D_AD25 AD27 AD26
B25 +3.3V AD24 A25 B24 AD25 GND A24
D_CBE#3 B26 A26 R2608 100 D_AD18 B25 A25 D_AD24
49,52,55 D_CBE#3 C/BE3# IDSEL# +3.3V AD24
D_AD23 B27 A27 D_CBE#3 B26 A26 R2609 100 D_AD19
AD23 +3.3V D_AD22 D_AD23 C/BE3# IDSEL#
B28 GND AD22 A28 B27 AD23 +3.3V A27
D_AD21 B29 A29 D_AD20 B28 A28 D_AD22
D_AD19 AD21 AD20 D_AD21 GND AD22 D_AD20
B30 AD19 GND A30 B29 AD21 AD20 A29
3 B31 A31 D_AD18 D_AD19 B30 A30 3
D_AD17 +3.3V AD18 D_AD16 AD19 GND D_AD18
B32 AD17 AD16 A32 B31 +3.3V AD18 A31
D_CBE#2 B33 A33 D_AD17 B32 A32 D_AD16
49,52,55 D_CBE#2 C/BE2# +3.3V AD17 AD16
B34 A34 D_FRAME# D_CBE#2 B33 A33
GND FRAME# D_FRAME# 49,52,55 C/BE2# +3.3V
D_IRDY# B35 A35 B34 A34 D_FRAME#
49,52,55 D_IRDY# IRDY# GND GND FRAME#
B36 A36 D_TRDY# D_IRDY# B35 A35
+3.3V TRDY# D_TRDY# 49,52,55 IRDY# GND
D_DEVSEL# B37 A37 B36 A36 D_TRDY#
49,52,55 D_DEVSEL# DEVSEL# GND +3.3V TRDY#
B38 A38 STOP# D_DEVSEL# B37 A37
GND STOP# D_STOP# 49,52,55 DEVSEL# GND
D_PLOCK# B39 A39 B38 A38 STOP#
49 D_PLOCK# LOCK# +3.3V GND STOP#
D_PERR# B40 A40 SDONE1 D_PLOCK# B39 A39
49,50,55 D_PERR# PERR# SDONE LOCK# +3.3V
B41 A41 SBO#1 D_PERR# B40 A40 SDONE2
D_SERR# +3.3V SBO# PERR# SDONE SBO#2
49,50,55 D_SERR# B42 SERR# GND A42 B41 +3.3V SBO# A41
B43 A43 D_PAR D_SERR# B42 A42
+3.3V PAR D_PAR 49,52,55 SERR# GND
D_CBE#1 B44 A44 D_AD15 B43 A43 D_PAR
49,52,55 D_CBE#1 C/BE1# AD15 +3.3V PAR
D_AD14 B45 A45 D_CBE#1 B44 A44 D_AD15
AD14 +3.3V D_AD13 D_AD14 C/BE1# AD15
B46 GND AD13 A46 B45 AD14 +3.3V A45
D_AD12 B47 A47 D_AD11 B46 A46 D_AD13
D_AD10 AD12 AD11 D_AD12 GND AD13 D_AD11
B48 AD10 GND A48 B47 AD12 AD11 A47
B49 A49 D_AD9 D_AD10 B48 A48
GND AD9 AD10 GND D_AD9
B49 GND AD9 A49
D_AD8 B52 A52 D_CBE#0

AD8 C/BE0# D_CBE#0 49,52,55
D_AD7 B53 A53 D_AD8 B52 A52 D_CBE#0
AD7 +3.3V D_AD6 D_AD7 AD8 C/BE0#
B54 +3.3V AD6 A54 B53 AD7 +3.3V A53
D_AD5 B55 A55 D_AD4 B54 A54 D_AD6
D_AD3 AD5 AD4 D_AD5 +3.3V AD6 D_AD4
B56 AD3 GND A56 B55 AD5 AD4 A55
B57 A57 D_AD2 D_AD3 B56 A56
D_AD1 GND AD2 D_AD0 AD3 GND D_AD2
B58 AD1 AD0 A58 B57 GND AD2 A57
2 B59 A59 D_AD1 B58 A58 D_AD0 2
1ACK64# +5V +5V 1REQ64# AD1 AD0
B60 ACK64# REQ64# A60 B59 +5V +5V A59
B61 A61 2ACK64# B60 A60 2REQ64#
+5V +5V ACK64# REQ64#
B62 +5V +5V A62 B61 +5V +5V A61
B62 +5V +5V A62
D_AD[0..31]
49,52,55 D_AD[0..31]
D_CBE#[0..3] YSLOT120 D_REQ#0
49,52,55 D_CBE#[0..3] VCC
D_GNT#0 R2610 2.7K YSLOT120
VCC3
AD18 R2611 8.2K
D_REQ#1
INT#[1,2,3,4] D_GNT#1 R2612 2.7K VCC
VCC3
REQ#/GNT#[0] R2613 8.2K
VCC VCC3
For EMI Requested
C2196 C2197 C2198 C2199 C2200 C2201 C2202 C2203 C2204 C2205
104P 104P 104P 104P 104P 104P 104P 104P 104P 104P VCC
VCC
1REQ64# 1 2 RP455
1ACK64# 3 4 D_DEVSEL# 1 5
1 SDONE1 D_TRDY# 1 5 1
5 6 2 2
D_PCICLK1 SBO#1 7 8 D_IRDY# 3
VCC VCC3 3VSB RN34 D_FRAME# 3
4 4
D_PCICLK2
SDONE2
8P4R-2.7K D_SERR#
D_PERR#
6 6 Micro Star Restricted Secret
1 2 7 7
SBO#2 3 4 D_PLOCK# 8 Title Rev
EC45 EC46 2ACK64# D_STOP# 8 PCI SLOT 1 & 2
5 6 9 9 10 10
C2206 C2207 + + + EC47 + EC48 + 2REQ64# 7 8 Document Number 0A
EC69 RN35 10P8R-2.7K
X_10P
X_10P 1000U/6.3V 1000U/6.3V 1000U/6.3V 1000U/6.3V 100U/16V 8P4R-2.7K MICRO-STAR INT'L CO.,LTD. Last Revision Date:
A B C D E
www.vinafix.vn
5 4 3 2 1
VCC AVDD25
D D
3 VIN OUT 2
VOUT 4
+ 104P 104P 103P +
EC71 C2125 1 C2126 C2127 EC30
49,51,55 D_AD[0..31] ADJ/GND
10U/16V/S 100U/16V
U215A U214 LX8117S R2032
D_AD0 V16 G1 100RST
AD0 SAD0/HCLK
D_AD1 W16 AD1 SAD1 G2 LT1117-2.5V
D_AD2 V15 G3
D_AD3 AD2 SAD2/HAD2
Y16 AD3 SAD3/HAD3 F2
D_AD4 W15 F1
AD4 SAD4/HAD4
20mil
D_AD5 Y15 F3 R2033
D_AD6 AD5 SAD5/HAD5 VCC 100RST
V14 AD6 SAD6/HAD6 E3
D_AD7 W14 E2
D_AD8 AD7 SAD7/HAD7 R2034 47K
Y14 AD8 DS/VIPCLK H2
D_AD9 V12 J1 R2035 47K
D_AD10 AD9 AS/HCNTL R2036 47K
Y13 AD10 SRDY/INT/HAD0 H3
D_AD11 W12
D_AD12 AD11
Y12 AD12 DVS/PDATA0 D1
D_AD13 V11 C1
D_AD14 AD13 DVS/PDATA1
Y11 AD14 DVS/PDATA2 C2
D_AD15 W11 B2
V8 AD16 DVS/PDATA4 A2
D_AD17 W8 C3
W7 AD18 DVS/PDATA6 B3
D_AD19 Y7 A3
V7 AD20 DVS/PCLK E1
C D_AD21 C
Y6 AD21
D_AD22 W5 H1 AVDD25
D_AD23 AD22 BYTCLK
Y5 AD23 NC/ZVHREF/LCD0 C9
D_AD24 W3 B9 L73 80S/0805
D_AD25 AD24 LPVDD/ZVVSYNC/LCD1
Y3 AD25 LPVSS/UV0/LCD2 A9
D_AD26 V3 C8 C2128
D_AD27 AD26 NC/UV1/LCD3
Y2 AD27 NC/UV2/LCD4 B8
D_AD28 W2 A8 104P
D_AD29 AD28 TXVSSR/UV3/LCD5
Y1 AD29 TXVDDR/UV4/LCD6 C7
D_AD30 V2 B7
AD30 TXCP/UV5/LCD7
D_AD31 W1 AD31 TXCM/UV6/LCD8 A7 LPVSS VCC
NC/UV7/LCD9 D6
49,51,55 D_CBE#0 V13 C/BE#0 TXVSSR/SDS/LCD10 C6
W10 B6 C2129
49,51,55 D_CBE#1 C/BE#1 TX0P/SAS/LCD11
Y8 A6 MONID2 R2042 2.2K
49,51,55 D_CBE#2 C/BE#2 TX0M/SSAD0/LCD12
W4 D5 104P
49,51,55 D_CBE#3 C/BE#3 NC/SSAD1/LCD13
V1 C5 MONID1 R2045 2.2K
23 PCICLK_VGA PCICLK TXVDDR/SSAD2/LCD14
51,55,58,65 PCIRST2# U2 RESET# TX1P/SSAD3/LCD15 B5
50 PCIIRQ#4 U3 INTA# TX1M/SSAD4/LCD16 A5
D_REQ#4 U1 C4 D_REQ#4
50 D_REQ#4 REQ# TXVSSR/SSAD5/LCD17 VCC
W9 B4 D_GNT#4 R2037 2.7K
49,51,55 D_FRAME# FRAME# TX2P/SSAD6/LCD18 VCC3
49,51,55 D_IRDY# Y9 IRDY# TX2M/SSAD7/LCD19 A4 TXVSSR R2038 8.2K
49,51,55 D_TRDY# V9 TRDY# MONID3/LCD23 J4
Y10 K3 MONID2
49,51,55 D_DEVSEL# DEVSEL# MONID2/LCD22 MONID2 54
V10 K2 MONID1 JVGA1_1-2
49,51,55 D_STOP# STOP# MONID1/LCD21 MONID1 54
49,51,55 D_PAR U10 PAR MONID0/LCD20 K1
D_GNT#4 T2 E4 VCC YJUMPER-MG
50 D_GNT#4 GNT# MONDET/LCDPE JP40
PCI33EN U16 D2
53 PCI33EN PCI33EN/M66EN/BIOSFFCLK/HAD1 NC/LCDCLK
T1 J3 R2039 47K D_AD21
ST0 SDA R2040 47K VGAEN R1960 100 1
T3 ST1 SCL J2 2
B R2041 22 B
R2 ST2 AGPCLAMP U8 3
F4 R2043 22
GIOCLAMP R2044 10K VCC3
N2 SBA0 TESTEN U15
N3 YJ103
SBA1 XTALIN
P2 SBA2 XTALIN A1
P3 SBA3
P1 B1 XTALOUT
SBA4 XTALOUT
V5 SBA5
W6 L1 RED
SBA6 R RED 54
M1 GREEN
G GREEN 54
VGAEN V6 N1 BLUE
IDSEL/SBA7 B BLUE 54
R3 M2 HSYNC# AVDD AVDD25
NC/RBF# HSYNC HSYNC# 54
M3 VSYNC#
VSYNC VSYNC# 54
W13 ADSTB0
Y4 L2 R2047 365 L74 80S/0805
ADSTB1 RSET
R1 SBSTB AVDD N4 (29.498928 MHz or 14.31818 MHz)
K4 C2130
AVSS 103P
U4 NC/AGPGPIO0/CLKRUN# AVSS L4
20mil
V4 C2131 XTALIN
NC/AGPGPIO1/STP_AGP# 22P
U5 NC/AGPGPIO2 PVDD L3
U13 NC/AGPGPIO3 PVSS M4 AVSS
1
R2048 Y6
1M 29.498928MHz
+
C2132 EC31
2
RAGE XL
103P 100U/16V C2133 XTALOUT
22P
A A
PVSS
RESET VALUE R92
RAGE XL 365
Title Rev
RAGE 128 374 ATI RAGE XL #1
Document Number 0A

5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
1.U1至U2 trace 等長
2.trace/space 5/10 mil U215B
3.clock trace/space VMD31

VMD30
A20
B20
DQ31 DQ32 B19
A19
DQ30 DQ33
5/15 mil VMD29
VMD28
C20
C19
DQ29 DQ34 B18
A18
VMD27 DQ28 DQ35
C18 DQ27 DQ36 C17
VMD26 D20 B17
VMD25 DQ26 DQ37
D19 DQ25 DQ38 A17
D
8MBytes SDRAM (64Mbit, 512Kx32x4)
VMD24 D
D18 DQ24 DQ39 C16
VMD23 D17 B16
DQ23 DQ40
VMD22 E20 DQ22 DQ41 A16 VMA8
VMD21 E19 C15
VMD20 DQ21 DQ42 INT Enable Open VCC3
E18 DQ20 DQ43 B15
VMD19 E17 A15
VMD18 DQ19 DQ44 INT Disable Close
F20 DQ18 DQ45 D14
VMD17 F19 C14
VMD16 DQ17 DQ46
F18 DQ16 DQ47 B14
VMD15 F17 A14 INTERRUPT always enable
35
41
49
55
75
81
15
29
43
DQ15 DQ48
3
9
1
VMD14 G20 D13 U216
VMD13 DQ14 DQ49
G19 C13
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VMD12 DQ13 DQ50 VMA0 VMD0
G18 DQ12 DQ51 B13 25 A0 DQ0 2
VMD11 G17 A13 VMA7 VMA1 26 4 VMD1
VMD10 DQ11 DQ52 VMA2 A1 DQ1 VMD2
H20 DQ10 DQ53 D12 27 A2 DQ2 5
VMD9 H19 C12 VGA Enable Open VMA3 60 7 VMD3
H18 DQ8 DQ55 B12 61 A4 DQ4 8
VMD7 J20 A12 VGA Close VMA5 62 10 VMD5
J19 DQ6 DQ57 D11 Disable 63 A6 DQ6 11
VMD5 J18 C11 VMA7 64 13 VMD7
DQ5 DQ58 VMA8 A7 DQ7
VMD4 K20 DQ4 DQ59 B11 VGA always enable 65 A8 DQ8 74 VMD8
VMD3 K19 A11 VMA9 66 76 VMD9
K18 DQ2 DQ61 C10 24 A10 DQ10 77
VMD1 L19 B10 VMA11 22 79 VMD11
VCC3 VMD0 DQ1 DQ62 DSF BA0 DQ11 VMD12
L18 DQ0 DQ63 A10 23 BA1 DQ12 80
82 VMD13
ROMCS# Close to VDQM#0 DQ13 VMD14
ROMCS# D3 16 DQM0 DQ14 83
T4 Chip VDQM#1 71 85 VMD15
VPP/VDDQ A0 A0 RN14 VDQM#2 DQM1 DQ15
U6 VPP/VDDQ A0 Y18 1 2 8P4R-22 VMA0 28 DQM2 DQ16 31 VMD16
U9 Y19 A1 A1 3 4 VMA1 VDQM#3 59 33 VMD17
C + C2136 C2137 VPP/VDDQ A1 A2 A2 VMA2 DQM3 DQ17 VMD18 C
U14 VPP/VDDQ A2 Y20 5 6 DQ18 34
EC32 104P C2135 W18 A3 A3 7 8 VMA3 VWE# 17 36 VMD19
10U/16V/S C2134 104P 105P 104P A3 A4 A7 RN15 VCAS# WE# DQ19
M17 VDDR/1 A4 W19 1 2 22 VMA7 18 CAS# DQ20 37 VMD20
K17 W20 A5 A6 3 4 VMA6 VRAS# 19 39 VMD21
VDDR/1 A5 A6 A5 VMA5 VCS#0 RAS# DQ21 VMD22
H17 VDDR/1 A6 V18 5 6 20 CS# DQ22 40
D16 V19 A7 A4 7 8 VMA4 VCKE 67 42 VMD23
VDDR/1 A7 A8 A8 RN16 VCLK0 CKE DQ23
D10 VDDR/1 A8 V20 1 2 8P4R-22 VMA8 68 CLK DQ24 45 VMD24
D7 U18 A9 A9 3 4 VMA9 47 VMD25
VDDR/2 A9 A10 A10 VMA10 DQ25 VMD26
D4 VDDR/2 A10 U19 5 6 14 NC DQ26 48
20mil G4
L17
VDDR/2
VDDC
A11/CKE U20 A11 A11 7 8 VMA11 21
30
NC
NC
DQ27
DQ28
50
51
VMD27
VMD28
AVDD25 D8 P19 M#0 M#0 RN17 1 2 8P4R-22 VDQM#0 57 53 VMD29
VDDC DQM#0 M#1 M#1 VDQM#1 NC DQ29 VMD30
P4 VDDC DQM#1 P18 3 4 69 NC DQ30 54
U11 R20 M#2 M#2 5 6 VDQM#2 70 56 VMD31
VDDC DQM#2 NC DQ31
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
R19 M#3 M#3 7 8 VDQM#3 73
DQM#3 NC
VSS
VSS
VSS
VSS
J9 VSS DQM#4 R18
+ C2139 C2140 J10 T20
EC33 104P VSS DQM#5 MWE# VWE# 512Kx32x4 - TSOP86
J11 VSS DQM#6 T19 1 2
12
32
38
46
52
78
84
44
58
72
86
10U/16V/S C2138 104P 105P J12 T18 MCAS# 3 4 VCAS#
6
VSS DQM#7 MRAS# VRAS#
K9 VSS 5 6
K10 P20 MRAS# MCS#0 7 8 VCS#0
VSS RAS# MCAS#
K11 VSS CAS# L20
K12 R17 MWE# RN18 8P4R-22
VSS WE# MCS#0
L9 VSS CS0/BA0 W17
Current provided by VDDC L10 VSS CS1/BA1 Y17 VCC3
is 600 mA L11 VSS DFPDAT/CS2/QS2 V17
L12 VSS NC/CS3/QS3 U17
M9 N18 VCKE
VSS CKE/QS0
M10 VSS
M11 VSS DFPCLK/QS1 M18 Only support RAGE XL
B R2049 150 + C2141 C2142 C2143 C2144 C2145 C2146 B
M12 VSS VCC3
T17 P17 DSF EC29
VSS DSF 100U/16V 104P 104P 104P 104P 104P 104P
J17 VSS
D15 N20 R2050 22 VCLK0
VSS MCLK/CLK0
D9 VSS NC/CLK0# N19
H4 M20 Close to Chip
VSS NC/CLK1
R4 VSS NC/CLK1# M19
U7
U12
VSS
VSS VREF N17
VCC3
One cap for two power pin
R2051
RAGE XL C2147 100
104P
Read BIOS straps Close
20mil
Don't Read BIOS Open Only support LVTTL
VCC3
VCC3
VMA5 R2052 10K
ROMCS# R2053 X_10K
1
2
Use System BIOS J54
VMA0 VMA6 YJ102
Bus Clock Select Bus Type PCI33EN
PCI 33MHz / 3.3V 1 0 1 STRAPPING RESISTORS VMA5
IDSEL Enable Open
PCI 33MHz / 5V 1 1 1 VCC3
A
VDDR I/O power for Memory & muitimedia IDSEL Disable Close A
PCI33EN R2054 10K
52 PCI33EN
VDDP Power for PCI or AGP Interface PCI 66MHz 0 1 0
VDDC Graphic controllor power

AGP 1/2X 0 0 0 VMA0 R2055 10K
AVDD Analog DAC Power - 2.5 V Title Rev
ATI RAGE XL #2
PVDD Phase Lock Loop Power - 2.5 V AGP Test Mode 1 Don't care 0 VMA6 R2056 10K Document Number 0A

5 4 3 2 1
www.vinafix.vn
8 7 6 5 4 3 2 1
D67
Place the PI-Filter in close
Video Connector VCC 1
X_YDI1PS226S
2
proximity to the VGA connector
L75 L76
3
1 2 CRT_R 1 2 ROUT
52 RED
D68
80S/0603 C2148 R2057 80S/0603 C2149
D 47P 47P D
X_YDI1PS226S 75RST
VCC 1 2
3
L77 L78 For EMI Suppression
1 2 CRT_G 1 2 GOUT
52 GREEN
D69
80S/0603 C2150 R2058 80S/0603 C2151
47P X_YDI1PS226S 75RST 47P
VCC 1 2
3
L79 L80 For EMI Suppression
1 2 CRT_B 1 2 BOUT
52 BLUE
80S/0603 C2152 R2059 80S/0603 C2153

47P 75RST 47P
Place Termination
C Resistor close to C
Place ferrite bead Place clamping diodes VGA connector.
close to Chip close to connector For EMI Suppression
VCC
L81
NOTE: 1 2 VGAVCC
D4,D5,D7,D8,D12 X_80S/0805
LIBRARY ERROR C2154

104P VGA Connector
JVGA1
17
RN19
MONID2 MONID1 1 2 RMONID1 RMONID2 15 5
52 MONID2
VSYNC# MONID2 3 4 RMONID2 10
52 VSYNC#
HSYNC# HSYNC# 5 6 RHSYNC# RVSYNC# 14 4
52 HSYNC#
MONID1 VSYNC# 7 8 RVSYNC# 9
52 MONID1
RHSYNC# 13 3
8P4R-33 8
B Place clamping diodes RMONID1 12 2 B
close to connector 7
3
11 1
VCC 1 2 VCC 1 2 6
1
3
5
7
CN1
D70 D71 For EMI X_8P4C-100P 16
Suppression
X_YDI1PS226S X_YDI1PS226S
YCN15F-003-1
2
4
6
8
R,G,B,Hsync,Vsync
以㆖訊號走 10/20/10 mil
並包GND
A A

Title Rev
VGA CONNECTOR
Document Number 0A

8 7 6 5 4 3 2 1
www.vinafix.vn
A B C D E
3V_STBY
VCC
R473
10K
G13
D10
K13
P12
A11
K10
K11
E12
A14
P14
L10
J10
J11
U46
G6
G5
G4
N8
N6
H5
H6
H7
H8
D9
H4
A3
A7
E1
K3
K5
K6
K7
K8
K9
K4
P2
A1
P1
L4
L5
L9
J5
J6
J7
J8
J9
J4
4 4
49,51,52 D_AD[0..31]
G2 A12
VCCPL1
VCCPL2
VCCPL3
VCCPL4
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
VCCPT
VCCPP1
VCCPP2
VCCPP3
VCCPP4
VCCPP5
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VIO LILED 2LINKLED 56
ACTLED C11 2ACTLED 56
D_AD0 N7 B11
AD0 SPEEDLED 2SPEEDLED 56
D_AD1 M7
D_AD2 AD1
P6 AD2 TDP C13 2_TDP 56
D_AD3 P5
D_AD4 AD3
N5 AD4 TDN C14 2_TDN 56
D_AD5 M5 AD5
D_AD6
D_AD7
P4
N4
AD6
AD7
82559 RDP E13 2_RDP 56
3V_STBY
D_AD8 P3 E14
AD8 RDN 2_RDN 56
D_AD9 N3
D_AD10 AD9
N2 AD10 FLA16/CLK25 P9
D_AD11 M1 M10 EESK
D_AD12 AD11 FLA15/EESK EEDO R482
M2 AD12 FLA14/EEDO N10
D_AD13 M3 P10 EEDI
D_AD14 AD13 FLA13/EEDI 4.7K
L1 AD14 FLA12/MCNTSM# M11
D_AD15 L2 M12
D_AD16 AD15 FLA11/MINT
K1 N13 U47
D_AD17 AD16 FLA10/MRING# EEDO
E3 AD17 FLA9/MRST P13 4 DO GND 5
D_AD18 D1 N14
D_AD19 AD18 FLA8/IOCHRDY EEDI
D2 AD19 FLA7/CLKEN M13 3 DI ORG 6
D_AD20 D3 M14
D_AD21 AD20 FLA6 EESK
C1 AD21 FLA5 L12 2 SK NC 7
D_AD22 B1 L13
D_AD23 AD22 FLA4 EECS
B2 AD23 FLA3 L14 1 CS VCC 8
D_AD24 B4 K14
D_AD25 AD24 FLA2 R475 2.2K C660
3 A5 J12 3V_STBY 93C66 3
D_AD26 AD25 FLA1/AUXPWR 0A:93C46S
B5 AD26 FLA0/PCIMODE# J13
D_AD27 B6 J14 0B:93C66S 0.1uF
D_AD28 AD27 FLD7 R476 4.7K
C6 AD28 FLD6 H12
D_AD29 C7 H13
D_AD30 AD29 FLD5
A8 AD30 FLD4 H14
D_AD31 B8 G12
49,51,52 D_CBE#[0..3] AD31 FLD3
FLD2 F12
D_CBE#0 M4 F13
D_CBE#1 C/BE0# FLD1
L3 C/BE1# FLD0 F14
D_CBE#2 F3
D_CBE#3 C/BE2# EECS
C4 C/BE3# EECS P7
49,51,52 D_FRAME# F2 FRAME# FLCS#/AEN N9
49,51,52 D_IRDY# F1 IRDY#
49,51,52 D_TRDY# G3 TRDY# FLOE# M8
49,51,52 D_DEVSEL# H3 DEVSEL# FLWE# M9
49,51,52 D_STOP# H1 STOP#
J1 A13 R477 10K
49,51,52 D_PAR PAR TEST 10K
H2 D13 R478
50 PCIIRQ#1 INTA# TEXEC 10K
J2 D14 R479
49,50,51 D_PERR# PERR# TCK 10K
A2 D12 R480
49,50,51 D_SERR# SERR# TI
LANEN A4 B12
D_REQ#2 IDSEL TO
49 D_REQ#2 C3 REQ#
D_GNT#2 J3 C12
49 D_GNT#2 GNT# VREF
51,52,58,65 PCIRST2# C2 RST#
23 PCICLK_ETHER2 G1 CLK
B9 B14 R481 549 STRAPPING OPTION
64 POWERGOOD ISOLATE# RBIAS10
65 3V_STBY_PWRGD A9 ALTRSt#
2 58 ETHER2_PME# A6 PME# 619
FLA1 - Pullup for STANDBY Voltage Present 2
C5 B13 R483
R484 10K C8
CSTSCHG/WOL RBIAS100 FLA0 - Pulldown for PCI Bus system
CLKRUN#
N11 LAN1_X1
X1
VSSPP1
VSSPP2
VSSPP3
VSSPP4
VSSPP5
VSSPP6
LAN1_X2
VSSPL1
VSSPL2
VSSPL3
VSSPL4
B10 P11
VSSPT
SMBALRT# X2
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
A10
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
SMBCLK
C9 SMBD
G14
G10
G11
C10
N12
H10
D11
H11
K12
E10
E11
F10
F11
L11
M6
G7
G8
G9
N1
H9
D4
D5
D6
D7
D8
P8
B3
B7
E2
K2
E5
E6
E7
E8
E9
E4
F5
F6
F7
F8
F9
F4
L6
LAN1_X1
LAN1_X2
R485 R486 Y7
R2110 2.7K D_REQ#2 10K 10K 2 1
3V_STBY R2111 4.7K D_GNT#2
25M-18pf-HC49S-D
C2155 C2156
22P 22P
3V_STBY
JLAN1_1-2
YJUMPER-MG
JLAN1
R474 D_AD20
LANEN 1
2
3
1 3V_STBY 22 1
YJ103
DECOUPLING CAPS FOR 82559
C662 C663 C664 Title Rev
+ EC70 C666 C667 C668 C669 C670 C661 C671 ETHERNET_82559
0.01uF 0.1uF 0.1uF 47U/10V/S Document Number 0A
0.01uF 0.01uF 0.01uF 0.01uF 0.1uF 0.1uF 0.1uF
A B C D E
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A B C D E
YLED GLED
4 4
FLOAT PLANE(CONNECT TO
CHASSIS GROUND BY 1500P
CAP) 15 1 3 5 7 16
2 4 6 8
T2
55 2_TDP 1 TD+ TX+ 16 9 10 11 12 AMP
2 15 JLAN2
TDC CMT
3 TD- TX- 14 15 Top View
1
R2656 6 11 2
100RST RD+ RX+
8 RD- RX- 9 3
7 10 4 12 R2657 300 2ACTLED
RDC RXC 2ACTLED 55
5 11 2LINKLED
2LINKLED 55
6
1
7 10 R2658 300
55 2_TDN 3VSB
C2230 C2231 1:1-TX 8 9 2SPEEDLED
22P 2SPEEDLED 55
22P 16
55 2_RDP
1
3
5
7
RJ45+LEDx2-D12-ML
R2659
120RST RN45
75
2
4
6
8
3 3
55 2_RDN
Place registers as
close to chip as
possiable
靠近chip RJ45
50 MIL
GROUND
TRACE
2 2
1 1

Title Rev
ETHERNET_82559_CONN
Document Number 0A

A B C D E
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A B C D E
VCC3
VCC
R454 RES_NOPOP
R455 RES_NOPOP
R448 Strapping option
1K (Do not Stuff)
4 4
U40B A_DTR#
A_RTS#
J12
1 2 DENSEL 74
1 2 DENSEL
3 3 4 4
5 5 6 6 DTR2_N_BOUT2 108
7 8 INDEX# 72 107 C639
7 8 MTR0# INDEX_N CTS2_N -12V
9 9 10 10 71 MTR0_N RTS2_N 105
11 12 DRV1# 70 103
11 12 DRV0# DR1_N/P16 DSR2_N
13 13 14 14 67 DR0_N SOUT2 106 0.1uF
15 16 MTR1# 66 104 SERIAL PORT2
15 16 DIR MTR1_N/P17 SIN2 U41
17 17 18 18 65 DIR_N DCD2_N 102
19 20 STEP# 64 109 R449 11 10
19 20 WDATA# STEP_N RI2_N B_RI# 0_OHM GND N12V
21 21 22 22 63 WDATA_N 12 ROUT5 RIN5 9 B_EIARI
23 24 WGATE# 62 B_TXD 13 8 B_EIATXD
23 24 TRK0# WGATE_N DIN3 DOUT3
25 25 26 26 61 TRK0_N
B_CTS# 14 ROUT4 RIN4 7 B_EIACTS
27 27 28 28 60 WP_N
B_RTS# 15 DIN2 DOUT2 6 B_EIARTS
29 30 RDATA# 59 B_DTR# 16 5 B_EIADTR
29 30 HDSEL# RDATA_N DIN1 DOUT1
31 31 32 32 58 HDSEL_N DTR1_N_BOUT1/BADDR 100 A_DTR# B_DSR# 17 ROUT3 RIN3 4 B_EIADSR
33 34 DSKCHG# 57 99 A_CTS# B_RXD 18 3 B_EIARXD
33 34 DSKCHG_N CTS1_N ROUT2 RIN2
RTS1_N/TRIS 97 A_RTS# B_DCD# 19 ROUT1 RIN1 2 B_EIACD
CON_2X17_NO_PIN5 RP253 DSR1_N 95 A_DSR# 20 VCC P12V 1 +12V_IO
5 4 73 DRATE0 SOUT1 98 A_TXD
VCC
FLOPPY 6
7
3
2
SIN1_N 96
94
A_RXD
A_DCD#
C640
GD75232 C641
DCD1_N 0.1uF
VCC 8 1 RI1_N 101 A_RI#
3 PD7 79 0.1uF 3
RP1K PD6 PD7
80 PD6
PD5 81 C645
PD4 PD5 R450
82 PD4
DRATE0_J R451 DRATE0# PD3 83 PD3 0_OHM
PD2 85 SERIAL PORT1 -12V
FOR TESTING PURPOSE PD2 U42 0.1uF
RES_NOPOP PD1 87
ONLY. PD0 PD1
89 PD0 11 GND N12V 10
( DONNT' STUFF FOR 12 9 A_EIARI
NORMAL OPERATION ) ROUT5 RIN5
A_TXD 13 DIN3 DOUT3 8 A_EIATXD
RPE 76 A_CTS# 14 7 A_EIACTS
MSEN0 58 PE ROUT4 RIN4
GPIO01/KBCLK 125 KBCLK 61 A_RTS# 15 DIN2 DOUT2 6 A_EIARTS
RINIT# 86 126 A_DTR# 16 5 A_EIADTR
INIT_N GPIO02/KBDAT KBDATA 61 DIN1 DOUT1
RERR# 88 A_DSR# 17 4 A_EIADSR
VCC VCC RACK# ERR_N ROUT3 RIN3
78 ACK_N GPIO03/MCLK 127 MSCLK 61 A_RXD 18 ROUT2 RIN2 3 A_EIARXD
RBUSY 77 128 A_DCD# 19 2 A_EIACD
BUSY_WAIT_N GPIO04/MDAT MSDATA 61 ROUT1 RIN1
RAFD# 90 20 1
RSTB# AFD_N_DSTRB_N R1340 1K VCC P12V +12V_IO
C651 91 STB_N_WRITE_N P12/PPDIS 121 VCC
C652 RSLCT 75 122 C649 C650
SLCT KBRST_N KBD_INIT# 10,11,50
0.1uF RSLIN# 84 123 GD75232
SLIN_N_ASTRB_N GA20 KBD_A20M# 50
0.1uF 0.1uF 0.1uF
R452
4.7K
LPT1
VCC3
48 SIO417
SERIAL PORT2
2 2
51 CN7 COM2
VCC 2 1 A_EIADTR B_EIACD B_EIARXD
1 2
4 3 A_EIADSR B_EIATXD
3 4
B_EIADTR
6 5 A_EIARXD 5 6
B_EIADSR
8 7 A_EIACD B_EIARTS
7 8
B_EIACTS
13 SLCT D81 B_EIARI
1N4148S 8P4C-180P 9
25
12 PE YJ205-CW
24 CN8
11 BUSY RSTB# R2654 33 STB# C2229 103P STB# R2655 2.7K 2 1 A_EIARI
23 4 3 A_EIATXD
10 ACK# RN37 RN38 8P4R-2.7K 6 5 A_EIACTS SERIAL PORT1
22 RSLCT 1 2 SLCT ACK# 1 2 SLCT 1 2 8 7 A_EIARTS Dtype-9pin
9 PRND7 RPE 3 4 PE BUSY 3 4 PE 3 4 COM1
21 RBUSY 5 6 BUSY PE 5 6 BUSY 5 6 8P4C-180P A_EIACD 1 6 A_EIADSR
PRND6 RACK# ACK# SLCT ACK# A_EIARXD 1 6 A_EIARTS
8 7 8 7 8 7 8 2 2 7 7
8P4R-33 CN9 CN10 A_EIATXD A_EIACTS
20 3 3 8 8
7 PRND5 RN39 8P4C-180P RN40 8P4R-2.7K 2 1 B_EIACD A_EIADTR 4 9 A_EIARI
PD7 PRND7 PRND4 1 PRND7 4 9
19 1 2 2 1 2 4 3 B_EIATXD 5 10
PRND4 PD6 PRND6 PRND5 3 PRND6 5 10
6 3 4 4 3 4 6 5 B_EIARTS 11
PD5 PRND5 PRND6 5 PRND5 11
18 5 6 6 5 6 8 7 B_EIARI
5 PRND3 PD4 7 8 PRND4 PRND7 7 8 PRND4 7 8
17 SLIN# 8P4R-33 CN11
4 PRND2 RN41 8P4C-180P RN42 8P4R-2.7K 8P4C-180P
16 XINIT# PD3 1 2 PRND3 PRND0 1 2 PRND3 1 2
PRND1 PD2 PRND2 PRND1 3 PRND2 CN13
3 3 4 4 3 4
15 ERR# PD1 5 6 PRND1 PRND2 5 6 PRND1 5 6 2 1 B_EIARXD
2 PRND0 PD0 7 8 PRND0 PRND3 7 8 PRND0 7 8 4 3 B_EIADTR
1 AFD# 8P4R-33 CN12 1
14 6 5 B_EIADSR
1 STB# RN43 8P4C-180P RN44 8P4R-2.7K 8 7 B_EIACTS
RSLIN# 1 2 SLIN# AFD# 1 2 SLIN# 1 2
RINIT#
RERR#
3 4 XINIT#
ERR#
ERR# 3
XINIT# 5
4 XINIT#
ERR#
3 4
8P4C-180P
5 6 6 5 6
RAFD# 7 8 AFD# SLIN# 7 8 AFD# 7 8 Title Rev
52 8P4R-33 CN14 SIO417_PPORT_FLPY_SPORT IF
8P4C-180P Document Number 0A

YCN25F-001-1 http://www.msi.com.tw 57 of 75
A B C D E
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A B C D E
RP251 RP4.7K S1_PCI_PME# R1385 10K

LPC_AD0 1 8
LPC_AD1 2 7 IO_PCIPME# R1386 10K
VCC3 3V_STBY
LPC_AD3 3 6
LPC_AD2 4 5 ETHER1_PME# R446 10K
SER_ISA_IRQ0_15 R437 4.7K ETHER2_PME# R447 10K
LPC_FRAME# R1341 4.7K U40A P1_PCI_PME# R1937 10K
S2_PCI_PME# R1938 10K

50,63 LPC_AD[0..3]
4 LPC_AD3 110 16 P2_PCI_PME# R1939 10K 4
LPC_AD2 LAD3 GPIO22/XA3
111 LAD2 GPIO23/XA2 17
LPC_AD1 112 18 BCM5701_PME# R1940 10K
LPC_AD0 LAD1 GPIO24/XA1
113 LAD0 GPIO25/XA0 19
114 EXTFAN R2615 4.7K
23 LPC_CLK_SIO LCLK
118 1 ETHER1_PME#
50 LPC_DRQ# LDRQ_N GPIO10/XA11
117 2 ETHER2_PME#
50,63 LPC_FRAME# LFRAME_N GPIO11/XA10 ETHER2_PME# 55
PCIRST2# 120 3 P1_PCI_PME#
51,52,55,65 PCIRST2# LRESET_N GPIO12/XA9 P1_PCI_PME# 29
SER_ISA_IRQ0_15 119 4 S1_PCI_PME#
49 SER_ISA_IRQ0_15 SERIRQ GPIO13/XA8
5 IO_PCIPME#
GPIO14/XA7 IO_PCIPME# 51
SPIO_XO 44 6 P2_PCI_PME#
32KX2 GPIO15/XA6 P2_PCI_PME# 44
42 7 S2_PCI_PME# 3V_STBY 3VSB
32KX1 GPIO16/XA5 S2_PCI_PME# 45
R438 10M 45 8 BCM5701_PME#
57 MSEN0 GPIO53/LFCKOUT GPIO17/XA4 BCM5701_PME# 41
22 SIOCLK48M 56 GPIO55/CLKIN
R439 10M SPIO_XIN 13 24 SLEDEN
GPIO7/HFCOUT GPIO30/XD7 SLEDEN 65
GPIO31/XD6 25
R1330 0_OHM 39 26 EXTFAN
63,66 PS_ON# ONCTL GPIO32/XD5 EXTFAN 65
49 GPIO43/PWBTOUT_N GPIO33/XD4 27
R440 54 28
3V_STBY GPIO54/VDDFALL GPIO34/XD3
47K 29
Y1 R441 4.7K GPIO35/XD2
47 ACBCLK GPIO36/XD1 30
1 2SPIO_XIN1 46 ACBDAT GPIO37/XD0 31
32_768KHz RES_NOPOP 20
C630 GPIO40/XCS3_N
3V_STBY 55 GPIO64/CKIN48 GPIO41/XCS2_N 21
C631 27P 124 22
5VSB 15P R442 GPIO00/CLKRUN_N GPIO26/XCS1_N
GPIO27/XCS0_N 23
9 GPIO05/XRDY
3
Strapping GPO60/XSTB2/XCNF2 32
33
3
GPIO61/XSTB1/XCNF1
R2639 Do not Stuff 10 GPIO06/XIRQ GPIO62/XSTB0/XCNF0 34
2K
RTCVCC 15 R443 4.7K
GPIO21/XWR_XRW
D74 41 14 3V_STBY
VBAT GPIO20/XRD_XEN
69 VDD1 GPIO42/SLBTIN_N 35
1N4148S VCC3 92 36
VDD2 GPIO50/PWBTIN_N SIO_SWITCH# 63,64
R2640 V_BAT 116 37 R1279 0_OHM EXT_SMI#
VDD3 GPIO51/SIOSMI_N EXT_SMI# 10,50
5.6K GPIO52/PWUREQ_SCI 38 SIO_WAKEUP 50
R2641
1K JBAT1
11
43
VSS1 GPIO63/ACBSA 48 Do not Stuff
VSS2 3V_STBY
1 3V_STBY
68
93
VSS3 R444 4.7K
(For testing
VBAT
2
3 115
VSS4
VSS5 GPIO44 50 PLED 62
R445
only3V_STBY
RES_NOPOP
)
GPIO45 51 SUSLED 62
D75 C2220 YJ103 12 52
104P VSB1 GPIO46/SLP3#
A C R2642 40 VSB2 GPIO47/SLP5# 53
1K
1N5817S
R2643 SIO417
1K
JBAT_1_1-2
2 2
1
YJUMPER-MG
R1342 R1343
BAT1 10K 10K
BATTERY
2
3V_STBY
VCC3
C1464
C1465 C1466 C1467 +
0.1uF 0.1uF 0.1uF
22uF/10V/20%
1 1

Title Rev
3V_STBY
C1468 SIO_LPC IF_GPORTS
C1469 C1470 + Document Number 0A
0.1uF 0.1uF
22uF/10V/20% MICRO-STAR INT'L CO.,LTD. Last Revision Date:
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XALAT#[0..2] 50
XALAT#0
XALAT#1
XALAT#2
XAD[0..7]
50 XAD[0..7]
U33
XAD0
XAD1
2
3
D1
D2
Q1
Q2
19
18
XA0
XA1 System BIOS FLASH RAM
4 XAD2 4 17 XA2 4
XAD3 D3 Q3 XA3
5 D4 Q4 16
XAD4 6 15 XA4
XAD5 D5 Q5 XA5
7 D6 Q6 14
XAD6 8 13 XA6
XAD7 D7 Q7 XA7 U34
9 D8 Q8 12
XA0 12 13 XAD0
XALAT#0 XA1 A0 DQ0 XAD1
11 CLK 11 A1 DQ1 14
1 XA2 10 15 XAD2
OC XA3 A2 DQ2 XAD3
9 A3 DQ3 17
74F574 XA4 8 18 XAD4
XA5 A4 DQ4 XAD5
7 A5 DQ5 19
U35 XA6 6 20 XAD6
XAD0 XA8 XA7 A6 DQ6 XAD7
2 D1 Q1 19 5 A7 DQ7 21
XAD1 3 18 XA9 XA8 27
XAD2 D2 Q2 XA10 XA9 A8
4 D3 Q3 17 26 A9
XAD3 5 16 XA11 XA10 23
6 D5 Q5 15 25 A11
XAD5 7 14 XA13 XA12 4
8 D7 Q7 13 28 A13
XAD7 9 12 XA15 XA14 29 VCC VCC
D8 Q8 XA15 A14
3 A15
XALAT#1 11 XA16 2
CLK XA17 A16
1 OC 30 A17
XA18 1 C629 C624
A18 0.1uF 0.1uF
74F574
50 ROM_CS# 22 CE
U36 50 XRC# 24
XAD0 XA16 XWC# OE
3 2 D1 Q1 19 50 XWC# 31 WE
3
XAD1 3 18 XA17
XAD2 D2 Q2 XA18
4 D3 Q3 17 AM29F040_PLCC
XAD3 5 16 XA19 XA20 TP7
XAD4 D4 Q4 XA20 1
6 D5 Q5 15
XAD5 7 14 XA21
XAD6 D6 Q6 XA22
8 D7 Q7 13
XAD7 9 12 XA23 XA22 TP9
D8 Q8 1
XALAT#2 11 CLK
1 OC
74F574
VCC VCC R424
0_OHM
C626 C628
0.1uF 0.1uF
2 2
POWER LEDs 5V_STBY VCC
R435 680 D25

1 1
2 1
X_DS4J1
R436 680 D26 Title Rev
2 1 FLASH_PORT80
Document Number 0A
X_DS4J1 MICRO-STAR INT'L CO.,LTD. Last Revision Date:

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L02-8008044
USB Connectors
F4
L82 80S/0805
VCC
YFUSE1.1AS-P
+ EC34 C2157
1000U/6.3V 104P
4 4
STACKED USB CONNECTOR
USB1
L85 1 5 L86
VCC VCC
1 2 2 6 1 2 USB1N
DATA0- DATA1-
3 DATA0+ DATA1+ 7
80S/0603 80S/0603 L88
L89 4 8
USB0N GND GND USB1P
1 2
USB0P 1 2 9 11
CGND CGND
10 12 80S/0603
RN46 CGND CGND
80S/0603
USBP0N USBP1P 7 8 USB1P
49 USBP0N
USBP0P USBP1N 5 6 USB1N USBx2-D8-BK
49 USBP0P
USBP1N USBP0P 3 4 USB0P
49 USBP1N
USBP1P USBP0N 1 2 USB0N
49 USBP1P
3 8P4R-27 3
8
6
4
2
2
4
6
8
1
3
5
7
RN20 CN3
CN2 8P4R-15K 8P4C-47P
X_8P4C-47P
7
5
3
1
1
3
5
7
2
4
6
8
RESVD
F5
L91 80S/0805
VCC
YFUSE1.1AS-P FOR EMI JUSB1

+ EC35 C2159 1 2
104P R2064 VCC1 GND3
1000U/6.3V
X_47K USB2# 3 4 USBGND2
USB2N GND4
USB2+ 5 6 USB3+
USB2P USB3P
7 8 USB3#
USBGND2 GND1 USB3N
2 2
9 GND2 VCC2 10
YJ205
CN4
L92 7 8 USB3#
5 6 USB3+
1 2 USB2# 3 4 USB2+
1 2 USB2#
80S/0603 8P4C-47P
L93 USBGND2
1 2 USB2+
RN21
7 8 USB2N
49 USBP2N
5 6 USB2P 80S/0603
49 USBP2P
3 4 USB3N
49 USBP3N
1 2 USB3P L94
49 USBP3P
8P4R-27 1 2 USB3#
1
3
5
7
1
3
5
7
RN22 80S/0603
CN5 L95
8P4R-15K
X_8P4C-47P USB3+
1 2
1 1
2
4
6
8
80S/0603
2
4
6
8
RESVD
Place close to OSB4. Title Rev
USB_PORT_and_FREE_GATES
Document Number 0A

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8 7 6 5 4 3 2 1
Keyboard/Mouse Ports
D D
5VSB
KBVCC
J55
J55_1-2 F3
3 L96 80S/0805
JC-D2-GN 2
1
D1x3-BK +
EC2 YFUSE1.1AS-P
R2067
STACKED PS2 CONNECTOR
C2161 X_47K JKBMS1
10U/16V/S 104P
VCC
14 16
FOR EMI 4 10
6 12
2 8
C 13 C
KBDATA L97 80S/0805 XKBDAT1 1 7
57 KBDATA
5 11
3 9
15 17
KBCLK L98 80S/0805 XKBCLK1
57 KBCLK
YMD12P-1
KBGND via Screw Hold

MSCLK L99 80S/0805 XMSCLK1 connect to System GND
57 MSCLK
MSDATA L100 80S/0805 XMSDAT1

57 MSDATA
B B
KBVCC
RN23 CN6
MSDATA 1 2 XMSCLK1 1 2
KBDATA 3 4 XKBCLK1 3 4
KBCLK 5 6 XKBDAT1 5 6
MSCLK 7 8 XMSDAT1 7 8
8P4R-4.7K 8P4C-180P
Place Close to Connector
A A

Title Rev
IO KB/MOUSE CONNECTOR
Document Number 0A

8 7 6 5 4 3 2 1
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5 4 3 2 1
C2162 VCC 5VSB VCC

IDE_LED 3VSB
101P
2
JFP1 C2163 R2069 R2070
4
1 10 R107 PLED RN24A 330 330
GNDK KEYLOCK VCC
330 8P4R-4.7K
D 2 NC NC 11 101P RN24B D
8P4R-4.7K PLED1 JGL1
HDD+ 3 12 IDE_LED
1
VCC HDD+ HDD- IDE_LED 49,65 1
R2071 330 RN24C
3
Q41 2
4 GNDL SPEAKER 13 5 6 3
2N3904S
R2072
PLED2 5 14 RN24D 8P4R-4.7K X_YJ103
SLED2 BUZ+ PLED Q42
X_0 58 PLED 7 8
PLED1 6 15 BUZZER# 2N3904S
PLED1 BUZ- 8P4R-4.7K
PWRSW# 7 16 R2074 5VSB
64 PWRSW# PWSW+ VCCSPK VCC
R2073 330 330
8 17 FP_RST# JFP1_14-15
PWSW- RESET FP_RST# 64
R2075 330
2
9 NC GNDR 18 YJUMPER-MG PLED2
2
YJ2090013 RN25A
BZ1 8P4R-4.7K
BUZZER
RN26
1 2
1
48 ALARM
3 4 RN25B
5 6 3 4 Q43
1
7 8 2N3904S
1N4148S RN25C 8P4R-4.7K
D73 8P4R-150 VCC 5 6 Q44
50,64 SOFF# 2N3904S
C Q32 C
50 SPKR
R2076 2.2K 2N3904S C2164 8P4R-4.7K
104P 5VSB
IPMI_SPKR
63 IPMI_SPKR
3VSB
VCC
8
PLED2
VCC RN25D
2
8P4R-4.7K
2
R2077
4.7K RN27A
8P4R-4.7K
7
14
RN27B
1
JGLBTN1 3 4 Q45 SCSI LED Control GPIO28

R2078 13 12 2N3904S
1
1 SLP_BTN# 50
330 RN27C 8P4R-4.7K
2
58 SUSLED 5 6 Q46 SCSILED Enable 1
2
U228F 74HC14 2N3904S

YJ102 C2165 8P4R-4.7K SCSILED Disable 0
7
4.7U/0805
1
B B
A A

Title Rev
FRONT PANEL
Document Number 0A

5 4 3 2 1
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8 7 6 5 4 3 2 1
5VSB 3VSB
D D
+
C2208 C2209 C2210 C2211 +
104P 104P EC49 104P 104P
10u EC50
10u
5VSB
14
IPMI_PSON# 1 2 PS_ON#
PS_ON# 58,66
7 U232A
5VSB 3VSB 74LVC07S
IPMI1
1 2
C 3 4 C
LPC_FRAME#
50,58 LPC_FRAME# 5 6
LPC_AD0
50,58 LPC_AD0 7 8
LPC_AD1 5VSB
50,58 LPC_AD1 9 10
LPC_AD2
50,58 LPC_AD2 11 12
LPC_AD3 14
50,58 LPC_AD3 13 14
RTCVCC 15 16 IPMI_PWRBTN# SIO_SWITCH#
17 18 3 4 SIO_SWITCH# 58,64
19 20 U232B
21 22 7
74LVC07S
23 24
25 26
27 28
29 30
31 32
33 34 IPMI_PSON#
RSMRST# 35 36 IPMI_PWRBTN# 5VSB
IPMI_SPKR 37 38 IPMI_ATXPOK#
62 IPMI_SPKR 39 40
1N4148S 14
D72 YJ220-CB
IPMI_ATXPOK# 5 6 PS_PWRGD
PS_PWRGD 64,66
7 U232C
B 74LVC07S B
5VSB
5VSB
IPMI_PSON# 1 2
R2616 IPMI_PWRBTN# 3 4
5VSB IPMI_ATXPOK# 5 6
22M
7 8
14 RN36
8P4R-2.7K
9 8 R2617 RSMRST#
4.7K
7 U232D
74LVC07S R2618
C2212 10K C2213
A 105P 105P A

Title Rev
IPMI
Document Number 0A

8 7 6 5 4 3 2 1
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A B C D E
+5VSB 5VSB 5V_STBY 5VSB
5VSB 5VSB
2
R2113 5VSB
10K
14
14
ON/OFF SWITCH
14
62 PWRSW# 1 25ns 2 3 25ns 4 1
4
18ns 3 R2114 1 2 1K 4
SIO_SWITCH# 58,63
From Front Panel U226A U226B 2
74HC14 74HC14 U227A To SIO417
2
74HC08
2
C2183
7
105P C2184
105P
1
5VSB
5VSB
5VSB
14
14
14
50,62 SOFF# 5 25ns 6 4
18ns 6 9 25ns 8
From SIO417 U226C POWERGOOD 5
74HC14 U227B U226D
74HC08 74HC14
7
7
3 ITP_RESET# 3
9 ITP_RESET#
To ITP
5VSB
VCC
VCC VCC 5VSB R412 1K
U28
14
VCC25
2
R2115 PS_PWRGD 4 2 9
14
10K VCC RESET# POWERGOOD
8
14
14
18ns POWERGOOD 55
12 10
11 P_DELAY 3 U227C
1
18ns MR
1 2 3 25ns 4 13 1 74HC08
62 FP_RST# GND
U227D
7
From Front Panel 74HC08 MAX6315 U229A
U228A 74HC14 U228B 74HC14
7
2
1 2
7
POWERGOOD_CMIC 12,15
C2185 VCC
105P RESET TIMEOUT = 140ms PS_PWRGD 74F07S
1
RESET THRESHOLD =
4.5V R1373 75
14
VCC25
R2652
5 6 X_0_OHM
CPU_VRM_OEN 67
2 2
U228C 74HC14
VCC
7
R2653
0_OHM
R1942 4.7K R409 1K
VCC25
14
VCC
U229B
PS_PWRGD 9 8 3 4 PS_PWRGD#
63,66 PS_PWRGD PS_PWRGD# 11,27,37,50
74F07S
U228D 74HC14
C1PWRGD R2080 0 C2PWRGD
7
ON_3VSB 66
POWERGOOD
VCC R406 39
VCC_P
R407 2.7K
14
VCC U229C
1
3 5 6 CPU1_PWRGD 3
C1PWRGD 2
67 CPU1_VRM_PWRGD
74F07S
1 U230A 1
7
74HC08 VCC R1388 39

VCC_P
R1389 X_4.7K
14
VCC U229D
4 Title Rev
6 9 8 POWER_ON_LOGIC
CPU2_PWRGD 5
C2PWRGD 5 Document Number 0A
U230B 74F07S
74HC08 MICRO-STAR INT'L CO.,LTD. Last Revision Date:
7

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+12V
+12V
R2619 4.7K R2620 4.7K

R2095
4 4.7K 4
VCC
R2116 330 JP1 R2621 1K Q60
1 SI2303DS-S-SOT23
C Q59 2
SCSILED2 B
31 SCSILED2
E HEADER 2 Q61
2N3904S 3
IDE_LED YFET-NDS7002AS 2
49,62 1
C Q58 C2214 + EC51 SFAN1
SCSILED1 B 10U/16V YJ103-BO
31 SCSILED1 X_104P
E
2N3904S
C Q57
58 SLEDEN B
E +12V
2N3904S
IDE DISK_ACTIVITY LED
R2622 4.7K R2623 4.7K
3 3
R2624 1K Q62
VCC3 SI2303DS-S-SOT23
VCC3 Q63
VCC3 3
YFET-NDS7002AS 2
1
2
4
6
8
C2186 C2215 + EC52 SFAN2

RN33 10U/16V YJ103-BO
R2614 104P 8P4R-1K X_104P
4.7K VCC3
14
1
3
5
7
PCIRST# 1 2.6ns 2 PCIRST1# +12V

49 PCIRST# PCIRST1# 11,27,37
7 U231A To CMIC_LE, 2 *CIOB_X2
74LVC07S
R2625 4.7K R2626 4.7K
VCC3
14
3 2.6ns 4 PCIRST3# R2627 1K Q64

PCIRST3# 49
2 SI2303DS-S-SOT23 2
7 U231B To IDE,TTL
74LVC07S
Q65
3
VCC3 R2628 330 YFET-NDS7002AS 2
58 EXTFAN 1
14 C2216 + EC53 SFAN3
10U/16V YJ103-BO
PCIRST2# X_104P
5 2.6ns 6 PCIRST2# 51,52,55,58
7 U231C
74LVC07S To VGA,82550,SIO,
P33slot
VCC3
VCC25
14 R2117 4.7K
U26
9 2.6ns 8 DIMM_RST# 3V_STBY 1K R408
DIMM_RST# 16,17,18,19 3V_STBY
PCIRST1# C2187 X_104P
7 U231D To DIMM 4 VCC RESET# 2 3V_STBY_PWRGD 55
74LVC07S
PCIRST3# C2188 X_104P C615 3 MR RESET TIMEOUT = 140ms

0.01uF 1
VCC GND RESET THRESHOLD =
1
MAX6315 4.5V 1
PCIRST2# C2189 X_104P
14
PCIRST# C2190 X_104P

PCIRST3# 11 10 RSTDRV Title Rev
25ns RSTDRV 48
RESET_LOGIC
W83782D/PC97317 Document Number 0A
U228E 74HC14 DIMM_RST# C2191 X_104P
7

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5VSB
VCC 3SBY Voltage Regulator
+5V_STBY 5V_STBY +5VSB
5VSB 3VALWAYS
VR1
YLT1087S-0.8A
4 3 2 4
C1498 + VIN VOUT
ADJ
22uF/10V
+ EC72 + EC73
10U/16V/S C2221 R2644 10U/16V/S C2222
104P 187RST 104P
1
R2645
332RST
5VSB VCC3 VCC VCC3 VCC -12V +12V
U143
1 13 3VALWAYS
3.3V 3.3V
2 3.3V 3.3V 14
3 3.3V GND6 15
4 GND1 GND7 16
5 17 +12V
GND2 +5V
6 +5V +5V 18
A
7 5VAUX +5V 19
8 GND3 -12V 20
3 9 GND4 +12V 21 3
10 22 R2646 Q66 D76 3VSB 3V_STBY
GND5 +12V 4.7K P-CH YFET-SI2303DS 1N5817S
63,64 PS_PWRGD 11 POWER GOOD On/Off 23
SOT-23
C
12 +3.3V GND8 24
POWERCONN2X12
C1431 C572
0.1uF R2647 4.7K Q67 +
64 ON_3VSB
4
2N3904S 22uF/10V
CR6 +
1 YFET-CEU603ALS EC74 C2223
TO-252 1000U/6.3V 104P
3
N-CH
5VSB
VCC3
5VSB
8
3V_STBY 5VSB
RN27D
8P4R-4.7K VCC3
2
R2079
R1268 RN28A
X_4.7K 8P4R-4.7K 4.7K XPS_ON#
7
C596 C597 C598 C599 C600

Q47 C594 + + C595 + + + + +
1
2N3904S
RN28B 100uF/10V/20% 22uF/10V 100uF/10V/20% 100uF/10V/20% 100uF/10V/20% 100uF/10V/20% 100uF/10V/20%
2 2
PS_ON# 3 4 Q48
58,63 PS_ON#
2N3904S C2166
8P4R-4.7K X_104P
+12V -12V
+12V_IO
FOR EMI
+ C1471 + C602 + C603

+ C605
100uF/16V/20% 100uF/16V/20% 100uF/16V/20% 22uF/25V/20%
+12V
+12V +12V_IO
VCC
U144
1 +12V COM 5
2 +12V COM 6
3 +12V COM 7
4 8 + C609 + C610 + C611 + C612 + C613 + C614
+12V COM
100uF/16V/20% 100uF/16V/20% 100uF/16V/20% 100uF/16V/20% 22uF/10V 22uF/10V
POWERCONN2X4
1 1

Title Rev
WTX_POWER_CONNECTORS
Document Number 0A

A B C D E
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5 4 3 2 1
VCC
VCC3
R2693
D VRM_VID[0..4] 20.5_1% D
8,48 VRM_VID[0..4]
R2081
120KRST
VCC
CPU1_VRM_PWRGD 64
C2167 R2600
105P X_1K
C2228
VCC_P
X_104P
DO NOT POP
U218
20 VCC R2094
PGOOD 19
10 VSEN Q68
HIP6301_COMP 6 8 YFET-NDS7002AS
COMP FS/EN CPU_VRM_OEN 64
120KRST
R2082 C2168 VRM_VID4 1
1.62KRST 0.1u VID4
C
VRM_VID3
VRM_VID2
2
3
VID3 PWM4 18
11
PWM4_C 68 CPU_VRM_OEN C
R2083
15K
VRM_VID1 4
VID2
VID1
PWM3
PWM2 14
PWM3_C
PWM2_C
68
68
HIGH: DISABLE VRM
VRM_VID0 5 15
VID0 PWM1 PWM1_C 68 LOW : ENABLE VRM
HIP6301_FB 7 17 ISEN4_C R2084 4.32K
FB ISEN4 ISEN3_C PHASE3_C 68
ISEN3 12
9 13 ISEN2_C
GND ISEN2 ISEN1_C
ISEN1 16
R2085
HIP6301 4.32K PHASE4_C 68
R2086
C2169 4.32K PHASE2_C 68
TP_6301_VRM_R4 R2087
2200p 4.32K PHASE1_C 68
C2170 VCC
120p
R2088
B 330K B
R2089
X_2K
A A

Title Rev
VRM-1
Document Number 0A

5 4 3 2 1
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5 4 3 2 1
+12V L101
1 2 COIL_P12V_CPU
2.5uH/20A
EC75
1800u-16V EC36 EC37 EC38 EC39 EC40 EC41
1800u-16V 1800u-16V 1800u-16V 1800u-16V 1800u-16V 1800u-16V
D +12V D
+12V
C2171 D77
PWM_BOOT_1 C2172 C2173 D78
C A
105P/0805 PWM_BOOT_2 C A C2174
105P/0805
0.1u 1N5817S
PWM_H_G_1 0.1u 1N5817S
PWM_H_G_2
COIL_P12V_CPU
COIL_P12V_CPU
4
R2648 Q49
4
0/0805 FDB6035AL R2649 Q50
U219 L102 VCC_P 0/0805 FDB6035AL
1 U220
1.1UH/25A/68-8 1 L103 VCC_P
1 2 1.1UH/25A/68-8
3
6 1 2
3
VCC
6 VCC
4
1 7 Q51
UGATE PVCC PWM_L_G_1 1 FDB7045L C2224 Q52
8 PHASE LGATE 5 1 UGATE PVCC 7
C 3 X_104P 8 5 PWM_L_G_2 1 FDB7045L C2225 C
67 PWM1_C PWM PHASE LGATE X_104P
2 3
3
BOOT 67 PWM2_C PWM
2
3
C2182 BOOT
4 105P/0805 C2175
GND 105P/0805
4 GND
HIP6601
HIP6601
67 PHASE1_C
67 PHASE2_C
+12V
+12V
C2176 D79
C2178 D80 PWM_BOOT_4 C2177
C A
PWM_BOOT_3 C A C2179 105P/0805
105P/0805
0.1u 1N5817S
0.1u 1N5817S PWM_H_G_4
B PWM_H_G_3 B
COIL_P12V_CPU
COIL_P12V_CPU
4
4
R2650 Q54 R2651 Q53
0/0805 FDB6035AL U221 0/0805 FDB6035AL VCC_P
U222 L105 VCC_P L104
1 1
1.1UH/25A/68-8 1.1UH/25A/68-8
1 2 6 1 2
3
3
VCC
6 VCC
4
4
1 7 Q55
Q56 UGATE PVCC PWM_L_G_4 FDB7045L
1 UGATE PVCC 7 8 PHASE LGATE 5 1
8 5 PWM_L_G_3 1 FDB7045L C2226 3 C2227
PHASE LGATE X_104P 67 PWM4_C PWM X_104P
3 2
3
67 PWM3_C PWM BOOT
2
3
BOOT C2180
C2181 4 105P/0805
105P/0805 GND
4 GND
HIP6601
HIP6601
67 PHASE4_C
A 67 PHASE3_C A

Title Rev
VRM-2
Document Number 0A

5 4 3 2 1
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A B C D E
VCC3
J51
1 RSB_SDA C1432
SDA 0.1uF
GND 2
3 RSB_SCL
SCL VCC3 VCC3 VCC25
VDD_CMIC VCC25
4 MOLEX0022447031 4
R372 R373 R374 R375 R376 R377 R378 R379 R380 R381
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
U15
50 RSB_SDA 19 SDA SDA0 5 CPU_SDA 3,5

50 RSB_SCL 18 SCL SCL0 6 CPU_SCL 3,5
SDA1 8 RCC_SDA 12,15,27,37,41,48

SCL1 9 RCC_SCL 12,15,27,37,41,48
R382 100 12
VCC3 SDA2 MEMA_SDA 18
1 A0 SCL2 13 MEMA_SCL 18
R383 100 2 A1
3 A2 SDA3 15 MEMB_SDA 16,17,19,24
SCL3 16 MEMB_SCL 16,17,19,24
R384 100
VCC3 4
INT0
INT1 7
20 VDD INT2 11
INT3 14
10 VSS
ADD. : 1110 001z INTOUT 17
3 Z - R/W BIT PCA9544 3
PLACE NEAR LOAD

VDD_IMB
22uF/10V 22uF/10V 22uF/10V
C1560 C1562 C561
1.5V @ 8 A
VDD_IMB
CR7
VCC L109 3.3UH YFET-CEU603ALS L110
R2691
4 3
YCUNI-004
1
C2249 C2250 EC88 EC89 C2251 C2252 3.3UH EC90 EC91 C2253 C2254
4
1u 1u 1000U/6.3V 1000U/6.3V 1u 1u 820UF_6.3V 820UF_6.3V 1u 1u
2 2
1 D88
R2680
3
4.7
VCC
SBG1040CT-S-TO263
R2681 VDD_IMB
10 R2682 R2683
1K 1K
R2684
U234
24
1 VCC GND 8
2 CS- FB 7
3 CS+ BST 6
C2255 C2256
1u R2685 1u 4 5 C2257
PGND DH 1u
2K SC1101CS
1 R2686 1
120RST

C2258 Title Rev
R2687 VDD_IMB VOLT.-REG_and_I2C
+12V 4.7 104P Document Number 0A

A B C D E
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A B C D E
R2660
0.005-2512
EC76 EC77 C2232 C2233 R2661
1800u-16V 1800u-16V 1u 1u VCC25
+12V L106 51RST
VCC_DDR
C2234
1.6u/30A 100p R2662
EC78 1.5KRST
4
4 C2235 C2236 R2663 Q69 150U/TANT 4
1u 1u 68RST R2664 4.7 FDB6035AL FB_VCC2_5
1
C2237
C2238 100p R2665
3
R2666 1KRST
2.2K 0.047u C R2667 2.2
VCC_SC2450_DDR B Q70 VCC25
C2239 E
0.1u 2N3904S
C2240
R2668 C2241 0.1u
1K 0.1u D82
R2669 L107
A C
4
2.5V AND 1.25V 3.01KRST
RB051L-40-S-SOD106 Q71
U233
C
R2670 1 FDB7045L 1.1u/30A
4.7 D83 EC79 EC80 EC81 C2242 C2243
FB_VCC2_5 1 28 R2671
3
FB1 RREF 75KRST RB051L-40-S-SOD106 820U_4V 820U_4V 820U_4V 0.1u 0.1u
2 COMP1 AGND 27
3 NC1 NC2 26
C2244
A
4 BG CLKOUT 25
FB_VTT 5 24 47p
FB2 EXTCLK
6 COMP2 OC-1 23
REGDRV 7 22
VCC_SC2450_DDR R2672 REGDRV OC-2 VCC_DDR
8 ENABLE OC+ 21
0 9 20
PHASE2 PGND
10 DRVH2 PHASE1 19
3 11 BSTH2 DRVH1 18 3
12 DRVL2 BSTH1 17
13 BSTL2 DRVL1 16
14 VCC BSTL1 15
SC2450ISW-SO28 VCC_DDR A_VTT
R2673
5.1K R2674
C
VCC_SC2450_DDR R2675 255
C2245 10RST D84
EC82 EC83
1u 10u 10u 1N5817S FB_VTT
A
R2676
C 1KRST
REGDRV B Q72
E
2N3904S
VCC_DDR
EC84 A_VTT
4
Q73 150U/TANT
FDB6030L1B
2
R2677 1 2
4.7 DPAK
4u
3
EC85
L108 EC86 EC87 C2246 EC93 EC92
1
C2247
R2678 D85 + + + +
2.2
RB051L-40-S-SOD106
C2248
2
0.1u
A
D86
A C
4
560uF/4V 560uF/4V 820U_4V 0.1u
RB051L-40-S-SOD106 Q74 560uF/4V 0.1u 560uF/4V
R2679 1 FDB6030L1B
4.7
3
C
D87
1N5817S
A
1 1

Title Rev
VCC25_VTT_GENERATION
Document Number 0A

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A B C D E
PLACE THESE CLOSE TO DIMMs

4 4
VCC25 VCC25
220pF/50V
220pF/50V
100
C1291
1uF/10V
100
C1293
1uF/10V
C1290
C1292
R338
R336
SSTLREF_D1 16,17
220pF/50V
220pF/50V
1uF/10V
SSTLREF_D2 18,19
220pF/50V
220pF/50V
1uF/10V
100
100
C463
C464
R341
C465
C457
C458
R339
C459
3 3
2 2
1 1

Title Rev
SSTL_VREF
Document Number 0A

A B C D E
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1
M1 M2
1 GND1 GND2 2 1 GND1 GND2 2 M4
3 GND3 GND4 4 3 GND3 GND4 4
5 GND5 GND6 6 5 GND5 GND6 6 1 GND1 GND2 2
5 GND5 GND6 6
7 GND7 GND8 8
MNT_HOLE_8PIN MNT_HOLE_8PIN
M5 M6 M7 MNT_HOLE_8PIN
MNT_HOLE_8PIN MNT_HOLE_8PIN MNT_HOLE_8PIN

M9 M10 M11
M8
3 GND3 GND4 4 3 GND3 GND4 4 3 GND3 GND4 4 1 GND1 GND2 2
7 GND7 GND8 8

A
MNT_HOLE_8PIN A
M12 M13 M14

J56
7 mil , 50 ohn at Top side
FM1 FM2 TTOP0
1 TTOP1
1 1 2
X_F_PADS X_F_PADS X_CON2
FM3 FM4
1 1
J57
X_F_PADS X_F_PADS 5.5 mil , 50 ohm at S1 side
FM5 FM6 SSS10
1 SSS11
1 1 2
X_F_PADS X_F_PADS X_CON2
FM7 FM8
1 1
J58
X_F_PADS X_F_PADS 5.5 mil , 50 ohm at S2 side
SSS20
1 SSS21
2 VCC3
X_CON2
J59
5.5 mil , 50 ohm at S3 side
SSS30
1 SSS31
2
X_CON2
J60 7 mil , 50 ohn at Bottom side

BBOT0
1 BOTT1
2
X_CON2
Title Rev
MOUNTING HOLES
Document Number 0A

1
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A B C D E
BCM5701
PCI RESOURCE TABLE I2C ADDRESS Map

(TO BE CHECKED)
DEVICE/ Bus/Num Signal Address Device
SLOT PCIIRQ REQ# GNT# PCIRESET IDSEL
4 CPU/0 CPU_SCL/SDA A0 MEMORY CPU 1 4
CSB5-PCI SLOT 1 PCIIRQ2# D_REQ#0 D_GNT#0 PCIRST# D_AD18 CPU/0 CPU_SCL/SDA 30 THERMAL SNSR CPU 1
PCIIRQ3# CPU/0 CPU_SCL/SDA A2 MEMORY CPU 2
D_AD19 CPU/0 CPU_SCL/SDA 32 THERMAL SNSR CPU 2

CSB5-PCI SLOT 2 PCIIRQ5# D_REQ#1 D_GNT#1 RCC/1 RCC_SCL/SDA C0 CMIC FUNCTION 0
RCC/1 RCC_SCL/SDA C0 CMIC FUNCTION 1
ETHERNET-2(i82559) PCIIRQ1# D_REQ#2 D_GNT#2 PCIRST# D_AD20 RCC/1 RCC_SCL/SDA C0 CMIC FUNCTION 2
RCC/1 RCC_SCL/SDA C8 CIOB 1
ATI Rage XL PCIIRQ4# D_REQ#4 D_GNT#4 D_AD21 RCC/1 RCC_SCL/SDA CA CIOB 2
RCC/1 RSB_SCL/SDA 80 RSB5
PCIIRQ8# S1_REQ#0 S1_GNT#0 S1_PCIRST# S1_AD18 MEMA/2 MEMA_SCL/SDA A0 DIMM1
CIOB-1-S_SCSI PCIIRQ9# MEMA/2 MEMA_SCL/SDA A2 DIMM2
MEMA/2 MEMA_SCL/SDA A4 DIMM3
PCIIRQ6# P1_REQ#0 P1_GNT#0 P1_PCIRST# P1_AD18 MEMA/2 MEMA_SCL/SDA A6 DIMM4
CIOB-1-P_PCI SLT -1
3
PCIIRQ7# MEMB/3 MEMB_SCL/SDA A0 DIMM5 3
MEMB/3 MEMB_SCL/SDA A2 DIMM6
CIOB-2-P_PCI SLT -1 PCIIRQ10# P2_REQ#0 P2_GNT#0 P2_PCIRST# P2_AD18 MEMB/3 MEMB_SCL/SDA A4 DIMM7
PCIIRQ11# MEMB/3 MEMB_SCL/SDA A6 DIMM8
BCM5701 PCIIRQ0# P2_REQ#1 P2_GNT#1 P2_PCIRST# P2_AD19
S2_GNT#0 S2_PCIRST# S2_AD18

CIOB-2-S_PCI SLT -1 PCIIRQ14# S2_REQ#0
PCIIRQ15#
CIOB-2-S_PCI SLT -2 PCIIRQ12# S2_REQ#1 S2_GNT#1 S2_PCIRST# S2_AD19

PCIIRQ13#
2 2
Power Supply Symbols & Usage

SYMBOL VALUE LOGIC
VCC_P Set by VID PROCESSORS, CMIC GTL TERMINATION

VCC25 +2.5V CORE Power for - CMIC, CIOB & CSB5
and Power for DIMMs
A_VTT +1.25V SSTL Termination Power for Memory Bus
VCC3 +3.3V CSB5 , PCI Connectors and MISC.
VCC +5V PCI Connectors and MISC.
1 1
+12V +12V CPU VRM Modules & PCI Connectors
-12V -12V PCI Connectors
5V_STBY +5V Misc. Title Rev
3V_STBY +3.3V Misc. Document Number
I2C ADDRESS & PCIIRQ MAP
0A
VDD_IMB 1.5V CMIC, CIOBs MICRO-STAR INT'L CO.,LTD. Last Revision Date:
A B C D E
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A B C D E
4 :- Add 0 Ohm Res to Isolate I2C From OSB.
REV-A1
1 :- Initial Release
4 4
CHANGES: REV-A3 TO REV-A4

1 :- Sync. Elca. Schematics and North_Dome (Date:04-20-01).
2 :- Change "Do Not Stuff Comp" to NOPOP.
3 :- Change IDSEL Res Value to 2K.
4 :- ADD 0 Ohm Series Res to PLLRST(PS_PWGD#) U100 , U127 & U63.
5 :- Change R1154 to 1.5K, Page 9.
6 :- Change R1339 to 4.7K; Page 48.
7 :- Change C1314, C1338, C1339, C1354, C1378, C1379, C1400 & C1550 from V33 to V25.
8 :- Change Q33 to MJD45H11, (Old Sym has a wrong pin out and MMJT9435 is EOL), Page 41.
9 :- Change 150 Ohm Termination Res for HIT#, HITM#, BNR#, BINIT#, and MCERR# to a 40 OHM Res, & 27PF cap. (Page 10)
10 :- Add Pull-up to P2_PCI_PME#, S2_PCI_PM#, P1_PCI_PME# & BCM5701_PME# pins. (Page 54)
11 :- Add LED/Res for LINK pin, Switch the place of Res and LED for LINK, LINK1000, LINK100 & Traffic Pins. (Page 41)
3 12 :- Add Series 200 OHM Res between U197-K18 and Y4-2. (Page 41) 3
13 :- Change R1118 to NOPOP, (Page 10).
CHANGES since 0423 Release to Vendor.

1 :- Change Memory CS to allow three configuration:1,2 Way Interleave, and No Interleave.(Page16,17,18.19)
2 :- Change C1983 PKG to C1210.
3 :- Remove R1125 Page 10.
CHANGES since 0430 Release to Vendor.

1 :- Add 4.7K pull-up to PS_PWRGD (Page 57).
2 :- Add Jumper for CMIC Strapping pins instead of Nopop.
3 :- CMIC has I2C=C0, change the I2C address for CIOBX to C2 and C4.
4 :- Add 0 Ohm Res to Isolate OSB5 I2C from CIOBX2, CMIC, if it is needed.
5 :- Add QS for BCM_SDA and BCM_SCL (Page 40).
2 6 :- Compare BCM logic and update the pinouts. 2
7 :- Page 57, Add Delay Reset Logic For Pass1 CIOBX2 FIB Part.
8 :- Page 22, Add Qswitch to be able to Switch between 12Mhz and 14Mhz.
9 :- Page 48, Add GIOP to control the Qswitch in page 22.
1 1

Title Rev
REV_HISTORY
Document Number 0A

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A B C D E
4 4
3 3
CLOCKING SCHEME
- CPU 0
- CPU1 DIMM PLL
- CMIC From CLK BCLK
SYNTH. 8 Pairs of 100MHz
- DIMM PLL BCLK#
Differential CLOCKs
- ITP Connector
for 8 DIMMs
- PROBE Header
P1_FBCLK
CLK SYNTH.
BCLK 6 Pairs of 100MHz
BCLK#
2 Differential FBOUT#
2
CLOCKs P1_CLKO TO PCI

FBOUT
33MHz 33MHz CONNs.
CIOB S1_CLKO
14.318 MHz 48MHz PCI-X PLLs

X-TAL 33MHz Low Skew
48MHz
Buffer n
14MHz 33MHz CLOCK TO RSB and TO PCI
DEVICES behind it.
CONNs.
S1_FBCLK
P1_FBCLK
P1_CLKO TO PCI
48MHz USB CLK to RSB 33MHz
CONNs.
CIOB S1_CLKO
1 1
48MHz CLK to SIO
PCI-X PLLs
14 MHz CLK to RSB Micro Star Restricted Secret
TO PCI Title Rev
CLOCK_BLOCK DIAGRAM
CONNs. Document Number 0A

S1_FBCLK Thursday, August 16, 2001
A B C D E
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A B C D E

IMB IMB 8 DIMMs

PCI BUS 3 PCI BUS 4 PCI BUS 1 PCI BUS 2

PAGE # DESCRIPTION PAGE # DESCRIPTION PAGE # DESCRIPTION

18. DIMM CONNECTOR 5, 6 41 BCM5701 Signal Pins 64 POWER ON LOGIC

21. MEMORY TERMINATIONS - 2 44 CIOBX2_PCIXP2_SLOT1 67 VRM-1 Document Number 0A

Size Document Number Rev

Date: Monday, August 20, 2001 Sheet 1 of 1

Micro Star Restricted Secret

MICRO-STAR INT'L CO.,LTD. Last Revision Date:

AB25 D8# VID1 E3

AA22 D10# VID3 C3

D16# GTLREF0 P1_GTLREF0 7

3 AD25 D18# DSTBP3# Y11 3

AC17 D34# SLP# AE6 SLP# 5,10

22 HCLK1 ADSTB#1 5,11

DRDY# 5,11 Micro Star Restricted Secret

VCC_P U125B VCC_P

N27 T24 Y25 AB3

VCC VCC VSS RSVD77

R7 V2 VCC_P AC7 AD17

VCC VCC VSS VSS

VCC VCC VSS VSS

MICRO-STAR INT'L CO.,LTD. Last Revision Date:

FOSTER Monday, August 20, 2001

PD#8 D7# VID0 P_VID1

AC24 D20# DSTBP1# Y17 DSTBP#[0..3] 3,11

AB16 D32# BPM5# E4

22 HCLK2 ADSTB#1 3,11

Place these close to CPU2 Micro Star Restricted Secret

VCC_P U126B VCC_P

N25 VCC VCC T8 Y7 VSS RSVD68 Y27

N29 VCC VCC T26 Y19 VSS RSVD73 AA3

R23 V6 AC7 AD17

VCC VCC VSS VSS

FOSTER FOSTER Monday, August 20, 2001

No. 69, Li-De St, Jung-He City,

Z = R/W bit VCC3

DON'T STUFF DON'T STUFF

4 Addr._0 : 0011X00Z OR P1_SM_ADDR0 4

: 1001X01Z DON'T STUFF

PLACE EACH 220pf OF Micro Star Restricted Secret

MICRO-STAR INT'L CO.,LTD. Last Revision Date:

VCC3 14 VDD GND 8

MICRO-STAR INT'L CO.,LTD. Last Revision Date:

25 25 CHAINED ALONG PROCS.

Look at Routing guidelines while

sheet Micro Star Restricted Secret

DON'T STUFF PLACE NEAR CPU2

3,5,8 A20M# SLP#

PLACE THESE CLOSE TO CPU2

L43 4.7uH L44 4.7uH

C1146 + C1147 C1148 +

C1150 Title Rev

L45 4.7uH MICRO-STAR INT'L CO.,LTD. Last Revision Date:

R1144 0_OHM 1 2 R1145 0_OHM 1 2 Monday, August 20, 2001

PA#3 K15 C2 PD#0

Micro Star Restricted Secret

MICRO-STAR INT'L CO.,LTD. Last Revision Date: