ERROR DETECTION AND CORRECTION FOR SMALL LOW COST

NON-VOLATILE MEMORIES

Paola Vega-Castillo1 , Wolfgang H. Krautschneider2

1
Instituto Tecnológico de Costa Rica, 2 Hamburg University of Technology

[email protected], [email protected]

ABSTRACT: 2. DESCRIPTION OF THE MEMORY

ARCHITECTURE
Error detection and correction strategies involve area
overhead and may slow down memories. In this paper,
two conventional error detection and correction strategies 2.1 Description of memory architecture
are discussed and compared with a self-reparable memory Figure 1 shows a block diagram of the general
approach. The specific case study of small, low cost single architecture of the studied memory systems.
poly non volatile memories in 0.35µm technology is
presented.

1. INTRODUCTION

The reliability of memory systems can be improved with

help of error detection and correction strategies. In case of
memories, a lot of effort has been put to improve the
reliability of volatile memories, especially in case of
SRAM. Much work has been done in the development of
testing algorithms, error correction and detection
approaches and built-in self-test memories. However most
of these strategies are of no practical application in case of
Figure 1. Block diagram showing the peripherals included
non-volatile memories due to speed constraints.
in the memory systems
In some non-volatile memories, the constraint is not
only limited to speed, since area consumption may play an The input stage includes input registers for address and
important role when error detection and correction is data. The bank and wordline decoders decode the memory
implemented. This is the case of single-poly non-volatile address to access the corresponding memory bank and
memories. wordline of the memory cells that are to be accessed. The
In this paper, possibilities to implement error detection timing unit provides the clock signal during the
and correction circuitry in non-volatile memories are programming and erasing operations. The program/verify
discussed. The case study of low cost, small non-volatile stage ensures that the data are correctly
memories implemented with single-poly memory cells is programmed/erased by checking that the current level of
presented with a description of the required peripherals for the cells corresponds to a ‘1’ or a ‘0’, according to the
the error detection and correction stage. For this memory contents that the user wants to store. Level
application, the silicon area occupied by the memory shifters control the wordline voltage level to adjust
system is of extreme importance, since the advantage of according to the required memory operation, that is,
the single poly memories resides in the cost savings related programming, erasing or reading. The bitline bias stage
to the use of 100% standard CMOS technology. provides the required bitline bias for the required memory
The paper is organized as follows: first, the architecture operation. For more details on the peripherals, the user is
of the memory systems for the case study is described. referred to [1], where a detailed description of the
After that, two error detection and correction approaches functionality and the circuitry of the peripherals is
are presented. In addition to this, a proposal of a self- presented.
reparable memory is described and discussed. Finally, the The memory systems described in this paper are small
case study of single-poly non-volatile memories in 0.35µm memories for applications such as calibration memories,
technology is presented. product identification, configurable products, multiple-

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time programmable memories (MTPs), one-time
programmable memories (OTPs) and small data/code
storage for ASICs and System on Chip ICs. Thus, memory
sizes of 256 bit, 1 kbit, 4 kB and 32 kB were considered.
These memories were chosen to have word widths of 8-
bit and 16-bit. Specifically, the 256-bit and 1 kbit
memories have 8-bit wide words, and the 4 kB and 32 kB
memories have 16-bit wide words. These word widths
were fixed considering power consumption issues during
the programming and erasing operations since the
memories were designed for word-access. For single-poly
non-volatile memories, power consumption during
programming and erasing is a very important concern. The
word width can of course be fixed according to the power
consumption constraints of each particular application.
Figure 2 presents a simplified diagram of the Figure 3. Block diagram of the architecture of the 32kB
architecture used to estimate the area consumption of the memory
256-bit memory and that of the 1 kbit memory. Both the
256-bit and 1 kbit memories follow the same scheme, 3. ERROR DETECTION AND CORRECTION
except that the 256 bit memory consists of only one APPROACHES
memory bank, whereas the 1kb memory includes four
memory banks. Therefore, the 256-bit memory does not 3.1 Hamming code error detection and correction
include the three-state buffers stage required for the 1 kb techniques
memory to direct the outputs of the sense amplifier banks The strategy for error detection and correction depends
to the output stage. Each memory bank is an array of 32 on the following factors:
words of 8 bits each.
-Memory size (especially word size)
-Hardware overhead
-Number of errors to be detected
-Number of errors to be corrected
In case of applications with small word size, the number
of bits required to represent the code (parity) word may
cause a large hardware overhead. The minimum number of
bits required for one-bit error correction applying
Hamming coding is [2]
D + P + 1 ≤ 2P
where D is the number of data bits and P the number of
parity bits.
This means 4 parity bits for 8-bit words and 5 parity bits
Figure 2. Block diagram of the architecture of the 256 bit for 16-bit words, leading to a memory array area overhead
and 1 kbit memories of about 50% and 31%, respectively. With this, single-
The architecture of the 4 kB memory is similar to that of error detection and single-error correction can be
the 1 kbit memory, as presented in figure 2. However in implemented.
this case the width of the word was increased from 8 bits Figure 4 presents the block diagram of the memory
to 16 bits, the number of memory banks was increased to system including the stages required to implement single
8, with 256 words per bank. In case of the 32 kB memory, error correction and single error detection (SED-SEC) by
the memory consists of eight memory blocks of 4 kB each, means of Hamming codes. The blue blocks show the
enabled by an additional memory bus controller, as shown additional circuitry required for the SED-SEC scheme.
in figure 3. Moreover, the blue rectangle in the memory array block
reminds about the several additional parity bits required to
implement the Hamming-coding.

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 Figure 5. Block diagram of memory system for the self-
reparable memory
In the programming procedure of conventional
memories, the input data is read into input registers and
Figure 4. Block diagram of memory system for Hamming kept ready for programming. Once the address data is read
error detection and correction in, the programming bias is applied and the program-verify
Single error correction and double error detection (SEC- operation starts.
DED) would be possible by adding one additional parity In contrast, in the self-reparable memory the input data
bit to the SED-SEC system. is read out and the parity bit is generated. After the address
data is read in, it is compared with the contents of a bank
of registers storing the address of defective locations. If
3.2 Two dimensional parity check
the address does not coincide with that of a defective
Single error correction and single error detection can location, the input data is programmed to the location
also be achieved by means of two dimensional parity addressed by the user.
checks. In this case, an additional parity bit is attached to Figure 6 shows a flow diagram of the programming
each word to determine the position of the erroneous word. operation of the self-reparable memory.
The position of the erroneous bit can be determined by
defining a parity word for a group of W words and letting
the ith bit of the parity word store the resulting parity of
the ith bits of the W words. This is the so called 2-
dimensional parity approach.
Although this approach would consume less area and
power than the Hamming codes, in case of non-volatile
memories the use of parity words would make cell
programming excessively slow, since every time a new
data is programmed, the parity word must be updated. If
the parity word is implemented using registers, the parity
word would be lost after power shuts down, and there
would be no safety that the stored data are correct. If the
parity word is implemented using non-volatile memory,
the memory must be updated after every programming Figure 6. Flow diagram of programming operation of the
operation, thus slowing down the whole system. self-reparable memory
3.3 Self-reparable memory In case the user attempts to write data to a defective
location, the system will issue a flag to redirect the input
As a compromise between parity checking and parity- data in order to program them into one of the replacement
based error correction, a self-reparable system can be
locations. In this way, the memory repairs itself by
implemented, which does not repair the memory contents
preventing data storage into defective memory cells,
but replaces defective locations by additional words without any effort from the user.
reserved for replacement of the defective memory
locations. Figure 5 shows the block diagram of the Initially, the address of the contents to be accessed is
memory system including the necessary stages for read in. After this, in a conventional memory, the data
implementation of the self-reparation feature. would be read out by the sense amplifiers and passed to

3
the output registers. In contrast, in the self-reparable
memory the outputs of the sense amplifiers would be
transferred to a parity checker before they are passed to the
output registers.
As its name indicates, the parity checker compares the
outputs of the sense amplifiers with the parity bit stored for
that word. If the memory contents are correct, the outputs
of the sense amplifiers are sent to the output registers. In
case the memory contents are corrupted, the address of the
defective location is stored, the memory contents are still
sent to the output buffers, but this time an error flag is
activated, indicating the user that the data at the output of
the memory contains an error. In addition to that, the
corrupted location is replaced by a replacement address, so
that every time the user attempts to access the contents of
that address, the memory fetches the replacement location.
When this correction takes place, an error flag and a Figure 8. Read procedure of self-reparable memory
correction flag are activated, indicating the user that the including verification of accessed address
output data contains an error but the defective location has
been replaced. Figure 7 illustrates the read procedure
4. CASE STUDY
including the steps performed when a replacement location
needs to be accessed. For this case study, the implementation and area
estimation of memory systems with storage capacity of
256 b, 1 kb, 4 kB and 32 kB are presented.
In order to estimate the area consumption of the memory
arrays, a parameterized Skill code was developed to
automatically generate the layout of the memory array
including guard rings in the design environment Cadence
Design Framework II. The configurable parameters of this
Skill code are the transistor width, transistor separation,
number of wordlines and number of bitlines.
To estimate the area consumption of the digital
peripherals, all the digital circuitry was designed with help
of Verilog Hardware Description Language using
parameterized code. The Verilog descriptions were
synthesized with Synopsys Design Compiler to obtain the
netlist description of the circuitry. After that, the area
consumption was estimated using Silicon Ensemble by
floorplanning each netlist with a row utilization of 75%.
The configurable parameters in these Verilog descriptions
are: number of memory banks, number of words and
Figure 7. Read procedure of self-reparable memory
number of bits per word.
showing access of a replacement location
Table 1 summarizes the area consumption of the analog
According to figure 8, if the user attempts to access the
and digital memory peripherals without including the area
corrupted location in the next read operation, the
consumption of charge pumps. The total area consumption
replacement location will be addressed, and the error flag
of the memory systems is presented in table 5.6 for the
and correction flag will be deactivated.
implementations with cell transistor widths of 10 µm and
2.5 µm.

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 Table 1. Area consumption of studied memory systems
Table 3. Area consumption of peripherals for self-
reparable memory system
Memory Cell array Digital Analog
Capacity area peripheral area peripheral
(µm2) (µm2) area (µm2) Memory Digital Analog Cell array
256 bit 4047 59 850 11 283 Capacity circuitry circuitry area
area area overhead
1 kbit 17 266 80 000 14 825 overhead overhead
4 kB 471 465 266 027 132 500 (µm2 / %)
(µm2 / %) (µm2 / %)
32 kB 3 968 868 2 168 400 1 060 000
256 bits 12 960 / 1 664 / 4.8% 2790 / 69%
22%
The area consumption estimation of the cell array as
1 kbit 23 773/ 3 435 / 23% 10 886 /63%
presented in table 1 is based on the layout of memory cells
29.7%
implemented with transistor width of 2.5 µm, which is the
best compromise between area consumption, power 4 kB 59 836/ 13 315 / 52 530/11%
consumption and programming/erasing efficiency for the 22.5% 10%
0.35 µm technology used to implement the cells [1]. 32kB 478 688/ 106 520 / 598 958
Table 2 presents a summary of the area overhead caused 22% 10% /15.1%
by implementing the additional circuitry to obtain the
Hamming code-based single error detection single error
correction (SED-SEC) scheme in for studied memory As can be seen from table 2, most of the area overhead
systems. of the Hamming code-based error detection and correction
is caused by the area increase of the memory array. In
Table 2. Area overhead of Hamming code-based error contrast, the area consumption of the self-reparable
detection and correction memory can be defined by the designer, who can vary the
number of replacement words according to the
requirements of a specific application.
Memory Digital Analog Cell array
Capacity circuitry circuitry area In case of the self-reparable memory, the area overhead
area area overhead of the digital peripherals can be reduced by optimizing the
overhead overhead implementation of some stages, i.e., a manual layout of the
(µm2 / %)
2 2 address decoders.
(µm / %) (µm / %)
When considering the area overheads of both
256 bits 13327/ 3456/ 1 368 approaches for the same memory capacities and
22% 30.6% /33.8% architectures, it can be seen that for all cases the self-
1 kbit 12637.5/ 3456/ 5 472 reparable memory saves area in comparison with the
16% 28.8% /30.4% Hamming code-based error detection and correction
scheme. Figure 9 presents a comparison of the area
4 kB 11164/ 34 560/ 116 599
overhead of the self-reparable memory and Hamming code
4.2% 26%
/24.73% SED-SEC. Design flexibility can be mentioned as one
additional valuable feature of the self-reparable memory.
32kB 18773/ 34560/ 1 110 230
3.2% In addition to that, the self-reparable memory saves
1% /29.28%
power consumption in comparison with the Hamming-
code SED-SEC scheme, since no parity bits must be
Table 3 presents a summary of the area overhead caused programmed/erased. This is of great importance for single-
by implementing the additional circuitry to obtain a self- poly non-volatile memory systems, since the programming
reparable memory. For the memory sizes of 256 bits, 1 and erasing mechanism of the cells is drain avalanche hot
kbit, 4 kB and 32 kB, a number of 16, 64 and 128 and carrier injection, and thus high cell currents.
1024 replacement words were included, respectively,
representing a total of 16 replacement words per memory
block.

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 Figure 9. Comparison of area overhead Hamming-code
SED-SEC and self-reparable memory.

5. CONCLUSIONS

Possibilities to enhance the reliability of non-volatile

memory systems were presented regarding the application
of Hamming-code based error detection and correction
strategies and the implementation of a self-reparable
memory. The comparison of these two schemes was
presented for the particular case of single-poly non-volatile
memory systems.
It was found that self-reparable memories offer the
advantage of design flexibility, lower area consumption
and lower power consumption.

6. REFERENCES

[1] P. Vega-Castillo. “Potentials and Constraints of Single-Poly

Non-volatile Memories”, ISBN 3-8322-5533-8, Shaker
Verlag, October 2006.
[2] A. van de Goor. “Testing Semiconductor Memories: theory
and practice”, ISBN 0471925861, Wiley and Sons, 1991.