MINI PROJECT REPORT

ON

DEVELOPMENT OF FPGA BASED SMART TRAFFIC LIGHTS

CONTROLLER SYSTEM WITH IMAGE PROCESSING

BACHELOR OF TECHNOLOGY IN
ELECTRONICS AND COMMUNICATION ENGINEERING

SUBMITTED BY

V.SASI KIRAN 19KQ1A04I9

CH.PRASANNA 19KQ1A04D2

N.SAI KUMAR 19KQ1A04H4

P.SAMARA SIMHA REDDY 19KQ1A04H7

U. SAI RAKESH 20KA5A0418

Under the Esteemed Guidance of

XXXXXXXX,XXXX

Assistant Professor

Department of Electronics & Communication Engineering

PACE INSTITUTE OF TECHNOLOGY AND SCIENCES
(Autonomous)
(Approved by AICTE, New Delhi, Accredited by NBA and NAAC with ‘A’
Grade) (Permanently Affiliated to Jawaharlal Nehru Technological University
Kakinada, Kakinada)Vallur,NH-16, Ongole, Prakasam District,A.P-523272
2020-2024
 PACE INSTITUTE OF TECHNOLOGY &SCIENCES
(Autonomous)
(Approved by AICTE, New Delhi, Accredited by NBA and NAAC with ‘A’ Grade)
(Permanently Affiliated to Jawaharlal Nehru Technological University Kakinada,
Kakinada) Vallur,NH-16, Ongole, Prakasam District,A.P-523272

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE
This is to certify that the mini project entitled “DEVELOPMENT OF
FPGA BASED SMART TRAFFIC LIGHTS CONTROLLER SYSTEM WITH
IMAGE PROCESSING is Bonafide work of V.SASI KIRAN(19KQ1A04I9),
CH.PRASANNA(19KQ1A04D2),N.SAIKUMAR(19KQ1A04H4),P.SAMARA
SIMHA REDDY(19KQ1A04H7),U. SAI RAKESH(20KQ5A0418) in the partial
fulfillment of the requirement for the 6th semester in ELECTRONICS AND
COMMUNICATION ENGINEERING for the Academic year 2022-2023.This
work is done under my supervision and guidance.

Signature of Guide Signature of Head of the Department

XXXXXXXXX,XXX Mr.Dr.M.RAJASEKHAR, MTech, Ph.D.

Assaiant Professor Associate Professor

Signature of the Evaluators

1.
2.
3.
 ACKNOWLEDGEMENT

We thank the almighty for giving us the courage and perseverance in completing the
mini-project. This project itself is an acknowledgement for all those people who have given
us their heartfelt cooperation in making this project a grand success.
We extend our sincere thanks to Dr. M. VENU GOPAL RAO, B.E, M.B.A, D.M.M.,

chairman of our college, for providing sufficient infrastructure and a good environment in the
college to complete our course.
We are thankful to our secretary Dr. M. SRIDHAR, M.Tech. M.B.A., for providing the
necessary infrastructure and labs and also permitting to carry out of this project.
We are thankful to our principal Dr. M. SREENIVASAN, M.S., Ph.D., for providing the
necessary infrastructure and labs and also permitting to carry out this project.
With extreme jubilance and deepest gratitude, we would like to thank the Head of the
E.C.E. Department, Dr. M. RAJASEKHAR, M.Tech., Ph.D., for his constant encouragement.
Our Special thanks to our mini project coordinator Dr. SK. SUBHANI, M.Tech., Ph.D.,

Assistant Professor, Electronics and Communication Engineering, for his support and
valuable suggestions regarding project work.
We are greatly indebted to project guide XXXXXXXX,XXXXX., ,Assistant Professor,
Electronics and Communication Engineering, for providing valuable guidance at every stage
of this project work. We are profoundly grateful towards the unmatched services rendered by
him.
Our special thanks to all the faculty of Electronics and Communication Engineering
and peers for their valuable advice at every stage of this work.
Last but not least, we would like to express our deep sense of gratitude and earnest
thanks giving to our dear parents for their moral support and heartfelt cooperation in doing
the main project.
V.SASI KIRAN 19KQ1A04I9
CH.PRASANNA 19KQ1A04D2
N.SAI KUMAR 19KQ1A04H4
P.SAMARA SIMHA REDDY 19KQ1A04H7
U.SAI RAKEH 20KQ5A0418
 INDEX
CONTENTS PAGE NO

1.ABSTRACT 5

2.INTRODUCTION 6

3.HARDWARE DESCRPTION 8
LANGAGUGE

4.METHODLOGY :
Proposed Project Architecture 9
System Working Principle 10
General flow of the system 11
Flowchart of Proposed System 11
Image Acquisition 12
Region of interest (ROI) 13
Image Enhancement (Histogram Equalization)
13
Colour-Based Segmentation 14

Morphological Operations 16

Vehicle Detection and Counting 19

UART- Serial communication 19

Serial Communication on Altera DE2 board

19

RECIEVER MODULE 20
5. UART- Serial Communication Connection 23
6. TRAFFIC LIGHT CONTROLLER SYSTEM
ON DE2 BOARD 24
7. TIMING ALGORTHIMS FOR TRAFFIC
LIGHT SIGNAL 32
8. COST ANALAYSIS OF THE PROJECT 34
9. RESULTS AND DISCUSSIONS 35
 vii

ABSTRACT
As the population of the city, as well as the number of automobiles travel on the
roads are increasing day by day, traffic congestion at the junctions is becoming a
huge problem for many major cities nowadays. One of the reasons behind this traffic
issue is the inefficiency of the techniques and algorithms used in the existing traffic
light system which unable to adapt to the continuous changing traffic situation and
eventually lead to traffic congestion spreads and occurrence of road accidents
increase. Therefore, to prevent the situations further deteriorate, there is a pressing
need for the introduction of advanced system and technology that able to improve the
current traffic light control system to better accommodate this increasing demand.

In this project, an FPGA based Smart Traffic Light Control System (STLCS) is
proposed with the aid of Computer Vision techniques in traffic signal control. The
developed STLCS is comprised two development boards; Altera DE2 board and
Raspberry Pi 3B+. Altera DE2 board is mainly used to execute the automated traffic
light signalling system while the Raspberry Pi 3B+ is utilized to in-charge the
computer vision tasks, for instance, video acquisition, processing, segmentation,
object detection, etc. In this system, a wide view angle digital camera is fixed at the
intersection road for real-time monitoring on four intersecting roads

Keywords: Traffic Congestion, FPGA, Image Processing, Raspberry Pi 3B+, Altera

DE2 FP
 8

INTRODUCTION

1.1 Background of Study

It is undeniable that traffic congestion is one of the main challenges in today’s

society and this issue is becoming serious day after day. Traffic congestion occurs
when the available street capacity is not able to accommodate the traffic demand and
there are several factors which cause traffic congestion, such as high rate of urban
population growth, rapid increase in the number of automobiles, ineffective road
construction strategies and management by government, and especially those non-
adaptive traffic light system which is becoming obsolete and unable to handle high
traffic density nowadays.

Traffic congestion has led to multiple negative impacts on our society and
environment, for instance, wasting the road users’ time and delays which reduces
productivity of employees, wasting the fuel and increasing the greenhouse gases
(especially CO2) emission which worsens the air quality and lead to global warming,
interferes or blocks the passage of emergency vehicles which are travelling to their
destination, etc. In order to overcome impacts from traffic congestion, the invention
of the Smart Traffic Light Controller System (STLCS) is vital to provide smooth
motion of vehicles in the transportation routes and also regulates the flow of vehicles
through the traffic intersections of many roads.

In Malaysia or any developing country, the traffic lights that are widely seen
nowadays consist of three lights: Green is the go sign, Yellow is the wait sign and
Red is the stop sign, while in some urban areas, there are some traffic light control
systems with countdown timers, which are able to improve the safety in the traffic by
allowing drivers to make better and safer traffic decisions based on the remaining
time of red or green light. Even though there are plenty of features that were
implemented to the traditional traffic light system to improve the traffic flow
efficiency, these traffic light control systems are still hardwired at the time of
installation which means most of them are pre-programmed for a fixed duration for
every change in the signals

interfaces to accommodate various application needs. Altera board provides

 9

Figure 1.1 : Block Diagram of Altera DE2 board (Philipp, 2019)

Figure 1.2 : Altera Development and Education Board (Terasic Technologies, 2012)

In the proposed system, the Altera DE2 FPGA Board is used to construct a
Traffic Light Controller (TLC). The design flow of the TLC using FPGA board is
shown in the figure below. In the circuit description process, Verilog HDL is used to
program the TLC software and then followed by the functional simulation and
synthesis. The design flow is followed until the time simulation and then the
generated file is downloaded into the Altera FPGA Board.

Figure 1.3 FPGA Design Flow (Dilip, 2012)

 10

1.1.1 Hardware Description Language (HDL)

Verilog is a Hardware Description languages (HDL) used to program the FPGA

chips. Verilog is relatively recent, and the programming concept is quite similar to
the C programming language, therefore, it allows the hardware design programmer to
easily familiarize and understand the programming styles that are used in Verilog.
Moreover, Verilog is a weakly typed programming language and it can be used to
design digital hardware at any level of abstraction. For example, Behavioural level,
Register-transfer level, and Gate level. In Behavioural level, the behaviour of a
system is described with a set of instructions or algorithms that are executed in
sequence, for example, Verilog uses always block, functions, and task to perform
sequential instructions in behavioural level design. Furthermore, in the Register
Transfer Level, the characteristic of a digital system is described using operations
(i.e. always, assign, etc). Operations in the register transfer level play around with the
data transfer between the registers, and it must be synchronized with the clock cycle.
In Gate level, it refers to the logic level design of a digital system that comprises a
network of gates and registers instanced from the technology library. It uses
predefined logic primitives like NOT, AND, NOR, and other gates in the design.

Nowadays, one of the two most commonly-used languages in digital

hardware design is Verilog HDL and the other is VHDL. In this project, Verilog
HDL is used to write the TLC and UART serial communication program into the
Altera DE2 board. The reason Verilog HDL is selected because Verilog
programming is easy to understand and write compare to VHDL since the
programming concept is quite similar to C programming
 11

METHODOLOGY

3.1 Proposed Project Architecture

Camera
module Red LEDs (4)

Raspberry Pi 3B+ USB to RS232

Serial cable Yellow LEDs
ALTERA (4)
Cyclone II- DE2
Board
Green LEDs (8)
Mouse and
Monitor
keyboard

Figure 3.1 : Block Diagram of the Proposed System Architecture

Hardware Modules: Software Modules:

 Raspberry Pi 3B+
 Spyder IDE
 Traffic lights circuit
 ModelSim
 Serial cable
 Quartus II
 Monitor
 Camera module
 Altera DE2 Board
 12

3.2 System Working Principle

Image Vehicle
Acquisition detection Timing
and and Calculation
Processing counting

Send signal back

to Raspberry PI Altera DE2 turn Send calculated
for next turn of ON green LED time from
detection and based on the Raspberry PI to
timing calculation
received value Altera DE2
 13

Figure 3.2 : General Flow of the System

The Figure 3.2 above shows the general flow of the developed Smart Traffic Light
Controller System (STLCS) with image processing. In the first step, a wide-angle
camera module is used to monitor and capture the traffic lanes at the junction. Next,
image processing techniques such as image enhancement, restoration, morphological
process, segmentation are applied to the captured image for queuing vehicle
detection and count on particular traffic lane. Moreover, the number of vehicles
counted on a particular lane is further used in the dedicated timing algorithm to
calculate the proper green time to maximize the traffic flow across the junction. After
timing calculation, the calculated time is sent via UART serial communication to
Altera DE2 which function as TLC, the TLC will display the green light according to
the received time value. After the green light, the yellow light will be turned ON and
the Altera DE2 Board will send a request signal to Raspberry Pi to perform timing
calculation for the next turn of green light and return the calculated value to Altera
DE2 to display it. These processes are repeated to provide optimal traffic flow at the
junction.

Figure 3.4 : Image Processing Flowchart

 14

3.4.1 Image Acquisition

Image acquisition is an action to retrieve an image from the external source. In the
proposed system, image acquisition is performed by the hardware-based source which
means the Pi camera module as shown in Figure 3.5 is used to capture the real-time
image of intersecting roads. Image acquisition plays an important role and a few
precautions need to be taken before proceeding to coming image processing steps.
First, the camera module must be placed at a position to ensure that the camera’s field
of view covers the junction roads which is as shown in Figure 3.6 below. Next, owing
to the limited focal length, the lack of autofocus abilities, and the relatively low
resolution of the Pi Camera, the distance between the camera module and traffic
prototype model becomes critical which may affect the image clarity and give rise to
some image noise that cannot be removed through image processing techniques.
Therefore, the position of the camera is vital and required gradual trial and error
attempts during the installation process for the better detection process.

Figure 3.5 : Pi Camera Module

Figure 3.6 : Camera’s Field of View

 15

3.4.2 Region of interest (ROI)

Region of interest (ROI) is referred to a portion or region of an image that consists of

useful or meaningful information and may be extracted out with the need image
operations. Region of interest (ROI) is a useful function in this smart traffic light
project because it is used to provide the boundaries for vehicle detection and ignore
the interferences or noises appearing outside the boundaries. In this project, ROIs are
created on each of four intersecting roads at the junction which is as shown in Figure
3.7 below. Vehicles that are present within the ROIs created will be detected using
segmentation operation.

Figure 3.7 : Region of interests (ROIs) selection

3.4.3 Image Enhancement (Histogram Equalization)

Histogram Equalization is an image enhancement technique that modifies or adjusts

the image intensities to have a better contrast image. The working concept of
histogram equalization is basically “equalizing” the original intensity histogram, so
that the output image contains a uniform distribution of intensities. From Figure 3.8
below, before applying the histogram equalization, the colour intensity of a colour
image is low in dynamic range which means a certain range of intensity levels are
held by many pixels than other intensity levels. As a result, the image shows fewer
details. However, when the histogram equalization is applied, it will alter the
image by adjusting the
 16

probability density function (PDF) of the original histogram so that all the range of
intensity levels are spread to each pixel almost equally, as a result, the image will
have more uniform distribution of intensities, improved image quality, enhanced
brightness and at the same time more details in low illumination image.

Figure 3.8: Image before and after Histogram Equalization

3.4.4 Colour-Based Segmentation

Colour-based segmentation is a segmentation technique that partition an image into

different regions such that each region shares homogeneous colours correspond to
useful information for the objects in the image. In other words, each region defines a
class of pixels that has similar colour properties. In this project, colour segmentation
is conducted using HSV (Hue, Saturation, and Value) colour model, because HSV is
able to separate colour from different intensity which is robust to remove the shaded
region and adapt to different illumination, thus, it is able to improve the accuracy and
effectiveness in the detection process.

In Table 3.3 below, it shows an RGB image that is converted to the HSV
colour model. After this, different range of hue, saturation and, value are adjusted to
create multiple masks for each RGB, white and black colour. The output HSV colour
segmentation will be a binary image which HIGH or 1 represent the pixels within the
 17

threshold while the remaining pixels which are not within the threshold will be set to
0 or LOW.

Table 3.3 : Colour Models and Masks

RGB colour image HSV colour image

Red Mask Green Mask

Blue Mask White Mask

Black Mask
 18

3.4.5 Morphological Operations

After segmentation, the images may be highly distorted due to amplified noises.
Therefore, morphological operation are required to remove all of these noises that
will affect the extracted shape and texture of the images. The morphological
operation requires two inputs, one is the binary images while the other is the kernel
which decides the nature of the operation. In this part, morphological opening with
3x3 kernel is applied first on the filtered binary image to remove the amplified noises
outside the segmented object which is as shown in Figure 3.9 below.

Figure 3.9: The Binary Image before and after Morphological Opening Operation

After removing the outer noises, erosion function with 4x4 kernel is used to
erode the boundaries of the foreground object to separate the clustering vehicles
region into two separate objects for better vehicle number estimation. From Figure
3.10 below, it shows the images before and after the morphological erosion operation.

Figure 3.10: Binary image before and after Morphological Erosion Operation
 19

Furthermore, morphological closing function with the closing kernel of 4x4 is

further applied to join or close the small holes inside the foreground objects and at
the same time minimize two foreground objects touching to each other. The figure
below shows the before and after morphological closing is being applied.

Figure 3.11: The Binary Image before and after Morphological Closing Operation

3.4.6 Vehicle Detection and Counting

After a series of image processing processes, the moving foreground objects

representing the moving vehicles can be distinguished and detected easily in the
binary image. The centroid for each of detected foreground object is calculated as
shown in Figure 3.12 below. The system will estimate the number of vehicles
according to the number of centroids detected.

Figure 3.12 : Centroid for Detected Vehicles

3.5 UART- Serial communication

3.5.1 Serial Communication on Altera DE2 board

The implementation of UART serial communication in the Altera DE2 board is

 20
divided into three sub-modules which are the receiver module, transmitter module,
and baud rate generator which is clearly shown in Figure 3.13 below. The
implementation of the UART communication module is the realization of the three
sub-modules. Firstly, the baud rate generator is used to produce a local clock signal
which is much higher than the baud rate to synchronize the UART reception and
transmission. Secondly, the receiver module is used to receive the serial data at RXD
and convert them into parallel data. Lastly, the transmit module is used to converts
the bytes into serial bits according to the basic frame format and transmits those bits
through TXD.

Figure 3.13 : UART Module (Mitu. R, 2017)

3.5.1.1 Receiver Module

As mentioned before, the receiver is basically used to receive the serial data from
transmitter and then convert it into 8-bit parallel data. During the UART reception, it
is critical to correctly define the start-bit from a frame of serial data since the
receiving clock are asynchronous with the transmitting clock. The receiver module
will receive serial data from receiving pin (RXD) and if the state of received data
transits from logic 1 to logic 0, it can be regarded as the beginning of a data frame
(start-bit). When the UART receiver module is idle, it has been waiting for RXD
logic state to transit. In the receiver module, after the start-bit has been identified, the
receiver will sample the logic state at the middle of each bit serial data by using half
of the clock cycle per
 21

bit value that is calculated in the baud rate generator module. Each sampled value of
the data state is then deposited in the 8-bit register by order. When the count equals
to 10 bit (start-bit + 8 bit data + stop-bit), and verified, received serial data are
converted into a byte of parallel data and stored. In this project, the UART receiver
module is implemented by using the finite state machine.

After the configurations, “ dmesg | grep tty” command is used to search the related
configuration files with the term “tty” and display the messages regarding to the
status of configuration. From the Figure 3.23 below, it shows that ttyUSB0 port is
enabled and ready to be used.
 22

Figure 3.23 : Verify the ttyUSB0

3.5.2 UART- Serial Communication Connection

Figure 3.24 below shows the connections of serial communication for the Raspberry
Pi 3B+ and Altera DE2 FPGA. From the figure, USB to serial RS232 converter cable
is used to provide connectivity between USB port (Raspberry Pi 3B+) and RS232
serial port (Altera DE2 FPGA). Within the USB to RS232 converter cable, it consists
of ch340 chip which function to equalize the voltage level for serial communication
between USB and RS232 port, and at the same time interconnect the receiver
terminal to transmitter terminal so that duplex communication can be made.

Raspberry PI 3B+ USB to Serial RS232 Alter DE2 FPGA (RS-232

(USB port) converter cable port)

Figure 3.24 : UART Connections

 23

3.6 Traffic light Controller System on Altera DE2 Board

3.6.1 Structure of Traffic Junction

Figure 3.25 : Model of the Traffic Junction

From the Figure 3.25 above, it depicts a general structure of traffic junction which
consists of North, East, and West and South directions. Four traffic lights with a set
of four lights: two green, yellow and red light are used to control the traffic flow or
discharge the vehicles from each direction of the lane. From the model of the traffic
junction above, vehicles are free to move from West to North, South to West, East to
South, and North to East directions. However, for the vehicles that need to move in
straight or right direction, drivers are required to obey the traffic signals with pre-
defined sequences or phases.
 24

To design a traffic light controller, traffic phase design is one of the important
steps to separate the conflict of vehicle movements in an intersection into various
phases. In the proposed system, four-phase signals are used in the implementation of
the TLC and the movement of vehicles across the traffic intersection in different
phases are shown in the figures below.

3.6.2 4 Phase Traffic Light Signals

Figure 3.26 : Phase 1 Traffic Signal Figure 3.27 : Phase 2 Traffic Signal

Figure 3.28 : Phase 3 Traffic Signal Figure 3.29 : Phase 4 Traffic Signal
 25

3.6.3 State table of the Traffic Light Controller

Table 3.4 : State Table of the Traffic Light Controller System

States Direction of lanes Output

Current Stored Next State North East South West S_light ,

State State W_light,
clr=0 clr=1 N_light,
E_light
0001
Idle A I Idle Red Yellow Red Red 0001
(D) 0001
0010
1100
A B Idle Green Red Red Red 0001
0001
C 0001
0010
B I Idle Yellow Red Red Red 0001
0001
0001
0001
C D Idle Red Green Red Red 1100
0001
E 0001
0001
D I Idle Red Yellow Red Red 0010
0001
0001
0001
E F Idle Red Red Green Red 0001
1100
G 0001
0001
F I Idle Red Red Yellow Red 0001
0010
0001
0001
G H Idle Red Red Red Green 0001
0001
A 1100
0001
H I Idle Red Red Red Yellow 0001
0001
0010
0001
I Stored Idle Red Red Red Red 0001
State 0001
0001
 26

3.6.4 Traffic Light Controller Flowchart

Figure 3.30 : Flowchart of the Traffic Light Controller

Figure 3.30 above illustrates the flowchart of the implemented TLC. At first, the
traffic light controller will send a request signal and receive the green time value
calculated by the Raspberry Pi. If the data is not received correctly due to connection
problem or received value is not within the range, the traffic light controller system
will use the default green light time for traffic control. Otherwise, the traffic light
will display the
 27

green light according to the received green time value from the Raspberry Pi, the
system will always compare the received data with counter value to limit the green
time period, if the green light period has reached, green light will be turned OFF and
yellow light will be turned ON, the system will send a signal to retrieve the green
time value for the next phase of traffic signal. This process is repeated continuously.

3.6.5 State Diagram of Traffic Light Controller System

Next State =A

D Next State =B
Stored Next State =
Next State = I
C

Next State = Stored Next

State
A B time < 3sec

I
time < 3sec

Next State = I Next state = Stored Next State

H I
time < 3sec time < 3sec

Next State =D
Stored Next State = E
C
G Next State =H
Stored Next State = A

Next State = I
Next State = Stored Next
State
time < 3sec D
I time < 3sec

Next State = I

F I time < 3sec

E
time < 3sec
Next State =F Next State = Stored Next
Stored Next State = State
G

Figure 3.31 : State Diagram of the Traffic Light Controller

 28

3.6.6 Hardware Implementation of Traffic Light Controller

Figure 3.32 below shows the TLC circuit is simulated using the build-in general-
purpose input output (GPIO) pins on the Altera DE2 board. From the circuit model,
one traffic light circuit consists of 4 resistors, 2 green LEDs, 1 yellow LED, and 1
red LED. Thus, a total of 16 LEDs (4 red LEDs, 4 yellow LEDs, and 8 green LEDs)
and resistors are required for all directions of the traffic light circuit.

Figure 3.32 : Schematic of the Traffic Light Controller

The precaution needs to be considered during the implementation of the TLC

circuit is the maximum current rating for LEDs. In the traffic light circuit, each LED
must have a resistor that is connected in series connection in order to prevent the
overflow of the current flow through the LED, otherwise the LED will burn out
instantly. In this project, 5mm LEDs with a maximum current rating is about 20mA.
Therefore, to ensure the reliability of the circuit, current flow with less than 10mA is
required. To obtain this current value, Ohm’s Law equation as shown in the equation
below is used to calculate the minimum required resistor value.
 29

Vs - Vf
R= I (3.2)

Vs - Vf 3.3V - 1.8V
R= I = 10mA

R = 150 Ω

Where,
Vs is voltage supply by GPIO output pin, maximum voltage is 3.3V.
Vf is forward voltage of LED, typical value is 1.8V.
I is current value, assume is 10mA.
R is resistance value in unit ohms, Ω

Based on the calculation above, a simple traffic light circuit consists of four
150 Ω resistors and 4 LEDs which is as shown in the PCB design. From the traffic
light PCB circuit below, the circuit consists of 6 connectors, 4 connectors were used
for each LED making the connection to the Altera DE2 board through the 150 Ω
resistor. Another one connector is the ground terminal of the LEDs.

Figure 3.33 : PCB Design of the Traffic Light Circuit

 30

3.7 Timing Algorithms for Traffic Light Signal

In order to make the system more comprehensive, the proposed STLCS comes with a
timing algorithm that aims to minimize the queuing time at each intersecting road
and make the system more effective in discharging the traffic load.

The timing algorithm is implemented based on Figure 3.34 below. From the
figure, the time needed for a vehicle to pass through the junction is referred to as
headway. Theoretically, the first headway will be relatively greater than the
remaining headway because it includes longer start-up loss time, en (driver’s reaction
time + vehicle acceleration time). The second headway is comparatively shorter
because the start-up loss time may partially overlap with the first driver and
continuously decline for the remaining headway. After a few vehicles, the headway
tends to be more saturated or stable at a constant value which means that the vehicles
queuing behind have more time to accelerate to high velocity, and eventually, it
achieved stable movement of vehicles across the junction. In real life the average
saturation headway, h is around 2.4 s/vehicles, however, to shorten the waiting time
during the demonstration, saturation headway, h is assumed to be half of the actual
value which is at 1.2 s /vehicle.

Figure 3.34 : Headways Departing Trend

To make the algorithm more reliable and practical, the total start-up loss time,
Sloss must be added to the algorithms. Since the start-up loss time, en is shown in a
 31

negative inverse trend, therefore, the total start-up loss time, Sloss can be calculated by
using equation,
𝑛
Sloss =∑𝑖=1 sloss[(𝑓𝑖−1)] (3.3)

Where,
Sloss is total start-up loss time.
sloss is standard start-up loss time (assume 2.5s).
f is decrease factor (assume 0.75).
n is number of detected vehicles.

Furthermore, the green time required to clear N vehicles can be estimated as

T = Sloss + h*N (3.4)

Where,
T is required green time.
Sloss is total start-up loss time
N is number of detected vehicles
h is saturation headway. (assume 1.2s / vehicle)

Lastly, though the system will calculate and adjust the green time depending
upon the traffic load, but it still provides a minimum and maximum time limit which
are fixed to 5 seconds and 25 seconds respectively, and this is considered as a
precautionary measure for vehicle detection error.

30
Green time against number of vehicles

25
Green Time, second

20
15

10
5
0
0 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 18
Number of queuing vehicles
Figure 3.35 : Maximum and Minimum Green Light Period
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3.8 Cost Analysis of the Project.

The total expenditure done in favour of the project right from its initiation up to its
completion has been tabulated in the Table 3.5 below.

Table 3.5 : Equipment and Components List with Price

No. Components Quantity Remarks Price

(RM)

1. Altera DE2 board 1 Acquired from Lab -

(2C35)

2. Raspberry Pi 3B+ 1 Acquired from Lab -

3. OV5647 camera Module 1 Website : Shopee.com RM49.67

- 175 ° view angle

Female to Female 1 Website : Lelong.com RM 5.80

jumper wires (40p)
4.
5. RS232 to USB serial 1 Website : Shopee.com RM10.10
cable
6. LEDs ( Red ) 4 Acquired from Lab -

7. LEDs ( Yellow ) 4 Acquired from Lab -

8. LEDs ( Green ) 8 Acquired from Lab -

9. Polystyrene -12x1 6 Website : Shopee.com RM14.40

inches
10. Polystyrene -10x1 5 Website : Shopee.com RM10.00
inches

11. Toy Cars 1 Giant Kampar RM 9.91

Total Cost : RM 99.88

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RESULTS AND DISCUSSIONS

4.1 Software Testing

The software testing process involves the utilization of simulation software to test
and check the behaviour and functionality of the implemented software and to
determine whether the program is able to generate the required outcomes when
different inputs or conditions were applied.

4.1.1 Traffic Light Controller Program Simulation

In this project, the traffic light controller program was written in Verilog HDL using
the ModelSim 10.1b simulator software. After implementation, a simple test-bench
as shown in Figure 4.1 was loaded to simulate the functionality of the FPGA based
traffic light controller program. The simulated output waveforms of the TLC are
shown in Figure 4.2 and 4.3 below, and the description for related output is shown in
Table 4.1.

Table 4.1 : Description for the Simulated Traffic Light Output

Simulated output Description
0001 Red light turn ON
0010 Yellow light turn ON
1100 Two green lights turn ON
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Figure 4.2 : Simulated Output Waveform of the TLC

Figure 4.3 : Simulated Output Waveform of the TLC

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Figure 4.5 : Output aveform of the Transmitter (0000000 to 0010000)

Figure 4.6 : Output Waveform of the Transmitter (11101111 to 11111111)

Figure 4.7 : Output Waveform of the Receiver (0000000 to 0010000)

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CONCLUSION AND RECOMMENDATIONS

5.1 Conclusion

The project “Development of FPGA based Smart Traffic Light Controller System
with Image Processing” which aims to improve the efficiency of existing automatic
traffic light signalling system by reducing the queuing time of each lane of the
vehicles and maximize the discharge of vehicles across an intersection was
successfully designed and developed.

The development of STLCS is divided into three major parts which are the
automatic traffic light control system, vehicle detection system and the UART
communication system. The implementation of the vehicle detection system was
done by using the Raspberry Pi 3B+ and written in Python programming language,
the vehicle detection approach emphasizes on the segmentation that is based on
colour properties of the object and the overall accuracy of this approach is 94.74%.
Furthermore, a full-duplex UART communication system was constructed on both
the Altera FPGA board and the Raspberry Pi to allow the communication of multiple
designed systems. Moreover, an automatic traffic light control system based on
FPGA was constructed successfully on the Altera FPGA board using the Mealy
finite-state machine design, the system can communicate with the vehicle detection
system to enhance the flexibility in traffic signal control.

Although the developed system has not been tested in the actual field, the
performance of the system was evaluated and satisfactory results were obtained. As
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mentioned above, some limitations still exist in the system and those limitations need
to be addressed and a few other modifications as well as enhancements can be made
in the future so that the system can be applied in the actual field.