BD9851EFV Rohm
BD9851EFV Rohm
BD9851EFV Rohm
Description
The BD9850FVM is a 1-channel DC/DC step-down switching regulator controller, while the BD9851EFV is a 2-channel DC/DC
step-down switching regulator controller. The BD9850FVM is adaptable for a maximum switching frequency of 2 MHz and the
BD9851EFV for that of 3 MHz. Both provide space saving in all applications.
Features
1) Adaptable for 2-MHz switching frequency (externally variable) (BD9850FVM)
Adaptable for 3-MHz switching frequency (externally variable) (BD9851EFV)
2) FET direct drive
3) High-accuracy reference voltage (Accuracy: ±1%)
4) Built-in Under Voltage Lock Out circuit (UVLO)
5) Built-in Thermal Shutdown circuit (TSD)
6) The BD9851EFV provides two channels:
Channel 1 available for selection of step-down/step-up switching
Channel 2 available for selection of step-down/inverting switching.
7) Compact MSOP8 package (BD9850FVM) / HTSSOP-B20 package (BD9851EFV)
Applications
TFT panel, TA / Router, digital consumer electronics, PC, and portable CD/DVD/DVC
Product lineup
BD9850FVM BD9851EFV
Input range 4V to 9V 4V to 18V
Oscillation frequency range 100kHz to 2MHz 10kHz to 3MHz
External synchronization Not provided Not provided
Standby function Not provided Provided
Operating temperature – 40˚C to 85˚C –40˚C to 85˚C
Package MSOP8 HTSSOP-B20
Sep. 2008
BD9850FVM
BD9851EFV
BD9850FVM
Limits
Item Symbol Unit
min. Typ. max.
Power supply voltage Vcc 4 7 9 V
Oscillation frequency fosc 100 – 2000 kHz
Operating temperature Topr –40 – + 85 ºC
BD9851EFV
Limits
Item Symbol Unit
min. Typ. max.
Power supply voltage Vcc 4 12 18 V
Oscillation frequency fosc 10 300 3000 kHz
Timing resistor RRT 3.3 – 47 kΩ
Timing capacitor CCT 33 – 10000 pF
2/16
BD9850FVM
3/16
BD9851EFV
1.02 100
1.015 90
ERROR-AMP. THRESHOLD VOLTAGE : VINV(V)
87
1.01
70
ON DUTY : DON(%)
1.005
60
1 50
0.995 40
30
0.99
20
0.985
10
0.98 0
–40 –20 0 20 40 60 80 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2
Fig.1 Error Amp threshold voltage vs. Ambient temperature Fig.2 FB voltage vs. ON Duty
1000 1000
900 900
400 400
Vcc=4V
300 Vcc=4V 300
200 200
100 100
0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
Fig.3 (Vcc-OUT) Voltage vs. Output source current Fig.4 Output voltage vs. Output sink current
2.53 650
640
2.52
OSCILLATING FREQUENCY : FOSC [kHz]
630
620
VREF VOLTAGE:VREF [V]
2.51
610
RT=24kΩ
2.5 600
590
2.49
580
570
2.48
560
2.47 550
–40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80
Fig.5 VREF vs. Ambient temperature Fig.6 Oscillation frequency vs. Ambient temperature
5/16
(BD9851EFV)
1.02 100
90
ERROR-AMP. THRESHOLD VOLTAGE : VEATH (V)
1.015
80
1.01
70
1 50
40
0.995
30
0.99 fosc=1MHz
20 fosc=300kHz
0.985
10
0.98 0
–40 –20 0 20 40 60 80 1.2 1.3 1.4 1.5 1.6 1.7 1.8 19
Fig.7 Error Amp threshold voltage vs. Ambient temperature Fig.8 FB voltage vs. ON Duty
1000 1000
Vcc=20V
900 900
800 800
OUT SOURCE CURRENT : IOUT (mA)
600 600
Vcc=12V
500 500
400 400
Vcc=4V
300 300 Vcc=4V
200 200
100 100
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 0 1.5 2 2.5 3 3.5 4
Fig.9 (Vcc-OUT) Voltage vs. Output source current Fig.10 Output voltage vs. Output sink current
2.55 320
RRT=24kΩ
2.54 315 CCT=220pF
OSCILLATING FREQUENCY : FOSC (kHz)
2.53
310
REFERENCE VOLTAGE : VREF (V)
2.52
305
2.51
2.5 300
2.49
295
2.48
290
2.47
285
2.46
2.45 280
–40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80
Fig.11 VREF vs. Ambient temperature Fig.12 Oscillation frequency vs. Ambient temperature
6/16
Block diagram / Pin assignment
(BD9850FVM)
Vcc
Vcc VREF RT
1 4 8
Vcc
U.V.L.O VREF
TRI
Vcc
5
INV
2
Error Amp Clamper OUT
1.0V VREF Vo
PWM COMP
6
FB
T.S.D
7 3
CTL/SS
GND
INV
RT
Vcc
18 Pin No. Pin name Function
Both channels 19 STB
VREF VREF ON/OFF
17 1 SEL1 CH1 drive FET setting (Vcc short: P-ch drive, GND short: N-ch drive)
(2.5V)
Vcc
FB1
2 RT Oscillation frequency setting resistor connection
15 SEL1
Vo1 1
3 CT Oscillation frequency setting capacitor connection
Vcc
PVcc1
4 NON2 Error Amp non-inverting input (CH2)
12
16 – 5 INV2 Error Amp inverting input (CH2)
INV1
– OUT1
+ – 11 6 FB2 Error Amp output (CH2)
+
1V
VREF 7 DTC2 Maximum duty/soft start setting (CH2)
Vo1
FIN on Make FIN on the reverse open or ground to GND (pin 20)
PVcc1
OUT1
–
DTC1
GND
INV1
SCP
VREF
FB1
STB
Vcc
reverse (However, open FIN on the reverse will degrade radiation performance.)
NON2
PGND
PVcc2
OUT2
DTC2
SEL1
INV2
FB2
RT
CT
7/16
Description of operations
6) Standby function
(BD9850FVM)
The CTL/SS pin allows for output ON/OFF control. Set the CTL/SS pin voltage to “H” to activate the output ON control.
(BD9851EFV)
The STB pin allows for output ON/OFF control. Set the STB pin voltage to “H” to activate the output ON control.
The standby mode circuit current should be set to less than 5 μA.
8/16
Timing chart
• In startup/normal operation
(BD9850FVM) FB pin voltage
Soft start set voltage
Oscillator output
Control threshold
Vcc waveform
Output voltage
waveform
(BD9851EFV)
FB
CT DTC
2.3V
Output voltage
waveform
9/16
Description of external components
• Setting of output voltage (BD9850FVM)
Setting of output voltage for the step-down application can be calculated by the formula below :
R1
INV (5)
R2
10000
RT (2)
RRT
Oscillating frequency [kHz]
1000
100
1 10 100 1000
Timing resistance(RT) [kΩ]
CT (3)
CCT
CCT=33pF
Oscillating Frequency (kHz)
RRT=4.7kΩ
CCT=1200pF
10 10
1 10 100 10 10 100 1000
Timing Resistance (kΩ) Timing Capacitance(pF)
TSCP : Time from output short circuit to latch stop [sec] SCP (14)
OSCP : Capacitance of capacitor between the SCP and CSCP
GND pins [F]
In order to use one channel, treat the pins of unused channel as shown above.
11/16
5
Application circuit / Directions for pattern layout
(BD9850FVM)
RT
Vo
Vcc R1
Vcc RT
GND FB
* R1 GND
Vcc Vcc RT VREF INV
C1
* C1
OUT CTL/SS C1: In order to reduce ripple noises, set the shortest
GND FB distance between the VCC pin and the capacitor pin,
C2 VREF
and the GND pin and the capacitor pin. Furthermore,
1µF VREF INV the OUT line may pass under the C1.
*
ON/OFF C2: In order to reduce ripple noises, set the shortest
[ HL::ON
OFF
] pattern between the VREF pin and the capacitor pin,
and the GND pin and the capacitor pin.
R1: In order to stabilize the switching frequency, set the
smallest pattern area so that PCB parasitic
capacitance for the RT pin will be minimized.
Fig.23 BD9850FVM Reference application
Equivalent circuit
(BD9850FVM)
2PIN(OUT) 4PIN(VREF) 5PIN(INV)
Vcc Vcc
Vcc
1.67k
50k
250k
OUT VREF
INV
200k
193k
GND GND GND
FB
500k
20p CTL/SS
RT
1k
200k
GND GND GND
12/16
BD9851EFV
1PIN (SEL1) 2PIN (RT) 7,13PIN (DTC2,DTC1)
Vcc Vcc Vcc VREF VREF Vcc Vcc
SEL1
DTC
RT
OUT2 CT NON2
PGND
STB
FB
VREF
13/16
8) IC pin input
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements to keep them isolated. Pin junctions are formed at the
intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the relation between each
potential is as follows:
When GND > Pin A and GND > Pin B, the Pin junction operates as a parasitic diode.
When Pin B > GND > Pin A, the PñN junction operates as a parasitic transistor.
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits,
operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the
GND (P substrate) voltage to an input pin, should not be used.
GND
N
P+ P P+ P+ P P+
N N
N N N N
Player Player
Parasitic element
(Pin B)
(Pin A) C
B
Parasitic element E
GND
GND
Other proximity element
Parasitic element
9) Common impedance
The power supply and ground lines must be as short and thick as possible to reduce line impedance. Fluctuating voltage on the power ground
line may damage the device.
10) On the application shown below, Vcc is short-circuited to the Ground with external diode charged, internal circuits may be damaged.
recommended to insert a backflow prevention diode in series with the Vcc or a bypass diode between each pin and Vcc.
Bypass diode
Vcc
Output pin
Fig. 29
14/16
11) Although ROHM is confident that the example application circuit reflects the best possible recommendations, be sure to verify circuit
characteristics for your particular application. Modification of constants for other externally connected circuits may cause variations in both static
and transient characteristics for external components as well as this Rohm IC. Allow for sufficient margins when determining circuit constants.
Oscillation frequency setting resistor
12) For the oscillation frequency setting resistor to be inserted between the RT pin and the GND pin, mount this resistor close to the RT pin and
provide the shortest pattern routing.
(2) 0.59 W 4
0.6
POWER DISSIPATION : Pd [W]
0 0
0 25 50 75 100 125 150 0 25 50 75 100 125 150
AMBIENT TEMPERATURE : Ta [˚C] AMBIENT TEMPERATURE : Ta [˚C]
(1) : Single piece of IC (1) : Single piece of IC
(2) : With ROHM standard PCB mounted PCB size: 70mmX70mmX1.6 mm2 (PCB incorporates thermal via)
(Glass epoxy PCB of 70mmX70mm X1.6mm) Copper foil area on the reverse side of PCB: 10.5X10.5mm2
(2) : 2-layer PCB (Copper foil area on the reverse side of PCB: 15mmX15mm
(3) : 2-layer PCB (Copper foil area on the reverse side of PCB: 70mmX70mm
(4) : 4-layer PCB (Copper foil area on the reverse side of PCB: 70mmX70mm
Fig.30 Fig.31
B D 9 8 5 0 F V M T R
MSOP8
8 5 Packaging
0.6 ± 0.2
(When holding a reel in left hand and pulling out the tape with
4.0 ± 0.2
2.8 ± 0.1
direction
right hand, No. 1 pin appears in the upper right of the reel.)
1 4 +0.05
0.475 0.145 –0.03
0.9max.
+0.05
0.22 –0.04
0.08 M
0.75 ± 0.05
0.08 ± 0.05
0.65 0.08 S
HTSSOP-B20
direction
6.4 ± 0.2
4.4 ± 0.1
1.0 ± 0.2
right hand, No. 1 pin appears in the upper left of the reel.)
0.325 1 10 +0.05
0.17 +0.03
1.0max.
S
0.08 S
0.85 ± 0.05
0.08 ± 0.05
+0.05
0.65 0.2 +0.04
12.34
12.34
12.34
12.34
12.34
12.34
12.34
12.34
15/16
Catalog No.08T679A '08.9 ROHM ©
Datasheet
Notice
Precaution on using ROHM Products
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(Note 1)
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CLASSⅢ CLASSⅡb
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Notice - GE Rev.002
© 2014 ROHM Co., Ltd. All rights reserved.
Datasheet
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