DATASHEET

VC Verification IP for AMBA AXI

Highlights Overview
• Native SystemVerilog/UVM Synopsys VC Verification IP for Arm® AMBA® AXI™ provides a comprehensive
• Verdi Performance Analyzer - latency and set of protocol, methodology, verification and productivity features, users are
throughput metrics able to achieve rapid verification convergence on of Arm AMBA based designs
supporting AMBA AXI5*, AXI4, AXI4-Lite and AXI3.
• Verdi integrated protocol-aware debug
• Verification plan and coverage Synopsys VC VIP can be integrated, configured and customized with minimal
• Built-in protocol checks effort. Testbench development is accelerated with built-in verification plans,
example tests, and functional coverage. VIP is natively integrated with Verdi
• Configurable interconnect model
Protocol Analyzer, a protocol-centric debug environment, to give users a
• Reference verification platform graphical view of VIP operations and transaction for easy and fast debug, and
• Runs natively on all major simulators to find and fix performance bottle necks.
• Optional solutions
––AutoTestbench generation AMBA System Env System Cfg

––AutoPerformance stimulus generation Virtual Sequencer

––Source code Test suite (EA) AXI System Env AHB System Env APB System Env
System Cfg System Cfg Seqnc Library System Cfg

Virtual Sequencer Virtual Sequencer Virtual Sequencer

Key Features AXI Master Agent AXI Slave Agent AHB Master Agent AHB Slave Agent APB Master Agent APB Slave Agent
Seqncrs Port Cfg Seqncr Port Cfg Seqncrs Port Cfg Seqncr Port Cfg Seqncr Port Cfg

• Complete protocol support for AXI5*,

Master

Master

System
Slave

Slave

Seqncr
Interconnect

Cfg
Master Port Slave Port Master Port Slave Port Slave Port
Monitor
AHB Bus

Driver Monitor Driver Driver Monitor Driver Monitor Driver Monitor

AXI4, AXI4-Lite, AXI3

…

…
…
…

Master Port
AXI Master Agent AXI Slave Agent AHB Master Agent AHB Slave Agent Driver Monitor APB Slave Agent
Seqncrs Port Cfg Seqncr Port Cfg Seqncrs Port Cfg Seqncr Port Cfg Seqncr Port Cfg

• Configurable interconnect model for AXI

Master

Master
Slave

Slave

Master Port Slave Port Master Port Slave Port Slave Port
Driver Monitor Driver Monitor Driver Monitor Driver Monitor Driver Monitor

• Port level protocol checks for all interfaces AXI System Monitor AHB System Monitor

• System-level checks for protocol, data

AMBA System Monitor
integrity and cache coherence
• Debug port for transaction
tracking on waveforms
Native SystemVerilog/UVM Methodology
• Ability to control delays for valid and ready
Synopsys VC VIP, based on its next generation architecture, is implemented
signals with respect to reference events
100% in native SystemVerilog and UVM. It runs on all major simulator.
• Ability to control signal values
during idle periods
UVM Source Code Test Suites
Writing tests to verify protocols is time consuming, challenging and requires
deep protocol and methodology expertise. Synopsys testbenches help
eliminate the task of writing compliance tests for today’s complex protocols.

The test suite for AMBA AXI is a complete self-contained, configurable

environment targeted at the verification of AMBA AXI3 and AXI4 interconnects.
It is provided as SystemVerilog UVM source code to simplify integration,
enable user customization and maximize reuse across projects. Test suites are
*Currently available as early access only. available as an option.

synopsys.com/VIP
AutoTestbench Generation
The AutoTestbench solution enables easy and quick integration and configuration of hundreds of coherent and non-coherent AMBA
ports and corresponding VIP instances. VC AutoTestbench is an available option for automatic SoC testbench generation.

AutoPerformance
The AutoPerformance solution is based on Arm traffic profile specification, enables user to define traffic profiles for measuring
performance metrics like throughput and latency with stimulus driven by VC VIP for AMBA (CHI™/ACE™/AXI). VC VIP AMBA
AutoPerformance is an available option for automatic performance verification stimulus generation.

Verdi Integrated Protocol Aware Debug

The growth in complexity and increasing number of protocols used on SoCs is creating a rapidly increasing verification challenge
and debug bottleneck for verification engineers. Verification engineers must quickly become protocol experts and try to correlate
information across different sources of information to find root cause of problems. Verdi Protocol Analyzer provides protocol-
centric debug which enables user to quickly understand protocol activity, identify bottlenecks and quickly find and debug
unexpected behavior.

Metric result
details

Supported Constraint
metrics setting
Constraint
violations

Selected
Selection
VIP instance attributes
hierarchy

Transactions
(concurrent)

Succesor
object

Verdi Performance Analyzer

The performance analyzer provides constraint specification and checking, constraint violation tracing and debug, and performance
report generation. Pre-defined and user-defined performance metrics can be used for transaction, cross transaction and cross
component analysis to measure latency, bus utilization, total byte count, outstanding transactions, total requests by all masters,
percent write bus bandwidth etc. Verdi Performance Analyzer is available as an option.

Verification Plan and Functional Coverage

Synopsys VIP comes with a verification plan. The verification plan shows how each functional coverage group is directly mapped
to the protocol specification. The verification plan is hierarchical with sub-plans based on the DUT feature set. The functional
coverage support in VIP supports coverage for protocol, toggle, transaction, configuration along with cross coverage. In addition,
sequential coverage is provided that covers complex sequences that are hard to derive directly from the protocol specification.
Coverage is “configuration aware” which means bins are ignored if they are not applicable to the VIP configuration. Users can extend
the built in coverage to add their own bins based on built in VIP sampling events and groups or create their own groups with any
sampling event or data.

Information on New Features

This data sheet provides a summary of supported protocol features and may not reflect all the features added in recent releases.
Please contact your local Synopsys sales office for complete information about new features and enhancements.

Synopsys offers a broad portfolio of interface, bus and memory Verification IP and Test Suites.
For more information visit: synopsys.com/VIP.
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01/26/18.CS11923_VIP_AMBA_AXI_DS.indd.