Intel 82802 Firmware Hub
Intel 82802 Firmware Hub
Intel 82802 Firmware Hub
Intel® 82802AB/82802AC
Firmware Hub (FWH)
Datasheet
November 2000
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® 82802AB/AC Firmware Hub (FWH) may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
2 2
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Contents
1. Architectural Overview ................................................................................................................. 9
1.1. Interface Overview........................................................................................................... 9
1.1.1. Intel Firmware Hub Interface....................................................................... 10
1.1.2. Address/Address-Multiplexed Interface ...................................................... 10
1.2. Nonvolatile Flash Memory Core .................................................................................... 10
2. Pinout Configurations ................................................................................................................. 13
2.1. Pin Descriptions............................................................................................................. 14
3. Interface Operation Description ................................................................................................. 17
3.1. Read 17
3.2. Write 17
3.3. Output Disable............................................................................................................... 17
3.4. Reset 17
3.5. Operational Effects of Hardware Write-Protect Pins TBL# and WP# ........................... 18
4. Functional Descriptions.............................................................................................................. 19
4.1. Read Array Command................................................................................................... 21
4.2. Read Identifier Codes Command .................................................................................. 21
4.3. Read Status Register Command................................................................................... 21
4.4. Clear Status Register Command................................................................................... 21
4.5. Block Erase Command ................................................................................................. 22
4.6. Program Command....................................................................................................... 22
4.7. Block Erase Suspend Command .................................................................................. 23
4.8. Program Suspend Comand........................................................................................... 23
4.9. Register Based Locking, General-Purpose Input, and Random Number Generator
Registers 23
4.9.1. T_BLOCK_LK and T_MINUSxx_LK — Block-Locking Registers ............... 25
4.9.2. General-Purpose Input Register ................................................................. 26
4.9.2.1. GPI_REG — General-Purpose Input Register ............................... 26
4.9.3. Random Number Generator Registers ....................................................... 27
4.9.3.1. RNG Hardware Status Register ..................................................... 27
4.9.3.2. RNG Data Status Register ............................................................. 27
4.9.3.3. RNG Data Register......................................................................... 28
4.10. Using the Random Number Generator ......................................................................... 28
4.11. Detecting and Initializing the RNG Device..................................................................... 28
4.11.1. Detecting the RNG Device .......................................................................... 28
4.11.2. Initializing the RNG Device.......................................................................... 29
4.11.3. Selecting Appropriate FWH IDs and Densities ........................................... 29
4.11.4. Mapping FWH Devices onto Memory Map ................................................. 30
4.11.5. Paging FWH Devices for Greater Than 4 MB of FWH Memory ................. 30
4.11.6. Programming Multiple FWH Devices .......................................................... 30
4.12. CUI Automation Flowcharts........................................................................................... 31
5. Electrical Specifications ............................................................................................................. 33
5.1. Absolute Maximum Ratings........................................................................................... 33
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Figures
Figure 1. Simplified Block Diagram ..................................................................................... 8
Figure 2. Device Memory Map with Intel FWH Hardware Lock Architecture .................... 11
Figure 3. Intel FWH Boot-Configuration System Memory Map......................................... 11
Figure 4. 32-Lead PLCC Intel Firmware Hub Pinout......................................................... 13
Figure 5. 40-Lead TSOP Intel Firmware Hub Pinout ........................................................ 13
Figure 6. Automated Block Erase Flowchart..................................................................... 31
Figure 7. Clock Waveform ................................................................................................ 37
Figure 8. Output Timing Parameters................................................................................. 38
Figure 9. Input Timing Parameters ................................................................................... 39
Figure 10. FWH Single-Byte Read Waveforms .................................................................. 42
Figure 11. Write Waveforms ............................................................................................... 43
Figure 12. Intel FWH Output Timing Parameters ............................................................... 45
Figure 13. Intel FWH Input Timing Parameters .................................................................. 46
Figure 14. A/A Mux Read Timing Diagram ......................................................................... 50
Figure 15. A/A Mux Write Timing Diagram ......................................................................... 52
Tables
Table 1. Pin Descriptions ................................................................................................. 14
Table 2. Command Definitions......................................................................................... 19
Table 3. Status Register Definition .................................................................................. 20
Table 4. Identifier Codes .................................................................................................. 21
Table 5. Intel Firmware Hub Register Configuration Map................................................ 24
Table 6. Register-Based Locking Value Definitions......................................................... 25
Table 7. Temperature and VCC....................................................................................... 33
Table 8. Intel FWH Interface DC Input/Output Specifications.......................................... 34
Table 9. Power Supply Specifications — All Interfaces ................................................... 35
Table 10. Intel FWH Interface AC Input/Output Specifications.......................................... 36
Table 11. Clock Specification............................................................................................. 37
Table 12. Signal Timing Parameters.................................................................................. 38
Table 13. Interface Measurement Condition Parameters .................................................. 39
Table 14. AC Waveform for Reset Operation.................................................................... 39
Table 15. Programming Times .......................................................................................... 40
Table 16. FWH Read Cycle ............................................................................................... 41
Table 17. FWH Write Cycle ............................................................................................... 42
Table 18. Signal Timing Parameters.................................................................................. 44
Table 19. RNG Timing Characteristics .............................................................................. 45
Table 20. RNG Statistical Characteristics.......................................................................... 45
Table 21. Bus Operations .................................................................................................. 48
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Revision History
Rev. Draft/Changes Date
-003 • Changed VIH min. spec to reflect actual value. May 2000
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The Intel® 82802 (FWH) firmware hub may contain design defects or errors known as errata that may cause the products to
deviate from published specifications. Current characterized errata are available upon request.
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Processor
Memory Memory
Controller
ISA Bridge
(optional)
SMBus Device(s) SMBus
PCI Bus PCI Slot
AC’97 Codec(s) AC’97 I/O
(optional) Controller PCI Agent
Keyboard,
Mouse, FD,
PP, SP, IR
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1. Architectural Overview
The Intel® 82802 Firmware Hub (FWH) discrete component is compatible with several Intel chipset
platforms and a variety of applications. The device operates under the LPC/FWH interface/protocol. The
hardware features of this device include a Random Number Generator (RNG), five General-Purpose
Inputs (GPIs), register-based block locking, and hardware-based locking. This combination of logic
features and non-volatile memory enables better protection for the storage and update of platform code
and data, adds platform flexibility through additional GPIs, and allows for quicker introduction of new
security/manageability features into current and future platforms. The platform RNG, accessed through
the Intel® Security Driver and third-party software, enables security features for the PC platform. See the
product features listed previously for a list of more key features that the Intel FWH provides.
An internal Command User Interface (CUI) serves as the internal control center for the
nonvolatilememory core in either of the two device interfaces (Intel FWH or A/A Mux). A single valid
commandsequence written to the CUI initiates an automated sequence of internal events to complete
various tasks. An internal Write State Machine (WSM) automatically executes the algorithms and
timings necessary for block erase and program operations.
Driving RST# or INIT# low resets the device, which resets the block-lock registers to their default
(write-locked) condition and clears the status register. A reset time (tPHQV A/A Mux) is required from
RST# or INIT# switching high until outputs are valid. Likewise, the device has a wake time (tPHRH A/A
Mux) from RST# or INIT# high until writes to the CUI are recognized. A reset latency will occur if a
reset procedure is performed during a programming or erase operation. Resetting the component will put
the component back into read-array mode.
Note: There is no chip enable (like CE#) in either interface. Stand-by current control in the Inel FWH interface
is enabled automatically, if the Intel FWH4 is high and the device is not working to complete a requested
activity.
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Intel® Flash Technology enables fast factory programming and low-power designs. Specifically designed
for 3-V systems, this component supports read operations at 3.3 V VCC and block erase and program
operations at 3.3 V and 12 V VPP. The 12 V VPP option yields the fastest program performance, which
will increase factory throughput, but is not recommended for standard in-system FWH operation in the
platform, due to an 80-hr limit for 12 V on the VPP pin over the lifetime of the device, whether or not
programming is taking place. With the 3.3-V VPP option (recommended for in-system operation), VCC
and VPP may be tied together for a simple, low-power 3-V design. In addition to the voltage flexibility,
the dedicated VPP pin provides complete data protection when VPP ≤ VPPLK. Internal VPP detection
circuitry automatically configures the device for block erase and program operations. While current for
12-V programming will be drawn from VPP, 3.3-V programming solutions should design their board such
that VPP draws from the same supply as VCC, and should assume that full programming current may be
drawn from either pin.
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Figure 2. Device Memory Map with Intel FWH Hardware Lock Architecture
0FFFFF
0F0000 64-Kbyte Block 15 } TBL# (8 Mb)
0EFFFF
0E0000
64-Kbyte Block 14
0DFFFF
0D0000 64-Kbyte Block 13
0CFFFF
0C0000
64-Kbyte Block 12
0BFFFF
0B0000 64-Kbyte Block 11
0AFFFF
0A0000
64-Kbyte Block 10
09FFFF
090000
64-Kbyte Block 9
08FFFF WP# (8 Mb)
080000 64-Kbyte Block 8
07FFFF Blocks 0-14
070000 64-Kbyte Block 7 }TBL# (4 Mb)
06FFFF
060000
64-Kbyte Block 6
05FFFF
050000 64-Kbyte Block 5
04FFFF
040000 64-Kbyte Block 4
03FFFF WP# (4 Mb)
030000 64-Kbyte Block 3
02FFFF
020000 64-Kbyte Block 2
01FFFF
010000
64-Kbyte Block 1
00FFFF
000000
64-Kbyte Block 0
mem_map_lock
FFF80000h
Block0
FFF00000h
Block 0
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2. Pinout Configurations
Figure 4. 32-Lead PLCC Intel Firmware Hub Pinout
A/A A/A
A8 A9 RST# VPP VCC R/C# A10
Mux Mux
FGPI2 FGPI3 RST# VPP VCC CLK FGPI4
4 3 2 1 32 31 30
A6 FGPI0 28 GNDa
6 GNDa
14 15 16 17 18 19 20
NC NC 1 40 GNDa GNDa
IC (VIH) IC (VIL) 2 39 VCCa VCCa
NC NC 3 38 FWH4 WE#
NC NC 4 37 INIT# OE#
NC NC 5 36 RFU RY/BY#
NC NC 6 35 RFU DQ7
A10 FGPI4 7 34 RFU DQ6
NC NC 8 Firmware Hub (FWH) 33 RFU DQ5
R/C# CLK 9 32 RFU DQ4
VCC 40-LEAD TSOP
VCC
10 31 VCC VCC
VPP VPP 11 10mm x 20mm 30 GND GND
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RST# I X X Interface Reset. Valid for both A/A Mux and Intel FWH interface
operation. When driven low, RST# inhibits write operations to
provide data protection during power transitions, resets internal
automation, and tri-states pins FWH[3:0] (in Intel FWH interface
mode). RST#-high enables normal operation. When exiting from
reset, the device defaults to read array mode.
INIT# I X Processor Reset. This is a second reset pin for in-system use. This
pin is internally combined with the RST# pin. If this pin or RST# is
driven low, identical operation is exhibited. This signal is designed to
be connected to the chipset INIT signal (Max. voltage depends on
the processor. Do not use 3.3 V).
A/A Mux = OE#
CLK I X 33-MHz Clock for Intel FWH Interface. This input is the same as
that for the PCI clock and adheres to the PCI specification.
A/A Mux = R/C#
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ID[3:0] I X Identification Inputs. These four pins are part of the mechanism
that allows multiple parts to be attached to the same bus. The
strapping of these pins is used to identify the component. The boot
device must have ID[3:0] = 0000, and it is recommended that all
subsequent devices use sequential up-count strapping (0001,
0010,0011,...). These pins are pulled down with internal resistors, with
values between 20 and 100 kΩ, when in the Intel FWH mode. Any
ID pins pulled high will exhibit a leakage current of approximately
200 µA. Any pins intended to be low may be left to float. In a single
Intel FWH system, all may be left floating.
A/A Mux = A[3:0]
OE# I X Output Enable. Gates the device’s outputs during a read cycle
Row-Column Address Select. For the A/A Mux interface, this pin
R/C# I X determines whether the address pins are pointing to the row
addresses (A[0:10]) or the column addresses (A[11:19]).
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Analog Power Supply. This supply should share the same system
VCCa PWR X X
supply as VCC.
Reserved For Future Use. These pins are reserved for future
generations of this product. They may be left disconnected or driven.
RFU X If they are driven, the voltage levels should satisfy VIH and VIL
requirements.
A/A Mux = DQ[7:4]
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3.1. Read
Memory information, identifier codes, GPI registers or the status register can be read, regardless of the
VPP voltage. Commands using the read mode include: reading memory from the array, reading the
identifier codes, reading the status register, reading the lock bit registers, reading the random number
generator, reading the GPI registers, and reading the RNG status register. Upon initial device power-up
or after exit from reset, the device automatically resets to read array mode.
3.2. Write
Writes to the memory array’s CUI are initiating by issuing a write through the Intel FWH interface. (See
the following information on timing and Intel FWH cycle write protocol specifics.) The CUI does not
occupy a single, specific memory location—any valid address may be given. However, certain
commands, such as block erase, require the address be within the range of the desired address block.
3.4. Reset
RST# or INIT# at VIL initiates a device reset. In the read mode, RST# or INIT# low deselects the
memory, places output drivers in a high-impedance state, and turns off all internal circuits. RST# or
INIT# must be held low for time tPLPH (A/A Mux and FWH operation). The Intel FWH resets to read
array mode upon return from reset, and all blocks are set to default (locked) status (see 4.9.1), regardless
of their locked state prior to reset.
During block erase or program, driving RST# or INIT# low will abort the operation underway, in
addition to causing a reset latency. Memory contents being altered are no longer valid, since the data may
be partially erased or programmed.
It is important to assert RST# or INIT# during system reset. When the system comes out of reset, it will
expect to read from the memory array of the device. If a system reset occurs with no FWH reset—this is
hardware dependent—it is possible that proper processor initialization will not occur. (The Intel FWH
memory may be providing status information instead of memory array data.)
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The TBL# and WP# pins must be set to the desired protection state prior to starting a program or erase
operation, since they are sampled at the beginning of the operation. Changing the state of TBL# or WP#
during a program or erase operation may cause unpredictable results.
If the state of TBL# or WP# changes during a program suspend or erase suspend state, the changes to the
device’s locking status do not take place immediately. The suspended operation may be resumed to
successfully complete the program or erase operation. The new lock status will take place after the
program or erase operation completes.
These pins function in combination with the register-based block locking described in Section 4.9. When
active, these pins write-protect the appropriate block(s), regardless of the associated block-locking
registers. (For example, when TBL# is active, writing to the top block is prevented, regardless of the
state of the write-lock bit for the top block’s locking register. In such a case, clearing the write-protect bit
in the register will have no functional effect, even though the register may indicate that the block is no
longer locked. The register may still be set to read-lock the block, if desired.) See Section 4.9 for further
information.
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4. Functional Descriptions
When the VPP voltage ≤ VPPLK, read operations from the status register, identifier codes or memory are
enabled, but programming and erase functions are disabled. Placing VPPH1/2 on VPP enables successful
block erase and program operations.
Command Bus Cycles Notes First Bus Cycle Second Bus Cycle
Required
Oper. Addr.(1) Data(2) Oper. Addr.(1) Data(2)
Note:
1. Key:
X = Any valid address within the device
IA = Identifier Code Address
BA = Address within the block being erased
WA = Address of memory location to be written
SRD = Data read from status register.
WD = Data to be written at location WA
ID = Data read from identifier codes
2. Following the Read Identifier Codes command, read operations access manufacturer and device.
See Table 4 for the read identifier code data.
3. The block must not be write locked when attempting block erase or program operations. Attempts
to issue a block erase or program to a write-locked block will fail.
4. Either 40h or 10h are recognized by the WSM as the program setup.
Note: Commands other than those shown previously are reserved by Intel for future device implementations
and should not be used.
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7 6 5 4 3 2 1 0
Bit Description
7 Write State Machine Status (SR.7). Check SR.7 to determine block erase or program completion.
SR.6–0 are invalid while SR.7 = 0.
1 = Ready
0 = Busy
5 Erase Status (SR.5). If both SR.5 and SR.4 are 1s after a block erase attempt, an improper command
sequence was entered.
1 = Error in block erasure
0 = Successful block erase
3 VPP Status (SR.3). SR.3 does not provide a continuous indication of VPP level. The WSM interrogates
and indicates the VPP level only after a block erase or program operation. SR.3 is not guaranteed to
reports accurate feedback only when VPP ≠ VPPH1/2.
1 = VPP low detect, operation abort
0 = VPP OK
1 Device Protect Status (SR.1). SR.1 does not provide a continuous indication of write-lock bit, TBL# pin
or WP# pin values. The WSM interrogates the write-lock bit, TBL# pin or WP# pin only after a block
erase or program operation. Depending on the attempted operation, it informs the system whether or not
the selected block is locked.
1 = Write-lock bit, TBL# pin, or WP# pin Detected, operation abort
0 = Unlock
0 Reserved for future enhancements (SR.0). SR.0 is reserved for future use and should be masked out
when polling the status register.
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Successful block erasure requires that the corresponding block’s write-lock-bit is cleared, and the
corresponding write-protect pin (TBL# or WP#) is inactive. If a block erase is attempted when the block
is locked, the block erase will fail, with the reason for failure in the status register.
Successful block erase only occurs when VPP = VPPH1 or VPPH2. If the erase operation is attempted at
VPP ≠ VPPH1 or VPPH2, erratic results may occur.
Reliable programming only occurs when VPP = VPPH1 or VPPH2. If programming is attempted at
VPP ≠ VPPH1 or VPPH2, erratic results may occur.
Successful program operation also requires that the corresponding block’s write-lock bit be cleared and
that the corresponding write-protect pin (TBL# or WP#) be inactive. If program operation is attempted
when the block is locked, the operation will fail.
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After a successful suspend, a Read Array command may be written to read data from a block other than
the suspended block. A Program command sequence may also be issued during erase suspend to program
data in blocks other that the block currently in the erase suspend mode.
The other valid commands while block erase is suspended include Read Status Register and Block Erase
Resume. After a Block Erase Resume command is written, the WSM will continue the block erase
process. VPP must remain at VPPH1/2 (the same VPP level initially used for the block erase) while block
erase is suspended. RST# or INIT# must also remain at VIH. Block erase cannot resume until program
operations initiated during block erase suspend have completed.
After a successful suspend, a Read Array command can be written to read data from locations other than
that which is suspended. The only other valid commands while program is suspended are Read Status
Register and Program Resume. After Program Resume command is written, the WSM will continue the
programming process. VPP must remain at VPPH1/2 (the same VPP level used for program) while in program
suspend mode. RST# or INIT# must also remain at VIH.
It is recommended that the GPI pins be in the desired state before FWH4 is brought low for the
beginning of the next bus cycle, and remain in that state until the end of the read.
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FFBF0002h T_BLOCK_LK Top Block Lock Register (4-8-Mbit FWH) 01h R/W
FFBE0002h T_MINUS01_LK Top Block [-1] Lock Register (4-8-Mbit FWH) 01h R/W
FFBD0002h T_MINUS02_LK Top Block [-2] Lock Register (4-8-Mbit FWH) 01h R/W
FFBC0002h T_MINUS03_LK Top Block [-3] Lock Register (4-8-Mbit FWH) 01h R/W
FFBB0002h T_MINUS04_LK Top Block [-4] Lock Register (4-8-Mbit FWH) 01h R/W
FFBA0002h T_MINUS05_LK Top Block [-5] Lock Register (4-8-Mbit FWH) 01h R/W
FFB90002h T_MINUS06_LK Top Block [-6] Lock Register (4-8-Mbit FWH) 01h R/W
FFB80002h T_MINUS07_LK Top Block [-7] Lock Register (4-8-Mbit FWH) 01h R/W
FFB70002h T_MINUS08_LK Top Block [-8] Lock Register (8-Mbit FWH) 01h R/W
FFB60002h T_MINUS09_LK Top Block [-9] Lock Register (8-Mbit FWH) 01h R/W
FFB50002h T_MINUS10_LK Top Block [-10] Lock Register (8-Mbit FWH) 01h R/W
FFB40002h T_MINUS11_LK Top Block [-11] Lock Register (8-Mbit FWH) 01h R/W
FFB30002h T_MINUS12_LK Top Block [-12] Lock Register (8-Mbit FWH) 01h R/W
FFB20002h T_MINUS13_LK Top Block [-13] Lock Register (8-Mbit FWH) 01h R/W
FFB10002h T_MINUS14_LK Top Block [-14] Lock Register (8-Mbit FWH) 01h R/W
FFB00002h T_MINUS15_LK Top Block [-15] Lock Register (8-Mbit FWH) 01h R/W
FFBC0100h FGPI_REG FWH General-Purpose Input Register N/A RO
FFBC015Fh RNG Hardware Status Register 40h* R/W
FFBC0160h RNG Data Status Register 0 RO
FFBC0161h RNG Data Register N/A RO
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Bit Function
7:3 Reserved
Read-Lock
2 1 = Prevents read operations in the block where set.
0 = Normal operation for reads in the block where clear. This is the default state.
Lock-Down
1 = Prevents further set or clear operations to the Write Lock and Read Lock bits. Lock-Down only can
be set, but not cleared. The block will remain locked-down until reset (with RST# or INIT#), or until
1
the device is power-cycled.
0 = Normal operation for Write Lock and Read Lock bit altering in the block where clear. This is the
default state.
Write-Lock
0 1 = Prevents program or erase operations in the block where set. This is the default state.
0 = Normal operation for programming and erase in the block where clear.
Data Reserved Read Lock, Lock-Down, Write Lock, Resulting block state (1).
Data 7:3 Data 2 Data 1 Data 0
Note: The write-lock bit must be set to the desired protection state prior to starting a program or erase
operation, since it is sampled at the beginning of the operation. Changing the state of the write-lock bit
during a program or erase operation may cause unpredictable results. If the state of the write-lock bit
changes during a program suspend or erase suspend state, changes in the block’s locking status do not
occur immediately. The suspended operation may be resumed successfully. The new lock status will take
place after the program or erase operation completes. The individual bit functions are described in the
following sections.
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Write Lock
The default write status of all blocks upon power-up is write-locked. Any program or erase operations
attempted on a locked block will return an error in the status register (indicating block lock). The status
of the locked block can be changed to unlocked by clearing the write-lock bit, provided the lock-down
bit also is not set. The current write-lock status of a particular block can be determined by reading the
corresponding write-lock bit. The write-lock functions in conjunction with the hardware write-lock pins,
TBL# and WP#. When active, these pins take precedence over the register locking function and write-
lock the top block or remaining blocks, respectively. Reading this register will not read the state of the
TBL# or WP# pin.
Read Lock
The default read status of all blocks upon power-up is read-unlocked. When a block’s read-lock bit is set,
data cannot be read from that block. An attempted read from a read-locked block will result in the data
00h. (Note that failure is not reflected in the status register.) The read-lock status can be unlocked by
clearing the read-lock bit, provided the lock-down bit has not been set. The current read-lock status of a
particular block can be determined by reading the corresponding read-lock bit.
Lock-Down
In the Intel FWH interface mode, the default lock-down status of all blocks upon power-up is not-locked-
down. The lock-down bit for any block may be set, but only once, because future attempts to change that
block-locking register will be ignored. The lock-down bit is cleared only upon a device reset with RST#
or INIT#. The current lock-down status of a particular block can be determined by reading the
corresponding lock-down bit. Once a block’s lock-down bit is set, the read- and write-lock bits for that
block can no longer be modified, and the block is locked-down in its current state of read and write
accessibility.
Bit Function
7:5 Reserved
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The advantages of random numbers over pseudo-random numbers as well as a brief overview of the
simple mathematics of testing RNGs are discussed superficially in the companion document, The Intel®
Platform RNG Tech Brief, which is available online.
Bit Function
7 Reserved
6 RNG Present—RO. Determines whether or not an RNG is present on this component, or if it has been
disabled.
1 = RNG Present
0 = RNG not present
5:1 Reserved
Bit Function
7:1 Reserved
0 RNG Output Valid. Determines whether the RNG data register contains a valid random number.
1 = RNG data register contians valid random data
0 = RNG data register contents not valid
Datasheet 27
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Bit Function
7:0 RNG Output: (Should only be used if RNG Data Status Register indicates valid output.)
Note: There is a chance that, even if no RNG device is present, the physical memory locations described above
may coincidentally match the values expected for an RNG device. For this reason, before random data is
sent to an application, the device should be exercised to verify that it is indeed an RNG. This can be
accomplished by enabling the device and running an initial test (e.g., FIPS (Federal Information
Processing Standard) 140-1) before use.
28 Datasheet
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The most straightforward method of using multiple FWH components is to use devices of equal density.
This is the recommended technique.
In special applications, when it is desirable to use multiple FWH components of different densities—if
multiple RNGs or more GPIs are required, for instance, without the need for greater array space—IDs
must be chosen such that component memory array spaces do not cross the boundaries delimited by the
highest-capacity device, as illustrated in the following table.
For example, in a design with 8- and 4-Mbit components, the 8-Mbit part must either be first or must be
after enough 4-Mbit parts to add up to a multiple of 8 Mbits.
Yes No Yes
8 Mbits 4 Mbits
4 Mbits 8 Mbits
Biggest is 8 Mbits.
Datasheet 29
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In the existing Intel ICH, the address map is broken up into eight 512-KB segments. The BIOS Select
Register in the Intel ICH is a 32-bit register that contains the needed mapping information, thereby
determining which FWH receives requests from which portion of the address map. For example, in a
system with four 8-Mbit devices, this register would be 00112233h, which is the default power-up state
for this register. In a system with eight 4-Mbit devices, the register must be changed to 01234567h.
Note: The FWH indicated in the most-significant nibble of the register may be shadowed elsewhere in the
system memory map. The FWH with ID 0 may not be re-mapped.
Note: The paging of FWH devices will also “page” features, potentially affecting the visibility or location of
the FGPI register (see Section 4.9.2.1) or of an active/ready RNG. When a paging scheme is used, it is
recommended that critical FPGIs be used only on the ID 0 FWH device, which must remain mapped at
the top of memory. Ideally, the RNG driver in a system with more than four FWHs should verify the
mapping of FWHs in order to keep track of which RNGs are active and which are present in the memory
map. There is no convenient way, aside from checking the select register, to determine which IDed FWH
is in which location in the memory map.
30 Datasheet
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Start Bus
Command Comments
Operation
Block Erase
Complete
Check SR.5
1 Standby
Command Sequence 1 = Block Erase Error
SR.4,5 = Error
0 SR.5, SR.4, and SR.3 are only cleared by the Clear Status
Register command in cases where multiple blocks are erased
before full status is checked.
1 Block Erase If error is detected, clear the Status Register before attempting
SR.5 = retry or other error recovery.
Error
Block Erase
Successful
Datasheet 31
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32 Datasheet
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5. Electrical Specifications
5.1. Absolute Maximum Ratings
Case temperature under bias:......................... –10 °C to +85 °C *WARNING: Stressing the device
beyond the “Absolute Maximum
Storage temperature: ................................... –65 °C to +125 °C Ratings” may cause permanent
damage. These are stress ratings
Supply voltage with respect to VSS ..................-0.2 V to 4.1 V only. Operation beyond the
“Operating Conditions” is not
Voltage On Any Pin (except VPP):–0.5 V to +VCC + 0.5 V(1,2,5)
recommended and extended exposure
VPP voltage: ........................................... –0.5 V to +14.0 V(1,2,4) beyond the “Operating Conditions”
may affect device reliability.
Output short-circuit current: ...................................... 100 mA(3)
Note:
1. All specified voltages are with respect to GND. The minimum DC voltage on the VPP pin is –0.5 V.
During transitions, this level may undershoot to –2.0 V for periods of <20 ns. During transitions,
this level may overshoot to VCC + 2.0 V for periods of <20 ns.
2. The maximum DC voltage on VPP may overshoot to +14.0 V for periods of <20 ns.
3. Output shorted for no more than one second. No more than one output is shorted at a time. This
note applies only to non-PCI outputs.
4. Connection to supply of VHH is allowed for a maximum cumulative period of 80 hours.
5. Do not violate processor or chipset limitations on the INIT# pin.
Note:
1. This temperature requirement differs from the normal commercial operating condition of flash
memories.
Datasheet 33
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IIL Input leakage current 0 < Vin < VCC ±10 µA 1,4
Note:
1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state
outputs.
2. Refer to PCI spec.
3. Inputs are not “5 volt safe.”
4. IIL may be changed on IC and ID pins (up to 200µ µA), if pulled against internal pull-downs. Refer
to the pin descriptions (Table 1).
5. Do not violate processor or chipset specifications regarding the INIT# pin voltage.
34 Datasheet
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ICCSL1 VCC stand-by current Voltage range of all inputs is 100 µA 2,3,4
VIH to VIL, FWH4 = VIH,
(FWH interface)
VCC = 3.6 V,
CLK f = 33 MHz
No internal operations in
progress.
Note:
1. All currents are RMS, unless otherwise noted. These currents are valid for all packages.
2. VPP = VCC
3. VIH = 0.9 VCC , VIL = 0.1 VCC per the PCI output VOH and VOL specifications of Table 8.
4. This number is the worst case of IPP + ICC memory core + ICC FWH interface.
Datasheet 35
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0.3 VCC < VOUT < 0.9 VCC -17.1 (VCC -VOUT) mA
0.6 VCC > VOUT > 0.1 VCC -17.1 (VCC -VOUT) mA
Note:
1. PCI specification output load is used.
36 Datasheet
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Note:
1. PCI components must work with any clock frequency between nominal DC and 33 MHz.
Frequencies less than 16 MHz may be guaranteed by design rather than testing. Refer to the PCI
specificaiton.
2. Applies only to the rising edge of the signal. See Chapter 4 of the PCI electrical specification.
T_cyc
T_high
T_low
0.6 Vcc
0.5 Vcc
0.2 Vcc
Datasheet 37
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Note:
1. Minimum and maximum times have different loads. See PCI spec.
2. For purposes of active/float timing measurements, the Hi-Z or Off state is defined as that in which
the total current delivered through the component pin is less than or equal to the leakage current
specification.
3. This parameter applies to any input type (excluding CLK).
V_th
CLK
V_test
V_tl
T_val
FWH[3:0]
(Valid Output Data)
FWH[3:0]
(Float Output Data)
T_on
T_off
38 Datasheet
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V_th
CLK
V_test
V_tl
T_su
T_h
FWH[3:0]
Inputs V_max
(Valid Input Data) Valid
Note:
1. The input test environment uses 0.1 VCC of overdrive over VIH and VIL. Timing parameters must
be met with no more overdrive than this. Vmax specifies the maximum peak-to-peak waveform
allowed for measuring the input timing. Production testing may use different voltage values, but
must correlate results back to these parameters.
Reset Operations
VIH
RST# (P)
V
IL
P1
P1(1) tPLPH RST# or INIT# pulse low time (If RST# or INIT# is tied 100 ns 1
to VCC, this specification is not applicable.)
Note:
1. There will be a 20-µs reset latency if a reset procedure is performed during a programming or
erase operation.
Datasheet 39
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Note:
1. Typical values measured at TA = +25°C and nominal voltages.
2. Excludes system-level overhead.
This section contains timing and protocol information for the Intel FWH interface. Note that the Intel
FWH interface is a licensed interface, so the appropriate license must be obtained from Intel for
components supporting the Intel FWH interface (e.g., ASICs, PLDs).
Addresses in this section refer to addresses as seen from the FWH’s “point of view,” so some calculation
will be required to translate these to the actual locations in the memory map (and vice versa).
40 Datasheet
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1 START 1101 IN FWH4 must be active (low) for the part to respond.
Only the last start field (before FWH4 transitioning high)
should be recognized. The START field contents
indicate an FWH memory read cycle.
2 IDSEL 0000 IN Indicates which FWH device should respond. If the
IDSEL (ID select) field matches the value ID[3:0], then
to
that particular device will respond to subsequent
1111 commands.
3-9 IMADDR YYYY IN These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
On multibyte data transfers, lower-order addresses will
be zero, depending on page size.
10 IMSIZE 0000 (1 byte) IN A field of this size indicates how many bytes will be
transferred during multibyte operations. The FWH will
only support single-byte transfers.
11 TAR0 1111 IN In this clock cycle, the master (Intel ICH) has driven the
then float bus to all 1s and then floats the bus, prior to the next
clock cycle. This is the first part of the bus “turnaround
cycle.”
12 TAR1 1111 (float) Float then The FWH takes control of the bus during this cycle.
OUT During the next clock cycle, it will be driving “sync
data.”
13-14 WSYNC 0101 (WAIT) OUT The FWH outputs the value 0101, a wait-sync
(WSYNC, a.k.a. “short-sync”), for two clock cycles. This
value indicates to the master (Intel ICH) that data is not
yet available from the part. This number of wait-syncs
is a function of the device’s access time.
15 RSYNC 0000 (READY) OUT During this clock cycle, the FWH will generate a “ready-
sync” (RSYNC) indicating that the least-significant
nibble of the least-significant byte will be available
during the next clock cycle.
16 DATA YYYY OUT YYYY is the least-significant nibble of the least-
significant data byte.
17 DATA YYYY OUT YYYY is the most-significant nibble of the least-
significant data byte.
17+ “DATA” 2 WSYNCS + OUT n = IMSIZE. Each subsequent byte of data requires 2
3 x 2n-1 + 1 RSYNC + wait-syncs + 1 ready-sync + 2 data nibbles.
2n 2 DATA The FWH supports only n=0000 (single-byte) reads.
Previous TAR0 1111 OUT In this clock cycle, the Inel FWH has driven the bus to
+1 then float all ones and then floats the bus prior to the next clock
cycle. This is the first part of the bus “turnaround cycle.”
Previous TAR1 1111 (float) Float then The master (Intel ICH) resumes control of the bus
+1 IN during this cycle.
Note:
1. Field contents are valid on the rising edge of the present clock cycle.
Datasheet 41
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CLK
FWH4
1 START 1110 IN FWH4 must be active (low) for the part to respond.
Only the last start field (before FWH4 transitioning
high) should be recognized. The START field
contents indicate an FWH memory write cycle.
3-9 IMADDR YYYY IN These seven clock cycles make up the 28-bit
memory address. YYYY is one nibble of the entire
address. Addresses are transferred most-significant
nibble first.
10 IMSIZE 0000 (1 byte) IN This size field indicates how many bytes will be
transferred during read/write operations. The FWH
only supports single-byte writes.
13 TAR0 1111 IN In this clock cycle, the master (Intel ICH) has driven
then float the bus to all 1s and then floats the bus prior to the
next clock cycle. This is the first part of the bus
“turnaround cycle.”
14 TAR1 1111 (float) Float then The FWH takes control of the bus during this cycle.
OUT During the next clock cycle it will be driving the “sync”
data.
15 RSYNC 0000 OUT The FWH outputs the values 0000, indicating that it
has received data or a flash command.
42 Datasheet
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16 TAR0 1111 OUT In this clock cycle, the FWH has driven the bus to all
then float 1s and then floats the bus prior to the next clock
cycle. This is the first part of the bus “turnaround
cycle.”
17 TAR1 1111 (float) Float then The master (Intel ICH) resumes control of the bus
IN during this cycle.
Note:
1. Field contents are valid on the rising edge of the present clock cycle.
CLK
FWH4
Once valid START, IDSEL, and IMSIZE fields are received, the Intel FWH always will respond to
subsequent inputs as if they were valid. As long as the states of FWH [3:0] and FWH4 are known, the
response of the Intel FWH to signals received during the FWH cycle should be predictable. The Intel
FWH will make no attempt to check the validity of incoming flash operation commands.
Datasheet 43
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During a write cycle, there is a possibility that an internal flash write or erase operation is in progress (or
has just been initiated). If FWH4 is asserted during this time frame, the internal operation will not abort.
The software must send an explicit flash command to terminate or suspend the operation.
The internal FWH state machine will not initiate a flash write or erase operation until it has received the
last data nibble from the chipset. This means that FWH4 can be asserted as late as this cycle (“cycle 12”)
and no internal flash operation will be attempted. However, since the Intel FWH will start “processing”
incoming data before it generates its SYNC field, it should be considered a non-buffered peripheral
device.
Note:
1. Minimum and maximum times have different loads. See the PCI specification.
2. For purposes of active/float timing measurements, the Hi-Z or “off” state is defined as the state
where the total current delivered through the component pin is less than or equal to the leakage
current specification.
3. This parameter applies to any input type (excluding CLK).
44 Datasheet
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Note:
1. Sampled, not 100% tested.
Note:
1. Sampled, not 100% tested.
V_th
CLK
V_test
V_tl
T_val
FWH[3:0]
(Valid Output Data)
FWH[3:0]
(Float Output Data)
T_on
T_off
Datasheet 45
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V_th
CLK
V_test
V_tl
T_su
T_h
FWH[3:0]
Inputs V_max
(Valid Input Data) Valid
46 Datasheet
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The following information applies only to the Intel® 82802 when in the A/A Mux mode. Information
regarding the FWH mode (i.e., the standard operating mode) is provided in earlier chapters of this
document
Datasheet 47
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Note:
1. When VPP ≤ VPPLK, the memory contents can be read, but not altered.
2. X can be VIL or VIH for the control and address input pins and VPPLK or VPPH1/2 for the VPP supply
pin. See the DC characteristics for the VPPLK and VPPH1/2 voltages.
3. See Table 4 for the read identifier code data and addresses.
4. Command writes involving block erase or program are reliably executed when VPP = VPPH1/2 and
VCC = VCC ± 0.3 V.
5. Refer to Table 2 for the valid DIN during a write operation.
6. VIH and VIL refer to the DC Characteristics associated flash memory output buffers:
VIL min = -0.5V, VIL max = 0.8V and VIH min = 2.0V, VIH max = VCC + 0.5V.
48 Datasheet
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P1 tPLPH RST# pulse low time (If RST# is tied to VCC, this 100 ns
specification is not applicable.)
P2 tPLRH RST# low to reset during block erase or program 1, 2 20 µs
Note:
1. If RST# is asserted when the WSM is not busy (RY/BY# = ‘1’), the reset will complete within 100
ns.
2. A reset time, tPHAV, is required from the latter of RY/BY# or RST# going high until outputs are
valid.
VIH
RY/BY# (R)
VIL
P2
Note:
1. See the AC input/output reference waveform for the maximum allowable input slew rate.
2. OE# may be delayed up to tCHQV – tGLQV after the rising edge of R/C# without affecting tCHQV.
3. Tc = 0 °C to + 85 °C, 3.3 V ± 0.3 V VCC
Datasheet 49
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R1
VIH x x
Row Address Column Address Next Address
ADDRESSES (A)
Stable Stable Stable
VIL x x
R2 R5
VIH
R3 R4
R/C# (C) R6
VIL
R7
VIH
OE# (G)
R10
VIL
R8 R11
VOH
High Z High Z
DATA (D/Q) Data Valid
VOL
R9
VIH
WE# (W)
VIL
VIH
RP# (P)
VIL
50 Datasheet
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Note:
1. Refer to Table 6-28 [?] for valid AIN and DIN for block erase or program or other commands.
2. Tc = 0 °C to + 85 °C, 3.3 V ± 0.3 V VCC
Datasheet 51
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A B C D E F
VIH
ADDRESSES (A) R1 C1 R2 C2
VIL
W5 W6 W7 W8
VIH
R/C# (C)
VIL
W1 W9 W10
VIH W2
WE# (W)
VIL W12
VIH
OE# (G)
VIL W4
W3
VOH
Valid
DATA (D/Q) DIN DIN SRD
VOL
W13
VIH
RY/BY# (R)
VIL
VIH
RP# (P) W15
VIL
W11 W14
VPPH1,2
VPP (V)
VIL
Note:
A VCC power-up and stand-by
B Write block erase or program setup
C Write block erase confirm or valid address and data
D Automated erase or program delay
E Read status register data
F Ready to write another command
52 Datasheet
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Phone: (800) 628-8686
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