GaN HEMT

Microelectronic Engineering 273 (2023) 111958
Contents lists available at ScienceDirect
Microelectronic Engineering
journal homepage: www.elsevier.com/locate/mee
Review article
Chip-level thermal management in GaN HEMT: Critical review on recent

patents and inventions
Mohd Faizol Abdullah *, Mohd Rofei Mat Hussin, Muhamad Amri Ismail,
Sharaifah Kamariah Wan Sabli
MIMOS Semiconductor (M) Sdn Bhd, Technology Park Malaysia, 57000 Kuala Lumpur, Malaysia
A R T I C L E I N F O A B S T R A C T
Keywords: The technological development of GaN high electron mobility transistor (HEMT) is on the right track to compete
GaN HEMT with Si and SiC-based power transistors for the market segment of >650 V. A proper thermal management
Self-heating 2DEG strategy at the chip-level is capably alleviating the impact of self-heating two-dimensional electron gas (2DEG);
Thermal management
hence increase the reliability, boosting the output power density, and widening the safe operating area of the
Patent
Review
GaN HEMT. This article compiles and discusses remarkable patents on chip-level thermal management in GaN
HEMT to understand the available solutions disclosed beyond academia and the concept behind the inventions.
These concepts, which are either proven or unproven, are critically being reviewed with support from relevant
peer-reviewed research articles. The main strategies can be distinguished as four: A) top layer heat spreader, B)
substrate heat spreader, C) buried heat spreader, and D) buried GaN in heat spreader. Strategies A and B using
diamond are the most common and proven effective for cooling the 2DEG. The trend is moving towards adopting
cheaper materials with high thermal conductivity, e.g. metals, 2D materials, and others. The strategies and
patents are assessed to summarize their practicality, effectiveness, sophistication, and cost levels for the adoption
of the proposed solutions.
1. Introduction indicator for GaN HEMT performance is not only BV. There are
numerous active research and development (R&D) works working on
The GaN high electron mobility transistor (HEMT) is expected to be a the improvement of GaN HEMT. They can be categorized into three
next-generation power device, catering to the market for power con main activities; 1) manufacturing and processing, 2) device architecture,
verters with a voltage rating of >650 V. This segment is currently and 3) thermal management. The main and sub-activities for each item
dominated by vertical devices of Si insulated gate bipolar transistor are listed in Table 1 including their goal and progress. For the market
(IGBT), Si superjunction metal-oxide-semiconductor field-effect tran segment of >650 V, the direct competitor of GaN HEMT would be SiC
sistor (MOSFET), SiC MOSFET, and SiC Schottky barrier diode. The MOSFET. Being also one of the family members of wide bandgap ma
demand for efficient, compact, robust, and safe power systems are now terials, SiC offers a similarly large BV but at a higher cost. The produc
booming for emerging applications, e.g. traction inverter in electric tion of electronic grade SiC by the combination of physical vapor
vehicle [1], photovoltaic string inverter [2], and high voltage DC grid transport and epitaxy processes is feasible for obtaining the SiC wafer
system [3]. In the previous generation, the Si lateral IGBT and MOSFET with a diameter of up to 150 mm [10].
have been widely utilized for low-power converters with a voltage rating The availability of large-area (diameter ≥ 200 mm) GaN-on-Si wafers
of up to several hundred volts [4]. Owing to the wide bandgap of GaN is a big progress towards the cost reduction of GaN HEMT. In the
approximately 3.4 eV (at 300 K), the breakdown voltage (BV) of GaN is established recipes, complete GaN epilayers can be grown by metal-
~3.3 MVcm− 1 which is roughly 10 times larger than Si [5–7]. The re organic chemical vapor deposition (MOCVD) system on Si(111) wafer,
ported BV of the GaN HEMT lateral device is as large as 2.2 kV with the either using AlN nucleation layer and step-graded AlGaN buffer layers
removal of the original Si substrate [8], and 2.274 kV from HEMT with [11], or GaN/AlN strained layer superlattice [12]. This results in a fully
AlGaN channel and ohmic/Schottky hybrid drains [9]. Indeed, the key relaxed c-plane GaN layer and strained c-plane AlGaN, which is similar
* Corresponding author.
E-mail address: [email protected] (M.F. Abdullah).
https://doi.org/10.1016/j.mee.2023.111958
Received 24 November 2022; Received in revised form 8 February 2023; Accepted 15 February 2023
Available online 21 February 2023
0167-9317/© 2023 Elsevier B.V. All rights reserved.
M.F. Abdullah et al. Microelectronic Engineering 273 (2023) 111958
Table 1 can also be found in the report by Tijent et al. [19] and Mendes et al.
Classification of R&D works on GaN HEMT consists of three main activities. The [20].
activities on ‘manufacturing and processing’ and ‘device architecture’ and their In this article, we enlarge the scope of chip-level thermal manage
corresponding sub-activities are not in the interest of this review. ment by providing a critical review of published patents and their sup
Main R&D work Sub-research work Goal and progress Ref. porting proofs from peer-reviewed research articles. The real scenario
Manufacturing • Substrate for - Increase wafer size, reduce [12] proves that the R&D players on GaN HEMT are not only limited to
and processing epitaxy the cost of GaN wafer academia. The list extends to a broad range of researchers and engineers
• Buffer layers - Increase vertical BV, crack- [11] from industries and research institutes across the globe. Therefore, many
free GaN, reduce dislocation concepts on chip-level thermal management in GaN HEMT appeared in
density in GaN, reduce deep
trap states, reduce current
(and only appeared in) patent publications instead of peer-reviewed
collapse journals. It is necessary to come out with a compilation and discussion
• CMOS- - Reduce capital using [21] on the concepts and proof of concepts for chip-level thermal manage
compatible existing Si CMOS fab, Au- ment to understand the most practical strategy for addressing the cur
process free metallization, reduce
rent issue of overheating GaN HEMT. In Section 2, we explain the
on-resistance
• Dielectric and - Reduce gate leakage [22] problem of self-heating in GaN HEMT and the available strategies to
passivation current, reduce dynamic on- minimize the problem. In Sections 3–6, we thoroughly discuss the pat
resistance, improve ents and inventions related to chip-level thermal management in GaN
reliability HEMT based on each classification described in Section 2. Finally, we
Device • Gate - Reduce gate leakage [23]
conclude this article by providing our opinion based on the presented
architecture current, normally-off
HEMT, improve safety, patents and inventions to recommend the future direction of this topic.
improve reliability
• Channel - Increase lateral BV, reduce [9] 2. Self-heating 2DEG in GaN HEMT
on-resistance
• Metal field plates - Increase lateral BV, reduce [24]
current collapse Fig. 1a shows the default device architecture of GaN HEMT as a
• Lateral to vertical - Increase current and power [25] lateral device. This structure does not provide details on the type and
device density, increase BV thickness of the substrate, nucleation, buffer, spacer, Al mole fraction in
Thermal • Chip-level heat - Increase current and power [26] AlxGaN1-xN, and its cap layers. The information on this part is critical
management spreader density, reduce hotspot
temperature, improve
only when reviewing on ‘manufacturing and processing’ part as elabo
reliability rated in the previous Table 1. A similar goes to the ‘device architecture’,
• Package-level - Increase current and power [27] where the default device architecture of GaN HEMT does not cover every
heat spreader density, reduce device aspect of designs, e.g. recessed gate, mesa isolation, field plates, etc.
and heat sink temperature, improve
Both component of ‘manufacturing and processing’ and ‘device archi
reliability
tecture’ can be discussed separately from ‘thermal management’ as the
hotspot location in GaN HEMT lateral device is always at the self-heating
to the one grown on c-plane sapphire and 4H-SiC. The use of c-plane of two-dimensional electron gas (2DEG) channel [26,28,29], which is
AlGaN/GaN is common for fabricating the normally-on HEMT. Even so, approximately below the gate contact towards the drain contact as
there is strong motivation on fabricating the normally-off HEMT by shown in Fig. 1b and Fig. 1c. During the high source-drain bias, the GaN
modifying gate architecture [13], especially for reducing the static HEMT is operating in the saturation regime with high field region on the
power consumption and ensuring fail-safe operation. The use of GaN-on- drain side. The electrons in 2DEG deliver power to the lattice by Pv =
Si however imposes a significant limitation on HEMT output power nqvd(E)E, where Pv is the power density per unit volume, n is the electron
density compared to GaN-on-SiC due to the accumulated heat in the density, q is the elementary charge constant, vd(E) is the field dependent
device from the self-heating channel. Note that the thermal conductiv drift velocity, and E is the electric field [30]. The hotspot under the gate
ity, k value of single-crystalline GaN is only kGaN ~ 130 Wm− 1 K− 1, is created since kGaN ∝ 1/T, which means there is high power dissipation
which is comparable to kSi ~ 148 Wm− 1 K− 1, but much lower than kSiC with lowered heat spreading capability of GaN, resulting in high tem
~ 350 Wm− 1 K− 1. Thanks to the high kSiC, chip-level thermal manage perature in the hotspot area.
ment for the SiC MOSFET is not critically required compared with GaN The formation of 2DEG by the spontaneous piezoelectric polarization
HEMT, and most of the time it is sufficient to rely on the package- or at AlGaN/GaN heterostructure is described elsewhere [20]. It is a high
module-level heat sink [14]. concentration of electron of ~1013 cm− 2 with high electron mobility of
The fabricated HEMT using a relatively higher k value GaN-on-SiC ~1500 cm2V− 1 s− 1 (at 300 K), confined in a potential well, and allows
wafer, although more costly than GaN-on-Si wafer, unfortunately still high current conduction during a high bias of source-drain electrode.
cannot tap the full potential of GaN HEMTs (DC and RF powers) since This however induced the self-heating of 2DEG and hotspot as explained
the heat is not fully dissipated from the devices. The reported value of earlier, increasing its resistance (thus lowering the source-drain cur
the DC power density of GaN-on-Si is ~4.5 Wmm− 1 [15], while GaN-on- rent), accelerating/inducing the material degradation, and determining
SiC is ~15 Wmm− 1 [16]. On a substrate with a higher k value than SiC, the reliability of the device [31–33]. For the multiple gates HEMT, there
the record DC power density for the GaN-on-diamond (k ~ 1800 Wm− 1 are multiple hotspots under the gate electrode similar to the one illus
K− 1) is recently reported as high as 56 Wmm− 1 [17]. As we already trated in Fig. 1d. In the plot, T2 is the base device temperature. The
know, the larger output power density can be directly translated into a middle gate finger (in this example third finger from the total five fin
wider safe operating area (SOA) of a certain power transistor. The use of gers) will be measured with the highest peak temperature of T4 due to
high k materials, e.g. diamond as a chip-level heat spreader in GaN the insufficient lateral heat dissipation and ‘thermal cross-talk’ [34–36].
HEMT is undeniably trending starting in the past decade. In a review Notice that the maximum hotspot temperature of T4 can be reduced to T3
article by Sang [18], the use of a diamond heat spreader for GaN HEMT by improving the heat dissipation, while the base device temperature of
is fairly discussed. Special attention on growing diamonds on GaN and T2 can only be reduced to T1 if proper heat sinking is available.
bonding GaN to diamonds are brought into the review. This is good, but Thermal management of GaN HEMT therefore can be separated into
the scope of materials is only limited to diamonds. Similar reviews on two categories; chip-level and package-level (including module-level)
diamond heat spreaders for GaN HEMT chip-level thermal management thermal solutions. Chip-level is purposely to spread the heat from the
hotspot to shave down the peak temperature. Even if the peak
2
Fig. 1. a) Schematic of GaN HEMT device architecture, and b) hotspot of self-heating 2DEG channel during the high-current operation. c) Top view of a single gate
GaN HEMT with an example of channel temperature taken from ref. [29]. d) Illustration of thermal crosstalk in multi-gate GaN HEMT with/without chip-level heat
spreader. e) An example of packaged GaN HEMT.
temperature is concentrated at a relatively small area, it is sufficient to The heat conductance in a solid can be distinguished into two types;
create an open circuit by burning out of the channel and neighboring dominant heat conduction by electrons and dominant heat conduction
metal contacts. The shaving of maximum temperature is not necessarily by phonons [40]. The electrically conductive metals with relatively high
come with the reduction of overall device temperature as the dissipated k values within 300–400 Wm− 1 K− 1, e.g. Cu, Au, and Ag are classified
heat from the hotspot needs a bulk material with the capability to into the first type of dominant heat conduction by electrons. On the
receive and dissipate the heat to the ambient. This is usually can be other hand, the non-electrically conductive ceramics, e.g. diamond and
addressed by a proper heat sink at package-level thermal management. BN fall into the second type of dominant heat conduction by phonons.
Fig. 1e shows an example of packaged GaN HEMT (TO-247) with a rear The integration of an electrically conductive heat spreader may or may
surface attached to the lead frame for heat sinking. The discussion on the not require a safe dielectric isolation layer, which is depending on the
designs and inventions related to package-level thermal management strategy of the chip-level thermal management developed by the
however is beyond the scope of this article. The topic of chip-level heat respective inventor.
spreader can be summarized as a map provided in Fig. 2 and each item
will be elaborated on later in the next sections. 3. Strategy A: Top layer heat spreader
In terms of material selection, the materials with high k values and
low thermal boundary resistance (TBR) with GaN are preferred. The in- The top layer heat spreader is front-side thermal management for
situ extraction of the k value for the heat spreader and its TBR at the GaN HEMT, where the idea is to shave down the peak temperature from
GaN/material interface can be done using thermoreflectance measure the self-heating 2DEG. If the top layer heat spreader is not thermally
ment [37]. The details on the concept and measurement technique for shorted to the heat sink, the overall device temperature will not be
this method are not provided in this article. Additionally, there are greatly reduced. Shaving down the peak temperature is not by any
several alternative methods for ex-situ k measurement on bulk and thin means less important than overall device temperature, as the physical
film, e.g. 3ω [38], modified Raman spectroscopy technique [39], etc. deteriorations, e.g. burning of channel and metal contacts are initiated
Fig. 2. Thermal management of GaN HEMT consisting of the chip-level heat spreader and package-level heat sink. The inventions related to the chip-level heat
spreader can be further separated into top layer heat spreader, substrate heat spreader, buried heat spreader, and buried GaN in heat spreader.
3
at the extreme temperature point within the self-heating 2DEG. This 2DEG. In an article (year 2014) in ref. [46], there is no observable ef
approach can be separated into two classes; ‘near-junction’ and ‘far- fect of self-heating using a 50 nm-thick SiNx and 400 nm-thick NCD top
junction’ top layer heat spreaders and they are elaborated on below. layer heat spreader. In ref. [47], even 500-nm thick NCD grown at
750 ◦ C (quality towards larger crystalline domains) cannot convince an
3.1. Strategy A1: Near-junction heat spreader effective heat spreading from GaN HEMT. In another article (year 2017)
in ref. [48], NCD heat spreader using the ‘gate after diamond’ process is
The concept of a ‘near-junction heat spreader’ is the heat spreader proven insignificant in improving the heat spreading. This material is
material is deposited directly on AlGaN/GaN, as it is considered nearest deposited at 750 ◦ C using microwave chemical vapor deposition
to the underneath 2DEG layer. The invention related to this concept can (MWCVD) and most probably is a polycrystalline diamond (PCD)
be separated into two types; the first is a diamond thin film heat instead of NCD as claimed by the authors. Although not lowering the
spreader, and the second is a two-dimensional (2D) materials heat channel temperature, the authors found gate leakage current is reduced
spreader. for the HEMT with NCD/PCD heat spreader. This condition however is
not related to the heat spreading of NCD/PCD, but it is unintentionally
3.1.1. Diamond thin film heat spreader contributed by the thin residual SiNx protection layer under the gate
Kub and Hobart in US8039301B2 (year 2011) elaborated a method contact.
to form a diamond heat spreader on HEMT using the ‘gate after dia Since the temperature of depositing high-quality diamonds is limited
mond’ approach [41]. The simplified fabrication process is illustrated in by the temperature of Ni diffusion into III-nitride layers, another
Fig. 3a. Starting with complete GaN epilayers, HEMT is partially fabri dielectric layer can be deposited before Ni/Au gate to act as a diffusion
cated until ohmic metallization of source/drain contact. The front sur barrier layer. In a peer-reviewed article (year 2021) in ref. [49], a 40
face is later deposited with a 0.2–100 nm-thick dielectric protection nm-thick SiNx is employed under Ni/Au gate, forming a Schottky metal-
layer, e.g. Al2O3, HfO, Gd2O3, Sc2O3, SiNx, SiO2, etc., and grown with insulator-semiconductor gate instead of a Schottky metal-semiconductor
700 nm-thick nanocrystalline (NCD) at a temperature below 400 ◦ C. gate. Later on, a 100-nm thick SiNx protection layer is deposited on the
Here, the use of a dielectric layer is required for protecting the GaN metalized HEMT, followed by a 2.5 μm-thick PCD with k > 200 Wm− 1
surface from the NCD growth process, but it may need to be engineered K− 1 deposited at 700 ◦ C. Since the diamond top layer heat spreader is
further to satisfy another aspect of device performances, e.g. for better deposited after the gate, this process can be known as ‘gate before dia
gate control by minimizing the interface traps [42–44]. The NCD is later mond’. The HEMT in this ref. [49] demonstrated lowered thermal
patterned and etched until exposing the GaN surface layer for depositing resistance from 12.7 mmKW− 1 down to 7.4 mmKW− 1, without
the Schottky gate metal. Finally, the front surface is once again degrading the gate leakage current.
patterned and etched to expose the surface of ohmic source/drain con In a patent of US10002958B2 (year 2018), the process can be
tacts. The ‘gate after diamond’ can be considered as a default method to modified into ‘gate before diamond’ without using the dielectric diffu
form Schottky-gated HEMT using a common stack of Ni/Au. The Au is a sion barrier layer under the gate electrode [50]. The simplified fabri
noble metal with a high work function of ~5.1 eV and is known to form a cation process is illustrated in Fig. 3b. The main idea is to use a metal
potential barrier with AlGaN. Applying reverse bias on Au/AlGaN nitride gate, i.e. TiN or TiNx, where nitrogen to metal atom ratio >1 will
junction allows the depletion of electron concentration in the 2DEG tune the work function up to 5.4 eV and suitable to form a Schottky
layer to turn off the normally-on HEMT. In the ‘gate after diamond’ junction with AlGaN/GaN surface layer. The metal nitride is claimed to
approach, the deposition of the diamond should not be carried out at have low (or none) diffusion into AlGaN. The experimental data is
high temperatures to avoid Ni diffusion into III-nitride layers which proven in the peer-reviewed article (year 2020) in ref. [51], where the
result in an undesirably high gate leakage current [45]. atomic interface between TiN and AlGaN after annealing is well pre
We can find many peer-reviewed articles providing experimental served under a transmission electron image. In the US10002958B2 [50],
data on the deposition of medium-temperature NCD using the ‘gate after the HEMT device is first complicated on the GaN front surface including
diamond’ approach. However, the crystal quality of NCD is hardly suf both source/drain and TiNx Schottky gate contacts. The dielectric pro
ficient to demonstrate effective heat removal from the self-heating tection layer and NCD nucleation layer are deposited on the device, and
Fig. 3. Simplified process steps for fabricating GaN HEMT with ‘near-junction top heat spreader’, examples are using diamond heat spreader: a) ‘gate after diamond’
approach, b) ‘gate before diamond’ approach. Concepts are taken from patents in ref. [41] and ref. [50].
4
later a 700 nm-thick PCD is grown at a temperature of 900–1000 ◦ C. At is an example taken from ref. [54], where the high-temperature growth
this temperature range, it is important to protect AlGaN/GaN surface of PCD is found only suitable on the substrate with a low coefficient of
with a robust, but not too thick protection layer (mostly SiNx) to avoid thermal expansion (CTE) mismatch with diamond. Take the examples
the etching of GaN in an H2-rich environment [52]. for CTE between diamond (~0.8 × 10− 6 K− 1), SiC (~3.8 × 10− 6 K− 1),
and sapphire (~7.5 × 10− 6 K− 1); the CTE mismatch is larger in the case
3.1.2. Concerns on diamond growth on GaN of diamond-sapphire compared to the diamond-SiC. In the case of grown
The concern with the deposition of a diamond as a top layer heat PCD on GaN-on-sapphire, the compressive residual stress in the diamond
spreader therefore can be summarized into three points. The first is on layer is higher compared to the grown PCD on GaN-on-SiC and even
the protection of the GaN layer during the growth of the diamond top tually leads to the delamination of the PCD layer from the GaN surface.
layer heat spreader. It is known that the quality of PCD is greater than
NCD due to the improvement in the crystal quality of diamonds by the 3.1.3. 2D materials heat spreader
high-temperature growth process. The larger grain size of PCD by the Zhang et al. in US2014/0353722A1 (year 2014) elaborated a method
high-temperature growth process is known to result in a higher kdiamond, to form an hBN/graphene heat spreader under the gate electrode [56].
especially at the columnar region above the coalescence (diamond This invention is actually can be classified as ‘buried GaN’ as in later
nucleation) region [39]. Fig. 4a shows the outer surface of the GaN layer Section 6 as the GaN layer is sandwiched in between two hBN/graphene
with and without SiNx protection after the growth of the PCD heat double layers. However, for the sake of discussion, we put this invention
spreader, indicating there is extensive deterioration in forms of voids at into the class of ‘near-junction top heat spreader’ as the process elabo
the unprotected diamond/GaN interface [53]. The record of the lowest ration emphasizes the forming of the HEMT on the front side of hBN/
TBR between top layer GaN (AlGaN) and PCD is 3.1 ± 0.7 m2K.GW− 1 graphene. Excluding the rear side hBN/graphene, the simplified fabri
using a 5 nm-thick crystalline Si3N4 interlayer [54]. Provided that if SiNx cation process is illustrated in Fig. 5a. Initially and optionally, the first
is too thin, hydrogen can penetrate towards AlGaN/GaN surface and graphene layer is either grown on SiC/Si substrate or deposited on SiO2/
eventually will increase the HEMT leakage current [55]. Si substrate. The first hBN layer is then deposited onto the first graphene
The second concern is specific to the ‘gate after diamond’, where the layer, and complete GaN layers are grown on hBN/graphene/substrate.
etching of grown diamond to open the gate area is a critical factor in The second graphene layer is deposited onto the GaN front surface. To
determining the performance of GaN HEMT. The anisotropic etching of fabricate HEMT, the second graphene layer is patterned and etched
diamond generally requires high-power O2-based inductively-coupled opening for the gate electrode to some extent recessing the GaN layer,
plasma (ICP) etching. Fig. 4b shows the etching of the NCD/PCD top deposited with the second hBN layer as a conformal coating. The source/
layer heat spreader using O2-based ICP recipes as developed in ref. [48], drain electrodes are formed with another patterning and etching of the
where a combination of O2/Ar high power (coil/platen of 800/300 W) front hBN/graphene layer on GaN. After the deposition of the T-gate, the
and O2 low power (coil/platen of 100/30 W) can result in a clean bottom device is now completed and they believe graphene will effectively act
surface exposing AlGaN/GaN. The etch stop and the quality of the bot as a near-junction heat spreader under the hBN gate dielectric.
tom surface will determine the gate threshold voltage of the fabricated In an actual situation, the realistic k value of CVD-grown graphene
GaN HEMT by the ‘gate after diamond’ approach. The third concern is can be estimated in the range of 300–450 Wm− 1 K− 1, accounting for the
the process compatibility of growing diamond with the substrate. Fig. 4c effect of grain boundaries [57]. While for hBN, it is realistic to expect k
Fig. 4. Concern on growing diamond top layer heat spreader on GaN: a) Concern #1 on the protection of front GaN surface by SiNx during the high-temperature PCD
growth process; case study is taken from ref. [53]. b) Concern #2 on the surface quality after etching of NCD/PCD top layer heat spreader for gate contact deposition;
case study is taken from ref. [48]. c) Concern #3 on the process compatibility of growing diamond top layer heat spreader on GaN-on-SiC and GaN-on-sapphire in
terms of delamination; case study is taken from ref. [54].
5
Fig. 5. a) Simplified process steps for fabricating GaN HEMT with 2D materials of hBN/graphene as ‘near-junction top heat spreader’. Concept is taken from a patent
in ref. [56]. b) Example #1: HEMT on GaN-on-SiC with few-layer graphene connected to the drain electrode, with HEMT output characteristic with and without a
few-layer graphene heat spreader. Case study is from ref. [59].
in the range of ~250 Wm− 1 K− 1 [58], and most probably lower after the lateral heat conduction and channeled to the substrate by vertical heat
transfer process. At present date, there is not much literature that can conduction. The heat path in this model is appealing in catering to peak
prove the effectiveness of 2D materials as top layer heat spreaders on a temperature shaving of the 2DEG channel and lowering the overall de
fabricated GaN HEMT. In a peer-reviewed article (year 2012) in ref. vice temperature by the connection of the top layer PCD with the sub
[59], a few-layer graphene quilt connected to drain electrodes is re strate. However, the k value of PCD and the vertical interface of GaN-
ported to help increase the magnitude of drain current. It is proof of the PCD will play a decisive factor in determining the effectiveness of this
alleviated effect of self-heating 2DEG and the results are provided in invention. As mentioned earlier, the low TBR between GaN and PCD can
Fig. 5b. The prototype however is using a mechanically exfoliated gra only be achieved using a thin interlayer, preferably a SiNx layer. For a
phene which is a stack of single-crystalline and pristine graphene layer perspective and comparison, 1 μm-thick PCD on the GaN top layer is
at a relatively small size. These results cannot represent the condition for measured with k of 320 ± 150 Wm− 1 K− 1 [68]. In another article, the
CVD-grown polycrystalline graphene as the k values are now largely measured k value for the 3 μm-thick PCD with an average grain size of 1
different. Additionally, the capping of graphene with a thick dielectric μm is as high as 900 Wm− 1 K− 1 [69]. In another report, a 1.46 μm-thick
layer in the actual completion of the HEMT process will further lower PCD is having a k value of 176–35/+40 Wm− 1 K− 1 and GaN-PCD TBR is
the k value, regardless of using pristine mechanically exfoliated gra 52.8–3.2/+5.1 m2K.GW− 1 [70]. In another report, 1 μm-thick PCD is
phene or CVD-grown graphene. Graphene with a finite electrical con having a k value of 132 + 22/− 21 Wm− 1 K− 1, and GaN-TBR (with 5 nm
ductivity as a consequence of having zero bandgap requires proper SiNx interlayer) is 9.5 + 3.8/− 1.7 m2K.GW− 1 [53].
isolation between source/drain and gate contacts to not short-circuit the The material and design of the top layer heat spreader are not limited
device. Many research articles vouched for the promising heat-spreading to the deposition of diamonds. Zhao et al. in CN108682663A (year
capability of graphene [60–63] and hBN [64–66] for electronics cooling; 2021) disclosed the use of a graphene/BN heat spreader [71]. The GaN
nevertheless, they are not working towards the integration with GaN HEMT is first fabricated on the front surface of GaN epilayers on the
HEMT. substrate, where the substrate can be either SiC, Si, or sapphire. Another
substrate which is either AlN or Al2O3 is deposited with the BN layer,
followed by the graphene layer, and finally ball-soldered to the source/
3.2. Strategy A2: Far-junction heat spreader drain electrodes of the fabricated HEMT on the first substrate. This re
sults in an inverted structure as shown in Fig. 6, which is also known as a
The concept of a ‘far-junction heat spreader’ is the thermally flip-chip packaged structure. The effectiveness of this invention cannot
conductive layer is not deposited during the HEMT fabrication process. be supported by any peer-reviewed article. Perhaps it will be beneficial
Therefore, the heat spreader is not directly on the AlGaN/GaN surface for heat spreading to the top layer if the BN layer is a sufficiently thick
and can be considered far from the self-heating 2DEG layer. Sfez et al. in crystalline cubic BN with k ~ 1600 Wm− 1 K− 1. The second substrate to
WO2021/130716A1 (year 2021) invented a method to fabricate a top be ball-soldered to the GaN HEMT according to this invention is not
layer PCD heat spreader adjacent to the GaN layer [67]. In the article, meant to be the same size as the diced HEMT chip. Nonetheless, the
the wafer is first deposited with a dielectric layer, e.g. SiO2, SiNx, etc., inventor needs to think of a suitable wire bonding and packaging scheme
and later is selectively deposited with a diamond seed layer through a for this top substrate heat spreader effectively connected to the package-
proper lithography process. The PCD is grown on a seeded location at a level heat sink.
temperature of 650 ◦ C or higher. After the process, the remaining
dielectric layer without PCD is etched and complete layers of GaN are 4. Strategy B: Substrate heat spreader
grown on the substrate adjacent to the PCD layer. Although the HEMT
device fabrication is not included in the disclosure, the heat generated in The substrate heat spreader is rear-side thermal management for
the GaN channel will be transferred to the neighboring PCD layer by
6
Fig. 6. Simplified process steps for fabricating GaN HEMT with ‘far-junction top heat spreader’, also known as a flip-chip packaged structure. The fabrication process
can be completed separately before fabricating the top heat spreader component. Concept is taken from a patent in ref. [71].
GaN HEMT, where the idea is to facilitate heat sinking of heat from self- polishing both GaN and PCD wafers, both of them are bonded by ad
heating 2DEG to the underlying package-level heat sinks via the sub hesive benzocyclobutene at a temperature not exceeding 150 ◦ C. The Si
strate. Even though it is considered a ‘far-junction’ approach, this support is removed from the GaN-on-diamond and the device fabrica
approach is less damaging to the 2DEG layer as the process modification tion is completed on the GaN surface. This invention however did not
is done on the rear side. The relatively large volume of substrate (heat detail how many portions of GaN removal along with the substrate
spreader) compared to the previous top layer heat spreader in Strategy A during the polishing after the laser lift-off process. The idea behind this
allows a higher amount of heat to be carried to the package-level heat invention is practical and has already been discussed in several peer-
sinks. This approach can be separated into two types; ‘full substrate reviewed articles. One notable example is, this CN106504988B (year
replacement’ and ‘partial substrate replacement’ and they are elabo 2019) [74] can be read along with an article (year 2013) in ref. [75],
rated on below. Substrate heat spreader by means of direct growth of where GaN is bonded with PCD using a ~ 50 nm-thick adhesion layer. In
GaN on diamond is omitted in this section as it is limited to a very small the article, the AlGaN buffer layer is preferably thinned before the
area [72], and hardly be found as a patented invention. bonding process, and the minimum TBR of 36 ± 12 m2K.GW− 1 between
GaN and PCD is reported with 142 nm-thick Al0.5Ga0.5N remaining
buffer layer under the GaN channel layer.
4.1. Strategy B1: Full substrate replacement The use of an adhesion layer to bond GaN with diamond is impeding
the heat propagation from 2DEG to the substrate heat spreader as
The replacement of low k wafers, e.g. Si (kSi ~ 148 Wm− 1 K− 1) and claimed by many experts. Therefore, another method to form bonding is
sapphire (ksapphire ~ 40 Wm− 1 K− 1) can be done by removal of the wafer by omitting the use of adhesive using the surface-activated bonding
after completing the GaN epitaxy process. For simplicity of discussion, (SAB) technique [76–78]. In brief, SAB is carried out at near room
we can assume that the substrate removal will not significantly change temperature by bombarding Ar atoms to sputter and activate both sur
the mobility and concentration of electrons in the 2DEG layer. This can faces, and later they are pressed together. Ou et al. in CN111540710A
be supported by a peer-reviewed article in ref. [73], where removing of (year 2020) elaborated on the process to obtain a GaN/SiC/metal wafer
Si substrate involves two phases of tensile-strain induced and plastic using the SAB technique [79]. Initially, a monocrystalline SiC wafer is
relaxation phases, which eventually result in negligible changes in final ion-implanted with a hydrogen ion, temporarily bonded to the dielec
in-plane bi-axial strain in AlGaN/GaN heterostructure. The simplified tric/Si wafer (dielectric thickness is up to 5 μm, either SiO2 or SiNx), and
fabrication process for full substrate replacement is illustrated in Fig. 7. SiC separated into two wafers from the embedded defect layer from the
In this approach, the GaN wafer after the removal of the original sub ion implantation. The rough surface of SiC is then planarized to obtain a
strate is then either bonded to a new wafer or deposited with a thick film flat SiC with a thickness of 0.1–2 μm. GaN is grown on SiC/dielectric/Si
of material with a higher k value for an effective substrate heat spreader. wafer and later another bonding of the second dielectric/Si wafer is
applied on the front GaN surface to replace the first dielectric/Si wafer.
4.1.1. Type I: Substrate by wafer bonding The exposed SiC surface is now bonded to the metal substrate using the
Wang in CN106504988B (year 2019) disclosed the method to form SAB technique. Finally, the second dielectric/Si wafer carrier is released
GaN-on-diamond by wafer bonding technique [74]. In the article, to obtain the GaN/SiC/metal wafer. The type of metals are not specific
complete GaN layers are grown on a sapphire substrate, before the and they may comprise Au, Ni, Al, Cu, etc. This invention of
sapphire is removed using a laser lift-off technique. The GaN/sapphire is CN111540710A [79] may slightly suffer from low adhesion of SiC, as a
attached to temporary Si(111) support, and a KrF laser (λ = 248–480 C-rich SiC surface is prone to be formed during the Ar atoms
nm, pulse width 38 ns) is employed to release the GaN layer. After
Fig. 7. Simplified process steps for fabricating complete GaN layers on ‘substrate heat spreader’ either ‘full substrate replacement by wafer bonding’ or ‘full substrate
replacement by deposition’ as indicated in Step 4. Concepts are taken from patents in ref. [74] and ref. [97].
7
bombardment and contributing to the weakened bonding strength and reduces the TBR between GaN and diamond. Both CN109860049B [84]
high TBR. The use of metal substrate to bond with SiC is probably and US10529820B2 [85] however did not provide and claim any value
reducing the side effect of C-rich SiC, thus may lead to a decent value of of TBR.
TBR. From another perspective, the original SiC wafer with k ~ 350 The use of vdW bonding to bond GaN with diamond can be supported
Wm− 1 K− 1 is not much poorer than metals, e.g. Au (kAu ~ 310 Wm− 1 by a peer-reviewed article. In ref. [86], the fabricated HEMT on GaN-on-
K− 1) and Cu (kCu ~ 390 Wm− 1 K− 1), which might not justify the cost of Si is processed for substrate replacement and bonded to PCD and single-
the substrate modification process. crystalline diamond (SCD), as illustrated in Fig. 8. The bonding tem
In the peer-reviewed articles on the SAB technique, GaN is most perature below 300 ◦ C can minimize the thermal stress during the
commonly bonded to the PCD wafer. For this purpose, a thin Si should be bonding and avoid damaging the pre-fabricated HEMT devices on front
deposited on both to-be-bonded GaN and diamond surfaces to improve GaN surface. In this case, the GaN-on-diamond is reported able to
the uniformity of SAB [80]. For example, in ref. [81], GaN is bonded to withstand mechanical stress applied by razor blades and extended
PCD using a ~ 4 nm-thick Si interlayer with a TBR of ~10.9 m2K.GW− 1. thermal stress at 250 ◦ C. In terms of heat spreading, HEMT on GaN-on
In ref. [82], GaN-on-SiC is bonded to the diamond using a thin Ti diamond (both PCD and SCD) demonstrated a higher drain saturation
interlayer. The SiC substrate is thinned down to 50 μm before the SAB current compared to the HEMT on GaN-on-Si. It is supported by the
process and it results in a TBR of 67 m2K.GW− 1 between SiC and dia simulated thermographs in Fig. 8, where 300 μm-thick bonded PCD and
mond. The use of diamond instead of a metal substrate as explained in SCD via vdW are outperforming the heat spreading of GaN-on-Si with a
CN111540710A [79] most probably is a cost-motivated invention, but bulk Cu heat sink.
again, the final heat-spreading performance of the metal substrate Zhang et al. in CN107634104B (year 2021) invented a method to
should be better than the original SiC substrate. In ref. [83], GaN HEMT obtain GaN/metal/substrate but with a different processing method
is directly grown and fabricated on Ag substrate (shown better heat [87]. They grow complete layers of GaN on the unspecified substrate
removal compared to HEMT on sapphire), and it is might be interesting and evaporated the first and second metal layers on the front surface of
for researchers working on the metal substrate heat spreader. GaN. Meanwhile, the third metal layer is evaporated on another sub
Besides bonding using adhesive and SAB techniques, there is a strate preferably with a higher thermal conductivity than the original
disclosure on hot-press bonding. Wu et al. in CN109860049B (year substrate for growing GaN. The surfaces of the second and third metals
2020) employed metal thin film before the bonding of GaN to diamond are bonded (by unspecified bonding technique). Finally, the original
[84]. Initially, complete GaN layers are grown on SiC and completed the substrate for GaN is etched out to release the GaN-metal-substrate. The
HEMT device fabrication process on its front side. The GaN/SiC is metal layer that is now buried, is either Ag/In/Ag, Au/In/Au, or Au/In/
attached to a temporary substrate on the front GaN side to remove the Ag. In our opinion, this invention is good for alleviating heat limitation
SiC using the ion etching technique. The exposed GaN is then polished in GaN HEMT if the second substrate is diamond. However, due to the
and sputtered with a stack of W/Au/W, and metal-coated GaN is hot- flipping of GaN, the exposed GaN surface in the final GaN-metal-
pressed with diamond to form a GaN-metal-diamond structure. They substrate is actually GaN from the buffer/nucleation layer and it is
proposed this method using a metal stack is desirable over SAB since it necessary to re-grown additional GaN and AlGaN for reducing crystal
can provide high flatness and tolerance to high-temperature annealing, defect/dislocation and creating 2DEG layer. The high-temperature
besides improving the heat spreading from GaN HEMT. In another MOCVD on this GaN-metal-substrate most probably will create
disclosure, Chu et al. in US10529820B2 (year 2020) explained the another problem related to the wafer bowing.
technique to obtain a GaN-on-diamond wafer from GaN-on-SiC by hot The concept brought in CN107634104B [87] is quite similar to a
bonding [85]. In the article, complete GaN layers are grown on the SiC peer-reviewed article (year 2020) in ref. [88]. It relies on metal-metal
substrate, completing HEMT device fabrication on the front GaN sur bonding with in-situ Ar+ bombardment and Mo/Au deposition on the
face, before the rear side SiC substrate and AlN nucleation layer are two surfaces to be bonded. In the article, GaN-on-sapphire is bonded to
removed by mechanical polishing. After both GaN and diamond are the Si wafer using Mo/Au interlayer to form Si/interlayer/GaN/sap
polished, they are bonded by the van der Waals (vdW) bond, and later phire. It results in a low bonding defect density of 0.2% and a strong
GaN/diamond is annealed at ~400 ◦ C to convert vdW into an electro/ bonding strength of 10.0 MPa between the Si/GaN interface. This is not
covalent bond. In this case, the complete removal of the highly defective exactly a demonstration for substrate replacement but the same concept
AlN nucleation layer and no adhesive used for wafer bonding will help is applicable for discussion. In another peer-reviewed article (year 2014)
Fig. 8. Thermal solution by full substrate replacement for the substrate heat spreader. Example #2: HEMT on GaN-on-diamond by wafer bonding. Top side is the
simplified fabrication process, while the bottom side is the cross-sectional thermograph for the HEMT on GaN-on-diamond (SCD and PCD) and GaN-on-Si obtained by
simulation. Case study is from ref. [86].
8
in ref. [89], HEMT from GaN-on-sapphire is replaced with GaN-on-metal interlayer is less popular compared to the SiNx. Some examples are for
using the metal-metal bonding technique. The simplified fabrication GaN on PCD substrate are; TBR of 12 m2K.GW− 1 using 28 nm-thick SiNx
process and results are provided in Fig. 9. The use of hBN as a release and 100 μm-thick PCD [91], and TBR of 17.4 ± 3.0 m2K.GW− 1 using 22
layer from sapphire substrate followed by In–Cu bonding enabled the nm-thick SiNx and 100 μm-thick PCD [92]. In other articles where the
reduction of negatively-sloped drain saturation current and device interlayer is not specified but most probably is SiNx, the reported TBR is
temperature, which is proof of reduced 2DEG temperature during the 27 ± 3 m2K.GW− 1 using a 50 nm-thick protection layer [16], and TBR of
self-heating process by the adoption of metal substrate heat spreader. 18 m2K.GW− 1 using ~30 nm interlayer [17]. All of them conclude the
same thing that the interlayer should be thin enough to reduce thermal
4.1.2. Type II: Substrate by thick film deposition resistance for heat propagating from the GaN to the PCD, while it must
The second approach to replace and form a substrate heat spreader is remain a few nanometers thick after the growth of PCD to avoid
by deposition of high k material, with a sufficient thickness to provide damaging GaN and forming a rough GaN/PCD interface. The other layer
mechanical strength for wafer handling. Not to mention, this approach of SiNx has converted into very thin SiC anyways during the growth of
also involves the removal of the original substrate, similar to the pre PCD to enable low TBR between GaN and PCD layer [54].
vious approach of wafer bonding. The new substrate for deposition is not The value of TBR is indeed not only determined by the interlayer, but
limited to and mostly is a thick film of PCD. Cho and Lee in also by the quality of the PCD layer itself. In an independent study of
US10128107B1 (year 2018) described a method to obtain GaN/SiC/PCD PCD, it is shown that PCD film should be thicker than 500 μm and as
wafer [90]. Initially, cubic SiC is formed on a Si wafer by the low- much as ~200 μm should be removed from the nucleation face to par
pressure chemical vapor deposition (LPCVD) technique. The SiC is with the quality of monocrystalline diamond (k > 2000 Wm− 1 K− 1)
then carbonized to deposit PCD (either seed or seedless), and the PCD is [38]. The PCD grown by hot filament chemical vapor deposition
polished to be deposited with the second layer of SiC. This second layer (HFCVD) is commonly opaque with k ~ 620 Wm− 1 K− 1, while PCD
of SiC is used to grow GaN and the device fabrication is completed first grown by MWCVD is translucent with k ~ 1500 Wm− 1 K− 1 [91]. The
on GaN/SiC/PCD/SiC/Si wafer. Finally, the substrate SiC/Si is removed. quality of PCD by CVD (either by MWCVD, HFCVD, etc.) is also deter
The SiC interlayer between GaN and PCD plays an important role in mined by the content of 12C and 13C, as emphasized in US9214407B2
determining the practicality of this method. It should be thin enough to (year 2015) [93]. In the disclosure, PCD with 13C content of less than a
minimize thermal resistance from GaN to PCD but need to be thick natural isotopic abundance of 1.1% is regarded as a high-quality syn
enough to mitigate lattice mismatch for the successful growth of GaN. thetic diamond and should be deposited close to the HEMT hotspot (self-
The thicknesses of both SiC interlayer and PCD however are not speci heating 2DEG) with a distance not further than 3 μm. The quoted k of
fied. If the SiC is crystalline, the interface of GaN/SiC/PCD will be better this high-quality PCD is within 400–3000 Wm− 1 K− 1, depending on its
compared to the interface of GaN/PCD. This is proven in a peer- thickness. Another similar patent is by Gu et al. in US9337278B1 (year
reviewed article (year 2020) in ref. [37], where TBR for GaN/SiC/PCD 2016), where they generally mention ‘thermoconductive layer’ should
and GaN/PCD in their work is measured at 30 ± 5 m2K.GW− 1 and 107 be within 1 μm distance from the GaN channel (self-heating 2DEG) for
± 44 m2K.GW− 1, respectively. effective heat spreading [94]. In the disclosure, this layer can be either
The survey of peer-reviewed articles shows that the use of SiC diamond, boron nitride, graphene, graphite, or cubic boron arsenide
Fig. 9. Thermal solution by full substrate replacement for the substrate heat spreader. Example #3: HEMT on GaN-on-metal by metal substrate bonding. Top side is
the simplified fabrication process, while the bottom side is the HEMT output characteristic and thermograph of the HEMT on GaN-on-metal and GaN-on-sapphire.
Case study is taken from ref. [89].
9
with k at least 500 Wm− 1 K− 1. deposited again with another thin protection layer, e.g. SiNx, AlN, SiC,
The substrate replacement by deposition is not limited to a specific etc. with a thickness of <50 nm. The second diamond layer with a
substrate, as long as the substrate can provide a suitable crystal orien similar thickness of 100–300 μm is deposited at a temperature range of
tation for GaN epitaxy. In CN107731903A (year 2018), it is said the 700–800 ◦ C. In this case, the first diamond layer alleviates GaN defor
process can be done using Si-on-insulator (SOI) substrate [95]. The main mation and cracking during the deposition of the second diamond layer.
idea is to grow 150 μm-thick PCD on the Si surface of SOI, depositing 50 Finally, the first diamond film is peeled off to obtain a GaN-on-diamond
μm-thick Si on the PCD, and removing the SiO2/Si layer under the Si to wafer. This method, even being costly, is believed can provide a sig
obtain Si/PCD/Si wafer. Complete GaN layers are grown on Si/PCD/Si nificant heat spreader performance if the first diamond layer is also
wafer and the HEMT device fabrication is completed on the GaN front utilized as a heat spreader. Even though the HEMT device fabrication
surface. Finally, the rear Si is removed using potassium hydroxide wet steps are not included in the article, a person having ordinary skill in the
etching. One of the main issues in this invention is whether a complete art might use the existing first diamond layer for the front-side heat
GaN layer can be grown on Si, which is most likely a poly or amorphous spreader with a suitable patterning and etching process.
Si layer after being deposited on the PCD layer. This concern is not The invention of a GaN-on-diamond wafer either from an original
addressed by the inventor in CN107731903A [95]. In a peer-reviewed substrate of Si, SiC, or sapphire might be further improved by combining
article (year 2022), SOI is used as an initial substrate to form a GaN- with a method disclosed by Francis et al. in WO2022/140575A1 (year
on-diamond wafer [96]. The simplified fabrication process and sup 2022) [98]. In the article, interlocking diamond and substrate can be
porting data are provided in Fig. 10. The scheme is all about growing achieved by substrate patterning and double seeding of NCD between
PCD on SOI, removing the underlying SiO2/Si, flipping the wafer, and the thin interlayer, e.g. SiNx. Increasing the contact area by this
growing complete layers of GaN on the Si surface as in a conventional approach is claimed effectively reduces the TBR between diamond and
recipe. This is more practical, but preferably a temporary carrier is used substrate, down to the value of 1–12 m2K.GW− 1. A similar concept of
to provide mechanical strength for the wafer during handling since the utilizing a larger contact area for reducing TBR also appeared in
thickness Si and PCD are just 410 nm and 150 μm, respectively during CN111785610A (year 2020) [99] and WO2022/041674A1 (year 2022)
the removal of the underlying SiO2/Si substrate. Since there is no pro [100], whereas the thermally conductive layer, e.g. diamond, AlN, etc. is
tection layer, e.g. SiNx, the single-crystalline Si is directly in the junction deposited on patterned GaN channel/buffer layer. This concept/claims
(atom-by-atom) with PCD. The maximum device temperature of the however are not in an agreement with reported data by a peer-reviewed
device on GaN/Si/PCD is found lower compared to the GaN/SiC coun article (year 2019) in ref. [101], where the textured interface is said to
terpart, suggesting an effective heat spreading in the PCD substrate even cost the value of TBR. In the article, the textured interface will
though there is an embedded Si layer with a relatively low k before the contribute to the toughness of GaN-on-diamond and there should be an
heat reaches the PCD layer. optimum point between the tradeoff in TBR and toughness by suitable
Wei et al. in WO2020/098258A1 (year 2020) proposed the deposi engineering of the GaN/diamond interface. At this point, more experi
tion of a diamond as a temporary carrier for the actual deposition of the mental works are necessary to prove the advantages and disadvantages
diamond as a substrate heat spreader [97]. Initially, complete GaN of the textured interface in terms of heat flow and other related aspects.
layers are grown on a substrate, e.g. Si, SiC, or sapphire. A protection It is worth to discuss on the last patent on substrate replacement by
layer with a thickness of 1–3 μm is deposited onto the GaN surface, deposition using a quite peculiar process. Lee in KR102273305B1 (year
where it may be either Si, Ti, W, Mo, SiO2, TiC, or a combination thereof. 2021) disclosed a method to obtain GaN-on-diamond wafer by uncon
The first diamond layer is deposited onto the protection layer with a ventional way of utilizing rear side GaN [102]. In the article, complete
thickness of 100–300 μm at the temperature range of 600–800 ◦ C using GaN layers are first grown on a SiC wafer, including an additional AlN
the CVD method, e.g. HFCVD, MWCVD, etc. The substrate is then protection layer on the outer front surface. Then, the SiC substrate is
removed using chemical etching or laser lift-off technique, and thinned by laser irradiation (pulsed laser beam, λ ~ 1064 nm) from the
Fig. 10. Thermal solution by full substrate replacement for the substrate heat spreader. Example #4: HEMT on GaN-on-diamond by thick film deposition. Top side is
the simplified fabrication process, while the bottom side is the transmission electron microscopy image of the Si-PCD interface. Next are thermographs of gateless
devices on GaN-on-diamond (with Si interlayer) and GaN-on-SiC. Case study is from ref. [96].
10
rear side of SiC to form embedded amorphous Si in close vicinity to SiC the rear side to pattern the opening on the substrate, and it is selectively
and GaN interface. PCD is grown on the front side AlN with a thickness etched until the AlN nucleation layer forms vias. A diamond seed layer is
preferably > 350 μm. During the high-temperature growth of PCD, the dispersed on the rear side and the PCD is subsequently grown at a suf
embedded amorphous Si soft layer in SiC minimizes wafer bow and ficient thickness to form a continuous PCD layer and PCD-filled vias.
crack, as it disperses the external stress applied to the substrate. In the They suggest the PCD can be deposited as a graded quality, where high
following, the embedded amorphous Si layer is removed along with a thermal conductivity PCD is deposited first and then slowly reducing the
major portion of the SiC substrate, and finally, the remaining SiC quality of the PCD during the growth process over time. The rear side of
attached to the GaN buffer layer is removed by dry etching. The PCD can be polished to provide better thermal contact to the packaging.
disclosure, however, did not address how the crystal quality of GaN can On the front side of GaN, the device is fabricated after the PCD depo
be fixed, as now the front surface is a GaN buffer layer instead of a sition process. The invention can be improved further if the etching is
relaxed GaN layer as in a conventional method. In the most possible deepened with the removal of the AlN nucleation layer and some portion
situation, there is a need for an additional MOCVD process to grow (if not all) thickness of the AlGaN buffer layer (if any). The AlN nucle
AlGaN/GaN, but the issue of wafer bow and crack will resurface and ation layer is having a high defect density (atomic vacancy density >
devalue the present invention. 1021 cm− 3) [104–106], with a low kAlN typically below 25 Wm− 1 K− 1
[107]. Therefore, it is not required to have a parasitic heat-impeding
4.2. Strategy B2: Partial substrate replacement layer between the GaN and PCD substrate heat spreader.
Hobart et al. in US2014/0264777A1 (year 2014) [108] and
The previous Strategy B1 deals with the complete removal of the US9196703B2 (year 2015) [109] suggest the diamond should only fill
substrate, while this Strategy B2 deals with the partial removal of the the vias, whereas the remaining area on the rear substrate should be free
substrate with a proper pattern transfer before the etching process. This of the diamond. This is can be regarded as an improvement for the
approach has advantages and disadvantages compared to the complete previous US8575657B2 [103] discussed above. The article uses NCD
removal of the substrate. When some parts of the original substrate are and PCD, respectively to fill the selectively etched substrate through
kept, it can contribute to the mechanical strength of the wafer (including selective growth on seeded vias. It is said the removal of the excess layer
GaN epilayer), reduce the negative effect of CTE mismatch, and reduce of the diamond from the via can help prevent wafer bowing and po
the amount of high k material to be deposited onto the etched substrate. tential wafer breakage due to the large CTE mismatch between the
Both can be translated into a more reliable and cost-saving process. The diamond and GaN/substrate. Other notable articles that support the
etched substrate is often referred to as via, trench, or others as claimed removal of the diamond layer to obtain only diamond-filled via under
by the inventors. In this section, we will use the term via and trench GaN HEMT are CN110379782A (year 2019) [110] and US2021/
interchangeably referring to the etched feature on the substrate. Fig. 11a 0320045A1 (year 2021) [111]. While the concept is the same, the in
shows the simplified fabrication process for the ‘partial substrate ventors are found not in agreement on where the etch stop of the via(s).
replacement’ approach. This approach can be further separated into four In US2014/0264777A1 [108] and CN110379782A [110], via ended in
types; ‘via under HEMT’, ‘via not specific under HEMT’, ‘via under the substrate at a distance of a few to tens of microns reaching the GaN
HEMT source and/or gate electrode’, and ‘via beside HEMT’, as illus buffer layer. In US9196703B2 [109] and US2021/0320045A1 [111], via
trated in Fig. 11b. ended until the surface of GaN buffer/nucleation layer.
4.2.1. Type I: Via under HEMT 4.2.2. Type II: Via not specific under HEMT
The first type is etched via from the substrate at a position directly The second type is forming via within the substrate, but not directly
under the HEMT structure on the GaN front surface. Gambin et al. in (or later unintentionally positioned) under HEMT. The concept of ‘via
US8575657B2 (year 2013) disclosed the method to form diamond vias not specific under HEMT’ can be understood as a simpler method
in the substrate [103]. Complete GaN layers are initially grown on a compared to the previous ‘via under HEMT’, as there is no need for
substrate that is either sapphire, Si, SiC, etc. The wafer is then flipped to precise alignment between the front and rear surface during the
Fig. 11. Substrate heat spreader by ‘partial substrate replacement’ approach: a) simplified process steps for fabricating complete GaN layers with thermal via, b) four
types of thermal via. Concepts are taken from patents discussed in Strategy B2.
11
lithography and the sequenced processing. Dai et al. in CN109742026A to fill the groove. They suggest a complete HEMT is fabricated first on
(year 2019) [112] and US11139176B2 (year 2021) [113] disclosed on the GaN front surface as the ‘HEMT first’ process before the substrate
PCD-filled via in SiC substrate, where the via etch stop is within the modification, but a person having ordinary skill in the art might opt for
substrate. One can easily notice the similarity of this concept with the the ‘HEMT last’ process.
previous inventions discussed in ‘via under HEMT’. The anticipated k In a peer-reviewed article (year 2019) in ref. [122], the trench under
values of PCD in the vias are within 1000–1400 Wm− 1 K− 1. The opening the HEMT is filled by Cu. Fig. 12 shows the simplified fabrication steps
of via can be in a large dimension, for example with a diameter of 0.5 for the HEMT with a Cu-filled trench in Si substrate, supported by the
mm, and arranged in a periodic array across the wafer [114]. From reduction of the negatively-sloped saturation drain current. The higher
another perspective, when via is not necessarily aligned under the magnitudes of the drain current and its saturation point are the in
HEMT, this process can be done first on the bare substrate before dicators for the improved heat dissipation from the self-heating 2DEG.
growing the GaN layer. A wafer supplier can process the substrate with The lowered maximum channel temperature also avoids physical
diamond-filled vias, complete with both planarized front and rear sur degradation, i.e. the burning of the device under high-power operation.
faces, before passing to the second manufacturer who specialized in Even though there is proof for the improved heat dissipation, the BV of
growing GaN on the substrate. This business model is adopted by Qro GaN HEMT most likely be greatly reduced since the Cu-filled via is more
mis, Inc., where they are supplying an engineered substrate of QST™ for electrically conductive compared to the original Si substrate. Another
the GaN epitaxy process [115–117]. concept/design of Cu-filled via proposed by simulation also are regu
Zhou et al. in CN105140122B (year 2018) elaborated on the method larly reported [123–125], but not accompanied by the potential dete
to obtain GaN on a modified substrate containing AlN and Au [118]. It rioration in BV from the actual fabricated device.
starts with laser etching of substrate (either Si or sapphire) to form a Viswanathan et al. in US9362198B2 (year 2016) elaborated the
deep hole with a depth-to-width ratio of <3:1. Then, AlN is sputter over method to fabricate a second type of via under and connected to the
to fill the holes with a sufficient thickness forming a complete coverage source electrode [126]. A complete GaN epitaxy on a substrate, e.g. SiC
on the front surface (excess thickness of 30–100 μm from the hole), with ‘HEMT first’ processing and a front surface with an insulator heat
annealed, and planarized. GaN is grown on flat AlN and completed the spreader is used to demonstrate the substrate modification process.
device fabrication process on its front side. The front GaN surface is Simply put, the substrate is patterned and selectively etched under the
temporarily bonded to a sapphire carrier to grind the backside substrate source electrode, until reaching the source electrode itself. The via and
until the bottom hole-filled AlN is exposed. Finally, Au is electroplated the rear surface of the substrate are deposited with thermally conductive
on the rear side at a thickness within 1–20 μm and the sapphire carrier is but electrically insulating materials, e.g. diamond, SiC, BN, or even a
detached from the GaN front surface. We believe this method although mixture with metals, e.g. Au, Ag, Al, or Cu. This material should have a k
involving many fabrication steps and is quite costly; may not be as value > 200 Wm− 1 K− 1, and TBR < 30 m2K.GW− 1 with the recessed
effective a solution as it is intended to be. This is because there is no surface as claimed by the inventors. In another similar article of
proof that AlN (which is in this case sputter-deposited AlN most likely a US2017/0294528A1 (year 2017) [127], this via is intended filled with
poly or nanocrystalline AlN) will have a high k value. In a peer-reviewed an electrically conductive metal, e.g. electroplated Au or Cu to provide
article (year 2019) in ref. [119], a trench of Si deposited with AlN/Cu backside source grounding. Another via can be made under the gate
(15/2 μm thick) double layers. The temperature of the front side GaN electrode with etch stop at the GaN buffer layer, also filled with metal for
HEMT metal gate is found higher compared to the device without etched the near hotspot heat dissipation and at the same time can be used as a
Si and concluded there is a high thermal spreading resistance within the back gate to improve front gate modulation. This approach can be
first few micrometers of the AlN/Cu device. Thus, the inventor needs to classified as the third type of via under source and gate electrode.
revisit the use of AlN and find the other proper material with a proven
high k value. 4.2.4. Type IV: Via beside HEMT
There are also some unconventional ways to fabricate via under the The last type of ‘via beside HEMT’, as its name suggests, is a thermal
GaN layer other than the rear side etching of the substrate. For example, solution by placing a substrate heat spreader adjacent to the HEMT. This
Maples and Ewing in US2017/0170094A1 (year 2017) proposed the approach is not popular but there is an invention elaborating on this
front side etching of GaN to form via [120]. After the deposition of the method. Lee in US2021/0249379A1 (year 2021) disclosed the step to
diamond in the via, the nucleation buffer layer can be deposited again on obtain GaN-on-diamond wafer with ‘via beside HEMT’ using sequences
the diamond via to grow another GaN layer for device fabrication on the of deposition process [128]. At first, complete GaN layers are grown on
front surface. This method, although it sounds simple, is actually not the Si wafer, including a protection layer, e.g. SiNx, AlN, etc. on the
easy to achieve with a high yield. Special attention is needed on re- outer front surface. This protective layer is later bonded to the Si carrier
growing the GaN layer on the diamond, especially on obtaining a suf wafer with a glass bonding interlayer. Later on, the rear Si substrate is
ficiently low defect and relaxed GaN layer (and strained AlGaN barrier removed. The AlN nucleation layer is removed along the Si substrate to
layer) for acceptable performance of HEMT. expose the GaN layer. They deposit an intermediate layer which may
comprise dielectric, e.g. SiN, and diamond seed layer onto the GaN front
4.2.3. Type III: Via under HEMT source and/or gate electrode surface for growing PCD. The PCD is polished to obtain a flat surface and
The third idea of ‘via under HEMT source and/or gate electrode’ is to the Si carrier is removed to obtain a GaN-on-diamond wafer. This GaN-
minimize the etching and deposition of a thermally conductive layer on-diamond wafer once again bonded to the temporary carrier of the Si/
within the substrate, without sacrificing more on heat dissipation per diamond wafer. The Front GaN surface is regrown with AlGaN/GaN and
formance of GaN HEMT compared to ‘via under HEMT’. This technique device fabrication is completed on the front surface. The front metal
can be further distinguished into at least three forms: 1) via under the layer after device fabrication is drilled with holes, extending down to the
gate electrode, 2) via under and connected to the source electrode, and bonded Si carrier. Later on, the Si carrier is removed to obtain a GaN-on-
3) a combination of both. One of the examples of the first form of via diamond wafer with fabricated devices and thru holes. The thru-holes
under the gate electrode can refer to an invention by Kotani and are finally coated with a metal layer, e.g. by Au plating technique or
Nakamura in US10242936B2 (year 2019) [121]. In the article, the rear others. This process is possible but quite sophisticated. It might be
side of the substrate is patterned and etched to obtain a truncated effective for heat removal from self-heating 2DEG even though it is not
groove, by removing materials up to some portion of the GaN channel physically close to it as this thermal via is not adjacent to every 2DEG
layer. Next, the intermediate layer of material containing any of SiC, channel.
AIC, SiCN, and CN is deposited in the groove. The heat dissipation layer
of either diamond, carbon nanotube, graphene, or NCD is then deposited
12
Fig. 12. Thermal solution by partial substrate replacement for the heat spreader. Example #5: GaN HEMT on Cu-filled trench, which is classified as ‘via under
HEMT’. Top side is the simplified fabrication process, while the bottom side is the device top/cross-sectional view, output characteristic, and thermograph of HEMT
with/without Cu-filled trench. Case study is from ref. [122].
5. Strategy C: Buried heat spreader multilayer (1–20 layers) graphene on the metal catalytic layer [135].
The idea delivered in this disclosure is basically the same in
The concept of a ‘Strategy C: Buried heat spreader’ is this thermally CN107170673A [129], except the final metal-filled via from the source
conductive material is sandwiched between two materials, which is electrode is now extended to reach both multilayer graphene and metal
most of the time positioned in between the substrate and GaN epilayer. catalytic layer as the embedded heat spreaders. Fig. 13 shows the
This is still categorized in the substrate heat spreader approach, except it simplified fabrication process for the ‘buried heat spreader’ approach.
is different from the family members discussed in Strategy B by not The catalytic metal for growing multilayer graphene, although not
involving substrate removal. Since the substrate remains, we can expect specified, is most probably Ni thin film [136]. If it is Ni with a sufficient
only a marginal improvement (if not none) in the ultimate heat- thickness to be considered bulk, the kNi is still only ~73 Wm− 1 K− 1. As
spreading performance of GaN HEMT. Therefore, the count of the in the thickness of polycrystalline multilayer graphene increases, the kgra
vention related to the ‘buried heat spreader’ is less available compared phene also will further decrease [134]. Considering both factors, we
to the invention in Strategy A and Strategy B. believe this process cannot justify its cost as the heat-spreading perfor
Yuan et al. in CN107170673A (year 2017) proposed the use of mance of embedded graphene is questionable.
embedded monolayer graphene as a heat spreader [129]. In the article, Zhao et al. in CN108389903A (year 2021) disclosed the method to
graphene is first deposited onto AlN/substrate and another AlN as form an embedded graphene heat spreader between GaN and SiC sub
nucleation layer is deposited onto the graphene/AlN/substrate. Gra strate [137]. The main idea of this invention is to grow 2 nm-thick
phene is grown beforehand on catalytic metal according to the well- graphene (multilayer graphene) on a SiC wafer, and later grow the AlN
established method [130–132] and transferred onto AlN. This makes nucleation layer and complete GaN epilayers for HEMT. Finally, HEMT
sense as the high-quality and defect-free graphene cannot be epitaxially device fabrication is completed on the front GaN surface and there is no
grown on AlN. A complete GaN layer is then grown conventionally on thermal via formed to contact the embedded graphene. They claimed
buried graphene in two AlN layers, and HEMT device fabrication is the TBR between SiC and graphene is 120 m2K.GW− 1, while the TBR
completed on the front GaN surface. The hole is etched on the front side between graphene and AlN nucleation layer is also 120 m2K.GW− 1. In
of GaN beside the source electrode until the embedded graphene layer. ventors provide the anticipated performance improvement and transfer
Finally, this hole is filled with metal to thermally connect the source characteristic of HEMT by simulation, where the kgraphene is assumed at
electrode with graphene. Even though the inventors are expecting k up 2000 Wm− 1 K− 1. In terms of processing, it is somewhat possible to
to 5300 Wm− 1 K− 1 for monolayer graphene, this expectation should be directly grow the AlN nucleation layer and an acceptable quality of GaN
lowered since this value is only measured (with large uncertainty) for layers on graphene. This is one of the active research activities, where
pristine monocrystalline graphene suspended in the air [133]. In many peer-reviewed articles have been discussing the quality of
another peer-reviewed article (year 2010) in ref. [134], encapsulated MOCVD-grown III-nitrides on 2D materials [138–140]. The key is; gra
graphene by two SiO2 layers reduced the kgraphene down to only ~160 phene needs to be defective, either by additional short O2 plasma
Wm− 1 K− 1 due to the phonon boundary and disorder scattering. treatment or be readily grown as a defective multilayer. These defect
In another similar document of CN107170674A (year 2017), Yuan points will act as nucleation initiation points for growing AlN. In this
et al. deposit a metal catalytic layer on AlN/substrate, and later grow the invention, the same graphene is intended to be functioning as a ‘buried
13
Fig. 13. Simplified process steps for fabricating GaN HEMT with ‘buried heat spreader’. In some inventions, shorting the embedded heat spreader layer to the
thermal via and package-level heat sink (bypassing the substrate) are optional. Concept is taken from a patent in ref. [135].
heat spreader’. It would be not as efficient as they think as defective as a ‘gate after diamond’ process. Thicker PCD_0 is preferable as it re
graphene most possibly cannot meet their expectation of kgraphene ~ sults in lower gate temperature, and the major heat dissipations are
2000 Wm− 1 K− 1. contributed by the rear side PCD_2 and PCD_1. The process proposed in
this disclosure involves ‘Strategy A1: Near-junction heat spreader’ and
6. Strategy D: Buried GaN in heat spreader ‘Strategy B1: Full substrate replacement’. This invention can be read
along with the previously discussed patents of US8039301B2 [41],
The last kind of invention is known as ‘buried GaN in heat spreader’, CN106504988B [74], and WO2020/098258A1 [97]. One could imagine
where the self-heating of the 2DEG layer is by design to be reduced by this invention to obtain a ‘buried GaN in heat spreader’ will consume the
the top, bottom, and adjacent (if any) layer of heat spreading materials. largest fabrication cost to achieve the maximum heat dissipation from
The number of inventions related to the ‘buried GaN in heat spreader’ is the self-heating 2DEG. The actual performance of this approach however
least available compared to the invention in Strategies A, B, and C. cannot be validated by any peer-reviewed article, most probably due to
Korenstein et al. in WO2010/075124A1 (year 2010) disclosed steps to the high cost defeating the motivation of the chip-level thermal solution.
obtain diamond/GaN/diamond wafer using deposition and wafer Kub et al. in US9685513B2 (year 2017) explained the method to
bonding processes [141]. Even though this invention is discussed later in form embedded GaN in diamond using a series of deposition processes
this article, it is actually filed earlier in 2008 and granted in 2011, thus [142]. Fig. 14 shows the simplified fabrication process for the ‘buried
superseding many inventions discussed in Strategies A, B, and C. The GaN in heat spreader’ approach. Initially, complete GaN layers are
method of obtaining diamond/GaN/diamond wafer started with com grown on a substrate, including an outer SiNx passivation layer. This
plete growth of GaN epilayers on the substrate, e.g. Si, SiC, or sapphire, wafer is then temporarily bonded to the carrier wafer and the rear side
followed up with deposition of diamond (PCD_0) on the front GaN sur materials are removed until exposing the GaN channel layer. The pattern
face, and removal of the substrate to obtain PCD_0/GaN. The second is applied and selective etching at opened window GaN is carried out to
substrate, e.g. Si is deposited with ~25 μm-thick diamond by HFCVD form GaN trench isolation. The first diamond layer is deposited on the
(PCD_1), followed by 50–100 μm-thick diamond (PCD_2) by MWCVD. trenched GaN rear side. In the following, the temporary wafer carrier at
The PCD_2 is having larger k value (k > 1500 Wm− 1 K− 1) compared with the GaN front surface is released, and the HEMT device is partially
PCD_1 (k within 800–1000 Wm− 1 K− 1). Finally, the PCD_0/GaN is completed up to ohmic source/drain contact metallization. The second
bonded to the PCD_2/PCD_1/Si, removing the Si, and obtaining the diamond layer is deposited onto the GaN front surface using either the
PCD_0/GaN/PCD_2/PCD_1 wafer. ‘gate before diamond’ or ‘gate after diamond’ approach. Using this
Still discussing on WO2010/075124A1 [141], the HEMT device is technique, the first and second layer diamond is connected at the trench
fabricated by patterning and selective removal of PCD_0 for depositing and leaving the GaN active device area isolated, which is in a similar
source/drain and T-gate contacts, where this approach can be classified concept of device isolation using field oxide in the Si CMOS process. The
Fig. 14. Simplified process steps for fabricating GaN HEMT with ‘buried GaN in heat spreader’ with an example of using diamond. Concept is taken from a patent in
ref. [142], combined with the concept of ‘gate after diamond’ and ‘gate before diamond’ from patents in ref. [41] and ref. [50].
14
process proposed in this US9685513B2 [142] is kind of inversed with The concepts and inventions related to this topic are summarized into
the one in WO2021/130716A1 [67] which is classified under ‘Strategy four strategies and they are critically discussed in this article. Table 2
A2: Far-junction heat spreader’. Even if it is inversed, the concern on the provides the analysis and summary of Strategies A – D in terms of
vertical interface of GaN-PCD as discussed with WO2021/130716A1 strength, weakness, opportunity, and threat. We believe the invention of
[67] is still valid, and most probably the key determining the heat Strategies A and B will be actively developed in the near future as they
spreading performance of this present invention of US9685513B2 [142]. are progressing towards an ideal solution for chip-level thermal man
Another non-conventional thermal solution employing the concept agement. At present, the diamond remains a dominant choice for both
of buried GaN in a heat spreader is an invention in CN108376705A (year Strategies A and B due to high kdiamond, maintaining (and even
2020) [143]. In the article, complete GaN layers are grown on a sub improving) the BV, and not short-circuiting the device. As the cost of
strate, e.g. Si, SiC, sapphire, and the HEMT device fabrication is diamond wafers and the cost of growing thick PCD are both high, we can
completed on the front GaN surface. The GaN/substrate after device see some of the R&D works are moving towards the direction of adopting
fabrication is inverted to deposit the graphene layer on the rear side of alternative cost-friendly materials, e.g. metals, 2D materials, and other
the substrate, creating an inverted structure of graphene/substrate/ high k composites. This is often paired with certain designs, e.g. via,
GaN/HEMT. The secondary substrate of diamond-like carbon (DLC) embedded structure, etc. It should be emphasized that the chip-level
deposited on AlN or Al2O3 substrate is ball-soldered using Au–Sn to the thermal management must not greatly affect the key indicators of GaN
metalized part of HEMT, creating a flip-chip packaged structure as HEMT performance, e.g. BV, gate leakage current, static/dynamic on-
shown in Fig. 6. This invention is much similar to the previously dis resistance, etc. Therefore, the discussion on the topic of ‘thermal man
cussed CN108682663A [71] in ‘Strategy A2: Far-junction heat agement’ in this article, although separated in the previous Table 1,
spreader’, except in here we classified it as a ‘Strategy D: Buried GaN in needs to be read closely with other review articles discussing the
heat spreader’ since there is graphene on the rear side of the first sub ‘manufacturing and processing’ and ‘device architecture’.
strate which is claimed effectively contributed to the improved heat Table 3 shows the summary and evaluation of the key inventions
dissipation. The use of DLC as a heat spreader most probably will related to chip-level thermal management in GaN HEMT. The strategies
contribute to mediocre heat spreading as the kDLC is not that great, only are further divided into each sub-strategies as they have been discussed
up to 10 Wm− 1 K− 1 as quoted in many peer-reviewed articles in the previous Sections 3–6. We provide four evaluation categories and
[144–146]. It is an amorphous carbon layer with a mixture of carbon sp2 five indicator levels to suggest the quality of the proposed inventions in
(graphite) and sp3 (diamond), where the increasing ratio of sp3/sp2 will terms of addressing the issue of chip-level thermal management in GaN
contribute towards the characteristic of the diamond. It is in a lower- HEMT. The rating is subjective based on the disclosed information in
class heat spreader compared to the NCD and PCD, thus we cannot each patent, i.e. concept, measured data, simulation, etc., which have
verify the effectiveness of this invention. been brought together with available proof from the peer-reviewed ar
ticles. In addition, we believe the topic of heat dissipation performance
7. Summary and conclusion from GaN HEMT still lacks a universal and fair point of comparison. The
future R&D works on chip-level thermal management for DC and RF
The chip-level thermal management in GaN HEMT is mainly on heat power devices, not limited to GaN HEMT, should provide a universal
spreading of self-heating 2DEG to shave down the hotspot temperature. and fair point of comparison to gauge the effectiveness of the proposed
Table 2
Analysis of available strategies on chip-level thermal management in GaN HEMT based on the published patents and peer-reviewed articles. The summary is provided
in terms of strength, weakness, opportunity, and threat.
Strategy Strength Weakness Opportunity Threat
A • Nearest to the self-heating • The deposition of the heat spreader • Explore more choices others than diamonds • Availability of the process
2DEG on AlGaN/GaN requires the (NCD and PCD) • Compatibility of material with GaN
• Specific to diamond, its optimization of a protection layer • The conventional heat sinking to the rear side • New or potential reliability issues
performance is proven to • Specific to diamond; the growth rate package-level heat sink can be revisited for with HEMT operation
be effective is slow and costly sinking at both sides of the chip (double
• Can be integrated along • Need a sufficiently thick layer on top sinking)
during the HEMT of AlGaN/GaN to be effective • If using an insulator heat spreader, may revisit
fabrication steps • The TBR with AlGaN/GaN is architecture to replace all/some components,
critically affecting the heat transfer e.g. gate dielectric, passivation
B • More effective than • Heat needs to travel low k GaN layers • Explore more choices others than diamonds • If using a metal substrate heat
Strategy A to the substrate (PCD and SCD) spreader, foreseen reduction in BV
• Not damaging to the front • More complicated process and more • Specific to via; there are rooms to optimize the • New or potential reliability issues
side AlGaN/GaN costly than Strategy A position, shape, and material in the via with HEMT operation
• Can be integrated into • Specific to wafer bonding; CTE • If using metal via, reduction in BV may be
HEMT mismatch will cause problems in the avoided if using via not directly under HEMT
• May be supplied as an next high-temperature processes
engineered substrate
• Metal can serve an
electrical function
C • Simplest strategy in terms • Not enough proof of its effectiveness, • If 2D materials have later proven effective, this • Growing GaN on a heat spreader
of process integration may not justify the efforts strategy will open more doors for future may require slight tuning in the
• Not damaging to the front • If too thin, the embedded film will exploration recipe of the nucleation layer
side AlGaN/GaN and 2DEG have a low k value compared to the • TBR of embedded heat spreader with GaN and • If using embedded metal, foreseen
layer bulk substrate should be studied reduction in BV
• Specific to graphene, k is
overestimated
D • Combine the effectiveness • May offer the best effectiveness but • Explore more choices others than diamonds • More concern during the GaN
of Strategies A and B no real proves (PCD and SCD) fabrication and process integration
• The large volume heat • Likely a most complicated process • The heat spreading to the side direction may to maintain yield
spreader may act as a chip- and most costly contribute to better performance • Excessive cost may defeat the
level heat sink purpose
15
Table 3
Summary and evaluation of the patent related to the chip-level thermal management in GaN HEMT. Evaluation categories: PL = practical level, EL = effectiveness
level, SL = sophistication level, and CL = cost level. Indicator for evaluation: 1= very poor, 2= poor, 3= neutral, 4 = good, and 5= very good.
Strategy Patent no. Main idea and remark PL EL SL CL Ref.
A1 US8039301B2 NCD deposition before Schottky gate 4 3 3 3 [41]

A1 US10002958B2 PCD deposition after 4 3.5 3 3 [50]
TiNx Schottky gate
A1 + D US2014/0353722A1 Graphene on GaN, hBN under the recessed gate 1 1.5 4 4 [56]
A2 WO2021/130716A1 PCD adjacent to GaN, lateral heat sinking 2.5 3 3 2 [67]
A2 CN108682663A Front side HEMT ball-soldered to graphene/BN 2 2 3 3 [71]
B1I CN106504988B Remove substrate, bond GaN to PCD before HEMT 4 3.5 3 3 [74]
B1I CN111540710A GaN/SiC-on-metal structure; Au, Ni, Cu, etc. 1.5 3.5 2 2.5 [79]
B1I CN109860049B W/Au/W as an interlayer to bond GaN with diamond 4 4 2.5 2 [84]
B1I US10529820B2 Remove substrate, bond GaN to PCD after HEMT 3.5 4 2.5 2.5 [85]
B1I CN107634104B Buried tripe metal layers of Ag, In, Au; bond to metal 2 3 2 2 [87]
B1II US10128107B1 GaN on SiC/PCD/SiC/Si, remove SiC/Si after HEMT 3.5 3.5 2.5 2.5 [90]
B1II US9214407B2 High and lower-quality PCD double layers 3.5 3.5 3 3.5 [93]
B1II US9337278B1 Thermal conductor within 1 μm from GaN channel 3 3 3.5 3.5 [94]
B1II CN107731903A PCD grown on SOI, remove SiO2, grown GaN on Si 1 3 2.5 2 [95]
B1II WO2020/098258A1 Temporary top side PCD for final bottom side PCD 3.5 3.5 2 1 [97]
B1II CN111785610A Groove to increase the contact area between GaN and PCD 2.5 3 2.5 2.5 [99]
B1II WO2022/041674A1 Patterned AlN for larger contact area 2.5 3 2.5 2.5 [100]
B1II KR102273305B1 PCD on front side GaN, remove substrate, and flip 1 2 2 2 [102]
B2I US8575657B2 PCD-filled via before HEMT, under the AlN layer 3 3 2.5 3 [103]
B2I US2014/0264777A1 NCD-filled vias, tapered vias stop within the substrate 3.5 3 3 3.5 [108]
B2I US9196703B2 PCD-filled vias, stop at the GaN layer 3.5 3.5 3 3 [109]
B2I CN110379782A PCD-filled vias, stop within the substrate 3.5 3 3 3.5 [110]
B2I US2021/0320045A1 Diamond-filled via, stop at AlN nucleation layer 3.5 3 3 3.5 [111]
B2II CN109742026A PCD-filled via in SiC, stop within the substrate 3.5 3.5 3 2.5 [112]
B23II US11139176B2 PCD-filled via in SiC, stop within the substrate 3.5 3.5 3 2.5 [113]
B2II CN105140122B Patterned AlN backside, electroplated with Au 3 2.5 2.5 2.5 [118]
B2II US2017/0170094A1 Diamond-filled channel, grow GaN on diamond 1.5 3.5 2.5 2.5 [120]
B2III US10242936B2 Carbon-based heat spreader in the groove 4 3.5 3 3.5 [121]
B2III + A1 US9362198B2 Top-side insulator heat spreader, backside metal 3.5 4 2.5 2.5 [126]
B2III US2017/0294528A1 Cu or Au-filled via; backside source field plate 3 3 3 2.5 [127]
B2IV + B1I US2021/0249379A1 GaN bond to a diamond wafer, metal-plated via 3.5 4 2 1.5 [128]
C CN107170673A Source metal via to buried monolayer graphene 1 1.5 3 4 [129]
C CN107170674A Source metal via to buried multilayer graphene 1 1.5 3 4 [135]
C CN108389903A GaN on graphene on SiC; all direct growth 1.5 1.5 3 3 [137]
D WO2010/075124A1 GaN between two layers PCD with varied quality 2.5 4.5 2 1 [141]
D US9685513B2 GaN island embedded in bottom and top PCD 3 4.5 1.5 1 [142]
D CN108376705A Front HEMT ball-soldered to DLC; backside graphene 2 2 3 3 [143]
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Microelectronic Engineering 273 (2023) 111958

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Chip-level thermal management in GaN HEMT: Critical review on recent

A1 US8039301B2 NCD deposition before Schottky gate 4 3 3 3 [41]

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