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VISHWAKARMA GOVERNMENT ENGINEERING COLLEGE, CHANDKHEDA
BE-II, SEM-III (COMPUTER ENGINEERING)

INDEX
Subject: Digital Fundamentals

(3130704) Academic Year:
ODD/WINTER 2020
Enrollment No. 190170107041
Name of the Student Nikhil kakadiya
Sr. Marks Faculty

Aim CO Mapping Date Page No.
No (out of 10) Signature
To study about Getting familiar with various digital integrated 31/07
circuits of different logic families (ICs).
1. Perform how to test Digital IC circuits using Digital IC
Tester.
1 2. The comparative study about various kind of simulators CO1, CO2
for Digital circuits.
3. To Design and Implement Logic Gates using configuration
of CMOS, TTL, Resistor, Diode in simulator for verification of
truth table of logic gates.
Implementation of Boolean Logic Functions using various 01/08
Logic Gates and do verification of truth table for logic gates.
1. To design and Implement basic logic Gates.
2. To design and Implement the Universal Gates & Exclusive
2 Gates. CO2, CO3
3. To study and Implement all gates using NAND and NOR
Gates.
4. Implementation of SOP Boolean Expression
5. Implementation of POS Boolean Expression
To Design and Implement the code conversion circuits for 03/08
number system.
1. Binary to Gray code conversion.
3 CO1
2. Gray to Binary code conversion.
3. Binary to BCD code conversion
4. BCD to Excess-3 code conversion
To design and implement the following Circuit and verify their 05/08
Truth Table.
4 1. HALF Adder and FULL Adder CO3
2. Subtractors
3. Magnitude Comparator (1 bit & 2 bit)
Truth Table.
5 CO3
1. 3 X 8 Decoder
2. 8 X 3 Encoder
Truth Table.
6 CO3
1. 4 in 1-line Multiplexer
2. 1 to 4-line De-multiplexer
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Truth Table.
7 1. R-S flip flop, J-K flip flop, D- flip flop, T- flip flop CO3
2. 4-bit shift Register
3. Asynchronous and Synchronous Counter
To study and Perform an experiment which demonstrates 29/09
8 CO3
function of 4 bit or 8 bit ALU.
To study and configuration of A to D and D to A converter 19/10
9 CO4
using Simulation.
To study and Implement the simulation of Programmable 03/10
10 CO5
Logic Devices (PLDs).
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Subject: Digital Fundamentals Enrollment no: 190170107041
Practical:1
Aim: To study about getting familiar with various digital integrated

circuits of different logic families (ICs).
Objective:
(1) Perform how to test Digital IC circuits using Digital IC Tester.
(2) The comparative study about various kinds of simulators for digital circuits.
(3) To Design and implement Logic Gates using configuration of CMOS, TTL,
Resistor, Diode in simulator for verification of truth table of logic gates.
Theory:
• What is an Integrated Circuit?
Integrated circuit (IC), also called microelectronic circuit, microchip, or chip, an

assembly of electronic components, fabricated as a single unit, in which
miniaturized active devices (e.g., transistors and diodes) and passive devices (e.g.,
capacitors and resistors) and their interconnections are built up on a thin
substrate of semiconductor material (typically silicon). The resulting circuit is thus
a small monolithic “chip,” which may be as small as a few square centimetres or
only a few square millimetres. The individualcircuit components are generally
microscopic in size.
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• Integration Levels of IC’s

❖ SSI Small scale integration 12 gates/chip
❖ MSI Medium scale integration 100 gates/chip
❖ LSI Large scale integration 1K gates/chip
❖ VLSI Very large scale integration 10K gates/chip
❖ ULSI Ultra large scale integration 100K gates/chip
• What is digital integrated circuit
Logic functions, such as AND, OR and NOT, are essential in building

functionality for modern digital systems. These Boolean functions are
implemented using transistors. For example, internal transistor structure of a
NAND gate is given in following figure.
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Digital integrated circuit
The semiconductor circuit is encapsulated in a plastic casing and it is

connected to the outer space by metal pins as shown in Figure A. Also, Figure B
shows the internal structure of the 4011 NAND IC. ICs are distinguished by a
combination of characters and/or numbers.
Figure b
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(1) Perform how to test Digital IC circuits using Digital IC Tester.
DIGITAL IC TESTER
Digital IC Tester is one kind of device which is used to check whether IC is in

working condition or not. Also, help us to Identify correct IC functionality. Below
figure represent example of Digital IC Testers which is available in market.
For example, if we want to check shift register (74194) the following steps
has to be followed:
1. IC i.e. is 74194 is inserted in the base.
2. You will see 2 mode options on the LCD. Mode 1: auto mode and Mode 2:
manual mode
Auto mode : Under the operation of Auto mode user don't need to use key pad, he
just need to insert IC in the IC socket and automatically the IC number is
communicated to the MCU which basically test the ICs for few sets of input which is
given through the MCU and corresponding output. The result is again
communicated to the first MCU confirming it to be either correct or faulty which is
displayed on the LCD. If the IC tested is ok “IC is Working” is displayed on the LCD.
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Otherwise “Bad IC” is displayed. 1. Insert any IC 2. Press 1 to activate auto mode 3.
Than it shows “Testing” 4. If IC is available, it shows “Found” 5. If IC is OK than it
prints the all possible ICs.
Manual mode : Under the operation of manual mode, the user enters the IC
number through keypad which is simultaneously displayed on the LCD. The IC
number is communicated to other MCU which basically test the ICs for few sets of
input which is given through the MCU and corresponding output. The result is
again communicated to the first MCU confirming it to be either correct or faulty
which is displayed on the LCD. If the IC tested is ok “IC is Working” is displayed on
the LCD. Otherwise “Bad IC” is displayed. IC number i.e. 74194 is typed using the
keypad & Enter key is then pressed.if IC is ok,” IC TESTED OK” is displayed on the
screen otherwise “IC TESTING FAILED” is displayed.
We also have the reset key. If by mistake a wrong IC number is typed, it can be
reseted using the reset key and then correct IC number can be typed.
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(2) The comparative study about various kinds of simulators for digital circuits.
LOGISIM:
Logisim is an educational tool for designing and simulating digital logic circuits.
With its simple toolbar interface and simulation of circuits as you build them, it is
simple enough to facilitate learning the most basic concepts related to logic
circuits. With the capacity to build larger circuits from smaller subcircuits, and to
draw bundles of wires with a single mouse drag, Logisim can be used (and is used)
to design and simulate entire CPUs for educational purposes.
Features
• It is free! (Logisim is open-source (GPL).)

• It runs on any machine supporting Java 5 or later; special versions
are released for MacOS X and Windows. The cross-platform nature is
important for students who have a variety of home/dorm computer
systems.
• The drawing interface is based on an intuitive toolbar. Color-
coded wires aid in simulating and debugging a circuit.
• The wiring tool draws horizontal and vertical wires,
automatically connecting to components and to other wires.
It's very easy to draw circuits!
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• The wiring tool draws horizontal and vertical wires,
automatically connecting to components and to other wires.
It's very easy to draw circuits!
• Completed circuits can be saved into a file, exported to a GIF file, or
printed on a printer.
• Circuit layouts can be used as "subcircuits" of other circuits,
allowing for hierarchical circuit design.
• Included circuit components include inputs and outputs, gates,
multiplexers, arithmetic circuits, flip-flops, and RAM memory.
Xcircuit:
XCircuit is a Unix/X11 and Windows program for drawing publication-quality

electrical circuit schematic diagrams and related figures and the production of
circuit netlists through schematic capture. XCircuit regards circuits as inherently
hierarchical and writes
both PostScript output and hierarchical SPICE netlists. Circuit components are
saved in and retrieved from libraries which are fully editable. XCircuit does not
separate artistic expression from circuit drawing; it maintains flexibility in style
without compromising the power of schematic capture.
SCILAB:
Scilab is a free and open-source, cross-platform numerical computational

package and a high-level, numerically oriented programming language. It can
be used for signal
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processing, statistical analysis, image enhancement, fluid dynamics simulations,

numerical optimization, and modeling, simulation of explicit and implicit
dynamical systems and (if the corresponding toolbox is installed) symbolic
manipulations.
Scilab is one of the two major open-source alternatives to MATLAB, the other one
being GNU Octave. Scilab puts less emphasis on syntactic compatibility with
MATLAB than Octave does, but it is similar enough that some authors suggest
that it is easy to transfer skills between the two systems
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3)To Design and implement Logic Gates using configuration of CMOS, TTL,
Resistor, Diode in simulator for verification of truth table of logic gates.
CMOS NOT Gate :
An inverter circuit outputs a voltage representing the opposite logic-level

to its input. Its main function is to invert the input signal applied. If the applied
input is low then the output becomes high and vice versa. Inverters can be
constructed using a single NMOS transistor or a single PMOS transistor coupled
with a resistor. Since this 'resistive-drain' approach uses only a single type of
transistor, it can be fabricated at a low cost. However, because current flows
through the resistor in one of the two states, the resistive-drain configuration is
disadvantaged for power consumption and processing speed. Alternatively,
inverters can be constructed using two complementary transistors in a CMOS
configuration. This configuration greatly reduces power consumption since one
of the transistors is always off in both logic states. Processing
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speed can also be improved due to the relatively low resistance compared to the
NMOS-only or PMOS-only type devices.
CMOS NAND Gate :
In digital electronics, a NAND gate (NOT-AND) is a logic gate which produces

an output which is false only if all its inputs are true; thus its output is complement
to that of an AND gate. A LOW (0) output results only if all the inputs to the gate
are HIGH (1); if any input is LOW (0), a HIGH (1) output results. A NAND gate is
made using transistors and junction diodes.
NAND gates are basic logic gates, and as such they are recognised in TTL and CMOS
ICs.
CMOS version
The standard, 4000 series, CMOS IC is the 4011, which includes four
independent, two- input, NAND gatee
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CMOS NOR Gate :
The NOR gate is a digital logic gate that implements logical NOR - it behaves
according to
the truth table to the right. A HIGH output (1) results if both the inputs to the
gate are LOW (0); if one or both input is HIGH (1), a LOW output (0) results. NOR
is the result of the negation of
the OR operator. It can also in some senses be seen as the inverse of an
AND gate. In the popular CMOS family, NOR gates with up to 8 inputs
are available:
• CMOS
o 4001: Quad 2-input NOR gate
o 4025: Triple 3-input NOR gate
o 4002: Dual 4-input NOR gate
o 4078: Single 8-input NOR gate
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CMOS XOR Gate :
XOR gate (sometimes EOR, or EXOR and pronounced as Exclusive OR) is a

digital logic gate that gives a true (1 or HIGH) output when the number of true inputs
is odd. An XOR gate implements an exclusive or; that is, a true output results if one,
and only one, of the inputs to the gate is true. If both inputs are false (0/LOW) or both
are true, a false output results. XOR represents the inequality function, i.e., the output
is true if the inputs are not alike otherwise the output is false. A way to remember
XOR is "must have one or the other but not both".
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Practical:2
Aim: Implementation of Boolean logic functions using various logic gates and do
verification of truth table for logic gates.
Objectives:
(1) To design and implement basic logic gates.
(2) To design and implement the universal gates & Exclusive gates.
(3) To study and implement all gates using nand gates & nor gates.
(4) Implementation of SOP Boolean expression.
(5) Implementation of POS Boolean expression.
(1) To design and implement basic logic gates.
The basic logic gates are categorized into seven different types : AND, OR, XOR, NAND,
NOR, XNOR and NOT.
Boolean function for each basic gate as shown below:

1. AND: Y = AB
2. OR : Y = A+B
3. NOT: Y = 𝐴̅
4. NAND: Y = 𝐴̅𝐵̅
5. NOR : Y = 𝐴̅+𝐵̅
6. XOR : Y = A ⊕ B
7. XNOR : Y = 𝐴̅⊕𝐵̅
Circuit diagram for these gates are shown below:
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Truth table for all the basic gates:
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(2) To design and implement the universal gates & Exclusive gates.
Theory:
What is universal logic gates?
Universal Logic Gates. Universal Logic gates can be used to produce any other logic
or Boolean function with the NAND and NOR gates being minimal. Individual
logic gates can be connected together to form a variety of different switching functions
and combinational logic circuits.
Circuit diagram of these gates:
What is universal exclusive logic gates?

XOR gate (sometimes EOR, or EXOR and pronounced as Exclusive OR) is a digital
logic gate that gives a true (1 or HIGH) output when the number of true inputs is odd. An
XOR gate implements an exclusive or; that is, a true output results if one, and only one,
of the inputs to the gate is true.
Boolean equation for universal gate:

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1.NAND: Y = 𝐴̅𝐵̅
2.NOR : Y = 𝐴̅+𝐵̅
Boolean equation for Exclusive gate:
1.XOR : Y = A ⊕ B
2.XNOR : Y = 𝐴̅
⊕
𝐵̅
Circuit diagram for these gates:
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Truth table for these gates:

NAND Gate
NOR Gate
A B Y
A B Y
0 0 1
0 0 1
0 1 1
0 1 0
1 0 0 1 0 1
1 1 0 1 1 0
XNOR Gate
A B Y
0 0 1
0 1 0
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1 0 0
1 1 1
XOR Gate
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
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(3) To study and implement all gates using nand gates & nor gates.
• Theory:
As nand gate & nor gate are universal gate,we can use them to implement other basic
logic gates.
AND gate using NAND:
Or gate using nand:
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Not gate using nand:
Or using nor:
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And using usingnor :
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Not using using nor:
(4) Implementation of SOP Boolean expression.
Theory:
Sum of product form:

-a logical product consisting of an AND op among literals.
e.g. : XYZ
f(a,b,c) = (A𝐵̅+𝐵̅C)
EXAMPLE FOR SOP:
Boolean equation : AB + C𝐷
Circuit diagram for example:
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Truth table for table:
A B C D x
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
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(5) Implementation of POS Boolean expression.
Theory:
Product of sum form:

The product of Sum expression has a specific schematic design of OR-AND. In OR-
AND the inputs go through an array of OR gates which is the first level of gates, the
output of the first level OR gates goes through the second level of the gate,which is an
AND gate.
Example:
f(x,y,z) = (X+Y)(X+𝑍̅)
EXAMPLE FOR POS:
Boolean equation : A(B+C)(C+D+F)
Circuit diagram for example:
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TRUTH TABLE:
A B C D E F x
0 0 0 0 0 0 0
0 0 0 0 0 1 0
0 0 0 0 1 0 0
0 0 0 0 1 1 0
0 0 0 1 0 0 0
0 0 0 1 0 1 0
0 0 0 1 1 0 0
0 0 0 1 1 1 0
0 0 1 0 0 0 0
0 0 1 0 0 1 0
0 0 1 0 1 0 0
0 0 1 0 1 1 0
0 0 1 1 0 0 0
0 0 1 1 0 1 0
0 0 1 1 1 0 0
0 0 1 1 1 1 0
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0 1 0 0 0 0 0
0 1 0 0 0 1 0
0 1 0 0 1 0 0
0 1 0 0 1 1 0
0 1 0 1 0 0 0
0 1 0 1 0 1 0
0 1 0 1 1 0 0
0 1 0 1 1 1 0
0 1 1 0 0 0 0
0 1 1 0 0 1 0
0 1 1 0 1 0 0
0 1 1 0 1 1 0
0 1 1 1 0 0 0
0 1 1 1 0 1 0
0 1 1 1 1 0 0
0 1 1 1 1 1 0
1 0 0 0 0 0 0
1 0 0 0 0 1 0
1 0 0 0 1 0 0
1 0 0 0 1 1 0
1 0 0 1 0 0 0
1 0 0 1 0 1 0
1 0 0 1 1 0 0
1 0 0 1 1 1 0
1 0 1 0 0 0 0
1 0 1 0 0 1 1
1 0 1 0 1 0 1
1 0 1 0 1 1 1
1 0 1 1 0 0 1
1 0 1 1 0 1 1
1 0 1 1 1 0 1
1 0 1 1 1 1 1
1 1 0 0 0 0 0
1 1 0 0 0 1 1
1 1 0 0 1 0 1
1 1 0 0 1 1 1
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1 1 0 1 0 0 1
1 1 0 1 0 1 1
1 1 0 1 1 0 1
1 1 0 1 1 1 1
1 1 1 0 0 0 0
1 1 1 0 0 1 1
1 1 1 0 1 0 1
1 1 1 0 1 1 1
1 1 1 1 0 0 1
1 1 1 1 0 1 1
1 1 1 1 1 0 1
1 1 1 1 1 1 1
A B C D E F x
0 0 0 0 0 0 0
0 0 0 0 0 1 0
0 0 0 0 1 0 0
0 0 0 0 1 1 0
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Practical: 3
Aim: To design and implement the code conversion circuits for number system.
Objectives:
(1) Binary to Gray code conversion.
(2) Gray to Binary code Conversion.
(3) Binary to BCD conversion.
(4) BCD to Excess-3 code conversion.
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1) Binary to Gray code conversion.
Step : 1 Truth table
Theory:
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Step-2 : drawing K-map for each output
(a) k-map for G1 (b) k-map for G2
(c)k-map for G3 (d) k-map for G4
Step-3 : Minimized Expression for each output :

G1=A
G2=A’B + AB’ = A⊕B
G3=B’C + BC’ = C⊕D
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G4=C’D + CD’ = C⊕D
Circuit diagram :
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(2) Gray to Binary code Conversion.
Theory:
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Step-2 : Drawing K-map for each output.
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(a) k-map for G1 (b) k-map for G2
(c) k-map for G3 (d) k-map for G4
Step-03 :Minimized Expression for each output :

G1 = A
G2 = A’B + AB’ = A ⊕ B
G3 = A’B’C + A’BC’ + ABC + AB’C’ = G1 ⊕ C
G4 = A’B’C’D + A’B’CD’ + A’BC’D’ +A’BCD + ABC’D + ABCD’ + AB’C’D’ +AB’CD = G3 ⊕ D
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Circuit diagram :
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(3) Binary to BCD conversion.

• Theory :
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Step-2 :drawing K-map for each output.
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(a) k-map for w (b) k-map for x (c) k-map for
(d) k-map for y (e) k-map for z
Step-03 :Minimized Expressiion for each output :

W = AB + AC
X = AB’C’
Y = A’B + BC
Z = ABC’ + A’C
E=D
Circuit diagram :
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(4) BCD to Excess-3 code conversion.
• Theory :
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Step-2 :drawing K-map for each output.
(a) k-map for w (b) k-map for x
(c) k-map for y (d) k-map for z
Step-3 : Minimized Expression for each output :
W = A + BC + BD
X = B’C + B’D + BC’D’
Y = CD + C’D’
Z=D
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• Circuit diagram :
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Practical: 4
Aim : To design and implement the following circuit and verify their truth table.
Objectives:
(1) Half adder and full adder.
(2) Subtractor.
(3) Magnitude Comparator(1-bit & 2-bit).
(1) Half adder and full adder.
Theory:
Half adder :
-A combinational circuit which adds two one-bit binary numbers is called a half-adder.
-The sum column resembles like an output of the XOR gate.
-The carry column resembles like an output of the AND gate.
• -Boolean equation:
S= A⊕ B
C = AB
• -Circuit diagram :
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• Truth table:
• inputs • outputs
A B sum carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Full adder :
-A full adder is a digital circuit that performs addition.
-A full adder adds three one-bit binary numbers, two operands and a carry bit. The adder
outputs two numbers, a sum and a carry bit. The term is contrasted with a half adder,
which adds two binary digits.
-A full adder takes two binary numbers plus a carry or overflow bit. The output is a sum
and another carry bit. Full adders are made from XOR, AND and OR gates in hardware.
Full adders are commonly connected to each other to add bits to an arbitrary length of
bits, such as 32 or 64 bits. A full adder is effectively two half adders, an XOR and an AND
gate, connected by an OR gate.
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-Boolean equation:
S=A⊕B⊕C(in)
C = C(out)
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• Circuit Diagram:
• Truth table:
Inputs Outputs
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
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(2) Subtractor.
Theory:
Half subtractor :
-A Half subtractor is used to perform two binary digits subtraction.

-The circuit of the half subtractor can be built with two logic gates namely NAND and EX-
OR gates.
-Subtractor subtracts one bit from the other and produces the difference. Output is to
specify if 1 is borrowed.
• Boolean equation:
D=A⊕B
B=A'B
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• Truth Table:
• Inputs • Outputs
A B d b
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Full subtractor :
-A full subtractor is a combinational circuit that performs subtraction of two bits, one is
minuend and other is subtrahend, taking into account borrow of the previous adjacent
lower minuend bit.
-The circuit of the fullsubtractor can be built with logic gates namely NAND,NOT and EX-
OR gates.
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-This circuit has three inputs and two outputs. The three inputs A, B and Bin, denote the
minuend, subtrahend, and previous borrow, respectively.
-Boolean equation:
D=A⊕B⊕B(i)
B=A'B+(A⊕B)'B(i)
• -Circuit diagram:
• Truth table:
• Input • Output
A B bi d D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
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(3) Magnitude Comparator(1-bit & 2-bit).

Theory :
1- bit magnitude comparator :
-a comparator circuit is used to compare the magnitudes of two binary numbers.

-Let the 1-bit numbers be A=A0 and B=B0
• If A0 = 1 and B0 = 0 then A>B,A>B : G = A0B0’
• If A0 = 0 and B0 = 1 then A<B,A<B : L = A0’B0
• If A0 = 1 and B0 = 1(coincides)
,then A=B, A = B : E = A0 ⊙ B0
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• Truth table:
A0 B0 L E G
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
2- bit magnitude comparator :
-Let the two 2-bit numbers be A = A1A0 and B=B1B0

• If A1 = 1 and B1 = 0,then A>B or
• If A1 and B1 coincide and A0 = 1 and B0 = 0,then A>B.
A>B : G = A1B1’ + (A1⊙B1) A0B0’
• If A1 = 0 and B1 = 1,then A<B or
• If A1 and B1 coincide and A0 = 0 and B0 = 1,then A<B.
A<B : L = A1’B1 + (A1⊙B1) A0’B0
• If A1 and B1 coincide and if A0 and B0 coincide then A=B.
A=b : E = (A1⊙B1)(A0⊙B0)
• -Circuit Diagram:
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• Truth Table :
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PRACTICAL: 5
• Aim: To design and implement the following circuit and verify their truth table.
• Objectives:
(1)3×8 Decoder
(2)3×8 Encoder
(1) 3×8 Decoder
Theory:
Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2n output
lines. One of these outputs will be active High based on the combination of inputs
present, when the decoder is enabled. That means decoder detects a particular code. The
outputs of the decoder are nothing but the min terms of ‘n’ input variables lines, when it
is enabled.
Here,3 inputs are decoded into 8 outputs, each output represent one of the minterm of
the 3 input variables. The three inverters provide the complement of the inputs, and each
one of the 8 AND gates generate one of the minterms. Enable input is provided to
activate decoded output based on data inputs A, B and C.
Boolean equation:
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• Truth table:
Inputs Outputs
EN A B C D0 D1 D2 D3 D4 D5 D6 D7
1 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 1 0 0 0 0 0 0
1 0 1 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 1
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• Circuit diagram:
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3×8 decoder can also be made by using prebuilt decoder in Logisim software. To make it
3×8 decoder we have to change decoder bites to 3.we have to put also one enable pin to
enable the decoder when its value will be one then and then it will work.
We can make full adder using 3×8 decoder, theory of Full adder given below:
• A full adder is a digital circuit that performs addition.
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• A full adder adds three one-bit binary numbers, two operands and a carry bit. The
adder outputs two numbers, a sum and a carry bit. The term is contrasted with a
half adder, which adds two binary digits.
• A full adder takes two binary numbers plus a carry or overflow bit. The output is a
sum and another carry bit. Full adders are made from XOR, AND and OR gates in
hardware. Full adders are commonly connected to each other to add bits to an
arbitrary length of bits, such as 32 or 64 bits. A full adder is effectively two half
adders, an XOR and an AND gate, connected by an OR gate.
Truth table:
Input Output
EN A B Cin S Cout
1 0 0 0 0 0
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 0 1
1 1 0 0 1 0
1 1 0 1 0 1
1 1 1 0 0 1
1 1 1 1 1 1
Circuit diagram:
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Five 2:4 decoders are required to design 4:16 decoder. Decoder 1 is used to enable one of
the decoder 2,3,4 and 5.Inputs of first decoder are the A and B,MSB inputs of 4:16
decoder. The inputs of decoder 2,3,4 and 5 are connected together forming C and D LSB
inputs 4:16 inputs.
When AB=00, decoder 1 is enabled, for AB = 01 decoder 2 is enabled, for AB= 10 is
decoder 3 is enabled and for AB=11, decoder 4 is enabled.
• Truth table:
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Theory:
(2) 3×8 Encoder
An Encoder is a Combinational Circuit that performs the reverse operation of Decoder. It

has maximum of 2^n Input lines and ‘n’ Output lines, hence it encodes the information
from 2^n inputs into an n-bit code. It will produce a binary code equivalent to the input,
which is active High. Therefore, the encoder encodes 2^n input lines with ‘n’ bits.
• Circuit diagram shows octal to binary encoder. It has eight inputs, one for each
octal digit, and three outputs that generate the corresponding binary code.
• In encoder it is assumed that only one input has a value of 1 at any given time;
otherwise the circuit is meaningless.
• Truth table shows the truth table of octal to binary converter.
Truth table:
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Input Output
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
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Circuit diagram:
8×3Priority encoder:
Priority encoders output the highest order input first for example, if input lines “D2“,
“D3” and “D5” are applied simultaneously the output code would be for input “D5”
(“101”) as this has the highest order out of the 3 inputs. Once input “D5” had been
removed the next highest output code would be for input “D3” (“011”), and so on.
Truth table:
Input Output
D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
0 0 0 0 0 0 0 1 0 0 0
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0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 1 X X 0 1 0
0 0 0 0 1 X X X 0 1 1
0 0 0 1 X X X X 1 0 0
0 0 1 X X X X X 1 0 1
0 1 X X X X X X 1 1 0
1 X X X X X X X 1 1 1
Circuit diagram:
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PRACTICAL: 6
AIM: To design and implement the following Circuit and verify their Truth Table.
Objectives:
(1) 4 in 1 line multiplexer.
(2) 1 in 4 line demultiplexer.
(1) 4 in 1 line multiplexer.

Theory:
In digital systems, many times it is necessary to select single data line from several data
input lines, and the data from the selected lines should be available on the output. The
digital circuit which does this task is a multiplexer.
It is a digital switch. It allows digital information from several sources to be routed onto a
single output line. The basic multiplexer has several data-input lines and a single output
line. The selection of a particular input lines is controlled by a set of selection lines. Sine
multiplexer select one of the input and routes it to output,it is also known as data
selector. Normally, there are 2n input lines and n selection lines whose bit combination
determine which input is selected. Therefore, multiplexer is ‘many to one’ and it provides
the digital equivalent of an analog selector switch.
Boolean equation:
Y = ES1’S0’D0 + ES1’S0D1 + ES1’S0D2 + ES1S0D3
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Truth Table:
E S1 S0 Y
1 0 0 D0
1 0 1 D1
1 1 0 D2
1 1 1 D3
0 × × 0
Circuit Diagram:
BY BASIC GATES:-
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BY INBUILT MULTIPLEXER:-
Application of Multiplexer:
Implement the following Boolean function using 4:1 multiplexer.
F(A,B,C) =∑m(1,3,5,6)
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(2) 1 in 4 line demultiplexer.
Theory:
A demultiplexer is a circuit that receives information on a single line and transmits this
information on 2n possible output lines. The selection of specific output line is controlled
by the values of n selection lines.
Demultiplexer has one input data line, 2n output lines, n select lines and one enable input.
Boolean equation:
Y0= ES1’S0’D0
Y1= ES1’S0D0
Y2= ES1S0’D0
Y3= ES1S0D0
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Truth Table:
Enable S1 S0 Y3 Y2 Y1 Y0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
Circuit Diagram:
BY BASIC GATES:-
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BY INBUILT MULTIPLEXER:-
Application of Multiplexer:
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1 to 8 demultiplexer using 1 to 4 demultiplexer
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PRACTICAL: 7
Aim: To design and implement the following Circuit and verify their Truth Table.
Objectives:
(1) R-S flip flop, J-K flip flop, D- flip flop, T- flip flop
(2) 4-bit shift Register
(3) Asynchronous and Synchronous Counter
(1) R-S flip flop, J-K flip flop, D- flip flop, T- flip flop
R-S Flip-Flop:
Theory:
The SR flip-flop, also known as a SR Latch, can be considered as one of the most basic
sequential logic circuit possible. This simple flip-flop is basically a one-bit memory bistable
device that has two inputs, one which will “SET” the device (meaning the output = “1”),
and is labelled S and one which will “RESET” the device (meaning the output = “0”),
labelled R.
Then the SR description stands for “Set-Reset”. The reset input resets the flip-flop back to
its original state with an output Q that will be either at a logic level “1” or logic “0”
depending upon this set/reset condition.
A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to
its opposing inputs and is commonly used in memory circuits to store a single data bit.
Then the SR flip-flop actually has three inputs, Set, Reset and its current output Q relating
to its current state or history. The term “Flip-flop” relates to the actual operation of the
device, as it can be “flipped” into a logic Set state or “flopped” back into the opposing
logic Reset state.
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Truth Table:
CP S R Qn Qn+1 State
↑ 0 0 0 0 No change
↑ 0 0 1 1
↑ 0 1 0 0 Reset
↑ 0 1 1 0
↑ 1 0 0 1 set
↑ 1 0 1 1
↑ 1 1 0 X indeterminate
↑ 1 1 0 X
Circuit Diagram:
S-R Flip-Flop using basic gates:-
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S-R Flip-Flop using inbuilt Flip-Flop:-
J-K Flip-Flop:
Theory:
The basic S-R NAND flip-flop circuit has many advantages and uses in sequential logic
circuits but it suffers from two basic switching problems.
• 1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided
• 2. if Set or Reset change state while the enable (EN) input is high the correct latching
action may not occur
Then to overcome these two fundamental design problems with the SR flip-flop design,
the JK flip Flop was developed.
This simple JK flip Flop is the most widely used of all the flip-flop designs and is
considered to be a universal flip-flop circuit. The two inputs labelled “J” and “K” are not
shortened abbreviated letters of other words, such as “S” for Set and “R” for Reset, but
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are themselves autonomous letters chosen by its inventor Jack Kilby to distinguish the
flip-flop design from other types.
The sequential operation of the JK flip flop is exactly the same as for the previous SR flip-
flop with the same “Set” and “Reset” inputs. The difference this time is that the “JK flip
flop” has no invalid or forbidden input states of the SR Latch even when S and R are both
at logic “1”.
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry
that prevents the illegal or invalid output condition that can occur when both inputs S
and R are equal to logic level “1”. Due to this additional clocked input, a JK flip-flop has
four possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The
symbol for a JK flip flop is similar to that of an SR Bistable Latch as seen in the previous
tutorial except for the addition of a clock input.
Truth Table:
CP J K Qn Qn+1 State
↑ 0 0 0 0 No change
↑ 0 0 1 1
↑ 0 1 0 0 Reset
↑ 0 1 1 0
↑ 1 0 0 1 Set
↑ 1 0 1 1
↑ 1 1 0 1 Toggle
↑ 1 1 1 0
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Circuit Diagram:
J-K Flip-Flop using inbuilt Flip-Flop:-
J-K Flip-Flop using basic gates:-
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D Flip-Flop:
Theory:
One of the main disadvantages of the basic SR NAND Gate Bistable circuit is that the
indeterminate input condition of SET = “0” and RESET = “0” is forbidden.
This state will force both outputs to be at logic “1”, over-riding the feedback latching
action and whichever input goes to logic level “1” first will lose control, while the other
input still at logic “0” controls the resulting state of the latch.
But in order to prevent this from happening an inverter can be connected between the
“SET” and the “RESET” inputs to produce another type of flip flop circuit known as a Data
Latch, Delay flip flop, D-type Bistable, D-type Flip Flop or just simply a D Flip Flop as it is
more generally called.
The D Flip Flop is by far the most important of the clocked flip-flops as it ensures that
ensures that inputs S and R are never equal to one at the same time. The D-type flip flops
are constructed from a gated SR flip-flop with an inverter added between the S and
the R inputs to allow for a single D (Data) input.
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Then this single data input, labelled “D” and is used in place of the “Set” signal, and the
inverter is used to generate the complementary “Reset” input thereby making a level-
sensitive D-type flip-flop from a level-sensitive SR-latch as now S = D and R = not D as
shown.
Truth Table:
CP J Qn Qn+1 State
↑ 0 0 0 Reset
↑ 0 1 0
↑ 1 0 1 Set
↑ 1 1 1
Circuit Diagram:
D Flip-Flop using inbuilt Flip-Flop:-
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D Flip-Flop using basic gates:-
T Flip-Flop:
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Theory:
The essential characteristic of a flip-flop is that it changes its output state in response to a
positive or negative transition on the control signal. But there is more to a flip-flop than
this: we also have to define the input-to-output relationship. This is why there are
different types of flip-flops; they are all sensitive to clock edges, but they perform
different actions in response to the input states.
The “T” in “T flip-flop” stands for “toggle.” When you toggle a light switch, you are
changing from one state (on or off) to the other state (off or on). This is equivalent to
what happens when you provide a logic-high input to a T flip-flop: if the output is
currently logic high, it changes to logic low; if it’s currently logic low, it changes to logic
high. A logic-low input causes the T flip-flop to maintain its current output state.
Truth Table:
CP T Qn Qn+1
↑ 0 0 0
↑ 0 1 0
↑ 1 0 1
↑ 1 1 0
Circuit Diagram:
T Flip-Flop using inbuilt Flip-Flop:-
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T Flip-Flop using basic gates:-
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(2) 4-bit shift Register
Serial-in to Parallel-out (SIPO) Shift Register
The operation is as follows. Let’s assume that all the flip-flops (FFA to FFD) have just been
RESET (CLEAR input) and that all the outputs QA to QD are at logic level “0” i.e., no parallel
data output.
If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the
output of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the
other outputs still remaining LOW at logic “0”. Assume now that the DATA input pin
of FFA has returned LOW again to logic “0” giving us one data pulse or 0-1-0.
The second clock pulse will change the output of FFA to logic “0” and the output
of FFB and QB HIGH to logic “1” as its input D has the logic “1” level on it from QA. The
logic “1” has now moved or been “shifted” one place along the register to the right as it is
now at QA.
When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC )
and so on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back
again to logic level “0” because the input to FFA has remained constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one place to the
right, and this is shown in the following table until the complete data value of 0-0-0-1 is
stored in the register. This data value can now be read directly from the outputs
of QA to QD.
Then the data has been converted from a serial data input signal to a parallel data output.
The truth table and following waveforms show the propagation of the logic “1” through
the register from left to right as follows.
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Clock Pulse No. QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 0 0 0 0
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Circuit Diagram:
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(3) Asynchronous and Synchronous Counter
Asynchronous counter:
Asynchronous counters are those whose output is free from the clock signal. Because the
flip flops in asynchronous counters are supplied with different clock signals, there may be
delay in producing output.
The required number of logic gates to design asynchronous counters is very less. So they
are simple in design. Another name for Asynchronous counters is “Ripple counters”.
The number of flip flops used in a ripple counter is depends up on the number of states of
counter (ex: Mod 4, Mod 2 etc). The number of output states of counter is called
“Modulus” or “MOD” of the counter. The maximum number of states that a counter can
have is 2n where n represents the number of flip flops used in counter.
For example, if we have 2 flip flops, the maximum number of outputs of the counter is 4
i.e. 22. So it is called as “MOD-4 counter” or “Modulus 4 counter”
4 bit Asynchronous UP counter:
The first flip-flop (the one with the Q0 output), has a positive-edge triggered clock
input, so it toggles with each rising edge of the clock signal.
Notice how the clock signal in this example has a duty cycle less than 50%.
I’ve shown the signal in this manner for the purpose of demonstrating how the clock
signal need not be symmetrical to obtain reliable, “clean” output bits in our four-bit
binary sequence.
In the very first flip-flop circuit shown in this chapter, I used the clock signal itself as one
of the output bits.
This is a bad practice in counter design, though, because it necessitates the use of
a square wave signal with a 50% duty cycle (“high” time = “low” time) in order to obtain a
count sequence where each and every step pauses for the same amount of time.
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Using one J-K flip-flop for each output bit, however, relieves us of the necessity of having
a symmetrical clock signal, allowing the use of practically any variety of high/low
waveform to increment the count sequence.
As indicated by all the other arrows in the pulse diagram, each succeeding output bit is
toggled by the action of the preceding bit transitioning from “high” (1) to “low” (0).
This is the pattern necessary to generate an “up” count sequence.
A less obvious solution for generating an “up” sequence using positive edge triggered flip-
flop is to “clock” each flip-flop using the Q’ output of the preceding flip-flop rather than
the Q output.
Since the Q’ output will always be the exact opposite state of the Q output on a J-K flip-
flop (no invalid states with this type of flip-flop), a high-to-low transition on the Q output
will be accompanied by a low-to-high transition on the Q’ output.
Circuit Diagram:
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Synchronous Counter:
The Asynchronous counter suffers from what is known as “Propagation Delay” in which
the timing signal is delayed a fraction through each flip-flop.
However, with the Synchronous Counter, the external clock signal is connected to the
clock input of EVERY individual flip-flop within the counter so that all of the flip-flops are
clocked together simultaneously (in parallel) at the same time giving a fixed time
relationship. In other words, changes in the output occur in “synchronization” with the
clock signal.
The result of this synchronization is that all the individual output bits changing state at
exactly the same time in response to the common clock signal with no ripple effect and
therefore, no propagation delay.
4-bit Synchronous binary up Counter:
In the circuit diagram 4-bit binary up counter is shown.

As counter is implemented with negative edge triggered flip-flops, the transitions occur at
the negative edge of the clock pulse.
In this circuit, first three flip-flops works same as 3-bit counter discussed previously.
For the fourth stage, flip-flop has to change the state when Qa=Qb= Qc = Qd= 1 .This
condition is decoded by 3-input AND gate G2.Therefore, when Qa=Qb= Qc = 1, flip-flop D
toggles and for all other times it is in no change condition.
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Circuit Diagram:
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PRACTICAL: 8
Aim: To study and perform an experiment which demonstrates function of 4 bit or 8 bit
ALU.
Objectives:
(1) 4-Bit ALU
(2) 8-Bit ALU
(1) 4-Bit ALU
In this circuit we have developed adder and subtractor using built-in adder in Logisim
software. First we have taken two input of 4-bit and then 4 adder circuit for adding
purpose and 4 x-or gates.
Inputs are named as A and B, Input A is given directly to adder circuit and input of B is
given to Xor gate and by this we can manage addition and subtraction operation. If we
want addition operation then we have to make add/subtract high and for subtraction we
have to make low.
All the carry-out of adder circuit are connected to next adder and last carry out is
connected to output.
Result will display A+B if add/subtract input is 0 and result will display A-B if add/subtract
input is 1.
Example:
(1) If A=0101
B=1000
Then in result it will show A+B which is equal to 1101
(2) If A=1111
B=1111
Then in result it will show A+B = 1110, and carry out will also be 1.
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(3) If we have activated add/subtractor then we will have A-B

If A=1000
B=0100
Then in result it will show A-B = 0100.
Circuit Diagram for 4-Bit ALU:
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(2) 8-Bit ALU
In this circuit we have developed adder and subtractor using built-in adder in Logisim
software. First we have taken two input of 8-bit and then 8 adder circuit for adding
purpose and 8 x-or gates.
Inputs are named as A and B, Input A is given directly to adder circuit and input of B is
given to XOR gate and by this we can manage addition and subtraction operation. If we
want addition operation then we have to make add/subtract high and for subtraction we
have to make low.
All the carry-out of adder circuit are connected to next adder and last carry out is
connected to output.
Result will display A+B if add/subtract input is 0 and result will display A-B if add/subtract
input is 1.
Example:
(1) If A=00000001
B=00000100
Then in result it will show A+B which is equal to 00010001
(2) If A=11111111
B=11111111
Then in result it will show A+B = 11111110, and carry out will also be 1.
(3) If we have activated add/subtractor then we will have A-B

If A=00001000
B=00000100
Then in result it will show A-B = 00000100.
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Circuit Diagram for 8-Bit ALU:
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PRACTICAL: 9
Aim: To study and configuration of A to D and D to A Converter using

Simulation.
Objectives:
(1) Analog to Digital Converter
(2) Digital to Analog Converter
(1) Analog to Digital Converter
Theory:
There are many A to D converters are in market like Dual slope ADC, flash
type ADC, successive approximation ADC, counter type ADC, tracking type
ADC. But in this practical for A to D converter we will talk about Flash type
ADC and we will simulate in xcircuit software.
Flash type ADC:
A Flash type ADC produces an equivalent digital output for a corresponding

analog input in notime. Hence, Flash type ADC is the fastest ADC.
The 3-bit flash type ADC consists of a voltage divider network, 7 comparators
and a priority encoder. The working of a 3-bit flash type ADC is as follows.
• The Voltage Divider Network contains 8 equal resistors. A reference
voltage VR is applied across that entire network with respect to the
ground. The voltage drop across each resistor from bottom to top with
respect to ground will be the integer multiples (from 1 to 8) of VR /8.
• The External Input Voltage Vi is applied to the non-inverting terminal of
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all comparators. The voltage drop across each resistor from bottom to top
with respect to ground is applied to the inverting terminal of comparators
from bottom to top.
• Circuit diagram for 3-bit Flash type ADC:
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• At a time, all the comparators compare the external input voltage with
the voltage drops present at the respective other input terminal. That
means, the comparison operations take place by each comparator
parallelly.
• The output of the comparator will be ‘1’ as long as Vi is greater than the
voltage drop present at the respective other input terminal. Similarly, the
output of comparator will be ‘0’, when, Vi is less than or equal to the
voltage drop present at the respective other input terminal.
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• All the outputs of comparators are connected as the inputs of Priority

Encoder. This priority encoder produces a binary code (digital output),
which is corresponding to the high priority input that has ‘1’.
• Therefore, the output of priority encoder is nothing but the binary equivalent
(digital output) of external analog input voltage Vi .
• The flash type ADC is used in the applications where the conversion
speed of analog input into digital data should be very high.
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Practical: 10
Aim: To study and Implement the simulation of Programmable Logic Devices

(PLDs).
Theory:
Programmable Logic Devices PLDs are the integrated circuits. They contain an array
of AND gates & another array of OR gates. There are three kinds of PLDs based on
the type of arrays, which has programmable feature.
1. Programmable Read Only Memory

2. Programmable Array Logic
3. Programmable Logic Array
The process of entering the information into these devices is known

as programming. Basically, users can program these devices or ICs electrically in
order to implement the Boolean functions based on the requirement. Here, the
term programming refers to hardware programming but not software
programming.
• Programmable Read Only Memory (PROM):
Read Only Memory ROM is a memory device, which stores the binary information
permanently. That means, we can’t change that stored information by any means
later. If the ROM has programmable feature, then it is called as Programmable
ROM PROM. The user has the flexibility to program the binary information
electrically once by using PROM programmer.
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• Example:
3- bit gray to binary code converter, Implement it using suitable PROM.
Truth Table:
Gray code Binary code

G2 G1 G0 B2 B1 B0
M0 0 0 0 0 0 0
M1 0 0 1 0 0 1
M3 0 1 1 0 1 0
M2 0 1 0 0 1 1
M6 1 1 0 1 0 0
M7 1 1 1 1 0 1
M5 1 0 1 1 1 0
M4 1 0 0 1 1 1
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• Programmable Array Logic
PAL is a programmable logic device that has Programmable AND array & fixed OR
array. The advantage of PAL is that we can generate only the required product
terms of Boolean function instead of generating all the min terms by using
programmable AND gates. The block diagram of PAL is shown in the following figure
Here, the inputs of AND gates are programmable. That means each AND gate has
both normal and complemented inputs of variables. So, based on the requirement,
we can program any of those inputs. So, we can generate only the required product
terms by using these AND gates.
Here, the inputs of OR gates are not of programmable type. So, the number of inputs
to each OR gate will be of fixed type. Hence, apply those required product terms to
each OR gate as inputs. Therefore, the outputs of PAL will be in the form of sum of
products form.
• Example:
A combinational circuit is defined by the functions :

F1 = ∑m (3,5,7),F2 = ∑m(4,5,7)
Implement the circuit with a PLA having 3 inputs,3 product terms and two outputs.
- From this equations we can derive:
F1 = AC+BC , F2 = AB’+AC
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• Programmable Logic Array
PLA is a programmable logic device that has both Programmable AND array &
Programmable OR array. Hence, it is the most flexible PLD. The block
diagram of PLA is shown in the following figure.
Here, the inputs of AND gates are programmable. That means each AND gate has
both normal and complemented inputs of variables. So, based on the requirement,
we can program any of those inputs. So, we can generate only the required product
terms by using these AND gates.
Here, the inputs of OR gates are not of programmable type. So, the number of inputs
to each OR gate will be of fixed type. Hence, apply those required product terms to
each OR gate as inputs. Therefore, the outputs of PAL will be in the form of sum of
products form.
• Example:
Design BCD to Excess-3 using PAL .
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• Truth Table:
• Decimal • BCD code • Excess-3 code
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
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VISHWAKARMA GOVERNMENT ENGINEERING COLLEGE, CHANDKHEDA

BE-II, SEM-III (COMPUTER ENGINEERING)

Subject: Digital Fundamentals

Sr. Marks Faculty

Aim: To study about getting familiar with various digital integrated

Integrated circuit (IC), also called microelectronic circuit, microchip, or chip, an

• Integration Levels of IC’s

• What is digital integrated circuit

Logic functions, such as AND, OR and NOT, are essential in building

Digital integrated circuit

The semiconductor circuit is encapsulated in a plastic casing and it is

(1) Perform how to test Digital IC circuits using Digital IC Tester.

Digital IC Tester is one kind of device which is used to check whether IC is in

1. IC i.e. is 74194 is inserted in the base.

• It is free! (Logisim is open-source (GPL).)

• The drawing interface is based on an intuitive toolbar. Color-

XCircuit is a Unix/X11 and Windows program for drawing publication-quality

Scilab is a free and open-source, cross-platform numerical computational

processing, statistical analysis, image enhancement, fluid dynamics simulations,

CMOS NOT Gate :

An inverter circuit outputs a voltage representing the opposite logic-level

CMOS NAND Gate :

In digital electronics, a NAND gate (NOT-AND) is a logic gate which produces

CMOS NOR Gate :

CMOS XOR Gate :

XOR gate (sometimes EOR, or EXOR and pronounced as Exclusive OR) is a

(1) To design and implement basic logic gates.

Boolean function for each basic gate as shown below:

Circuit diagram for these gates are shown below:

Truth table for all the basic gates:

What is universal logic gates?

Circuit diagram of these gates:

What is universal exclusive logic gates?

Boolean equation for universal gate:

Boolean equation for Exclusive gate:

Circuit diagram for these gates:

Truth table for these gates:

AND gate using NAND:

Or gate using nand:

Not gate using nand:

And using usingnor :

Not using using nor:

(4) Implementation of SOP Boolean expression.

Sum of product form:

Truth table for table:

(5) Implementation of POS Boolean expression.

Product of sum form:

1) Binary to Gray code conversion.

Step : 1 Truth table

Step-2 : drawing K-map for each output

(a) k-map for G1 (b) k-map for G2

(c)k-map for G3 (d) k-map for G4

Step-3 : Minimized Expression for each output :

G4=C’D + CD’ = C⊕D

(2) Gray to Binary code Conversion.

Step : 1 Truth table

Step-2 : Drawing K-map for each output.

(a) k-map for G1 (b) k-map for G2

(c) k-map for G3 (d) k-map for G4