UNIVERSITY OF BRISTOL

FACULTY OF ENGINEERING

First Year Examination for the Degrees of

Bachelor and Master of Engineering

MAY/JUNE 2009 3 Hours

DIGITAL CIRCUITS & SYSTEMS

EENG14000

This question paper is to be left on your desk at the end of the examination with any
rough work crossed through.

This paper contains three sections - A, B, and C - and you should attempt all three
sections.

Each question is labelled with its marks value.

You should attempt ALL questions.

Answer each section in the appropriate printed answer book provided. Do not show
working unless the question asks for it.

Only calculators bearing the Faculty of Engineering Seal of Approval may be used

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SECTION A

QA1 State the number of control input lines needed for a 4:1 multiplexer.
(1 mark)

QA2 One input of a 2-input NAND gate is tied to logic 0. State what logic value
appears at its output.
(1 mark)

QA3 Express (J.K.L +L'.M)' in POS form.

(2 marks)

QA4 The two data inputs of a full adder are both 1, and its carry input is 0. Give the
values of its carry output and its sum output.
(2 marks)

QA5 Give the dual of A.B + G'.

(2 marks)

QA6 State what Boolean function is performed by a 2-input NAND gate with its
inputs tied together.
(2 marks)

QA7 Consider a VHDL bit array defined as myarray(7 downto 0). After a certain
type of left shift of a certain number of places is applied, the resulting value is
myarray(2 downto 0)&myarray(7 downto 3).
Give the type and direction of the shift and the number of places.
(5 marks, split 2 + 1+ 2)
QA8 One of the prime implicants of the function ∑P,Q,R(0, 2, 3, 6, 7) contains two
minterms.
a) Give their numbers.
b) Give the minimal POS Boolean expression for the function.
(5 marks, split 2 + 3)
QA9 A Moore state machine with 30 states is implemented using the smallest
necessary ROM for its combinational logic and the minimal necessary number
of D flip-flops for its state register. The ROM generates the flip-flop driver
signals as well as the system's outputs. It has 8 address lines and it outputs 8
data bits.
a) Give the number of binary "present state" signals.
b) Give the number of 8-bit locations is the ROM.
c) Give the number of binary inputs entering the system.
d) Give the number of flip-flop driver signals.
e) Give the number of binary outputs leaving the system.

(10 marks, split 2 each)

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QA10 a) The Boolean function M = (Q' + S).(P' + Q + S').(Q + R' + S'). Give one
of the minimal SOP expressions for M. HINT: USE A KARNAUGH MAP.

b) Underline the essential prime implicant(s) in your answer to (a), excluding

any secondary essential prime implicants.
c) Consider a PLA with 16 inputs, 8 outputs and 48 product terms. Give the
number of AND gates, the number of OR gates and the number of inputs
per OR gate in the PLA.
(10 marks, split 5 + 2 + [1 + 1 + 1])
QA11 a) A certain Mealy machine has an output, Z. A stream of bits is applied to
its input, X, one bit per clock cycle. Z goes to 1 whenever the most recent
bits received on X match a certain sequence of 0s and 1s. The machine’s
two binary state variables are G and H, and the starting state is GH = 00.
The transition equations are G* = X'.H and H* = X. The output equation
is Z = X.G.

(i) Say which combination of G, H values is not used;

(ii) Give the pattern mentioned above; and

(iii) Say what the next state would be if the machine ever enters the
unused state with X = 0.

b) A state machine with two state variables, a and b, and no inputs, uses D
flip-flops as its state register, and generates the continuous sequence ab =
00, 11, 10, 00… Give the minimal SOP expressions for the
excitation/driver signals, Da and Db, treating the ab=01 case as “can’t
happen”.
(10 marks, split [2 +3 + 1] +[2 + 2])

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SECTION B

QB1 Name the addressing mode in which the address of the operand is given in the
machine code of the instruction.
(1 mark)

QB2 Reading a certain input port delivers eight bits, in the pattern xxxggggx, where x
means ‘undefined’ and g is good data. Give, in hexadecimal, the value that
should be ANDed with these bits so as to clear the x bits to 0 and leave the g bits
unchanged.
(2 marks)

QB3 A LIFO stack grows towards address 0 and the stack pointer indicates the top-
of-stack item. State the addressing mode used in a PUSH operation.
(2 marks)

QB4 A certain processor (not the 68HCS12) has a branch instruction occupying three
bytes of machine code. A ten-bit field in the machine code is a 2’s complement
displacement value indicating the destination relative to the current value of the
Instruction Pointer (IP). The IP points to the start of the instruction located after
the branch.
a) Give, in hexadecimal, the range of values that can be represented by the 2’s
complement value. HINT: AVOID DOING YOUR WORKING IN DECIMAL
b) Assuming that one of these branch instructions starts at address hexadecimal
6000, give the lowest and highest addresses that could be reached using the
branch.
(5 marks, split 2 + 3)

QB5 Say whether each of the following sentences is true or false (assume the
microprocessor and development system used in the DCS laboratory).
a) The instruction ldaa #mike+jane takes the same time to execute on the
68HCS12 as the instruction ldaa #brian.
b) The fcb directive, when used to define a table, is best placed between the
ldaa ,x and inx instructions used to access the table.
c) When executing a loop N times on the 68HCS12, it is better to count the
loop variable down to zero rather than up to N.
d) An equ statement may be placed between any two statements in a
program without disrupting the flow of execution.
e) A ble instruction will always act the opposite way to a bgt instruction in
the same situation (i.e. one branch will/will not be taken and the other will
not/will be taken).
(1 mark for each correct, -1 for each incorrect. If you are not sure of the
answer, it’s best to leave it unanswered so that you avoid losing a mark.)

(5 marks)

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QB6 Consider the following rather unrealistic program for the 68HCS12. Note that
the stack grows towards 0 and the stack pointer indicates the top-of-stack item.
lds #0X4000 ;line 1
jsr init ;line 2
again: jsr calc ;line 3
ldaa mysum ;line 4
cmpa #37 ;line 5
blo again ;branch if lower

init: ldaa #8 ;line 7

staa sue ;line 8
ldaa #3 ;line 9
staa fred ;line 10
clr mysum ;clears mysum to zero
rts ;line 12

calc: ldaa mysum ;line 13

adda sue ;line 14
adda fred ;line 15
staa mysum ;line 16
rts ;line 17

sue: rmb 1
fred: rmb 1

a) Write a piece of pseudocode equivalent to lines 2 to 6.

HINT: IF YOU FIND
YOU ARE MENTIONING REGISTERS YOU ARE SHOWING TOO MUCH DETAIL
b) Give the value in mysum at the end of the first execution of calc.
c) State how many times the calc routine will be called.
d) Give the value of the stack pointer immediately after the second execution
of line 3.
e) By mistake, a programmer writes jmp instead of jsr in line 3. Give the
line number where failure resulting from this error is likely to be seen
when the program runs.

(10 marks, split 3 + 1 + 2 + 2 + 2)

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SECTION C

QC1 Label the transistor symbol in the answer book and in the space provide give its
name.
(1 mark)
QC2 The V-I plot in the answer book shows an actual diode characteristic. Draw on
the plot, labelling them clearly, the characteristics of:-
i) an ideal diode, DIDEAL, and
ii) the DrON model that closely approximates to a real diode.
(2 marks)
QC3 On the plot given in the answer book show the cut-off, saturation and triode
regions on the output characteristic of the n-MOSFET. What is the equation for
the dotted line shown there?
(2 marks)
QC4 Figure QC4(a) shows a diode formed with a depletion region under no bias
voltage. In the other two diagrams state the operating conditions. State in cases
(b) and (c) which of the voltages across anode and cathode listed are the most
likely.
2V; 5V; -5V; 0V; 0.7V; 0.2V;
(3 marks)
(a) (b) (c)
A C A C A C
p n p n p n

depletion region

Figure QC4 Diode biasing.

QC5 The figure in the answer book shows the cross section of a MOS FET. State the
names of the parts labelled (i) to (iii) and for (iv) state whether it is a n-type or
p-type MOSFET device. On the diagram draw the shape of the channel region
when the transistor is just reaching pinch-off conditions - as would occur for the
given voltage levels.
(3 marks)
QC6 Write the logic equation for F2 in the CMOS circuit in Figure QC6.

R
F2

Figure QC6 A 3-input CMOS logic circuit

(4 marks)
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QC7 It is known that the transistor in the circuit in Figure QC7 is operating in the
saturated region. Using the “Blob of Solder” model of a transistor in saturation,
determine the voltage at the transistor terminals and the currents in each resistor
for the circuit. Note:- it is a p-n-p transistor with β = 100.
State the value of βforced under these conditions. Determine with the “blob of
solder” model the value, in the 10% resistor range, of the base resistor needed to
make the circuit move into the onset of the linear region.
(10 marks)
+3V

1k0

e
+0V Q2
7k5 b
c

10k

-15V
Figure QC7 A BJT circuit.

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