BASIC ELECTRONICS 18ELN14/24

MODULE 5 : FUNDAMENTALS OF DIGITAL ELECTRONICS

Structure

5.0 Introduction
5.1 Objectives
5.2 Switching and Logic Levels
5.3 Digital Waveform
5.4 Number Systems:
5.4.1 Decimal Number System,
5.4.2 Binary Number System,
5.4.3 Converting Decimal to Binary
5.4.4 Hexadecimal Number System
5.4.5 Converting Binary to Hexadecimal & Vice versa
5.4.6 Converting Hexadecimal to Decimal & Vice versa
5.4.7 Octal Number System
5.4.8 Octal to Binary & Binary to octal Conversion
5.5 Complement of Binary Numbers
5.6 Boolean Algebra Theorems
5.7 Digital Circuits
5.7.1 Logic gates
5.7.2 Algebraic Simplification
5.7.3 NAND and NOR Implementation
5.7.4 Half adder & Full adder
5.8 Flip Flops
5.8.1 S R Flip Flop
5.8.2 J K Flip Flop
5.8.3 Shift Register
5.8.4 Binary Counter
5.9 Principle of Communication system
Course outcome
5.11 Further Reading

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5.0 INTRODUCTION:

Definitions of Analog vs Digital signals

An Analog signal is any continuous signal for which the time varying feature (variable) of the
signal is a representation of some other time varying quantity, i.e., analogous to another time
varying signal. It differs from a digital signal in terms of small fluctuations in the signal which
are meaningful.
A digital signal uses discrete (discontinuous) values. By contrast, non-digital (or analog)
systems use a continuous range of values to represent information. Although digital
representations are discrete, the information represented can be either discrete, such as
numbers or letters, or continuous, such as sounds, images, and other measurements of
continuous systems.

Figure. 3.0 Analog and digital signal

5.1 OBJECTIVES
1. To Understand the Number systems and conversion of one Number system to other
2. To define a Logic gate and understand the different types of Logic Gates
3. To state different laws of Boolean Algebra
4. Simplify the Logical expressions using Boolean algebra and implement using Universal

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Gates
5. Design and implementation of Half adder and Full adder

5.2 SWITCHING AND LOGIC LEVELS

In digital circuits, a logic level is one of a finite number of states that a signal can have. Logic levels are
usually represented by the voltage difference between the signal and ground (or some other common
reference point), although other standards exist. The range of voltage levels that represents each state
depends on the logic family being used.

In binary logic the two levels are logical high and logical low, which generally correspond to a binary 1
and 0 respectively. Signals with one of these two levels can be used in boolean logic for digital circuit
design or analysis.

In three-state logic, an output device can also be high impedance. This is not a logic level, but means
that the output is not controlling the state of the connected circuit.

5.3 DIGITAL WAVEFORMS

In computer architecture and other digital systems, a waveform that switches between two
voltage levels representing the two states of a Boolean value (0 and 1) is referred to as a
digital signal, even though it is an analog voltage waveform, since it is interpreted in terms of
only two levels.
The clock signal is a special digital signal that is used to synchronize digital circuits. The
image shown can be considered the waveform of a clock signal. Logic changes are triggered
either by the rising edge or the falling edge.
The given diagram is an example of the practical pulse and therefore we have introduced two new
terms that are:
 Rising edge: the transition from a low voltage (level 1 in the diagram) to a
high voltage (level 2).
 Falling edge: the transition from a high voltage to a low one.

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Figure 3.1 Digital Waveforms

5.4 NUMBER SYSTEMS

The human need to count things goes back to the dawn of civilization. To answer the questions like
―how much‖, or ―how many‖, people invented number system. A number system is any scheme
used to count things. The decimal number system succeeded because very large numbers can be
expressed using relatively short series of easily memorized numerals. Decimal or base 10 number
system„s origin: can be traced to, counting on the fingers with digits. ―Digit‖ taken from the Latin
word digitus meaning ―finger‖In any number system, the important terms to be known are :
Base or radix, numerals, positional value, absolute value, radix point and the prevalent number systems
of interest for study.
Base: Base is the number of different digits or symbols or numerals used to represent the number
system including zero in the number system. It is also called the radix of the number system. Numeral :
Numeral is the symbols used to represent the number system
Each digit in the number system has two values: a) Absolute value
b) Positional value
The absolute value is the value of the digit itself, representing the no. system. The positional
value is the value it possesses by virtue of its position in the no. system
The different number systems of interest for study, from the point of view of application to
computers are:
Examples of commonly used number systems : Decimal,Binary,Hexadecimal.
Important properties of these systems need to be studied.
Polynomial Notation (Series Representation) :Any number system can be represented by the
following polynomial.

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N = an-1 x rn-1 + an-2 x rn-2 + .. + a0 x r0 + a-1 x r-1 ... + a-m x r–mWhere r

= radix or base
n = number of integer digits to the left of the radix point
m = number of fractional digits to the right of the radix point
an-1 = most significant digit (MSD)
a-m = least significant digit (LSD)

Example:

N = (251.41)10 = 2 x 102 + 5 x 101 + 1 x 100 + 4 x 10-1 + 1 x 10-2

5.4.1 DECIMAL NUMBER SYSTEMS

The decimal system is composed of 10 numerals or symbols. These 10 symbols are 0, 1, 2, 3, 4, 5, 6, 7,

8, 9. Using these symbols as digits of a number, we can express any quantity. The decimal system is
also called the base-10 system because it has 10 digits.
In decimal system, the no. 1000.111 is represented as:
Integer part Fractional part
103 102 101 100 10-1 10-2 10-3
=1000 =100 =10 =1 . =0.1 =0.01 =0.001
Least
Most Significant Digit Decimal point Significant
Digit
Example : Multiply the value of the symbol by the value of the position, then add In decimal,
1954.89means
1 times 1,000 plus 9 times 100 plus 5 times 10 plus 4 times 1 plus 8 times 1/10

plus 9 times 1/100 = The number is 1954.89 in decimal. and is represented by (1954.89)10. The digits

are separated by a point “.” called the radix point.

Examples of decimal numbers
1410 5210 102410 6400010
5.4.2 BINARY NUMBER SYSTEMS

In the binary system, there are only two symbols or possible digit values, 0 and 1. This base-
2 system can be used to represent any quantity that can be represented in decimal or other

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base system.
Integer part Fractional part
3 2 1 0 -1
2 2 2 2 2 2-2 2-3
=8 =4 =2 =1 . =0.5 =0.25 =0.125
Least
Most Significant Digit Binary point Significant Digit

Binary Counting
The Binary counting sequence to represent decimal numbers is shown in the table below :

23 22 21 20 Decimal
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15

Representing Binary Quantities

In digital systems the information that is being processed is usually presented in binary form. Any
device that has only two operating states or possible conditions can represent binary quantities. E.g..
a switch which can be either be only open or closed. We arbitrarily (as we define them) let
an open switch represent binary 1 and a closed switch represent binary 0. Thus we can represent any
binary number by using series of switches

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Typical Voltage Assignment

Binary 1: Any voltage between 2V to 5V
Binary 0: Any voltage between 0V to 0.8V
Not used: Voltage between 0.8V to 2V in 5 Volt CMOS and TTL Logic is not used as it may cause error
in a digital circuit
We can see another significant difference between digital and analog systems. In digital systems, the
exact voltage value is not important; eg, a voltage of 3.6V means the same as a voltage of 4.3V. In
analog systems, the exact voltage value is important
Binary addition and subtraction: Examples of addition and subtraction in this number system is
shown below:
The addition of binary numbers is done as follows:
a) 1 + 1 = 0 with a carry of 1, and can be represented as (10) 2 , with 0 taking LSD position and 1
taking MSD.
b) 1 + 0 = 1 c) 0 + 1 = 1 d) 0
+0= 0
Example: Add the binary numbers 101011 and 11001 Sol: The binary addition process is indicated
below,
Addition
111011 Carries the carries generated during addition is indicated here.
101011 Augend
+1001 Addend
1000100
The answer is : (101011) 2 + (11001) 2 = ( 1000100) 2
The subtraction of binary numbers is done as follows:
e) 1 - 1 = 0 f) 1 - 0 = 1
g) 0 - 1 = 0 with a barrow of 1 from previous stage
h) 0 - 0 = 0

Example: Subtract the binary numbers 11011 from100101. Sol: The binary subtraction process is

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indicated below,
The answer is : (100101) 2 - (11011) 2 = ( 01010) 2

5.4.3 BINARY TO DECIMAL & DECIMAL TO BINARY CONVERSION

Binary to Decimal Conversion

The binary number system is the most important one in digital systems, but several others are also
important. The decimal system is important because it is universally used to represent quantities
outside a digital system. This means that there will be situations where decimal values have to be
converted to binary values before they are entered into the digital system.
Any binary number can be converted to its decimal equivalent simply by summing together the weights
of the various positions in the binary number which contain a together the weights of the various
positions in the binary number which contain a 1. Technique

Multiply each bit by 2n, where n is the “weight” of the bit

The weight is the position of the bit, starting from 0 on the right Add the results
Example:
Binary Decimal
101101012
27+06+25+24+03+22+01+20 =128+0+32+16+0+4+0+1
Result 18110
You should have noticed that the method is to find the weights (i.e., powers of 2) for each bit position
that contains a 1, and then to add them up.
Binary to decimal Fractions:
Example :
10.1011 =>

1 x 2-4 = 0.0625 1 x 2-3 = 0.125 0 x 2-2 = 0.0

1 x 2-1 = 0.5

0 x 20 = 0.0

1 x 21 = 2.0 =2.6875

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Procedure: Same principles with following exception ;.

Use negative powers of the base to the right of the radix point. (Only call it a decimal point in
the decimal number system.)
Decimal-To-Binary Conversion There are 2 methods:
 Reverse of Binary-To-Decimal Method
 Repeat Division
Reverse of Binary-To-Decimal Method
Example :
Decimal Binary
4510 =32 + 0 + 8 + 4 +0 + 1
=25+0+23+22+0+20
Result =1011012
Repeat Division-Convert decimal to binary
This method uses repeated division by 2.
Example :
Conversion of 2710 to binary
Division Remainder Binary
25/2 = 12+ remainder of 1 1 (Least Significant Bit)
12/2 = 6 + remainder of 0 0
6/2 = 3 + remainder of 0 0
3/2 = 1 + remainder of 1 1
1/2 = 0 + remainder of 1 1 (Most Significant Bit)
Result 2510 = 110012
Procedure :
 Divide by two, keep track of the remainder
 Group the remainders in the following order
 First remainder is bit LSB (least-significant bit)
 Last remainder is bit MSB (Most-significant bit)

5.4.4 HEXA DECIMAL NUMBER SYSTEM

The hexadecimal system uses base 16. Thus, it has 16 possible digit symbols. It uses the digits 0 through

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9 plus the letters A, B, C, D, E, and F ,to represent 10 through 16, as the 16 digit symbols Digits = {0, 1,
2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F}

(B65F)16 = 11 x 163 + 6 x 162 + 5 x 161 + 15 x 160 = (46,687)10

Sometimes, it is necessary to use a numbering system that has more than ten base digits One such
numbering system is hexadecimal number system, useful in computer application. Hexadecimal number,
is widely used in micro processors and micro controllers in assembly programming, and in embedded
system development.
Hexadecimal addition and subtraction: Examples of addition and subtraction in this number
system is shown below:
Addition
1011 Carries
5 BA9 Augend
+ D 0 5 8 Addend 1 2 C 0
1 Sum
Subtraction
9 10 A 10 Borrows
A 5 B 9 Minuend
+ 5 8 0 D Subtrahend
1 D A C Difference
5.4.5 BINARY-TO-HEXADECIMAL /HEXADECIMAL-TO-BINARY CONVERSION

Hexadecimal Digit 0 1 2 3 4 5 6 7
Binary Equivalent 0000 0001 0010 0011 0100 0101 0110 0111

Hexadecimal Digit 8 9 A B C D E F
Binary Equivalent 1000 1001 1010 1011 1100 1101 1110 1111
Each Hexadecimal digit is represented by four bits of binary digit
5.4.5 HEXADECIMAL TO DECIMAL/DECIMAL TO HEXADECIMAL CONVERSION

Example: 2AF16 = 2 x (162) + 10 x (161) + 15 x (160) = 68710

Hexadecimal to Decimal ConversionTechnique

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 Multiply each bit by 16n, where n is the “weight” of the bit

 The weight is the position of the bit, starting from 0 on the right
 Add the results
Example:

ABC.6D16 =>C x 160 = 12 x 1 = 12 B x 161 = 11 x 16 = 176

A x 162 = 10 x 256 = 2560 6 x 1/16 = 6 x .0625

D x 1/162 = 13 x .0039= 2748.066410

Ans: ABC16 = 2748.066410

Decimal To Hexadecimal
Repeat Division- Convert decimal to hexadecimal - This method uses repeated division by 16.
Example: convert 37810 to hexadecimal and binary:
Division Result Hexadecimal
378/16 = 23+ remainder of 10 A (Least Significant Bit)23
23/16 = 1 + remainder of 7 7
1/16 = 0 + remainder of 1 1 (Most Significant Bit)
Result 37810 = 17A16
Binary = 0001 0111 10102

5.4.6 OCTAL NUMBER SYSTEM

The octal number system has a base of eight, meaning that it has eight possible
digits: 0,1,2,3,4,5,6,7.
83 82 81 80 8-1 8-2 8-3
=512 =64 =8 =1 . =1/8 =1/64 =1/512
The octal numbering system includes eight base digits (0-7).After 7, the next placeholder to the
right begins with a “1”
0, 1, 2, 3, 4, 5, 6, 7, 10, 11, 12, 13 ...

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Octal to Decimal Conversion

2378 = 2 x (82) + 3 x (81) + 7 x (80) = 15910 24.68 = 2 x (81) + 4 x (80) + 6 x (8-

1
) = 20.7510 11.18 = 1 x (81) + 1 x (80) + 1 x (8-1) = 9.12510 12.38 = 1 x (81) + 2

x (80) + 3 x (8-1) = 10.37510

Octal addition and subtraction:

Examples of addition and subtraction in this number system is shown below:
Example: Add the octal numbers 5471 and 3754
Sol : The addition process with procedure is shown below :
Addition
111 Carries the carries generated during addition is indicated here.
5 4 7 1 Augend
+ 3 7 5 4 Addend
1 1 4 4 5 Sum
Procedure :
Addition of first column 1+4= 5
Addition of second column 7+5= 12 and 12-8 = 4, with a carry of 1 to left Addition of third column
1+4+7= 12 and 12-8 = 4, with a carry of 1 to left
Addition of fourth column 1+5+3= 9 and 9-8 = 1, with a carry of 1 to left The final carry forms the
MSD.
The answer is : (5471) 8 + (3754) 8 = ( 11445) 8
Subtraction
Example: Subtract the octal numbers 7451 and 5643
Sol : The subtraction process with procedure is shown below :
6 10 4 10 Borrows the barrows taken during subtraction is indicated here.
7 4 5 1 Minuend
- 5 6 4 3 Subtrahend
1 6 0 6 Difference
Procedure :

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 Subtraction of first column 1-3= 6,by borrowing carry from previous stage 1+8= 9, hence 9-
3=6
 Subtraction of second column 4-4= 0,now after the barrow 5 becomes 4 in II column.
Subtraction of third column 4-6= 6, by borrowing from previous stage, 8+4=12, Hence 12-6 = 6
 Subtraction of fourth column 6-5= 1, 7 will become 6 after a barrow to the right. The answer is :
(7451) 8 - (5643) 8 = ( 1606) 8

5.4.7 Binary to Octal and Octal to binary conversion

Binary to octal
Group 3 Bits and write its corresponding octal equivalent
Example: 100 111 0102 = (100) (111) (010)2 = 4 7 28
Octal to Binary
Octal 0 1 2 3 4 5 6 7
Binary
000 001 010 011 100 101 110 111
Equivalent

Each Octal digit is represented by three binary digits.

5.5 COMPLEMENT OF BINARY NUMBERS

The 1„s complement of a given binary no. is the new no. obtained by changing all the 0„ to 1, and
all 0„s to 1
Ex : 11010„s 1„s complement is 00101
The 2„s complement of a given binary no. is the new no. obtained by changing all the 0„ to 1, and
all 0„s to 1 and then adding 1 to the least significant it
Ex : 11010„s 2„s complement is 1„s complement 00101+1=00110 Subtraction of smaller number
from larger number
Method:
1. Determine the 1„s complement of the smaller no.
2. Add the first complement to the larger no.
3. Remove the carry and add it to the result. This is called end-around carry.

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Ex : Subtract 1010112 from 1110012 using the 1„s complement method Solution :
111001
-101011 - Take 1„s complement of101011 = 010100 -------------
111001 + 010100
-----------------Carry 1) 001101
------- --+1 - end around carry -------------------
1110 Final answer
Subtraction of larger number from smaller number
Method :
1. Determine the first complement of the larger no.
2. Add the first complement to the smaller no.
3. Answer is in the 1„s complement form.To get the answer in true form take the 1„s complement
and assign –ve sign to the answer.
Advantages of 1’s complement method
1. The first complement subtraction can be accomplished with a binary adder. There fore,
this method is useful in arithmetic logic circuits.

2. The first complement of a no. is easily obtained by inverting each bit in the no.
2’s complement method of subtraction
Subtraction of smaller number from larger number
Method:
1. Determine the 2„s complement of a smaller no.
2 Add the 2„s complement to the larger no.
3 Discard the carry.
Subtract 1010112 from 1110012 using the 1„s complement method
Solution :
111001
-101011 -
Take 2„s complement of101011 = 1„s complement+1=010100+1 ------------- =010101
111001 + 010101

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-----------------
Carry 1) 001110------- discard the carry -------------------
1110 Final answer
Subtraction of larger number from smaller number
Method:
1. Determine the 2„s complement of a larger no.
2 Add the 2„s complement to the smaller no.
3 When there is no carry, answer is in the 2„s complement form.
To get the answer in the true form take the 2„s complement and assign –ve sign to the
answer.
Ex :Subtract 1110012 from1010112 using the 1„s complement method Solution :
101011
-111001 - Take 2„s complement of111001 = 1„s complement+1=000110+1 -------------
=000111
101011 + 000111
-----------------
110010------- no carry generated,hence take 2„s complement of the result -------------------
and attach –ve sign to it.i.e 001101+1=001110
001110
Therefore the answer is -0011

5.6 BOOLEAN ALGEBRA THEOREMS

Symbolic Logic
Boolean algebra derives its name from the mathematician George Boole. Symbolic Logic uses values,
variables and operations
True is represented by the value 1. False is represented by the value 0.:
Variables are represented by letters and can have one of two values, either 0 or 1. Operations are
functions of one or more variables

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AND is represented by X.Y OR is represented by X + Y

NOT is represented by X' . Throughout this tutorial the X' form will be used and sometime !X
will be used.
These basic operations can be combined to give expressions
Example :X X.Y W.X.Y + Z
Precedence
As with any other branch of mathematics, these operators have an order of precedence. NOT operations
have the highest precedence, followed by AND operations, followed by OR operations. Brackets can be
used as with other forms of algebra. e.g.
X.Y + Z and X.(Y + Z) are not the same function
Function Definitions
The logic operations given previously are defined as follows :
Define f(X,Y) to be some function of the variables X and Y.
f(X,Y) = X.Y
f(X,Y) = X.Y
1 if X = 1 and Y = 1
0 Otherwise
f(X,Y) = X + Y
1 if X = 1 or Y = 1
0 Otherwise
f(X) = X'
1 if X = 0
0 Otherwise
Boolean Switching Algebras
A Boolean Switching Algebra is one which deals only with two-valued variables. Boole's general theory
covers algebras which deal with variables which can hold n values.
Identity :- X + 0 = X, X.1=X
Commutative Laws : X + Y = Y + X,
Distributive Laws : X.(Y + Z ) = X.Y + X.Z,

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Complement : X + X' = 1, X . X' = 0,

The complement X' is unique.
Idempotent Law : X + X = X, X . X = X
X + Y.Z = (X + Y) . (X + Z)
Boundedness Law: X + 1 = 1: X.0=0
Absorption Law : X + (X . Y) = X: X . (X + Y ) = X
Elimination Law : X + (X' . Y) = X + Y, X.(X' + Y) = X.Y

Involution theorem : X'' = X

5.7 DIGITAL CIRCUITS

5.7.1 Logic Gates

A logic gate is an electronic circuit/device which makes the logical decisions. To arrive at this
decisions, the most common logic gates used are OR, AND, NOT, NAND, and NOR gates. The
NAND and NOR gates are called universal gates. The exclusive-OR gate is another logic gate
which can be constructed using AND, OR and NOT gate.
Logic gates have one or more inputs and only one output. The output is active only for certain
input combinations. Logic gates are the building blocks of any digital circuit. Logic gates are also
called switches. With the advent of integrated circuits, switches have been replaced by
TTL (Transistor Transistor Logic) circuits and CMOS circuits. Here I give example circuits on
how to construct simples gates.

Symbolic Logic
Boolean algebra derives its name from the mathematician George Boole. Symbolic Logic uses
values, variables and operations.

Inversion
A small circle on an input or an output indicates inversion. See the NOT, NAND and NOR gates
given below for examples.

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Figure 3.2 Inverter

Multiple Input Gates
Given commutative and associative laws, many logic gates can be implemented with more than two
inputs, and for reasons of space in circuits, usually multiple input, complex gates are made. You will
encounter such gates in real world (maybe you could analyze an ASIC lib to find this)
AND Gate
The AND gate performs logical multiplication, commonly known as AND function. The AND gate has
two or more inputs and single output. The output of AND gate is HIGH only when all its inputs are
HIGH (i.e. even if one input is LOW, Output will be LOW).
If X and Y are two inputs, then output F can be represented mathematically as F = X.Y, Here dot (.)
denotes the AND operation. Truth table and symbol of the AND gate is shown in the Figure below.
Symbol

Figure. 3.3 AND Gate

Truth Table
X Y F
0 0 0
0 1 0
1 0 0
1 1 1

Two input AND gate using "diode-resistor" logic is shown in Figure below, where X, Y are inputs and F
is the output

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Figure 3.4 Diode resistor logic

If X = 0 and Y = 0, then both diodes D1 and D2 are forward biased and thus both diodes conduct and
pull F low.
If X = 0 and Y = 1, D2 is reverse biased, thus does not conduct. But D1 is forward biased, thus conducts
and thus pulls F low
If X = 1 and Y = 0, D1 is reverse biased, thus does not conduct. But D2 is forward biased, thus conducts
and thus pulls F low.
If X = 1 and Y = 1, then both diodes D1 and D2 are reverse biased and thus both the diodes are in cut-off
and thus there is no drop in voltage at F. Thus F is HIGH.
Switch Representation of AND Gate
In the Figure below, X and Y are two switches which have been connected in series (or just cascaded)
with the load LED and source battery. When both switches are closed, current flows to LED.

Figure 3.5 Switch representation

OR Gate
The OR gate performs logical addition, commonly known as OR function. The OR gate has two or more

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inputs and single output. The output of OR gate is HIGH only when any one of its inputs are HIGH (i.e.
even if one input is HIGH, Output will be HIGH)
If X and Y are two inputs, then output F can be represented mathematically as F = X+Y. Here plus sign
(+) denotes the OR operation. Truth table and symbol of the OR gate is shown in the Figure below.
Symbol

Figure 3.6 OR Gate

Truth Table
X Y F
0 0 0

0 1 1

1 0 1

1 1 1

Circuit

Figure. 3.7 Circuit Representation

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If X = 0 and Y = 0, then both diodes D1 and D2 are reverse biased and thus both the diodes are in cut-off
and thus F is low
If X = 0 and Y = 1, D1 is reverse biased, thus does not conduct. But D2 is forward biased, thus conducts
and thus pulling F to HIGH.
If X = 1 and Y = 0, D2 is reverse biased, thus does not conduct. But D1 is forward biased, thus conducts
and thus pulling F to HIGH.
If X = 1 and Y = 1, then both diodes D1 and D2 are forward biased and thus both the diodes conduct and
thus F is HIGH.
Switch Representation of OR Gate
In the Figure, X and Y are two switches which have been connected in parallel, and this is connected in
series with the load LED and source battery. When both switches are open, current does not flow to
LED, but when any switch is closed then current flows.

Figure 3.8 Switch representation

NOT Gate
The NOT gate performs the basic logical function called inversion or complementation. NOT gate is also
called inverter. The purpose of this gate is to convert one logic level into the opposite logic level. It has
one input and one output. When a HIGH level is applied to an inverter, a LOW level appears on its
output and vice versa.
If X is the input, then output F can be represented mathematically as F = X', Here apostrophe (') denotes
the NOT (inversion) operation. There are a couple of other ways to represent inversion, F= !X, here !
represents inversion. Truth table and NOT gate symbol is shown in the Figure below

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Figure 3.9 NOT Gate

Truth Table
X F
0 1
1 0

NOT gate using "transistor-resistor" logic is shown in the Figure below, where X is the input and F is the
output

Figure. 3.10 Transistor resistor logic

When X = 1, The transistor input pin 1 is HIGH, this produces the forward bias across the emitter base
junction and so the transistor conducts. As the collector current flows, the voltage drop across RL
increases and hence F is LOW.
When X = 0, the transistor input pin 2 is LOW: this produces no bias voltage across the transistor base
emitter junction. Thus Voltage at F is HIGH.

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NAND Gate
NAND gate is a cascade of AND gate and NOT gate, as shown in the Figure below. It has two or more
inputs and only one output. The output of NAND gate is HIGH when any one of its input is LOW (i.e.
even if one input is LOW, Output will be HIGH).
NAND From AND and NOT

Figure.3.11 NAND gate realization from AND and NOT

If X and Y are two inputs, then output F can be represented mathematically as F = (X.Y)', Here dot (.)
denotes the AND operation and (') denotes inversion. Truth table and symbol of the N AND gate is
shown in the Figure below.
Symbol

Figure. 3.12 NAND Gate

Truth table

X Y F
0 0 1
0 1 1
1 0 1
1 1 1

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NOR Gate
NOR gate is a cascade of OR gate and NOT gate, as shown in the Figure below. It has two or more
inputs and only one output. The output of NOR gate is HIGH when any all its inputs are LOW (i.e. even
if one input is HIGH, output will be LOW)
Symbol

Figure. 3.13 NOR Gate

If X and Y are two inputs, then output F can be represented mathematically as F = (X+Y)'; here plus (+)
denotes the OR operation and (') denotes inversion. Truth table and symbol of the NOR gate is shown in
the Figure below.
Truth Table
X Y F=(X+Y)'
0 0 1
0 1 0
1 0 0
1 1 0

XOR Gate
An Exclusive-OR (XOR) gate is gate with two or three or more inputs and one output. The output of a
two-input XOR gate assumes a HIGH state if one and only one input assumes a HIGH state. This is
equivalent to saying that the output is HIGH if either input X or input Y is HIGH exclusively, and LOW
when both are 1 or 0 simultaneously
If X and Y are two inputs, then output F can be represented mathematically as F = X Y, Here denotes
the XOR operation. X Y and is equivalent to X.Y' + X'.Y. Truth table and symbol of the XOR gate is
shown in the Figure below

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XOR From Simple gates

Figure 3.13 XOR from simple gate

Symbol

Figure.3.14 XOR symbol

Truth Table
X Y F
0 0 1
0 1 0
1 0 0
1 1 1

XNOR Gate
An Exclusive-NOR (XNOR) gate is gate with two or three or more inputs and one output. The output of
a two-input XNOR gate assumes a HIGH state if all the inputs assumes same state. This is equivalent to
saying that the output is HIGH if both input X and input Y is HIGH exclusively or same as input X and
input Y is LOW exclusively, and LOW when both are not same.
If X and Y are two inputs, then output F can be represented mathematically as F= X Y, Here denotes
the XNOR operation. X Y and is equivalent to X.Y + X'.Y'. Truth table and symbol of the XNOR gate
is shown in the Figure below.

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Symbol

Figure. 3.15 XNOR symbol

Truth Table

X Y F=(X Y)'
0 0 1
0 1 0
1 0 0
1 1 1

Universal Gates
Universal gates are the ones which can be used for implementing any gate like AND, OR and NOT, or
any combination of these basic gates; NAND and NOR gates are universal gates. But there are some
rules that need to be followed when implementing NAND or NOR based gate
To facilitate the conversion to NAND and NOR logic, we have two new graphic symbols for these gates
NAND Gate

Figure. 3.16 NAND symbol

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NOR Gate

Figure. 3.15 XNOR symbol

3.7.2 REALIZATION OF LOGICAL EXPRESSIONS USING NAND GATES

Any logic function can be implemented using NAND gates. To achieve this, first the logic function has
to be written in Sum of Product (SOP) form. Once logic function is converted to SOP, then is very easy
to implement using NAND gate. In other words any logic circuit with AND gates in first level and OR
gates in second level can be converted into a NAND-NAND gate circuit.
Consider the following SOP expression
F = W.X.Y + X.Y.Z + Y.Z.
The above expression can be implemented with three AND gates in first stage and one OR gate in
second stage as shown in Figure

If bubbles are introduced at AND gates output and OR gates inputs (the same for NOR gates), the above
circuit becomes as shown in Figure

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Now replace OR gate with input bubble with the NAND gate. Now we have circuit which is fully
implemented with just NAND gates.

Realization of logic gates using NAND gates

Implementing an inverter using NAND gate
Input Output Rule
(X.X)' = X' Idempotent

Implementing AND using NAND gates

Input Output Rule
((XY)'(XY)')' = ((XY)')' Idempotent
= (XY) Involution

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Implementing OR using NAND gates

Input Output Rule

((XX)'(YY)')' = (X'Y')' Idempotent

= X''+Y'' DeMorgan
= X+Y Involution

Implementing NOR using NAND gates

Input Output Rule

((XX)'(YY)')' =(X'Y')' Idempotent

=X''+Y'' DeMorgan
=X+Y Involution
=(X+Y)' Idempotent

5.7.3 REALIZATION OF LOGICAL EXPRESSIONS USING NOR GATES

Any logic function can be implemented using NOR gates. To achieve this, first the logic function has to
be written in Product of Sum (POS) form. Once it is converted to POS, then it's very easy to implement
using NOR gate. In other words any logic circuit with OR gates in first level and AND gates in second
level can be converted into a NOR-NOR gate circuit.

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Consider the following POS expression

F = (X+Y) (Y+Z)
Input Output Rule The
abov
e expression can be implemented with three OR gates in first stage and one AND gate in second stage as
shown in Figure.

If bubble are introduced at the output of the OR gates and the inputs of AND gate, the above circuit
becomes as shown in Figure.

Now replace AND gate with input bubble with the NOR gate. Now we have circuit which is fully
implemented with just NOR gates.

Realization of logic gates using NOR gates

Implementing an inverter using NOR gate

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(X+X)' = X' Idempotent

Implementing AND using NOR gates

Output Rule
((X+X)'+(Y+Y)')' =(X'+Y')' Idempotent
= X''.Y'' DeMorgan
= (X.Y) Involution

Implementing OR using NOR gates

Input Output Rule

((X+Y)'+(X+Y)')' = ((X+Y)')' Idempotent

= X+Y Involution

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Implementing NAND using NOR gates

Input Output Rule

((X+Y)'+(X+Y)')' = ((X+Y)')' Idempotent
= X+Y Involution
= (X+Y)' Idempotent

Arithmetic circuits are the ones which perform arithmetic operations like addition, subtraction,
multiplication, division, parity calculation. Most of the time, designing these circuits is the same as
designing muxers, encoders and decoders.
In the next few pages we will see few of these circuits in detail.

5.7.4 HALF ADDERS AND FULL ADDER

Adders are the basic building blocks of all arithmetic circuits; adders add two binary numbers and give
out sum and carry as output. Basically we have two types of adders
Half Adder
Adding two single-bit binary values X, Y produces a sum S bit and a carry out C-out bit. This operation
is called half addition and the circuit to realize it is called a half adder.
Truth Table
X Y SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
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Symbol

S (X,Y) = (1,2)
S = X'Y + XY'
S=X Y
CARRY(X,Y) = (3)
CARRY = XY
Circuit

Full Adder
Full adder takes a three-bits input. Adding two single-bit binary values X, Y with a carry input bit C-in
produces a sum bit S and a carry out C-out bit.
Truth Table
X Y Z SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
SUM (X,Y,Z) = (1,2,4,7)
CARRY (X,Y,Z) = (3,5,6,7)
Full Adder using AND-OR
The below implementation shows implementing the full adder with AND-OR gates, instead of

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using XOR gates. The basis of the circuit below is from the above Kmap.
Circuit-SUM

Circuit-CARRY

Full Adder using AND-OR

Circuit-SUM

Circuit-CARRY

5.8 FLIPFLOPS
Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one
bit of information. The main difference between latches and flip-flops is that for latches, their outputs
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are constantly affected by their inputs as long as the enable signal is asserted. In other words, when they
are enabled, their content changes immediately when their inputs change. Flip-flops, on the other hand,
have their content change only either at the rising or falling edge of the enable signal. This enable signal
is usually the controlling clock signal. After the rising or falling edge of the clock, the flip-flop content
remains constant even if the input changes. There are basically four main types of latches and flip-flops:
SR, D, JK, and T. The major differences in these flip-flop types are the number of inputs they have and
how they change state. For each type, there are also different variations that enhance their operations.
The simplest sequential circuit or storage element is a bistable element, which is constructed with two
inverters connected sequentially in a loop as shown in Figure . It has no inputs and two outputs labeled
Q and Q‟. Since the circuit has no inputs, we cannot change the values of Q and Q‟. However, Q will
take on whatever value it happens to be when the circuit is first powered up. Assume that Q = 0 when
we switch on the power. Since Q is also the input to the bottom inverter, Q‟, therefore, is a 1. A 1 going
to the input of the top inverter will produce a 0 at the output Q, which is what we started off with.
Similarly, if we start the circuit with Q = 1, we will get Q‟ = 0, and again we get a stable situation. A
bistable element has memory in the sense that it can remember the content (or state) of the circuit
indefinitely. Using the signal Q as the state variable to describe the state of the circuit, we can say that
the circuit has two stable states: Q = 0, and Q = 1; hence the name “bistable.”

Fig Bistable Element

5.8.1 S R FLIPFLOP

The R-S (Reset Set) flip flop is the simplest flip flop of all and easiest to understand. It is basically a
device which has two outputs one output being the inverse or complement of the other, and two inputs.
A pulse on one of the inputs to take on a particular logical state. The outputs will then remain in this

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state until a similar pulse is applied to the other input. The two inputs are called the Set and Reset input
(sometimes called the preset and clear inputs).

Such flip flop can be made simply by cross coupling two inverting gates either NAND or NOR gate
could be used Figure (a) shows on RS flip flop using NAND gate and Figure (b) shows the same circuit
using NOR gate

Figure : Latch R-S Flip Flop Using NAND and NOR Gates

To describe the circuit of Figure 4.6(a), assume that initially both R and S are at the logic 1 state and
that output is at the logic 0 state.

Now, if Q = 0 and R = 1, then these are the states of inputs of gate B, therefore the outputs of gate B is
at 1 (making it the inverse of Q i.e. 0). The output of gate B is connected to an input of gate A so if S =
1, both inputs of gate A are at the logic 1 state. This means that the output of gate A must be 0 (as was
originally specified). In other words, the 0 state at Q is continuously disabling gate B so that any change

in R has no effect. Also the 1 state at is continuously enabling gate A so that any change S will be
transmitted through to Q. The above conditions constitute one of the stable states of the device referred
to as the Reset state since Q = 0.

Now suppose that the R-S flip flop in the Reset state, the S input goes to 0. The output of gate A i.e. Q
will go to 1 and with Q = 1 and R = 1, the output of gates B ( ) will go to 0 with now 0 gate A is
disabled keeping Q at 1. Consequently, when S returns to the 1 state it has no effect on the flip flop

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whereas a change in R will cause a change in the output of gate B. The above conditions constitute the
other stable state of the device, called the Set state since Q = 1. Note that the change of the state of S
from 1 to 0 has caused the flip flop to change from the Reset state to the Set state.

There is another input condition which has not yet been considered. That is when both the R and S

inputs are taken to the logic state 0. When this happens both Q and will be forced to 1 and will remain
so far as long as R and S are kept at 0. However when both inputs return to 1 there is no way of
knowing whether the flip flop will latch in the Reset state or the Set state. The condition is said to be
indeterminate because of this indeterminate state great care must be taken when using R-S flip flop to
ensure that both inputs are not instructed simultaneously.

Table 1: The truth table for the NAND R-S flip flop

Initial Conditions Inputs (Pulsed) Final Output

Q S R Q

1 0 0 indeterminate

1 0 1 1 0

1 1 0 0 1

1 1 1 1 0

0 0 0 indeterminate

0 0 1 1 0

0 1 0 0 1

0 1 1 0 1

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or more simply shown in Table 2

Table 2: Simple NAND R-S Flip Flop Truth Table

S R Q
0 0 indeterminate

0 1 Set (1)

1 0 Reset(0)

1 1 No Change

When NOR gate are used the R and S inputs are transposed compared with the NAND version. Also the
stable state when R and S are both 0. A change of state is effected by pulsing the appropriate input to
the 1 state. The indeterminate state is now when both R and S are simultaneously at logic 1. Table 3
shows this operation.

Table 3: NOR Gate R-S Flip Flop Truth Table

S R Q
0 0 No Change

0 1 Reset (0)

1 0 Set (1)

1 1 Indeterminate

5.8.2 J K FLIPFLOP

The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to

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logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input combinations,
“logic 1”, “logic 0”, “no change” and “toggle”. The symbol for a JK flip flop is similar to that of an SR
Bistable Latch as seen in the previous tutorial except for the addition of a clock input.

Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs called
the J and K inputs, respectively after its inventor Jack Kilby. Then this equates to: J = S and K = R.

The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-
input NAND gates with the third input of each gate connected to the outputs at Q and Q. This cross
coupling of the SR flip-flop allows the previously invalid condition of S = “1” and R = “1” state to be
used to produce a “toggle action” as the two inputs are now interlocked.

If the circuit is now “SET” the J input is inhibited by the “0” status of Q through the lower NAND gate.
If the circuit is “RESET” the K input is inhibited by the “0” status of Q through the upper NAND gate.
As Q and Q are always different we can use them to control the input. When both inputs J and K are
equal to logic “1”, the JK flip flop toggles as shown in the following truth table.

The Truth Table for the JK Function

Input Output
Description
J K Q Q

0 0 0 0
Memory
same as
no change
for the 0 0 0 1
SR Latch
0 1 1 0
Reset Q » 0
0 1 0 1

1 0 0 1 Set Q » 1

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1 0 1 0

1 1 0 1
toggle
Toggle
action
1 1 1 0

Then the JK flip-flop is basically an SR flip flop with feedback which enables only one of its two input
terminals, either SET or RESET to be active at any one time thereby eliminating the invalid condition
seen previously in the SR flip flop circuit.

Also when both the J and the K inputs are at logic level “1” at the same time, and the clock input is
pulsed “HIGH”, the circuit will “toggle” from its SET state to a RESET state, or visa-versa. This results
in the JK flip flop acting more like a T-type toggle flip-flop when both terminals are “HIGH”.

Although this circuit is an improvement on the clocked SR flip-flop it still suffers from timing problems
called “race” if the output Q changes state before the timing pulse of the clock input has time to go
“OFF”. To avoid this the timing pulse period ( T ) must be kept as short as possible (high frequency).
As this is sometimes not possible with modern TTL IC‟s the much improved Master-Slave JK Flip-
flop was developed.

5.8.3 Shift register

We know that one flip-flop can store one-bit of information. In order to store multiple bits of

information, we require multiple flip-flops. The group of flip-flops, which are used to hold (store) the
binary data is known as register.

If the register is capable of shifting bits either towards right hand side or towards left hand side is

known as shift register. An „N‟ bit shift register contains „N‟ flip-flops. Following are the four types of
shift registers based on applying inputs and accessing of outputs.

 Serial In - Serial Out shift register

 Serial In - Parallel Out shift register

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 Parallel In - Serial Out shift register

 Parallel In - Parallel Out shift register

Serial In - Serial Out (SISO) Shift Register

The shift register, which allows serial input and produces serial output is known as Serial In – Serial

Out (SISO) shift register. The block diagram of 3-bit SISO shift register is shown in the following
figure.

This block diagram consists of three D flip-flops, which are cascaded. That means, output of one D flip-

flop is connected as the input of next D flip-flop. All these flip-flops are synchronous with each other
since, the same clock signal is applied to each one.

In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this

input is also called as serial input. For every positive edge triggering of clock signal, the data shifts

from one stage to the next. So, we can receive the bits serially from the output of right most D flip-flop.
Hence, this output is also called as serial output.

Example

Let us see the working of 3-bit SISO shift register by sending the binary information “011” from LSB
to MSB serially at the input.

Assume, initial status of the D flip-flops from leftmost to rightmost is Q2Q1Q0=000Q2Q1Q0=000. We

can understand the working of 3-bit SISO shift register from the following table.

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No of positive edge of Clock Serial Input Q2 Q1 Q0

0 - 0 0 0

1 1(LSB) 1 0 0

2 1 1 1 0

3 0(MSB) 0 1 1(LSB)

4 - - 0 1

5 - - - 0(MSB)

The initial status of the D flip-flops in the absence of clock signal is Q2Q1Q0=000Q2Q1Q0=000.

Here, the serial output is coming from Q0Q0. So, the LSB (1) is received at 3rd positive edge of clock

and the MSB (0) is received at 5thpositive edge of clock.

Therefore, the 3-bit SISO shift register requires five clock pulses in order to produce the valid output.
Similarly, the N-bit SISO shift register requires 2N-1 clock pulses in order to shift „N‟ bit information.

Serial In - Parallel Out (SIPO) Shift Register

The shift register, which allows serial input and produces parallel output is known as Serial In –

Parallel Out (SIPO) shift register. The block diagram of 3-bit SIPO shift register is shown in the
following figure.

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This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is

connected as the input of next D flip-flop. All these flip-flops are synchronous with each other since,
the same clock signal is applied to each one.

In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this

input is also called as serial input. For every positive edge triggering of clock signal, the data shifts

from one stage to the next. In this case, we can access the outputs of each D flip-flop in parallel. So, we
will get parallel outputs from this shift register.

Example

Let us see the working of 3-bit SIPO shift register by sending the binary information “011” from LSB
to MSB serially at the input.

Assume, initial status of the D flip-flops from leftmost to rightmost is Q2Q1Q0=000Q2Q1Q0=000.

Here, Q2Q2 & Q0Q0 are MSB & LSB respectively. We can understand the working of 3-bit SIPO

shift register from the following table.

No of positive edge of Serial Input Q2(MSB) Q1 Q0(LSB)
Clock

0 - 0 0 0

1 1(LSB) 1 0 0

2 1 1 1 0

3 0(MSB) 0 1 1

The initial status of the D flip-flops in the absence of clock signal is Q2Q1Q0=000Q2Q1Q0=000. The

binary information “011” is obtained in parallel at the outputs of D flip-flops for third positive edge of

clock.

So, the 3-bit SIPO shift register requires three clock pulses in order to produce the valid output. Similarly,
the N-bit SIPO shift register requires N clock pulses in order to shift „N‟ bit information.

Parallel In - Serial Out (PISO) Shift Register

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The shift register, which allows parallel input and produces serial output is known as Parallel In – Serial
Out (PISO) shift register. The block diagram of 3-bit PISO shift register is shown in the following figure.

This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is

connected as the input of next D flip-flop. All these flip-flops are synchronous with each other since, the
same clock signal is applied to each one.

In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1.

For every positive edge triggering of clock signal, the data shifts from one stage to the next. So, we will
get the serial outputfrom the right most D flip-flop.

Example

Let us see the working of 3-bit PISO shift register by applying the binary information “011” in parallel
through preset inputs.

Since the preset inputs are applied before positive edge of Clock, the initial status of the D flip-flops

from leftmost to rightmost will be Q2Q1Q0=011Q2Q1Q0=011. We can understand the working of 3-bit

PISO shift register from the following table.

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Q2 Q1 Q0
No of positive edge of Clock

0 0 1 1(LSB)

1 - 0 1

2 - - 0(LSB)

Here, the serial output is coming from Q0Q0. So, the LSB (1) is received before applying positive edge

of clock and the MSB (0) is received at 2nd positive edge of clock.

Therefore, the 3-bit PISO shift register requires two clock pulses in order to produce the valid output.
Similarly, the N-bit PISO shift register requires N-1 clock pulses in order to shift „N‟ bit information.

Parallel In - Parallel Out (PIPO) Shift Register

The shift register, which allows parallel input and produces parallel output is known as Parallel In −

Parallel Out (PIPO) shift register. The block diagramof 3-bit PIPO shift register is shown in the
following figure.

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This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is

connected as the input of next D flip-flop. All these flip-flops are synchronous with each other since,
the same clock signal is applied to each one.

In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1.

We can apply the parallel inputs through preset or clear. These two are asynchronous inputs. That

means, the flip-flops produce the corresponding outputs, based on the values of asynchronous inputs.

In this case, the effect of outputs is independent of clock transition. So, we will get the parallel
outputs from each D flip-flop.

Example

Let us see the working of 3-bit PIPO shift register by applying the binary information “011” in parallel
through preset inputs.

Since the preset inputs are applied before positive edge of Clock, the initial status of the D flip-flops

from leftmost to rightmost will be Q2Q1Q0=011Q2Q1Q0=011. So, the binary information “011” is

obtained in parallel at the outputs of D flip-flops before applying positive edge of clock.

Therefore, the 3-bit PIPO shift register requires zero clock pulses in order to produce the valid output.

Similarly, the N-bit PIPO shift register doesn‟t require any clock pulse in order to shift „N‟ bit
information.

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