ATmega328P

8-bit AVR Microcontroller with 32K Bytes In-System

Programmable Flash

DATASHEET

Features

● High performance, low power AVR® 8-bit microcontroller

● Advanced RISC architecture
● 131 powerful instructions – most single clock cycle execution
● 32  8 general purpose working registers
● Fully static operation
● Up to 16MIPS throughput at 16MHz
● On-chip 2-cycle multiplier
● High endurance non-volatile memory segments
● 32K bytes of in-system self-programmable flash program memory
● 1Kbytes EEPROM
● 2Kbytes internal SRAM
● Write/erase cycles: 10,000 flash/100,000 EEPROM
● Optional boot code section with independent lock bits
● In-system programming by on-chip boot program
● True read-while-write operation
● Programming lock for software security
● Peripheral features
● Two 8-bit Timer/Counters with separate prescaler and compare mode
● One 16-bit Timer/Counter with separate prescaler, compare mode, and capture
mode
● Real time counter with separate oscillator
● Six PWM channels
● 8-channel 10-bit ADC in TQFP and QFN/MLF package
● Temperature measurement
● Programmable serial USART
● Master/slave SPI serial interface
● Byte-oriented 2-wire serial interface (Phillips I2C compatible)
● Programmable watchdog timer with separate on-chip oscillator
● On-chip analog comparator
● Interrupt and wake-up on pin change
● Special microcontroller features
● Power-on reset and programmable brown-out detection
● Internal calibrated oscillator
● External and internal interrupt sources
● Six sleep modes: Idle, ADC noise reduction, power-save, power-down, standby,
and extended standby

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● I/O and packages
● 23 programmable I/O lines
● 32-lead TQFP, and 32-pad QFN/MLF
● Operating voltage:
● 2.7V to 5.5V for ATmega328P
● Temperature range:
● Automotive temperature range: –40°C to +125°C
● Speed grade:
● 0 to 8MHz at 2.7 to 5.5V (automotive temperature range: –40°C to +125°C)
● 0 to 16MHz at 4.5 to 5.5V (automotive temperature range: –40°C to +125°C)
● Low power consumption
● Active mode: 1.5mA at 3V - 4MHz
● Power-down mode: 1µA at 3V

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1. Pin Configurations

Figure 1-1. Pinout

TQFP Top View

PC4 (ADC4/SDA/PCINT12)
PC5 (ADC5/SCL/PCINT13)
PC6 (RESET/PCINT14)

PC2 (ADC2/PCINT10)
PC3 (ADC3/PCINT11)
PD2 (INT0/PCINT18)

PD0 (RXD/PCINT16)
PD1 (TXD/PCINT17)

32 31 30 29 28 27 26 25

(PCINT19/OC2B/INT1) PD3 1 24 PC1 (ADC1/PCINT9)

(PCINT20/XCK/T0) PD4 2 23 PC0 (ADC0/PCINT8)
GND 3 22 ADC7
VCC 4 21 GND
GND 5 20 AREF
VCC 6 19 ADC6
(PCINT6/XTAL1/TOSC1) PB6 7 18 AVCC
(PCINT7/XTAL2/TOSC2) PB7 8 17 PB5 (SCK/PCINT5)

9 10 11 12 13 14 15 16
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4

32 MLF Top View

PC4 (ADC4/SDA/PCINT12)
PC5 (ADC5/SCL/PCINT13)
PC6 (RESET/PCINT14)

PC2 (ADC2/PCINT10)
PC3 (ADC3/PCINT11)
PD2 (INT0/PCINT18)

PD0 (RXD/PCINT16)
PD1 (TXD/PCINT17)

32 31 30 29 28 27 26 25

(PCINT19/OC2B/INT1) PD3 1 24 PC1 (ADC1/PCINT9)

(PCINT20/XCK/T0) PD4 2 23 PC0 (ADC0/PCINT8)
GND 3 22 ADC7
VCC 4 21 GND
GND 5 20 AREF
VCC 6 19 ADC6
(PCINT6/XTAL1/TOSC1) PB6 7 18 AVCC
(PCINT7/XTAL2/TOSC2) PB7 8 17 PB5 (SCK/PCINT5)

9 10 11 12 13 14 15 16
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4

NOTE: Bottom pad should be soldered to ground.

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1.1 Pin Descriptions

1.1.1 VCC
Digital supply voltage.

1.1.2 GND
Ground.

1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have
symmetrical drive characteristics with both high sink and source capability. As inputs, port B pins that are externally pulled
low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting oscillator amplifier.
If the internal calibrated RC oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the asynchronous
Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of port B are elaborated in Section 13.3.1 “Alternate Functions of Port B” on page 65 and
Section 8. “System Clock and Clock Options” on page 24.

1.1.4 Port C (PC5:0)

Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5..0 output buffers have
symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled
low will source current if the pull-up resistors are activated. The port C pins are tri-stated when a reset condition becomes
active, even if the clock is not running.

1.1.5 PC6/RESET
If the RSTDISBL fuse is programmed, PC6 is used as an input pin. If the RSTDISBL fuse is unprogrammed, PC6 is used as
a reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not
running. The minimum pulse length is given in Table 28-4 on page 261. Shorter pulses are not guaranteed to generate a
reset.
The various special features of port C are elaborated in Section 13.3.2 “Alternate Functions of Port C” on page 68.

1.1.6 Port D (PD7:0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The port D output buffers have
symmetrical drive characteristics with both high sink and source capability. As inputs, port D pins that are externally pulled
low will source current if the pull-up resistors are activated. The port D pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
The various special features of port D are elaborated in Section 13.3.3 “Alternate Functions of Port D” on page 70.

1.1.7 AVCC
AVCC is the supply voltage pin for the A/D converter, PC3:0, and ADC7:6. It should be externally connected to VCC, even if
the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that PC6..4 use digital
supply voltage, VCC.

1.1.8 AREF
AREF is the analog reference pin for the A/D converter.

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1.1.9 ADC7:6 (TQFP and QFN/MLF Package Only)
In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the
analog supply and serve as 10-bit ADC channels.

1.2 Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of actual ATmega328P AVR®
microcontrollers manufactured on the typical process technology. automotive min and max values are based on
characterization of actual ATmega328P AVR microcontrollers manufactured on the whole process excursion (corner run).

1.3 Automotive Quality Grade

The ATmega328P have been developed and manufactured according to the most stringent requirements of the international
standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive characterization
(temperature and voltage). The quality and reliability of the ATmega328P have been verified during regular product
qualification as per AEC-Q100 grade 1. As indicated in the ordering information paragraph, the products are available in only
one temperature.

Table 1-1. Temperature Grade Identification for Automotive Products

Temperature Temperature Identifier Comments

–40°C; +125°C Z Full automotive temperature range

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2. Overview
The Atmel® ATmega328P is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATmega328P achieves throughputs approaching 1MIPS per MHz
allowing the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

GND VCC

Watchdog
Power debugWIRE
Timer
Supervision
POR/ BOD
and
Watchdog RESET Program
Oscillator Logic

Oscillator
Circuits/ Flash SRAM
Clock
Generation

AVR CPU
EEPROM

AVCC

AREF

GND
2
8-bit T/C 0 16-bit T/C 1 A/D Conv.
DATA BUS

Analog Internal 6
8-bit T/C 2 Comp. Bandgap

USART 0 SPI TWI

PORT D (8) PORT B (8) PORT C (7)

RESET

XTAL[1..2]

PD[0..7] PB[0..7] PC[0..6] ADC[6..7]

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The AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
The Atmel® ATmega328P provides the following features: 32K bytes of in-system programmable flash with read-while-write
capabilities, 1K bytes EEPROM, 2K bytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three
flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte-
oriented 2-wire serial interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a
programmable watchdog timer with internal oscillator, and five software selectable power saving modes. The idle mode
stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire serial interface, SPI port, and interrupt system to
continue functioning. The power-down mode saves the register contents but freezes the oscillator, disabling all other chip
functions until the next interrupt or hardware reset. In power-save mode, the asynchronous timer continues to run, allowing
the user to maintain a timer base while the rest of the device is sleeping. The ADC noise reduction mode stops the CPU and
all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In standby
mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low power consumption.
The device is manufactured using Atmel high density non-volatile memory technology. The on-chip ISP flash allows the
program memory to be reprogrammed in-system through an SPI serial interface, by a conventional non-volatile memory
programmer, or by an on-chip boot program running on the AVR core. The boot program can use any interface to download
the application program in the application flash memory. Software in the boot flash section will continue to run while the
application flash section is updated, providing true read-while-write operation. By combining an 8-bit RISC CPU with
in-system self-programmable flash on a monolithic chip, the Atmel ATmega328P is a powerful microcontroller that provides
a highly flexible and cost effective solution to many embedded control applications.
The ATmega328P AVR is supported with a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

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3. Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.

4. Data Retention
Reliability qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at
85°C or 100 years at 25°C.

5. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. These code
examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors
include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C
compiler documentation for more details.
For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced
with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and
“CBR”.

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6. AVR CPU Core

6.1 Overview
This section discusses the AVR® core architecture in general. The main function of the CPU core is to ensure correct
program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and
handle interrupts.

Figure 6-1. Block Diagram of the AVR Architecture

Data Bus 8-bit

Flash Program Status and

Program Counter Control
Memory

Interrupt
32 x 8
Unit
General
Instruction
Purpose
Register
Registers SPI
Indirect Addressing Unit

Instruction
Direct Addressing

Decoder Watchdog
ALU Timer

Control Lines Analog

Comparator

I/O Module 1
Data
SRAM
I/O Module 2

I/O Module n
EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a harvard architecture – with separate memories and
buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions
to be executed in every clock cycle. The program memory is in-system reprogrammable flash memory.

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 The fast-access register file contains 32  8-bit general purpose working registers with a single clock cycle access time. This
allows single-cycle arithmetic logic unit (ALU) operation. In a typical ALU operation, two operands are output from the
register file, the operation is executed, and the result is stored back in the register file – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling
efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in
flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register
operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect
information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole
address space. Most AVR® instructions have a single 16-bit word format. Every program memory address contains a 16- or
32-bit instruction.
Program flash memory space is divided in two sections, the boot program section and the application program section. Both
sections have dedicated lock bits for write and read/write protection. The SPM instruction that writes into the application flash
memory section must reside in the boot program section.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and
the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are
executed). The stack pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through
the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance
with their interrupt vector position. The lower the interrupt vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, SPI, and other I/O functions.
The I/O memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5F. In
addition, the ATmega328P has extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and
LD/LDS/LDD instructions can be used.

6.2 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a
single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are
executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some
implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and
fractional format. See Section “” on page 281 for a detailed description.

6.3 Status Register

The status register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the status register is
updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for
using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine and restored when returning from an
interrupt. This must be handled by software.

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6.3.1 SREG – AVR Status Register
The AVR status register – SREG – is defined as:
Bit 7 6 5 4 3 2 1 0
0x3F (0x5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – I: Global Interrupt Enable

The global interrupt enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then
performed in separate control registers. If the global interrupt enable register is cleared, none of the interrupts are enabled
independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is
set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the
SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The bit copy instructions BLD (bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit
from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a
register in the register file by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The half carry flag H indicates a half carry in some arithmetic operations. Half carry Is useful in BCD arithmetic. See Section
“” on page 281 for detailed information.

• Bit 4 – S: Sign Bit, S = N V

The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See Section “”
on page 281 for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The two’s complement overflow flag V supports two’s complement arithmetics. See Section “” on page 281 for detailed
information.

• Bit 2 – N: Negative Flag

The negative flag N indicates a negative result in an arithmetic or logic operation. See Section “” on page 281 for detailed
information.

• Bit 1 – Z: Zero Flag

The zero flag Z indicates a zero result in an arithmetic or logic operation. See Section “” on page 281 for detailed
information.

• Bit 0 – C: Carry Flag

The carry flag C indicates a carry in an arithmetic or logic operation. See Section “” on page 281 for detailed information.

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6.4 General Purpose Register File
The register file is optimized for the AVR® enhanced RISC instruction set. In order to achieve the required performance and
flexibility, the following input/output schemes are supported by the register file:
● One 8-bit output operand and one 8-bit result input
● Two 8-bit output operands and one 8-bit result input
● Two 8-bit output operands and one 16-bit result input
● One 16-bit output operand and one 16-bit result input
Figure 6-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 6-2. AVR CPU General Purpose Working Registers

7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte

Most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle
instructions.
As shown in Figure 6-2, each register is also assigned a data memory address, mapping them directly into the first 32
locations of the user data space. Although not being physically implemented as SRAM locations, this memory organization
provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the
file.

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6.4.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address
pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described
in Figure 6-3.

Figure 6-3. The X-, Y-, and Z-registers

15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)

15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)

15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and
automatic decrement (see the instruction set reference for details).

6.5 Stack Pointer

The stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after
interrupts and subroutine calls. Note that the stack is implemented as growing from higher to lower memory locations. The
stack pointer register always points to the top of the stack. The stack pointer points to the data SRAM stack area where the
subroutine and interrupt stacks are located. A stack PUSH command will decrease the stack pointer.
The stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are
enabled. initial stack pointer value equals the last address of the internal SRAM and the stack pointer must be set to point
above start of the SRAM, see Figure 7-2 on page 18.
See Table 6-1 for stack pointer details.

Table 6-1. Stack Pointer instructions

Instruction Stack pointer Description
PUSH Decremented by 1 Data is pushed onto the stack
CALL
ICALL Decremented by 2 Return address is pushed onto the stack with a subroutine call or interrupt
RCALL
POP Incremented by 1 Data is popped from the stack
RET Return address is popped from the stack with return from subroutine or return
Incremented by 2
RETI from interrupt

The AVR stack pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent. Note that the data space in some implementations of the AVR® architecture is so small that only
SPL is needed. In this case, the SPH register will not be present.

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6.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register
Bit 15 14 13 12 11 10 9 8
0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
7 6 5 4 3 2 1 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND

6.6 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR® CPU is driven by the CPU
clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the harvard architecture and the
fast-access register file concept. This is the basic pipelining concept to obtain up to 1MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 6-4. The Parallel Instruction Fetches and Instruction Executions

T1 T2 T3 T4
clkCPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch

Figure 6-5 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register
operands is executed, and the result is stored back to the destination register.

Figure 6-5. Single Cycle ALU Operation

T1 T2 T3 T4

clkCPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

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6.7 Reset and Interrupt Handling
The AVR® provides several different interrupt sources. These interrupts and the separate reset vector each have a separate
program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic
one together with the global interrupt enable bit in the status register in order to enable the interrupt. Depending on the
program counter value, interrupts may be automatically disabled when boot lock bits BLB02 or BLB12 are programmed. This
feature improves software security. See the Section 27. “Memory Programming” on page 241 for details.
The lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. The complete
list of vectors is shown in Section 11. “Interrupts” on page 49. The list also determines the priority levels of the different
interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the
external interrupt request 0. The interrupt vectors can be moved to the start of the boot flash section by setting the IVSEL bit
in the MCU control register (MCUCR). Refer to Section 11. “Interrupts” on page 49 for more information. The reset vector can
also be moved to the start of the boot flash section by programming the BOOTRST fuse, see Section 26. “Boot Loader
Support – Read-While-Write Self-Programming” on page 229.
When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The user software can
write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine.
The I-bit is automatically set when a return from interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these
interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine,
and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit
position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt
flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more
interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and
remembered until the global interrupt enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily
have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any
pending interrupt is served.
Note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from
an interrupt routine. This must be handled by software.

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 When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed
after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can
be used to avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending
interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */

6.7.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR® interrupts is four clock cycles minimum. After four clock cycles the
program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the program
counter is pushed onto the stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock
cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is
served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four
clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the program counter (two
bytes) is popped back from the stack, the stack pointer is incremented by two, and the I-bit in SREG is set.

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7. AVR Memories

7.1 Overview
This section describes the different memories in the ATmega328P. The AVR® architecture has two main memory spaces,
the data memory and the program memory space. In addition, the ATmega328P features an EEPROM memory for data
storage. All three memory spaces are linear and regular.

7.2 In-System Reprogrammable Flash Program Memory

The ATmega328P contains 32Kbytes on-chip in-system reprogrammable flash memory for program storage. Since all AVR
instructions are 16 or 32 bits wide, the flash is organized as 16K 16. For software security, the flash program memory space
is divided into two sections, boot loader section and application program section in ATmega328P. See SELFPRGEN
description in Section 25.3.1 “SPMCSR – Store Program Memory Control and Status Register” on page 228 and Section
26.9.1 “SPMCSR – Store Program Memory Control and Status Register” on page 239 for more details.
The flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega328P program counter (PC) is 14
bits wide, thus addressing the 16K program memory locations. The operation of boot program section and associated boot
lock bits for software protection are described in detail in Section 25. “Self-Programming the Flash, ATmega328P” on page
223 and Section 26. “Boot Loader Support – Read-While-Write Self-Programming” on page 229. Section 27. “Memory
Programming” on page 241 contains a detailed description on flash programming in SPI- or parallel programming mode.
Constant tables can be allocated within the entire program memory address space (see the LPM – load program memory
instruction description).
Timing diagrams for instruction fetch and execution are presented in Section 6.6 “Instruction Execution Timing” on page 14.

Figure 7-1. Program Memory Map ATmega328P

Program Memory
0x0000

Application Flash Section

Boot Flash Section

0x3FFF

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