LBIST designs and test challenges

Saransh Choudhary
[email protected]

1 Introduction
With each passing day, the complexity of modern day SoCs is rising sharply.
The demand for aggressive compute capabilities in post-COVID world, mostly
in the space of Cloud, Connected Devices and (very recently) Edge have been
picking up steam. Ever increasing workloads being run on systems have pushed
engineers, both hardware and software alike, to figure out novel ways of keeping
up with the consumer demands. In the context of hardware designing, engi-
neers always look out for striking the perfect balance within the holy trinity
of semiconductor design : Power, Performance and Area (colloquially termed
PPA). Thus, as important it is to ensure that the SoCs of tomorrow support a
wide range of features, testing them before releasing to the market is equally
critical. With state-of-the-art SoCs integrating several hundreds of intellectual
properties (IPs), to single out any one defective part in actual silicon can be
really challenging.
Along the same lines, Logic built-in self-test (BIST) is a design for testability
(DFT) technique in which a portion of a circuit on a chip, board, or system is
used to test the digital logic circuit itself. Logic BIST is crucial for many
applications, particularly for life critical and mission-critical applications. These
applications commonly found in the aerospace/defense, automotive, banking,
healthcare and other similar industries require on-chip, on-board, or in-system
self-test to improve the reliability of the entire system, as well as the ability to
perform remote diagnosis.

2 Need for LBIST

Traditional test techniques used automatic test pattern generation (ATPG)
software to target single faults for digital circuit testing. This worked for some
time, but with designs breaking the GHz frequency barrier, the approach is no
more economical or scalable. Further they can no longer provide sufficiently
high fault coverage for deep submicron or nanometer designs from the chip level
to the board and system levels. Also, as designs grow in size, the time required
to test a given block in an exhaustive manner assumes a fractal growth pattern.

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 Example : Consider a 32-bit adder. If one wishes to test all combinations
of corner cases as inputs, then total number of bit patterns which need to be
tested are ,
264 = 18446744073709551616 (1)
Even if we can have a very high speed testing suite which takes only 1ns per
measurement, then we would need,
18446744073709551616ns = 5124095hrs = 213503days = 584 years!
So, if it takes such amount of time to test just one 32-bit adder, relative to
this it may take virtually infinite amount of time to test all the possible combi-
nations for a modern day SoC, which is unrealistic. Under such circumstances,
it is inevitable to look for solutions which can reduce the number of test pat-
terns, thus accelerating the testing speed. Using some pseudorandom pattern
generation techniques could help in this regard and thankfully LBIST supports
this. This is explained in a detailed manner in the upcoming sections, so that
we appreciate the role of LBIST in VLSI testing. At the same time, it is vital
to go over the challenges associated with it too.

3 LBIST architectures
BIST techniques can broadly be classified into two categories : Online and
Offline.
Online BIST is performed when the functional circuitry is in normal op-
erational mode. It can be done either concurrently or nonconcurrently. In
concurrent online BIST, testing is conducted simultaneously during normal
functional operation. The functional circuitry is usually implemented with cod-
ing techniques or with duplication and comparison. In nonconcurrent online
BIST, on the contrary, testing is performed when the functional circuitry is in
idle mode. This is often accomplished by executing diagnosis software routines.
Offline BIST is performed when the functional circuitry is not in normal
mode. This technique does not detect any real-time errors but is widely used
in the industry for testing the functional circuitry at the system, board, or chip
level to ensure product quality. Functional offline BIST performs a test based
on the functional specification of the functional circuitry and often employs a
functional or high-level fault model. Normally such a test is implemented as
diagnostic software or firmware. Structural offline BIST performs a test
based on the structure of the functional circuitry. Figure 1 shows general form
of LBIST techniques :

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 Figure 1: High level overview of LBIST techniques

3.1 Typical LBIST architecture

Figure 2 shows a typical logic BIST system using the structural offline BIST
technique. The test pattern generator (TPG) automatically generates test
patterns, which is fed as an input to the circuit under test(CUT). The output
response analyzer (ORA) then compacts the output responses of the CUT into
a signature. Specific BIST timing control signals, including scan enable signals
and clocks, are generated by the LBIST controller for coordinating the BIST
operation among the TPG, CUT, and ORA. The logic BIST controller provides
a pass/fail indication once the BIST operation is complete. Additionally, the
CUT must comply with additional BIST-specific design rules to ensure that no
unknown (X) values be allowed to propagate from the CUT to the ORA.

Figure 2: A typical logic BIST system

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 On a finer scale, there can be multiple variations of offline BIST architec-
ture. Let’s have a bird’s-eye view of these and then we shift our focus to the
STUMPS architecture, which is the most widely followed one in industry.

3.1.1 BIST architectures for circuits without scan chains

The first BIST architecture uses a pseudo-random pattern generator (PRPG)
as well as a single-input signature register (SISR) or multiple-input sig-
nature register (MISR) for testing a combinational or sequential circuit that
does not assume any special structure. Hewlett-Packard was among the first
companies to adopt this BIST architecture for board-level fault diagnosis.
There are two ways to follow this approach : centralized and separate
board-level BIST architecture(CSBL) and the built-in evaluation and
self-test(BEST) methods. The logic being tested on the chip is typically a
sequential circuit (S) but can be a combinational circuit (C) as well in both the
cases. However, for the first one, additional circuitry (not shown in the figure)
is used to compare the final signature of the SISR with an embedded golden
signature(known good signature). It also provides a pass/fail indication once
the test is complete.The respective architectures are shown in Figure 3.

Figure 3: BIST architectures without scan chains

3.1.2 BIST architectures using concurrent checking circuits

For systems that include concurrent checking circuits, it is possible to use the
circuitry to verify the output response during offline testing; hence, the need to
implement a separate response analysis circuit can be knocked off. A popular
architecture in this regard shown in Figure 4, is concurrent self-verification
(CSV). A PRPG is applied to the functional circuitry (CUT) and the dupli-
cate circuitry. The duplicate circuitry is realized in complementary form to
reduce design and common-mode faults. Because the checking circuitry rec-
ommended involves comparing the outputs of the two implementations, this
technique avoids the aliasing problem and consequent loss of effective fault cov-
erage.

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 Figure 4: CSV and BILBO architectures

3.1.3 BIST architectures using register reconfiguration

A concern with BIST designs is the amount of test time required. One technique
for reducing the test time is to make use of the storage elements already in the
design for both test generation and response analysis. The storage elements are
redesigned so they can function as pattern generators or signature analyzers for
test purposes. This BIST architecture is generally referred to as a test-per-clock
BIST system.
One approach in this regard is built-in logic block observer (BILBO), whose
architecture is shown in Figure 4. The BILBO is operated in four modes: normal
mode, scan mode, test generation or signature analysis mode, and reset mode.
It can be controlled by two inputs, B1 and B2 in below fashion :
• B1 = 1 , B2 = 1 : normal mode (inputs Yi gated directly into the D
flip-flops)

• B1 = 0 , B2 = 0 : shift register mode

• B1 = 1 , B2 = 0 : MISR mode
• B1 = 0 , B2 = 1 : reset mode

This technique is most suitable for testing circuits, such as RAMs, ROMs, or
bus-oriented circuits, where input and output registers of the partitioned mod-
ules can be reconfigured independently.

3.1.4 BIST architectures for circuits with scan chains

If a design incorporates scan structures, it is possible to reuse this for BIST
purposes too. This is generally referred to as a test-per-scan BIST system.
Belonging to this category is a very famous architecture, called STUMPS(self-
testing using MISR and parallel SRSG ; SRSG stands for Shift Register
Sequence Generator), as shown in Figure 5. Here, the scan chains are loaded

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 Figure 5: STUMPS architecture

in parallel from the PRPG. The system clocks are then triggered and the test
responses are shifted to the MISR for compaction. New test patterns are shifted
in at the same time while test responses are being shifted out. Due to the
ease of integration with traditional scan architecture, the STUMPS architecture
is the only BIST architecture widely used in industry to date. In order to
further reduce the lengths of the PRPG and MISR and improve the randomness
of the PRPG, a STUMPS-based architecture that includes an optional linear
phase shifter and an optional linear phase compactor is often used in industrial
applications.

4 LBIST vs SCAN
LBIST has revolutionized the whole philosophy of testing in VLSI engineering,
which is a testament of the significant edge it has over the conventional SCAN
methodology. Below are some of the advantages of structural offline BIST :

• Since the chip is self-sufficient to do most of the testing, the overall cost
involved is drastically reduced due to low test time, no requirement of test
equipments, etc.

• BIST can be made to effectively test and report the existence of errors on
the board or system and provide diagnostic information as required; it is
always available to run the test and does not require the presence of an
external tester
• As BIST implements most of the tester functions on-chip, the origin of
errors can be easily traced back to the chip; some defects are detected
without being modeled by software.

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5 Advantages and Disadvantages
5.1 Advantages
• Significantly low testing cost

• Can be used across all levels : board, subsystem, system etc.

• Reusable and scalable
• Quite useful in rootcausing the original point of fault in a design

5.2 Disadvantages
• Increased area penalty to accommodate LFSRs
• Increased switching activity, leading to overheating and eventually having
serious implications on reliability and aging of a design
• Since pseudo-random patterns are mostly used for BIST pattern genera-
tion, additional test points may have to be added to improve the circuit’s
fault coverage
• More stringent BIST-specific design rules are required to deal with un-
known (X) sources originating from analog blocks, memories, non-scan
storage elements, etc.

6 Summary
LBIST testing might increase design complexity but it is ideal for field and
system testing throughout the product life cycle. However, it can be used for
fast manufacturing test bring up as well in conjunction with normal scan testing.
With a small area overhead and the ability to achieve desired testing target in
limited time, LBIST helps designers in taping-out a quality silicon. While BIST-
specific design rules are required and the BIST fault coverage may be lower than
that using scan, this approach does eliminate the expensive process of software
test pattern generation and the huge test data volume necessary to store the
output responses for comparison. Periodic in-system self-test, even using test
patterns with less than perfect fault coverage, can diagnose problems down to
the level where the BIST circuitry is embedded. This allows system repair to
become trivial and economical. All of this has led BIST to become the most
widely accepted test method in industry.