COMPUTER

ORGANIZATION
TOPIC FOR THE WEEK: Basic Operational Concepts

NOTES:
_____________________
_____________________ How to Fetch/Read Data or Instruction from MM
_____________________
_____________________ Von Neumann architecture requires that all programs together with data
must be stored in main memory during execution. In the case of the
_____________________
processor, it should have a way to read or fetch the program to be
_____________________ executed from the main memory. Programs cannot be executed in the
_____________________ main memory because it is merely a storage device and does not have
_____________________ circuits that can process data as what processor can do.
_____________________
_____________________ In order to fetch/read an instruction or data from main memory:
_____________________
1. The CPU first sends the address of the memory location to be
_____________________ read.
_____________________
_____________________ 2. The CPU then issues or sends the read signal to the memory.
_____________________
_____________________ A control signal is needed in order to fetch the data from the main
memory. The read signal that is generated by the control unit
_____________________
indicates the type of operation that is to be performed in the main
_____________________ memory. This operation makes a copy of the content of the given
_____________________ memory address.
_____________________
_____________________ 3. The word is then read out of memory and is loaded into a CPU
_____________________ internal register.
_____________________
_____________________
_____________________
_____________________ How to Write/Store Data into MM
_____________________
_____________________ During the execution of an instruction or program, there are instances
_____________________ that data or operand needs to be stored into the main memory. How
does the processor determine the location in the main memory where
_____________________ data is to be stored?
_____________________
_____________________ In order to store/write data into main memory:
_____________________
_____________________ 1. The CPU first sends the address of the memory location to be
_____________________ written.
_____________________ In writing data into the main memory, it is necessary that the
_____________________ location in the main memory where data is to be stored should
_____________________ be identified first.
_____________________
_____________________ 2. The CPU then sends the write signal together with the data or
_____________________ word to be written to memory.
_____________________ The write signal is generated by the control unit and it indicates
_____________________ a write operation. In this operation, the current content of the
_____________________ location will be lost.
_____________________

CODE: CSP107
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 COMPUTER Example 1
ORGANIZATION
Example of a typical assembly language instruction:

NOTES: MOV R0, LOCA

_____________________ The above instruction is an assembly language data transfer instruction.
_____________________ Copy the contents at memory location LOCA into a register in the
_____________________ processor, R0. The source address is LOCA which is a location in the
_____________________ main memory. Memory locations are usually named in this manner. The
_____________________ destination address is R0 which is a register in the processor. For the
_____________________ purpose of discussion, all register names is preceded by letter R and a
number.
_____________________
_____________________ The given instruction requires the performance of several steps:
_____________________
_____________________ 1. The instruction must be transferred or fetched from the MM into
_____________________ the CPU.
_____________________ 2. The operand at LOCA must be fetched.
3. The operand is stored in register R0.
_____________________
_____________________
_____________________
_____________________
_____________________ Example 2
_____________________
_____________________ Take a look at another example of a typical assembly language
instruction:
_____________________
_____________________ ADD R0, LOCA
_____________________
_____________________ Add the operand at memory location LOCA to the operand in a register
_____________________ in the processor, R0 and place the result into register R0. This instruction
_____________________ adds two numbers one from the main memory and one from a register in
the processor. This instruction requires the ALU for the addition
_____________________ process.
_____________________
_____________________ The given instruction requires the performance of several steps:
_____________________
_____________________ 1. The instruction must be transferred or fetched from the MM into
_____________________ the CPU.
2. The operand at LOCA must be fetched and added to the
_____________________ contents of R0.
_____________________ 3. The resultant sum is stored in register R0.
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________

CODE: CSP107
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 COMPUTER Connections Between the Processor and the MM
ORGANIZATION
Main Memory

NOTES:
_____________________ MAR MDR
Control
_____________________
PC
_____________________ R0
_____________________ IR R1
ALU
.
_____________________ .
_____________________ CPU .
_____________________ Rn-1
n General Purpose
_____________________ Registers
_____________________
_____________________
Figure 1. The Processor and MM Connections
_____________________
_____________________
_____________________ The PC (Program Counter) contains the memory address of the
_____________________ instruction to be executed. During execution, the contents of the PC are
_____________________ updated to point to the next instruction.
_____________________
Every time that an instruction is to be executed, the program counter
_____________________ releases its contents to the internal bus and sends it to the memory
_____________________ address register.
_____________________
_____________________ The MAR (Memory Address Register) holds the address of the location
_____________________ to or from which data are to be transferred.
_____________________
As can be seen from the figure above, the connection of the MAR to the
_____________________ main memory is one-way or unidirectional.
_____________________
_____________________ The MDR (Memory Data Register) contains the data to be written or
_____________________ read out of the addressed location.
_____________________
During the fetch operation, the MDR contains the instruction to be
_____________________
executed or data needed during execution. In write operation, MDR
_____________________ contains the data to be written into the main memory.
_____________________
_____________________ The IR (Instruction Register) contains the instruction that is being
_____________________ executed.
_____________________
Before the IR executes the instruction it needs to be decoded first. As
_____________________
soon as the content of the MDR is transferred to the IR, the decoding
_____________________ process commences. After decoding, execution of the instruction will
_____________________ take place.
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________

CODE: CSP107
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 COMPUTER Operating Steps
ORGANIZATION
1. PC is set to point to the first instruction of the program (the operating
system loads the memory address of the first instruction).
NOTES: 2. The contents of the PC are transferred to the MAR (which is
automatically transmitted to the MM) and a Read signal is sent to the
_____________________
MM.
_____________________ 3. The addressed word is read out of MM and loaded into the MDR.
_____________________ 4. The contents of MDR are transferred to the IR. The instruction is
_____________________ ready to be decoded and executed.
_____________________ 5. During execution, the contents of the PC are incremented or
_____________________ updated to point to the next instruction.
_____________________
If operand or data needed by the instruction resides in MM:
_____________________
_____________________ 1. It will have to be fetched by sending its address to the MAR and
_____________________ initiating a read cycle.
_____________________ 2. When the operand has been read from MM into the MDR, it may
_____________________ be transferred from the MDR to the ALU.
_____________________
If result is to be stored in MM:
_____________________
_____________________ 1. The result is sent to the MDR.
_____________________ 2. The address of the location where the result is to be stored is
_____________________ sent to the MDR and a write cycle is initiated.
_____________________
_____________________
_____________________ Example
_____________________
_____________________ Enumerate the different steps needed to execute the machine instruction
_____________________
_____________________ ADD LOCA, R0
_____________________
Assume that the instruction itself is stored in the main memory at location
_____________________ INSTR, and that this address is initially in register PC. The first two steps
_____________________ might be expressed as:
_____________________
_____________________ 1. Transfer the contents of register PC to register MAR.
_____________________ 2. Issue a READ command to the main memory, and then wait until it
_____________________ has transferred the requested word into register MDR.
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________

CODE: CSP107
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 COMPUTER CPU Instruction Execution Steps
ORGANIZATION
Instruction execution in a CPU can now be summarized by the following
steps:
NOTES:
1. Fetching the instruction from the memory into the instruction
_____________________ register.
_____________________ 2. Incrementing the PC to point to the next instruction to be
_____________________ executed.
_____________________ 3. Determining the type of instruction fetched (instruction
_____________________ decoding).
_____________________ 4. Determining the location of data in the memory. If the instruction
uses data.
_____________________ 5. Fetching the required data into internal CPU registers.
_____________________ 6. Executing the instruction.
_____________________ 7. Storing the results in the designated locations.
_____________________ 8. Return to Step 1.
_____________________
_____________________ This is commonly referred to as the fetch-decode-execute cycle.
_____________________
_____________________
_____________________ Bus Structure
_____________________
_____________________ A bus is a collection of wires that connect several devices within a
_____________________ computer system.
_____________________
When a word of data is transferred between units, all its bits are
_____________________ transferred in parallel.
_____________________
_____________________ A computer must have some lines for addressing and control purposes.
_____________________
_____________________ Three main groupings of lines:
_____________________
1. Data Bus. This is for the transmission of data.
_____________________ 2. Address Bus. This specifies the location of data in MM.
_____________________ 3. Control Bus. This indicates the direction of data transfer and
_____________________ coordinates the timing of events during the transfer.
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________

CODE: CSP107
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 COMPUTER Single Bus Structure
ORGANIZATION

NOTES:
_____________________
_____________________
_____________________
_____________________
_____________________ Figure 2. A Single Bus Structure Diagram
_____________________
_____________________ All units are connected to a single bus, so it provides the sole means of
interconnection.
_____________________
_____________________ Single bus structure has advantages of simplicity and low cost. Single
_____________________ bus structure has disadvantages of limited speed since usually only two
_____________________ units can participate in a data transfer at any one time. This means that
_____________________ an arbitration system is required and that units will be forced to wait.
_____________________ (This requires Time Domain Multiplexing or TDM, the transmission of
different types of information on the same lines, but at different times.)
_____________________
_____________________ Only two units can actively use the bus at any given time. Bus control lines
_____________________ are used to arbitrate multiple requests for the use of the bus.
_____________________
_____________________ Buffer Registers are used to hold information during transfers. These
_____________________ prevent a high-speed processor from being locked to a slow I/O device
during a sequence of data transfers.
_____________________
_____________________ Two-Bus Structure
_____________________
_____________________ Configuration 1

_____________________
_____________________
_____________________ Memory
_____________________ Memory
_____________________ Bus

_____________________ I/O Bus

_____________________
_____________________ Configuration 2
_____________________
_____________________
_____________________
_____________________ Processor
_____________________ Memory
Bus
_____________________
I/O Bus
_____________________
_____________________
_____________________ Figure 2. A Two-Bus Structure Diagram
_____________________
_____________________ In the first configuration, the processor is placed between the I/O unit
_____________________ and the memory unit. The processor is responsible for any data transfer
_____________________ between the I/O unit and the memory unit. The processor acts as a
“messenger.” In this structure, the processor performance and capability
_____________________
is not being maximized. Most of the time, the processor is doing data
transfer between these units instead of performing more complex
applications. Also, the processor is idle most of the time waiting for
these slow devices.
CODE: CSP107
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 COMPUTER In the second configuration, I/O transfers are made directly to or from
ORGANIZATION the memory. A special purpose processor called peripheral processor
or I/O channel is needed as part of the I/O equipment to control and
facilitate such transfers. This special processor for the main memory is
the direct memory access (DMA) controller. It allows main memory to
NOTES:
perform data transfer between I/O units.
_____________________
_____________________
_____________________
_____________________ Memory Locations and Addresses
_____________________
_____________________ MM is organized so that a group of n bits can be stored or retrieved in a
single basic operation.
_____________________
_____________________
n bits
_____________________
_____________________ 0 word 0
_____________________ 1 word 1
_____________________ .
_____________________ .
.
_____________________
i bn-1 . . . b1 b0 word i
_____________________
_____________________ .
.
_____________________ .
_____________________ M-1 word M - 1
_____________________
_____________________
_____________________ Figure 3. Sample of Memory Locations
_____________________
_____________________ The M addresses constitute the address space of the computer system.
_____________________
_____________________ Example: For the Intel 8088/86 Microprocessor
_____________________
_____________________ Address Space = 1,048,576 addresses or memory locations using binary
encoding of addresses, 20 bits are needed to represent all addresses,
_____________________ 20
2 = 1,048,576
_____________________
_____________________ Parts of an Instruction
_____________________
_____________________ The contents of memory locations can represent either:
_____________________
_____________________ 1. instructions
2. operands or data (numbers or characters)
_____________________
_____________________ An instruction usually contains two parts:
_____________________
_____________________ 1. the part that specifies the operation to be performed (op-code
_____________________ field).
_____________________ 2. the part that may be used to specify operand addresses.
_____________________ Examples:
_____________________
_____________________ 1. 32-bit instruction
_____________________
_____________________
8 bits 24 bits

Operation Addressing Information

Field
CODE: CSP107
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 COMPUTER
ORGANIZATION 2. 16-bit instruction (8088/86)

10001011 11101100
MOV SP TO BP
NOTES:
_____________________
_____________________
_____________________ Main Memory Operations
_____________________
_____________________ Fetch or Read. This transfers the contents of a specific MM location to
_____________________ the CPU. The word in the MM remains unchanged.
_____________________ Read/Fetch Cycle:
_____________________ 1. CPU sends address of the desired location.
_____________________ 2. MM reads the data stored at that address and sends it to the
_____________________ CPU.
_____________________
_____________________ Store or Write. This transfers a word of information from the CPU to a
specific MM location. This destroys the former contents of that location.
_____________________
_____________________ Write/Store Cycle:
_____________________
_____________________ 1. CPU sends address of the desired location to the MM, together
_____________________ with the data to be stored into that location.
_____________________ 2. Data is written at desired location.
_____________________
_____________________
_____________________ Instructions and Instructions Sequencing
_____________________
_____________________ Types of Instructions:
_____________________
_____________________ 1. Data transfers between MM and CPU registers.
2. Arithmetic and logic operations on data.
_____________________ 3. Program sequencing and control.
_____________________ 4. I/O operations or transfers.
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________

CODE: CSP107
Page 8 of 13
 COMPUTER Notations
ORGANIZATION
R1 [LOC]

NOTES: The contents of memory location LOC are transferred into register R1.
_____________________
C [A] + [B]
_____________________
_____________________ The operands in memory locations A and B are fetched from MM and
_____________________ transferred into the CPU, where they will be added in the ALU. Then the
_____________________ resulting sum is to be stored into memory location C in MM.
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________ Address Notations
_____________________
Three-Address Instructions
_____________________
_____________________ ADD A, B, C A [B] + [C]
_____________________
_____________________ B and C = source operands
_____________________ A = destination operands
_____________________
- The operands in memory locations B and C are fetched from
_____________________ MM and transferred into the CPU, where they will be added in
_____________________ the ALU. Then the resulting sum is to be stored into memory
_____________________ location A in MM.
_____________________
_____________________ Two-Address Instructions
_____________________
ADD A, B A [A] + [B]
_____________________
_____________________ - The operands in memory locations A and B are fetched from
_____________________ MM and transferred into the CPU, where they will be added in
_____________________ the ALU. Then the resulting sum is to be stored into memory
_____________________ location A in MM.
_____________________
MOVE B, C B [C]
_____________________
_____________________ - The contents of memory location C are transferred into
_____________________ memory location B in MM.
_____________________
_____________________ A common convention used is to write two-operand instructions in the
form:
_____________________
_____________________ operation destination, source
_____________________
_____________________
_____________________
_____________________
_____________________

CODE: CSP107
Page 9 of 13
 COMPUTER One-Address Notation
ORGANIZATION
Since addition is a two-operand operation, an implicit assumption must
be made regarding the location of one of the operands as well as the
NOTES: result.
_____________________ A general purpose CPU register, usually called the accumulator, may
_____________________ be used for this purpose.
_____________________
_____________________ Examples:
_____________________
_____________________ ADD A ACC [A] + [ACC]
_____________________ Add the contents of memory location A to
_____________________ the contents of the accumulator and place
_____________________ the sum into the accumulator.
_____________________
_____________________ LOAD A ACC [A]
_____________________
Move the contents of memory location A
_____________________ into the accumulator.
_____________________
_____________________ STORE A A [ACC]
_____________________
_____________________ Move the contents of memory location A
_____________________ into the accumulator.
_____________________
_____________________
_____________________ Examples
_____________________
_____________________ LOAD A ACC [A]
_____________________ ADD B ACC [B] + [ACC]
STORE C C [ACC]
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________

CODE: CSP107
Basic Operational Concepts
Page 10 of 13
 COMPUTER Zero-Address Instructions
ORGANIZATION
Instructions where the locations of all operands are defined implicitly.

NOTES: ➢ Example:
❖ Inc (increment the accumulator by 1)
_____________________
_____________________ ❖ Dec (decrement the accumulator by 1)
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
Two-Phase Procedure in Instruction Execution
_____________________
_____________________ Instruction Fetch
_____________________
_____________________ Instruction is fetched from MM location whose address is in the program
_____________________ counter. The instruction is then placed in the instruction register in the
_____________________ CPU.
_____________________
Instruction Execute
_____________________
_____________________ The instruction in the instruction register is examined to determine which
_____________________ operation is to be performed. The CPU then performs the specified
_____________________ operation.
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________

CODE: CSP107
Basic Operational Concepts
Page 11 of 13
 COMPUTER Instruction Execution and Straight-Line Sequencing
ORGANIZATION
Contents
Addresses
i MOVE R0, A 3-Instruction
NOTES: i+1 Program
ADD R0, B
_____________________ i+2 MOVE C, R0 Segment
_____________________ .
_____________________ .
.
_____________________ A
_____________________ .
_____________________ .
.
_____________________ B
Data for the
_____________________ program
.
_____________________ .
_____________________ .
_____________________ C
_____________________
_____________________
_____________________ Figure 4. The Instruction Execution
_____________________
To begin the execution of this program, the address of its first instruction
_____________________ (i) must be placed into the PC.
_____________________
_____________________ The CPU control circuits automatically proceed to fetch and execute
_____________________ instructions, one at a time, in the order of increasing addresses. This is
_____________________ straight-line sequencing.
_____________________ Contents
Addresses
_____________________ i MOVE R0, NUM1
_____________________ i+1 ADD R0, NUM2
_____________________ i+2 ADD R0, NUM3
_____________________ .
_____________________ .
.
_____________________ i+n-1 ADD R0, NUMn
_____________________ i+n MOVE SUM, R0
_____________________ .
_____________________ .
.
_____________________
SUM
_____________________ NUM1
_____________________ NUM2
_____________________ .
_____________________ .
_____________________ .
NUMn
_____________________
_____________________
_____________________ Figure 5. The Straight-Line Sequencing
_____________________
_____________________
This program will add a list of n numbers. The addresses of the memory
_____________________
locations containing the n numbers are symbolically given as NUM1,
_____________________ NUM2, . . ., NUMn, and the resulting sum is placed in memory location
_____________________ SUM.
_____________________

CODE: CSP107
Basic Operational Concepts
Page 12 of 13
 COMPUTER Branching
ORGANIZATION
The fundamental idea in program loops is to cause a straight-line
sequence of instructions to be executed repeatedly.
NOTES:
_____________________
CLEAR R0
_____________________
MOVE R1, N
_____________________ LOOPSTART Determine address of
_____________________ "Next" number and
add "Next" number to
_____________________ R0 Program
_____________________ DEC R1
Loop

_____________________ Branch > 0

LOOPSTART
_____________________ MOVE SUM, R0
_____________________ .
_____________________ .
.
_____________________ SUM
_____________________ N
NUM1
_____________________
NUM2
_____________________ .
_____________________ .
.
_____________________ NUMn
_____________________
_____________________
_____________________ Figure 6. The Branching Diagram
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________
_____________________

CODE: CSP107
Basic Operational Concepts
Page 13 of 13