5.

1 Design Overview
The project entitled Implementation of multi-channel UART controller based on FIFO technique using Spartan3 FPGA is under taken to establish a simultaneous and asynchronous data transmission and reception between a host system and a sub system or between any two sub systems. The multi channel UART controller block consists of multiple UART blocks or UART channels, in which these channels transmit and receive the data serially at different clock domains also called baud rates. The data bytes which need to be transmitted are initially stored in a RAM memory block, which we call it as transmit FIFO. This is applicable to all the UART channels. Then the buffered data bytes are read one by one from the transmit FIFO. The first byte read from transmit FIFO is temporarily stored in transmit shift register present in the transmit circuit. The transmit shift register now refers to the particular baud clock assigned to it for transmitting the data bit by bit serially. This data is initially provided with the start bit (active low) and a stop bit (active high) before transmitting. The transmitted data serially over a long distance (in case if the host system and the sub system are at larger distance) is received serially by the respective receive shift register of the other UART channel present at the sub system. The receive shift register receives data serially along with start bit and stop bit at a baud rate similar to that assigned for the transmitter circuit on the host system. The received 8 bit data from the receive shift register is now buffered to another RAM memory called receive FIFO. This received data can be make used of by the sub system.

Similarly the UART transmit circuit of the sub system can at the same time be transmitting while receiving because of the asynchronous property of the UART, that too at same or at different baud rates.

Steps related to working of entire multichannel UART controller are listed below

Step1: initialize all the input and output parameters Step2: Wait for host system to provide data inputs to the transmit FIFOs Step3: If the data_in_rdy signal is set to 1, then write that data of all UART channels to their respective transmit FIFO memory using write signal. Step4: Now upon a read signal going high, the first input data from the transmit FIFOs are read to the transmit shift registers respectively for all UART channels. Step5: This 8-bit input data which is read is padded with start and stop bit before transmitting serially. Step6: The 8-bit data becomes a 10 bit data and is transmitted serially with the first bit as start bit. This indicates the receive block that a new 8-bit data is being transmitted serially. Step7: The start bit is followed by 8 data bits and then a stop bit. This stop bit is used to indicate the correct operation. Step8: The receiver after receiving 8 bit data and fails to receive a stop bit, by default this 8-bit data is rejected and will not be considered as a valid data byte. Step9: Upon receiving the stop bit, the 8 bit received data is buffered to receive FIFO memory block by initiating a write signal of receive FIFO. Step10: This completes the transmit and reception of one 8-bit data. Step11: Simultaneously the transmit circuits and receive circuits of all 4 UARTs can work asynchronously or simultaneously i.e., by performing the transmit and receive
operation without interruption of any data values.

Step12: This process is repeated continuously by going back to step2 The datas are transmitted and received using different baud rates that are assigned to particular UART channels.

5.2 Flow Charts

A flowchart is diagrammatic representation of our design, showing the steps as boxes of various kinds, and their order by connecting these with arrows. Flowcharts are used in analyzing, designing, documenting or managing a process or program in various fields. Here each block in a multi channel UART controller is represented in terms of flow chart. Firstly we represent the top level design module that is the entire multi channel UART controller, then the sub modules or blocks consisting of FIFO blocks, Baud rate generator blocks, transmitter blocks and receiver blocks.

Start

Initialize all the input & output variables C

Load the input data values namely data_in1, data_in2, data_in3, data_in4

Is

data_in_rdy1, data_in_rdy2, data_in_rdy3, data_in_rdy4 No

Yes
Write all the input data to respective transmit FIFOs Write11=1, Write21=1, Write31=1, Write41=1

Read data values from respective transmit FIFOs to transmit shift registers Xmit_dataH1, Xmit_dataH2, Xmit_dataH3, Xmit_dataH4

F A

Fig. 5.1: Flow chart of entire top level module

Assign baud clocks to all the UART blocks for transmission and reception

Y
Transmit the data present in transmit shift registers (at the desired baud rate that has been assigned) serially i.e., bit by bit Tx1_data, Tx2_data, Tx3_data, Tx4_data

Is Tx1_done, Tx2_done, Tx3_done, Tx4_done?

No

Yes
Receive the serial transmitted data to respective receive shift registers Rec_dataH1, Rec_dataH2, Rec_dataH3, Rec_dataH34

Is Rec_readyH1, Rx_readyH2, Rx_readyH3, Rx_readyH4 ?

No

Yes B Fig. 5.2: Flow chart of entire top level module (contd.)

Write the received data from receive shift registers to respective receive FIFOs. Write 12=1, Write 22=1, Write 32=1, Write 42=1

E
Read the data from receive FIFOs (host system makes use of this data as an information received from subsystems) Rx1_data, Rx2_data, Rx3_data, Rx4_data

Is Rx1_rdy, Rx2_rdy, Rx3_rdy, Rx4_rdy ?

No

Yes
Increments write and read pointers for transmitting and receiving the next data byte serially (from the host system to several subsystems or between the subsystems)

Fig. 5.3: Flow chart of entire top level module (contd.)

5.2.1 Top level module of multi channel UART controller

The flow of proposed multi channel UART controller is as shown in above Figs. in terms of flow charts. Firstly initialize all input and output parameters. The incoming data values are loaded to respective transmit FIFOs (data_in1, data_in2, data_in3, data_in4) upon the occurrence of write signals (write11, write22, write33, write44). Then these data values present in transmit FIFOs are read to respective transmit shift registers (xmit_dataH1, xmit_dataH2, xmit_dataH3, xmit_dataH4) upon occurrence of read signal. The data bytes present in shift registers are transmitted serially at a desired Baud rate. This serially transmitted data is being received by receive shift registers of respective receive circuits. These data bytes in receive shift registers are buffered on to the respective receive FIFO

blocks. This process repeats continuously, till the new data values keep appearing at the input sides which are written into FIFO blocks.

Start

Initialize all the input & output variables

Load the values of crystal frequency and desired baud rates to calculate the baud count

Baud_clk_val. = (baud rate)*16*2 Baud_count = (XLAT freq.)/ Baud_clk_val.

Is Baud_sel

00 BAUD= Baud_count1

01 BAUD= Baud_count2

10 BAUD= Baud_count3

11 BAUD= Baud_count4

Value =BAUD

Clk_div = Clk_div+1

Is Clk_div= = Value

No

Yes X Fig. 5.4: Flow chart of Baud rate generator block

Clear Clk_div

Baud_clk = not (Baud_clk)

Fig. 5.5: Flow chart of Baud rate generator blocks (contd.)

5.2.2 Baud rate generator block

The Baud rate generator block is mainly used to generate different Baud clock signals to UART transmit and receive circuits. Here the system crystal oscillator frequency is making used to calculate Baud_clk, which is the output signal of Baud rate generator block. Baud_count is calculated using equation Baud_cunt=(crystal frequency)/ Baud_clk_val. Baud_sel is used as a select input line for selecting different Baud rate values as shown in Fig. 5.4. Here Clk_div is used as a counter which increments and is compared with the calculated Baud_count. Once Clk_div equals the Baud_count, the output signal Baud_clk is inverted. This process repeats continuously their by generating a Baud clock signal, which is going to be used by the transmit and receive circuits.

Start

Initialize all the input & output variables

Wait for rising edge of clock

No

Yes Is reset = =1 No

Yes
Is

No

data_in_rdy ? Yes
Write the data into FIFO memory and increment write pointer

P Fig. 5.6: Flow chart of FIFO memory blocks

Is Read = =1

No

Is Write = =1

No

Yes Is FIFO Empty = =1

Yes Is FIFO Full = =1

No Readout the data from FIFO and set data_out_rdy =1

No Write data into FIFO

Yes Finish or not ? Yes End Fig. 5.7: Flow chart of FIFO memory blocks (contd.) No

Yes

5.2.3 FIFO memory block

Initialize all the input and output variables. On the occurrence of rising edge of system clock, check for the reset signal to be high. If data_in_rdy signal is high, then write the input data (data_in) to the FIFO memory location where the write pointer (wr_ptr) is pointing. Simultaneously if the read signal is high, read the data value out of FIFO in which location the read pointer (rd_ptr) is pointing. Initially upon reset, FIFO is empty and data cannot be read, which is indicated by an EMPTY flag. If the FIFO memory is full, then further data cannot be written into FIFO. This is indicated by a FULL flag. This process repeats and is applicable for all transmit and receive FIFOs.

Start

Initialization of all data values T Read the data to be transmitted from transmit FIFO to transmit shift register xmit_dataH

Send initial signal of start bit (low)

Delay of T/2 to sample start bit, data bits & stop bit Shift out the data bits serially Increment bit counter

Is bit counter<8 8

Yes

No Send the stop bit (high)

Finished transmitting a byte, set tx_done T

Fig. 5.8: Flow chart of UART transmitter blocks

5.2.4 Transmitter block

The data values read from transmit FIFO is buffered on to transmit shift register (xmit_dataH). This 8-bit data is then padded with a start bit (active low) and a stop bit (active high). Send the start bit initially, then 8 data bits by shifting the register xmit_dataH content. After transmitting 8 data bits at a predefined Baud rate, a stop bit is transmitted as an indication of correct transmission operation. This process in Fig. 5.10 repeats continuously every time new data enters into xmit_dataH register and is applicable to all UART transmit circuits.

Start

Initialization all data values Q Receive the serially transmitted data with the desired band rate

Is start bit detected?

Yes

No

Delay of T/2 to sample start bit

Correct start bit?

Yes

No

Sample the remaining data bits and shift the receive shift register data each time when a bit is received

Is stop bit detected after 8 data bits? Discard the received data since, error in transmission

No

Yes

Fig. 5.9: Flow chart of UART receiver blocks

Buffer or store the received data to receive FIFO Set rxd_readyH flag and start detecting for next start bit

R
Fig. 5.10: Flow chart of UART receiver blocks (contd.)

5.2.4 Receiver block

Receives the serially transmitted data into the receive shift register (rec_dataH) by detecting a start bit. Then the 8 data bits are received serially with a delay of T/2 between any 2 bits (where T is the period). After receiving the 8th data bit, a stop bit (active high) must be received. If this high pulse of stop bit is not detected, the receiver simply discards the received data bits and waits for next start bit. In case if the correct stop bit is received, the 8-bit data value in rec_dataH is buffered on to receive FIFO. Then the rec_readyH signal is set high to indicate that the transmitted data is safely received and the receiver gets ready for next start bit. This process repeats continuously and is applicable for all UART receiver circuits.