Logic Reference Guide

Advanced
Micro
Devices

INTRODUCTION The standard schematic symbols used to represent

these gates are shown in Figure 1.
Throughout this data book and design guide we have
assumed that you have a good working knowledge of
logic. Unfortunately, there always comes a time when
you are called on to remember something which can NOT
only be found in that logic textbook which you threw
away years ago.
AND
This section is intended to provide a quick review and
reference of the basic principles of digital logic. We will
cover three general areas: OR
90000A-1

Basic logic elements

Figure 1. Schematics Symbols for the Three
Basic storage elements Fundamental Gates
Binary numbers
The AND and NOT functions can be combined into the
Throughout the text, we will use the notation that was
NAND function. This is equivalent to an AND gate fol-
used throughout this book. If you are unfamiliar with the
lowed by an inverter, as shown in Figure 2a. Likewise,
syntax, you will probably find it easy to understand as
the OR and NOT gates can be combined into the NOR
you read; if you wish for a more detailed explanation of
function, as shown in Figure 2b. Each of these gates is
the symbols, please refer to the Basic Design with PLDs
functionally complete; any logic function can be ex-
section where they are defined.
pressed solely as a function of NAND or NOR gates.
As this is a logic reference only, we cannot take on
lengthy discussions, nor can we train you in the basic
principles of digital logic if you have not previously been =
trained. In such a case, we must refer you to your
favorite logic textbook. a. The NAND Function
BASIC LOGIC ELEMENTS
=
In this section, we will discuss the concepts surrounding
combinatorial logic functions.
b. The NOR Function
90000A-2
The Three Basic Gates
There are three basic logic gates from which all other Figure 2. The NAND and NOR Functions
combinatorial logic functions can be generated. These
functions are NOT, AND, and OR. A truth table indicat-
Precedence of Operators
ing these functions is shown in Table 1. Since they can
be used to generate any function, they are said to be Logic functions may be created with any combination of
functionally complete. the three basic functions. How those functions are ex-
pressed affects the evaluation of the function. The
Table 1. Truth Table for the NOT, AND, and OR normal order of evaluation is:
Functions
NOT, AND, OR
A B /A A*B A+B
0 0 1 0 0 Evaluation proceeds in order from left to right.
0 1 1 0 1
1 0 0 0 1
1 1 0 1 1

Publication# 90000 Rev. A Amendment /0

6-3
Issue Date: June 1993
 AMD
This order may be altered by inserting parentheses in Some example functions are evaluated in Table 2.
the function. The contents of the parentheses will al-
ways be evaluated before the rest of the expression,
from left to right.
Table 2. Using Parentheses to Change the Order of Evaluation
A*B+/A* A*B+/A* A*(B+/A)* A*(B+/A)*
A B C D C+D (C+D) C+D (C+D)
0 0 0 0 0 0 0 0
0 1 1 0 1 1 0 0
1 0 0 1 1 0 1 0
1 1 1 1 1 1 1 1

Commutative, Associative, and Duality

Distributive Laws The two distributive laws give an example of the concept
The AND and OR functions are commutative and asso- of duality. This principle states that:
ciative. This means that the operands can appear in any
Any identity will also be true if the following substitutions
order without affecting the evaluation of the function.
are made:
This is illustrated in Tables 3 and 4.
* for +
Table 3. Commutativity + for *
1 for 0
A B A*B B*A A+B B+A 0 for 1
0 0 0 0 0 0
0 1 0 0 1 1 Thus, it is only necessary to prove the first of the distribu-
1 0 0 0 1 1
tive laws; the second one will then be true by duality.
Note that duality is not required to prove the second law;
1 1 1 1 1 1
it can also be proven by truth table or by logic
manipulation.
Table 4. Associativity
Manipulating Logic
A B C (A*B)*C A*(B*C) (A+B)+C A+(B+C)
Logic functions may be manipulated by the use of
0 0 0 0 0 0 0
Boolean algebra. The logic functions may be expressed
0 1 1 0 0 1 1
in one of the two canonical forms, or by using a simpli-
1 0 1 0 0 1 1 fied expression.
1 1 1 1 1 1 1

There are actually two distributive laws; one of them re-

sembles standard algebra more than the other. These
two laws state that:
A*(B+C) = (A*B) + (A*C)
A+(B*C) = (A+B) * (A+C)

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Canonical Forms or maxterm number, as shown in Table 5. Within each
minterm or maxterm, the individual variables are re-
There are two fundamental canonical forms: sum-of-
ferred to as literals.
minterms and product-of-maxterms. The former is by far
the most widespread. These are special cases of what For the case of sum-of-minterms form, the expression
are more generally referred to as sum-of-products and for a function may be found by ORing the minterms
product-of-sums forms. Minterms and maxterms are which correspond to the 1’s in the function’s truth table.
products and sums of the variables involved in a func- Likewise, the product-of-maxterms expression may be
tion. Each particular combination of noninverted and found by ANDing the maxterms which correspond to the
inverted variables in a product or sum is given a minterm 0’s in the truth table. This is illustrated in Figure 3.
Table 5. Minterms and Maxterms
Table of Minterms for Three Table of Maxterms for Three
Variables Variables

Minterm Name Maxterm Name

/x*/y*/z m0 x+y+z M0
/x*/y*z m1 x + y +/z M1
/x*y*/z m2 x +/y + z M2
/x*y*z m3 x +/y + /z M3
x*/y*/z m4 /x + y + z M4
x*/y*z m5 /x + y + /z M5
x*y*/z m6 /x + /y + z M6
x*y*z m7 /x + /y + /z M7

Conversion Between Canonical Forms One can convert back and forth between these repre-
sentations by using the rules shown in Table 6.
It is a simple matter to convert between canonical forms.
Given a truth table for a function F, there are four differ-
ent representations that can be used:
Sum-of-minterms form of F
Product-of-maxterms form of F
Sum-of-minterms form of /F
Product-of-maxterms form of /F

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Minterm/
Maxterm
A B C D X Y Number
0 0 0 0 1 1 0
0 0 0 1 0 1 1
0 0 1 0 1 1 2
0 0 1 1 1 1 3
0 1 0 0 0 1 4
0 1 0 1 1 0 5
0 1 1 0 0 0 6
0 1 1 1 1 1 7
1 0 0 0 1 1 8
1 0 0 1 1 1 9
1 0 1 0 0 0 10
. . . . . . .
. . . . . . .
. . . . . . .
1 1 1 1 0 0 15
a. Truth Table

X = m0+m2+m3+m5+m7+m8+m9 X = M1*M4*M6*M10*M11*M12*M13*M14*M15
= ∑m (0,2,3,5,7,8,9) ΠM (1,4,6,10,11,12,13,14,15)
= /A * /B * /C * /D ;m0 =(A+B+C+/D) ;M1
+ /A * /B * C * /D ;m2 *(A+/B+C+D) ;M4
+ /A */B* C * D;m3 *(A+/B+/C+D) ;M6
+ /A * B * /C * D ;m5 *(/A+B+/C+D) ;M10
+ /A * B * C * D ;m7 *(/A+B+/C+/D) ;M11
+ A * /B * /C * /D ;m8 *(/A+/B+C+D) ;M12
+ A */B* /C * D;m9 *(/A+/B+C+/D) ;M13
*(/A+/B+/C+D) ;M14
Y = m0+m1+m2+m3+m4+m7+m8+m9 *(/A+/B+/C+/D) ;M15
= ∑m (0,1,2,3,4,7,8,9)
Y = M5*M6*M10*M11*M12*M13*M14*M15
= /A * /B * /C * /D ;m0 = ΠM (5,6,10,11,12,13,14,15)
+ /A */B* /C * D;m1
+ /A */B* C * /D;m2 =(A+/B+C+/D) ;M5
+ /A */B* C * D;m3 *(A+/B+/C+D) ;M6
+ /A * B * /C * /D ;m4 *(/A+B+/C+D) ;M10
+ /A * B * C * D ;m7 *(/A+B+/C+/D) ;M11
+ A */B* /C * /D;m8 *(/A+/B+C+D) ;M12
+ A */B* /C * D;m9 *(/A+/B+C+/D) ;M13
*(/A+/B+/C+D) ;M14
*(/A+/B+/C+/D) ;M15

b. The Sum-of-Minterms Expression c. The Product-of-Maxterms Expression

Figure 3. Finding the Canonical Form from the Truth Table

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Table 6. Conversion of Forms Table
Desired Form
Given Form Minterm Maxterm Inverted Minterm Inverted Maxterm
Expansion of F Expansion of F Expansion of F Expansion of F
Minterm – Maxterm numbers List Minterms not Maxterm numbers
expansion are those numbers present in F are the same as
of F not in the Minterm Minterm numbers
list of F of F
Maxterm Minterm numbers – Minterm numbers
expansion are those numbers are the same as List Maxterms not
of F not on the Maxterm Maxterm numbers present in F
list of F of F

Simplifying Logic There are four basic postulates, two of which are the
commutative and distributive laws which were dis-
Canonical forms are convenient in that it is easy to de-
cussed above. From these postulates, it is possible to
rive and convert them. However, the representation is
derive nine basic theorems. The postulates and theo-
bulky, since all variables must appear in each sum or
rems are listed in Table 7.
product. These expressions can be simplified by apply-
ing the basic laws and theorems of Boolean algebra.
Table 7. Postulates and Theorems of Boolean Algebra
Postulate 1 (A) X + FALSE = X
(B) X*TRUE = X
Postulate 2 (A) X + /X = TRUE
(B) X * /X = FALSE
Postulate 3 (A) X + Y = Y + X
(B) X*Y = Y*X
Postulate 4 (A) X * (Y + Z) = (X*Y) + (X*Z)
(B) X + (Y*Z) = (X + Y) * (X + X)
Theorem 1 (A) X + X = X
(B) X * X = X
Theorem 2 (A) X + TRUE = FALSE
(B) X*FALSE = FALSE
Theorem 3 / (/X) = X
Theorem 4 (A) X + (Y + Z) = (X + Y) + Z
(B) X * (Y*Z) = (X*Y) * Z
Theorem 5 (A) / (X + Y) = /X * /Y
(B) / (X * Y) = /X + /Y
Theorem 6 (A) X + (X * Y) = X
(B) X * (X + Y) = X
Theorem 7 (A) (X*Y) + (X*/Y) = X
(B) (X + Y) * (X + /Y) = X
Theorem 8 (A) X + (/X*Y) = X + Y
(B) X * (/X + Y) X*Y
Theorem 9 (A) (X*Y) + (/X*Z) + (Y*Z) = (X*Y) + (/X*Z)
(B) (X + Y) * (/X + Z) * (Y + Z) = (X + Y)*(/X + Z)

Notice that each theorem and postulate (with the excep- As the logic expression is simplified, it no longer con-
tion of theorem 3) has two forms. This is a result of the tains minterms (or maxterms), since some of the
duality principle; once one form of a theorem is estab- minterms and literals are being eliminated. What was a
lished, the dual representation follows immediately. sum-of-minterms (product of maxterms) representation
Theorem 3 has no dual because it does not involve any is now simplified to a sum-of-products (product of
of the elements that have duals (+, *, 1, or 0). sums).

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DeMorgan’s Theorem Values of A
Values of B
Once an expression has been simplified, it is no longer
possible to invert the function by using Table 6. Inverting A
simplified logic requires DeMorgan’s theorem: Moving to an
C B 00 01 11 10 Adjacent Cell
/(X*Y) = /X + /Y Changes the
0 Value of one
/(X + Y) = /X*/Y Variable only.
This is theorem 5 in Table 7. 1
There is one shortcut which can be used. The effect of
inversion can be accomplished by inverting all literals Values of C
and then using the dual representation. For example, Groups Can
given the expression Wrap Around
/(A*/B + A*C + /A*B*D) 90000A-3

we can invert to obtain:

Figure 4. A Karnaugh Map for Three Variables
/A*B + /A*/C + A*/B*/D ;step one,
invert The truth table for a function is then transferred to the
literals K-map by placing the 1’s and 0’s in the appropriate cells.
(/A + B)*(/A + /C)* ;step two,
(A + /B + /D) take dual Since each cell differs from its neighbor only in the polar-
ity of one of the literals, 1’s in adjacent cells can be
This expression must still be simplified to obtain a sum- combined by theorem 7a, which says that
of-products representation, but this shortcut eliminates
some of the early steps. x*y + x*/y = x

Karnaugh Maps: Minimizing Logic In this manner, two product terms are combined into
one. This procedure can conceptually be repeated to al-
Simplifying by hand by using algebraic manipulation can low groupings of two, four, eight, or any group of
be a tedious and error-prone procedure. When only a adjacent cells whose size is a power of two. A cell may
few variables are used (generally less than 5 or 6), appear in more than one group. Just enough groups are
Karnaugh maps (also called K-maps) provide a simpler found to include all of the 1’s. The groups should be as
graphical means of simplifying logic. K-maps not only al- large as possible.
low for logic simplification, but for logic minimization,
where an expression has a minimal number of product This process provides a minimal sum of products. The
terms (or sum terms) and literals. product-of-sums form can be obtained by grouping 0’s
instead of 1’s and inverting the header for each cell.
A Karnaugh map consists of a box which has one cell for
each minterm. These cells are arranged so that only one The two functions from Figure 3 have been placed into
literal is inverted when moving from one cell to an adja- K-maps in Figure 5. The groups are then used as indi-
cent cell. The headings placed by each row and column vidual product terms. When reading the product terms
indicate the polarities of the literals for that row or col- from the map, the only literals which will appear in the
umn. The literals themselves are indicated in the top left product term are the ones whose values are constant for
corner of the map. An example of a Karnaugh map for each cell in the group. If that value is 1, then the non-
three variables is shown in Figure 4. inverted form of the literal is used. If the value is 0, then
the inverted form of the literal is used.
For active-LOW functions, the same procedure is used,
except that the 0’s are grouped instead of the 1’s. The
active-LOW version of the functions from Figure 3 are
derived in Figure 6.
Hand simplification and minimization is not needed as
frequently today as in the past, since software is now
available for handling these logic manipulations. Most
software can perform logic simplification and minimiza-
tion automatically.

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A A*/C*/D A /C*/D
C B C B
D 00 01 11 10 D 00 01 11 10

00 1 0 1 1 B*/C*D 00 1 1 1 1 A*B*/C

0 1 1 0 01 1 0 1 0
01 /A*/B*/C

11 0 0 0 0 11 0 0 0 0

10 1 1 0 0 10 1 1 0 0

/A*/B*/D /A*/C*/D /A*/D

X Y

X = /A*/B*/D Y = /A*/D
+ A*/C*/D + /C*/D
+ B*/C*D + /A*/B*/C
+ /A*C*/D + A*B*/C
90000A-4

Figure 5. Using a K-map to Minimize the Functions in Figure 3

A A*B*/C*/D A /A*B*D
C B C B
D 00 01 11 10 D 00 01 11 10
/B*D 1 0 1 1 1 1 1 1
00 00
A*/B*D

0 1 1 0 01 1 0 1 0
01

C*D C*D
11 0 0 0 0 11 0 0 0 0 A*C

10 1 1 0 0 10 1 1 0 0

A*C
X Y

/X = C*D /Y = C*D
+ /B*D + A*D
+ A*C + /A*B*D
+ /A*B*/C*/D + A*/B*D 90000A-5

Figure 6. Finding Inverse Functions

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Comparison and Equivalence: the XOR
XOR
and XNOR Gates
The Exclusive-OR (XOR) and Exclusive-NOR (XNOR)
gates are two special gates which are relatively com- XNOR
mon. These gates have schematic symbols as shown in 90000A-6
Figure 7a. They are actually compound gates, and can a. Schematic Symbols
be generated by AND, OR, and NOT gates using the
functions:
A B A:+:B A:*:B
x :+: y = x*/y + /x*y ;XOR gate 0 0 0 1
x :*: y = x*y + /x*/y ;XNOR gate 0 1 1 0
1 0 1 0
The XOR and XNOR functions are actually inverses of 1 1 0 1
each other; that is,
b. XOR and XNOR Truth Table
x :+: y = /(x :*: y)
The truth tables for these gates are shown in Figure 7b. Figure 7. The Exclusive-OR and Exclusive-NOR
Note that the XOR function is true if and only if the oper- Functions
ands are different. For this reason, it is useful as a
comparator. The XNOR function is true if and only if its Some basic properties of the XOR and XNOR functions
operands are the same; therefore it is used as an are listed in Table 8.
equivalence indicator.
Table 8. Properties of the XOR and XNOR Functions
XOR XNOR
x :+: 0 = x x :*: 0 = /x
x :+ 1 = /x x :*: 1 = x
x :+: x = 0 x :*: x = 0
x :+: /x = 1 x :*: /x = 1
x :+: y = y :+: x x :*: y = y :*: x
x :+: y = :+: z = (x :+: y) :+: z x :*: y :*: z = (x :*: y) :*: z)
= x :+: (y :+: z) = x :*: (y :*: z)
x :+: y = /x :+: /y x :*: y = /x :*: /y
/ (x :+: y) = /x :+: y / (x :*: y) = /x :*: y
= x :+: /y = x :*: /y
= x :+: y = x :+: y
x :+: y = x* /y + /x*y x :*: y = x* y + /x*/y
x :+: x* y = x*/y x :*: x* y = /x + y
x :+: /x*y = x + y x :*: /x*y = /x * /y
x* (y :+: z) = (x*y) :+: (x*z) x + (y :*: z) = (x + y) :*: (x + z)
/x*(y :+: z) = (x + y) :+: (x + z) /x + (y :*: z) = (x*y) :*: (x*z)

When deriving equations from a Karnaugh map, XOR The XOR gate can be used as an “UNLESS” operator. In
and XNOR functions can usually be identified by their other words, the function, A = X :+: Y can be
characteristic pattern. Exactly what the operands are interpreted as:
may or may not be obvious for more complicated func-
tions. Some examples are shown in Figure 8. “A will have the same value as X UNLESS Y is true.”
This can be helpful when trying to derive a logic equation
for a function which can be described in words.

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P P
R Q R Q
J 00 01 11 10 S 00 01 11 10

00 1 0 1 0 00 0 0 0 1

1 0 1 0 01 1 0 1 0
01

11 0 1 0 1 11 1 0 1 0

10 0 1 0 1 10 0 0 0 1

J K

J = /P*/Q*/R K = /P*/Q*S
+ P*Q*/R + P*Q*S
+ /P*Q*R + P*/Q*/S
+ P*/Q*R = ((/P*/Q) + (P*Q))*S
= ((/P*/Q) + (P*Q))*/R + P*/Q*/S
+ ((/P*Q)+(P*/Q))*R
= (P:*:Q)*/R = (P:*:Q)*S
+ (P:+:Q)*R + P*/Q/*/S
= /(P:+:Q)*/R
+ (P:+:Q)*R

= (P:+:Q):*:R 90000A-7

Figure 8. Finding XOR and XNOR Functions in Karnaugh Maps

Basic Storage Elements Flip-flops can also be characterized by their control

scheme. There are four types of flip-flops, each of which
Storage elements provide circuits with the capability of
can be unclocked or clocked:
remembering past conditions or events. The prototypi-
cal storage element is just a pair of cross-coupled NAND S-R
gates, as shown in Figure 9. These elements are nor- J-K
mally called flip-flops. D
T
The discussion below will be divided between un-
clocked and clocked flip-flops. Each of the four flip-flop
types will be treated for each section.

Unclocked Flip-Flops—Latches
90000A-8 S-R Latches
An S-R latch can be built out of NOR gates as shown in
Figure 10, and behaves according to the truth table in
Figure 9. Basic Storage Element Table 9. ‘S’ stands for ‘set’ and ‘R’ stands for ‘reset,’ as
suggested by the truth table.
In general, there are two primary classes of flip-flops:
Note that the latch actually has two outputs, which are
Unclocked flip-flops, or latches complementary. These are referred to as Q and Q. If
Clocked flip-flops both S and R are raised at the same time, then both Q
and Q will be HlGH; although this is physically possible,
Clocked flip-flops are sometimes referred to as regis- it does not make sense if Q and Q are to be complemen-
ters, although technically speaking, a register is a bank tary signals. Thus, this condition is not allowed.
of several flip-flops with a common clock signal.

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There are some applications where it is desirable for the
input data to be effective only when another signal—
R Q usually called a control signal—is active. The circuit of
S Q
Figure 10 can be modified to give an S-R latch with a
control input, as shown in Figure 13. The operation of
this circuit is summarized in Table 10 and Figure 14.
Q R Q
S
The S-R latch is somewhat restrictive, since both inputs
90000A-9 cannot be HIGH at the same time. The other latch types
are based on the S-R latch, but have additional logic
Figure 10. An S-R Latch which removes the input restrictions.

Table 9. S-R Latch Truth Table

S R Q+ S
0 0 Q
0 1 0
1 0 1 R
1 0 Not allowed

The transfer function for this latch can be derived with a

Karnaugh map, as shown in Figure 11. By choosing Q
either 1’s or 0’s, we can obtain two representations:
90000A-11
a. Q+ = S+/R*Q
b. /Q+ = R+/S*/Q
Figure 12. S-R Latch Behavior

Q Q
S S
R 0 1 R 0 1 S Q
S Q S Q
00 0 1 00 0 1
C C

01 01 R Q
0 0 0 0 R R Q Q

90000A-12
11 X X 11 X X

Figure 13. Adding a Control Input to an S-R Latch

10 1 1 10 1 1

90000A-10 Table 10. Truth Table for an S-R Latch with a

Q+ /Q+ Control Input
a. Q+ = S + /R*Q b. /Q+ = R + /S*/Q S R C Q+
X X 0 Q
0 0 1 Q
Figure 11. Karnaugh Map for an S-R Latch
0 1 1 0
1 0 1 1
Waveforms illustrating the operation of the S-R latch are
1 1 1 Not allowed
shown in Figure 12.

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90000A-13

Figure 14. Behavior of an S-R Latch with a Control Input

D-Type Latches (Transparent Latches)

A single-input latch can be formed by adding some logic D
to the controlled S-R latch in Figure 13; this gives rise to
the D-type latch in Figure 15. This latch is often called a
transparent latch, since data on the input passes right G
through to the output as long as the control input is
HlGH. If the control input is set LOW, then the latch
holds whatever data was present when the control went Q
LOW. With this type of latch, the control is usually called
a gate. 90000A-15

The behavior of the D-type latch is shown in Table 11

and Figure 16. Figure 16. D-Type (Transparent) Latch Behavior

The basic transfer function for a D-type latch can be de-

rived from the Karnaugh map in Figure 17. Q+ = D*G + Q*/G /Q+ = /D*G + /Q*/G

Q Q
D D
G 0 1 G 0 1
D S Q Q
D Q 00 0 1 00 0 1
G C
01 0 0 01 0 0
R Q Q G Q

90000A-14 11 1 1 11 1 1

10 0 1 10 0 1
Figure 15. A D-Type (Transparent) Latch

Table 11. Truth Table for a D-Type Latch Q+ /Q+

D G Q+ a. Q+ = D*G + D*/G b. /Q+ = /D*G + /Q*/G

X 0 Q 90000A-16
0 1 0
1 1 1 Figure 17. Karnaugh Maps for a D-Type Latch

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If realized exactly as the transfer function indicates, the There are still some potential problems here for the case
result is actually a glitchy circuit. where J and K are both HIGH. If J and K are left HIGH for
too long, the output may change more than one time; if
J-K Latches left HIGH forever, the output will oscillate. Thus, J and K
Another two-input latch can be derived from the S-R should not be asserted for a time longer than the propa-
latch as shown in Figure 18. This is called a J-K latch, gation delay of the latch. There are also potential race
and operates in the same manner as an S-R latch, ex- conditions if J and K are not asserted and removed at
cept that the condition where both inputs are HIGH is exactly the same time. If one of the inputs is raised
now allowed. The truth table is shown in Table 12; the slightly ahead of the other, it may give the output time to
waveforms are shown in Figure 19. react, giving the wrong output once the second input is
raised. The same problem can occur if one input is low-
ered slightly before the other. This is illustrated in
Figure 20.
J Q
S Q J Q There are several ways to derive transfer functions for
J-K latches. Two can be derived directly from Karnaugh
maps, as shown in Figure 21; the others are not as obvi-
K R Q Q K Q
ous, and make use of the XOR gate described before.
The basic transfer functions are listed in Table 13.
90000A-17

Table 13. Transfer Functions for a J-K Latch

Figure 18. A J-K Latch
Q+ = J * /Q /Q+ = /J* /Q
+ /K*Q + K*Q
Table 12. Truth Table for a J-K Latch Q+ = Q /Q+ = /Q
J K Q+ :+: (J* /Q :+: (J*/Q
0 0 Q + K*Q) + K*Q)
0 1 0
Q+ = /Q /Q+ = Q
1 0 1
:+: (/J*/Q :+: (/J*/Q
1 1 Q
+ /K*Q) + /K*Q)

90000A-18

Figure 19. Behavior of a J-K Latch

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δτ δτ

Expected
Levels
a. Falling Edge Race Conditions

δτ δτ

Expected
Levels
b. Rising Edge Race Conditions

tPD OF Latch c. Possible Oscillation

90000A-19

Figure 20. Hazards Inherent in a J-K Latch

Logic Reference Guide 6-15

 AMD
Q Q
J J
K 0 1 K 0 1 Q Q
J Q
00 0 1 00 0 1 T T
Q
K Q Q
01 0 0 01 0 0
90000A-21

11 1 0 11 1 0
Figure 22. A T-Type Latch

10 1 1 10 1 1
Table 14. The Truth Table for a T-Type Latch
T Q+
Q+ /Q+ 0 Q
a. Q+ = J*/Q + /K*Q b. /Q+ = /J*/Q + K*Q 1 /Q

90000A-20
This Latch also has the problem that if T is left HIGH for
too long, the output will oscillate. However, since there is
Figure 21. Karnaugh Maps for a J-K Latch only one input, the race condition problems of the J-K
latch have been eliminated. Unfortunately, this comes at
T-Type Latches the cost of initialization. There is now no way to get the
output into a fixed state without knowing what the
T-type latches are formed by connecting the J and K in- previous state was. Thus, this device is not very useful
puts of a J-K latch together to form a single input, as without some kind of initialization circuit.
shown in Figure 22. This latch has two possible func-
tions: hold the present state or invert the output, as The general waveforms for a T-type latch are shown in
summarized in Table 14. ‘T’ stands for ‘trigger’ or Figure 23.
‘toggle’ depending on who you talk to. That is, when T is
HIGH, a change at the output is triggered; or, put an-
other way, raising T causes the output to toggle.

tPD OF Latch 90000A-22

Figure 23. Behavior of a T-Type Latch

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 AMD
From the Karnaugh map in Figure 24, we can generate sition is detected. A device is classified as positive
the following transfer functions: edge-triggered or negative edge-triggered, depending
on whether it responds to the rising or falling edge of the
Q+ = T*/Q /Q+ = T*Q clock signal, respectively. The behavior to a clocked
+ /T*Q + /T*/Q S-R flip-flop is illustrated in Figure 25.
Q+ = Q:+:T /Q+ = /Q :+: T The clock provides two basic advantages. It removes
Q+ = /Q:+: /T /Q+ = Q :+: /T the hazards inherent in the J-K and T flip-flops, since all
inputs will have settled by the time the clock edge ar-
rives, and only one transition is possible for each clock
Q Q edge. The clock also allows the design of synchronous
T T
0 1 0 1 systems, where all signals are coordinated with other
signals. The entire system is then regulated by the
0 0 1 0 0 1 clock.
The basic behavior of the four flip-flops types does not
1 1 0 1 1 0 change with the addition of a clock; the output changes
are merely made to wait for the clock edge. Thus, the ba-
Q+ /Q+ sic transfer equations for most of the flip-flops are the
a. Q+ = T*/Q + /T*Q b. /Q+ = T*Q + /T*/Q same. We can indicate the clocked nature of the flip-
flops by using the “registered” assignment ‘:=’ instead
90000A-23 of ‘=.’
D-Type Flip-Flops
Figure 24. Karnaugh Maps for a T-Type Latch
This is the only flip-flop type whose basic transfer char-
acteristic changes, because the clock input replaces the
Clocked Flip-Flops gate input. Thus the transfer equations become:
Latches can be modified by adding a clock input. The Q+:= D/Q+ := /D
purpose of the clock is to delay any output changes until
the clock signal changes. Whereas latch control inputs That is, whatever data appears on the input will be trans-
(such as the gate) are level-sensitive, clock inputs are ferred to the output after the next clock edge. The input
generally edge-sensitive (or edge-triggered), meaning is not changed in any way.
that output transitions can occur only when a clock tran-

Logic Reference Guide 6-17

 AMD
The simplicity of this flip-flop makes it the most widely Table 15 summarizes the transfer functions for all of the
used flip-flop. However, functions are sometimes more flip-flop types. These functions can directly be used to
conveniently expressed using J-K flip-flops, or using emulate a particular flip-flop type in a D-type flip-flop.
T-type flip-flops. If we replace the D signal with the This can be particularly useful since D-type flip-flops are
transfer function for one of the other flip-flop types, we available in most registered PLDs.
can then emulate that flip-flop type in the D-type flip-flop.
This is equivalent to taking a latch and placing a clocked
D-type flip-flop after the latch output for synchronization.
Figure 26 illustrates how each flip-flop can be emulated
in a D-type flip-flop. The standard schematic symbols for
the flip-flop types are also shown.

Clock

Qp

Qn

90000A-24

Figure 25. Behavior of a Clocked S-R Flip-Flop for Positive (Qp) and Negative
(Qn) Edge-Triggered S-R Flip-Flops

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 AMD

D Q

Clock Q

a. Clocked D-Type Flip-Flop

J J Q D Q Q J Q

K K Q Q Q K Q

Clock

b. Clocked J-K Flip-Flop

Q D Q Q T Q
T T

Q Q Q Q

Clock

c. Clocked T-Type Flip-Flop

S S Q D Q Q S Q

R T Q Q Q R Q

Clock

d. Clocked S-R Flip-Flop

90000A-25

Figure 26. Clocked Flip-Flops. All can be Emulated with a D-Type Flip-Flop

Logic Reference Guide 6-19

 AMD
Table 15. Clocked Flip-Flop Transfer Functions
D-Type Q+ := D /Q+ := /D
Q+ := J*/Q /Q+ := /J* /Q
+ /K*Q + K*Q
Q+ := Q /Q+ := /Q
J-K-Type :+: (J*/Q :+: (J*/Q
+ K*Q) + K*Q)
Q+ := /Q /Q+ := Q
:+: (/J*/Q :+: (/J*/Q
+ /K*Q) + /K*Q)
Q+ := T*/Q /Q+: = T*/Q
+ /T*Q + /T*/Q
T-Type Q+ := Q:+:T /Q+ := /Q :+: T
Q+ := /Q :+: /T /Q+ := Q :+: /T
S-R-Type Q+ := S /Q+ := R
+ /R*Q + /S*/Q

Binary Numbers decimal number 25 would be written 2510 if its base were
in doubt.
The concept of a number is taken for granted by most
people. And most people equate numbers in general A number can thus be expressed in terms of some base
with the decimal system, with which we are most famil- x as follows:
iar. However, there is nothing particularly special about
the decimal system; the choice of system is actually anxn+an-1xn-1+...+a1x1+a0x0+a–1x–1+...
rather arbitrary. History has chosen the decimal system +a–mX–m
for most humans. (1)

For electronic systems, the binary system is more ap- The numbers an...a–m are called digits. The value of
propriate. It makes possible arithmetic and logical each digit can range from 0 to x–1. Each digit is repre-
calculations that would be much more difficult—likely sented by a symbol, called a numeral. X numerals are
impractical—if implemented directly in a decimal sys- required to represent a number in base x. The most fa-
tem. Closely related to the binary system are the octal miliar numerals are the symbols ‘0,’ ‘1,’...‘9.’ There are
and hexadecimal systems, which will also be discussed ten of them, since they are used for the decimal system.
here. Arithmetic is normally performed using binary For binary numbers, only ‘0’ and ‘1’ are used; for octal
numbers in a computer. Octal and hexadecimal repre- numbers, the numerals ‘0’ through ‘7’ are used. Hexa-
sentations are generally used as a way to “abbreviate” decimal numbers are more difficult, since sixteen
what might otherwise be lengthy binary numbers. This numerals are required. Therefore, the numerals ‘0’
will be seen when conversion is discussed below. through ‘9’ are used to represent the quantities 010
through 910; the letters A through F are used to represent
There are several terms which must be defined before the quantities 1010 through 1510.
proceeding further. A number is an abstract entity
which is used to describe quantity. There are many The number expressed by equation 1 is normally repre-
ways of representing a number. Normally, the represen- sented as a string of digits:
tation is designed around a base. The number is
anan–1...a1a0.a–1...a–m
expressed as a sum of multiples of the powers of the
base. The decimal system is a base-10 system, mean- The digits representing negative powers of the base are
ing that 10 is used as the base. The binary system is separated from those representing non-negative pow-
base-2; the octal system is base-8; and the hexadecimal ers by a point. In the decimal system, this is referred to
system is base-16. The binary, octal, and hexadecimal as a decimal point; in the binary system, it is referred to
systems are closely related because 8 and 16 are both as a binary point.
powers of 2. When different bases are being used, a
number will often be followed by its base in subscript, to There are two basic classes of manipulation which will
indicate exactly what the base is. For example, the be discussed: conversions between bases and arithme-
tic within a base.

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 AMD
Converting Between Bases Here we see that the fraction will repeat, since we have
Base-2 <–> Base-10 already multiplied 0.6 earlier. Thus

Converting a binary number to a decimal number is 0.162510 = 0.00101001100110011...2

accomplished by using equation 1 directly.
For mixed numbers, it is necessary to calculate the
Example: whole and fractional portions separately. Thus, for ex-
ample, we know that
Converting 110100.0112 to decimal:
61.162510 = 111101.0010100110011...2
Y = 110100.011
These are actually general procedures which can be
= 1•25 + 1•24 + 0•23 + 1•22+ 0•21+ 0•20+ 0•2–1 + used to convert a decimal number into any base, and
1•2–2 + 1•2–3 vice versa.
= 32 + 16 + 4 +.25 + .125
= 52.375 Examples:
When converting whole numbers from decimal to bi- 1. Converting 321.548 to decimal:
nary, the decimal number is repeatedly divided by 2.
Integer division is used, so the quotients are “rounded Y = 3•82 + 2•81+1•80+ 5•8–1+ 4•8–2
down” to the next integer. The remainders form the dig- = 192 + 16 + 1 + .625 + .0625
its of the number. The least significant digit is the first = 209.6875
one calculated. 321.548 = 209.687510
Example: 2. Converting 106.1037510 to octal:
Converting 6110 to binary: 106/8 = 13 remainder = 2 LSB
13/8 = 1 remainder = 5
61/2 = 30 remainder = 1 LSB
1/8 = 0 remainder = 1 MSB
30/2 = 15 remainder = 0
15/2 = 7 remainder = 1 Thus, the whole portion is 1518.
7/2 = 3 remainder = 1
3/2 = 1 remainder = 1 0.10375•8 = 0.83 whole portion = 0 MSB
1/2 = 0 remainder = 1 MSB 0.83•8 = 6.64 whole portion = 6
0.64•8 = 5.12 whole portion = 5
6110 =1111012 0.12•8 = 0.96 whole portion = 0
0.96•8 = 7.68 whole portion = 7
When converting a decimal fraction into a binary frac-
0.68•8 = 5.44 whole portion = 5
tion, the decimal number is multiplied by 2. This results
in a whole number and a fraction. The whole number is a At this point we have enough significant digits. We could
digit; the procedure is repeated on the new fraction. This continue either until the procedure terminated, or until
procedure is repeated until the fractional portion is zero. the pattern started repeating. However, those last digits
If the procedure does not terminate, then the result is a are not likely to be significant. Thus, we can approxi-
repeating fraction. The first digit calculated is the most mate by saying that...
significant digit.
106.1037510=152.0650758
Example:
3. Converting 31F.A216 to decimal:
Converting .162510 to binary:
Y = 31F.A216
0.1625•2 = 0.3250 whole portion = 0 MSB = 3•162+ 1•161 + 15•160+ 10•16–1+2•16–2
0.3250•2 = 0.65 whole portion = 0 = 768 + 16 + 15 + 0.625 + 0.0078125
0.65•2 = 1.3 whole portion = 1 = 799.6328125
0.3•2 = 0.6 whole portion = 0
0.6•2 = 1.2 whole portion = 1 31F.A216 = 799.632812510
0.2•2 = 0.4 whole portion = 0 4. Converting 7689.10085410 to hexadecimal:
0.4•2 = 0.8 whole portion = 0
0.8•2 = 1.6 whole portion = 1 7689/16 = 480 remainder = 9 LSB
0.6•2 = 1.2 whole portion = 1 480/16 = 30 remainder = 0
30/16 = 1 remainder = E
1/16 = 0 remainder = 1 MSB

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 AMD
Thus, the whole portion is 1EO916. Examples:
0.100854•16 = 1.613664 whole portion = 1 MSB 1. Convert 7324.348 to binary:
0.613664•16 = 9.818624 whole portion = 9
0.818624•16 = 13.097984 whole portion = D 7 3 2 4 . 3 4
0.097984•16 = 1.567744 whole portion = 1 111 011 010 100 . 011 100
0.567744•16 = 9.083904 whole portion = 9
Thus 7324.348 = 111011010100.01112
0.083904•16 = 1.342464 whole portion = 1
2. Convert 1A2.3F516 to binary:
Again, we likely have enough digits at this point. The ex-
act fraction could be either very long or a long repeating 1 A 2 . 3 F 5
pattern. For our purposes, we can approximate the 0001 1010 0010 . 0011 1111 0101
overall result as:
Thus 1A2.3F516= 110100010.0011111101012
7689.10085410 = 1E09.19D19116
Binary Arithmetic
Binary <–> Octal, Hexadecimal
Positive binary arithmetic is very simple, and completely
Converting between the binary-related systems is very analogous to decimal arithmetic. However, if we are re-
easy. The procedure consists of dividing the binary dig- stricted to positive numbers, then we are also restricted
its into groups, and replacing each group with an to addition. We need a means of representing negative
appropriate digit. For this reason, octal and hexadeci- numbers. Using a dash ‘–’ is unacceptable for represen-
mal numbers are often used to shorten long binary tation in a computer. There are two general schemes
numbers. which can be used. In binary systems, they are referred
to as 1s complement and 2s complement representa-
To convert from binary to octal, group the digits by three,
tion, although they can be generalized for any base
starting on each side of the binary point, and then con-
system as diminished-radix complement and radix com-
vert each group of three digits into its corresponding
plement representation.
octal digit. Leading and trailing zeroes may have to be
added to the left of the whole portion and the right of the One’s Complement Representation
fractional portion, respectively, to make complete
groups of three binary digits. The one’s complement of a binary number can be calcu-
lated by inverting all of the bits of the number. Fractions
Example: are handled exactly the same way, although this is con-
venient only for fixed-point arithmetic. Floating-point
Converting 11011010110101.0010011012 to octal: arithmetic requires other methods, which will not be dis-
Divide into groups of three digits: cussed here.

011 011 010 110 101 . 001 001 101 Example:

3 3 2 6 5 . 1 1 5 Finding the one’s complement of 110111.0101:
Thus 11011010110101.0010011012 = 33265.1158 110111.0101
001000.1010 (Inverting each bit)
To convert from binary to hexadecimal, the digits are di-
vided into groups of four digits, and then given their Thus, the one’s complement of 110111.0101 is
corresponding hexadecimal digits. Again, leading and/ 001000.1010.
or trailing zeroes may be needed.
The sign of a number is determined by the most signifi-
Example: cant bit. If the MSB is 0 the number is positive; if the MSB
is 1, then the number is negative. Zero is represented by
Converting 100101011101100.1101100012 to hexa-
all bits being zero. However, one normally thinks of zero
decimal:
as being its own complement. But if we take the one’s
Divide into groups of four digits: complement of zero,

0100 1010 1110 1100 . 11011000 1000 0000

4 A E C . D 8 8 1111

Thus 100101011101100.1101100012 = 4AEC.D8816 we see that 1111 is another representation of zero.

Thus, in an eight-bit representation, positive numbers
To convert from octal or hexadecimal to binary, merely range from 00000001 to 01111111; negative numbers
expand each digit into its corresponding binary range from 10000000 to 11111110. Note that there are
representation. just as many negative numbers as positive numbers.

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 AMD
This eight-bit code allows us to represent the numbers Add 3 + 2:
from –127 to +127. 0011 3
+ 0010 + 2
When performing addition with one’s complement num- 0101 5 result meaningful
bers, it is important to watch for overflow results.
Whenever an overflow occurs, a correction must be Add 7 + 7 (14 cannot be represented):
made by adding 1 to the result.
0111 7
In some cases, the results of an operation will not be + 0111 + 7
meaningful, since the intended result cannot be repre- 1110 –1 result
sented. For instance, in the eight-bit system above, meaningless
adding 127 to 127 will give a meaningless result, since Subtract 3 from 7:
254 cannot be represented in this system. Thus, the op- 0111 7
eration must be evaluated to ensure that the result is + 1100 + –3
meaningful. 10011 overflow – add 1,
+1 discard overflow
Examples: 0100 4 bit
All examples will use 4-bit systems. Thus, the range of Subtract 5 from 2:
representable numbers is from –7 to +7.
0010 2
+ 1010 + –5
1100 –3 result meaningful

Subtract 6 from –5 (–11 cannot be represented):

1010 –5
+ 1001 + –6
10011 overflow – add 1,
+1 discard overflow bit
0100 4 result meaningless

Subtract 5.25 from 3.5 (fixed point; requires 6 bits):

0011.10 3.5
+ 1010.10 + –5.25
1110.00 –1.75 result meaningful

Subtract 7 from 7:
0111 7
+ 1000 + –7
1111 0 one of the
representations of 0

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 AMD
The advantage of one’s complement code is the fact Examples:
that it is easy to compute the complement. However, the
fact that there are two representations for zero is a prob- Add 3 + 2:
lem. In addition, the results of subtraction frequently 0011 3
have to be adjusted for overflow by adding 1. + 0010 + 2
0101 5 result meaningful
Two’s Complement Representation
Add 7 + 7 (14 cannot be represented):
The two’s complement of a binary number is more diffi-
cult to calculate. It is generated by taking the one’s 0111 7
complement, and then adding 1. Any overflow is dis- + 0111 + 7
carded. Fractions are again handled in the same way, 1110 –2 result meaningless
although 1 is added to the least significant bit.
Subtract 3 from 7:
Example: 0111 7
+ 1101 + –3
Finding the two’s complement of 110111.0101: 10100 4 overflow – discard
110111.0101 overflow bit
001000.1010 (take one’s Subtract 5 from 2:
+1 complement) 0010 2
001000.1011 + 1011 + –5
1101 –3 result meaningful
Thus, the two’s complement of 110111.0101 is
001000.1011. Subtract 6 from –5 (–11 cannot be represented):
The sign of a number is again determined by the most 1011 –5
significant bit. If the MSB is 0 the number is positive; if + 1010 + –6
the MSB is 1, then the number is negative. Zero is repre- 10101 5 overflow – discard
sented by all bits being zero. In this case, if we take the overflow bit result
two’s complement of zero, we get: meaningless

0000 Subtract 5.25 from 3.5 (fixed point; requires 6 bits):

1111 0011.10 3.5
+1 + 1010.11 + –5.25
0000 (overflow is discarded) 1110.01 –1.75 result meaningful

giving only one representation for zero. Subtract 7 from 7:

Thus, in an eight-bit representation, positive numbers 0111 7
range from 00000001 to 01111111; negative numbers + 1001 + –7
range from 10000000 to 11111111. This means that 10000 0 overflow – disregard
there is one more negative number than there are posi- overflow bit
tive numbers. So this eight-bit code allows us to
The benefits of two’s complement lie in the fact that
represent the numbers from –128 to +127.
there is only one representation for zero, and the fact
Addition is handled in the same fashion as with one’s that the results of operations never need adjusting due
complement code, except that when an overflow oc- to overflow. The disadvantage is the fact that it is harder
curs, the overflow bit is disregarded. No correction must to generate the two’s complement of a number.
be made to the results.
After any operation, one must still make sure that the re-
sults are meaningful.

6-24 Logic Reference Guide