IIT Syllabus
IIT Syllabus
IIT Syllabus
Semester 2
Subject L-T-P Credits
Core 3 High Performance Computer Arch. 4-0-0 4
Elective 4 3-0-0 3
Elective 5 3-0-0 3/4
Elective 6 3-0-0 3/4
Elective 7 3-0-0 3/4
Semester 3
Subject L-T-P Credits
CS67001 Project 20
CS68002 Comprehensive Viva Voce 3
Total: 23
Semester 4
Sub. No. Subject L-T-P Credits
CS67002 Project 20
Total: 20
Out of 20 credit in Project, 4 credits for project work during Summer vacation (from
May to July)
Propositional logic, First Order Logic: syntax and semantics, deduction, Herbrand
interpretation and resolution methods, Syntax and Semantics of Logic Programs,
Inference Rules, Unification and SLD-Resolution, Negation as Failure, Logic
programming language PROLOG - a case study. Basic concepts, Recursive
programming, Cuts and negation, Non-deterministic programming, Abstract
computational model - Warren s Abstract Machine (WAM), Implementation of
Prolog on WAM. Introduction to Constraint Logic Programming: Constraint logic
programming scheme, Constraint satisfaction, constraint propagation, Constraint
Logic Programming over the reals, Constraint Logic Programming over finite
domains. Introduction to nonclassical logics. Modal logic. Accessibilty. Relation and
Kripke possible world semantics. The logic of knowledge and belief, Autoepistemic
knowledge, Temporal logic.
Suggested Text:
Physical faults and their modeling. Fault equivalence and dominance; fault collapsing.
Fault simulation: parallel, deductive and concurrent techniques; critical path tracing.
Test generation for combinational circuits: Boolean difference, D-algorithm, Podem,
etc. Exhaustive, random and weighted test pattern generation; aliasing and its effect
on fault coverage. PLA testing: cross-point fault model, test generation, easily testable
designs. Memory testing: permanent, intermittent and pattern-sensitive faults; test
generation. Delay faults and hazards; test generation techniques. Test pattern
generation for sequential circuits: ad-hoc and structures techniques, scan path and
LSSD, boundary scan. Built-in self-test techniques. Verification: logic level
(combinational and sequential circuits), RTL-level (data path and control path).
Verification of embedded systems. Use of formal techniques: decision diagrams,
logic-based approaches.
Problem solving by search: state space, problem reduction, game playing, constraint
satisfaction; Automated Reasoning: proposition and first order logic, inference and
deduction, resolution refutation, answer extraction, knowledge based systems, logic
programming and constrained logic programming, non-monotonic reasoning;
Planning: state-space, plan space and partial order planning, planning algorithms;
Reasoning under Uncertainty: probabilistic reasoning, belief networks; Learning:
inductive learning, decision trees, logical approaches, computational learning theory,
Neural networks, reinforcement learning; Intelligent Agents; Natural Language
Understanding; Applications.
Introduction to real time system, embedded systems and reactive systems; Hard and
Soft Real Time Systems; Handling real time; Specification and Modeling; Design
methods; Real Time operating systems; Validation and Verification; Real time
Process and Applications; Distributed Real Time Systems.
Introduction to VLSI Design, Different types of VLSI design styles: Full custom,
standard cell based, gate array based, programmable logic, field programmable gate
arrays etc. VLSI Design flow. CMOS logic: PMOS, NMOS and CMOS, Electrical
characteristics, operation of MOS transistors as a switch and an amplifier, MOS
inverter, stick diagram, design rules and layout, delay analysis, different type of MOS
circuits: Dynamic logic, BiCMOS, pass transistors etc. CMOS process,
Combinational logic cells, Sequential logic cells, Datapath logic cells, I/O cells. ASIC
Library Design: Transistors as Resistors and parasitic Capacitance, Logical effort,
gate array, standard cell and datapath cell design. Introduction to hardware description
language (HDL) Verilog/VHDL. A logic synthesis example. Floor-planning and
Placement: I/O and power planning, clock planning. Routing global and detailed.
Example design technique: mapping of architecture to silicon.
Formal languages and their related automata, Turing machines, type-0 languages,
linear bounded automata and CSLs. Time and tape bounded Turing machines, time
and space bounds for recognizing CFLs. Turing Computability: number theoretic
computations by Turing machines and indexing. Axiomatic systems, their soundness
and completeness. Recursive function theory: primitive recursive functions and
primitive recursive predicates. Ackermann's function, recursive and general recursive
functions. Computability and decidability: computable functions, computable sets,
decision problems. Fixpoint theory of programs, functions and functionals,
verification methods, Lambda calculus and applications.
CS 60076 Advances in Digital & Mixed Signal Testing L-T-P: 3-0-0, Credit: 3
Delay fault testing: path delay test, transition faults, delay test methodologies. IDDQ
testing: basic concept, faults detected, test generation, limitations, IDDQ design for
testability. Functional testing of arithmetic and regular arrays. Functional testing of
microprocessors and microcontrollers. Sequential circuit testing: time frame
expansion and simulation-based approaches to ATPG, design of testable FSMs, use of
coding theory. Advanced BIST techniques: theory of linear machines, practical BIST
architectures. System-on-chip design and test: SOC testing problem, core-based
design and system wrapper, proposed test architectures for SOC, platform-based
design and testability issues.
DSP-based analog and mixed-signal test: functional DSP-based testing, static ADC
and DAC testing methods, realizing emulated instruments, CODECD testing, future
challenges. Model-based analog and mixed-signal test: analog fault models, levels of
abstraction, analog fault simulation, analog ATPG. Analog test bus standard: analog
circuit DFT, analog test bus, IEEE 1149.4 standard.
3. A. Krstic and K-T. Cheng, “Delay fault testing for VLSI circuits”, Kluwer
Academic Publishers, 2003.
Models of network growth: Price's model, Barabasi and Albert's model, other
growth models, vertex copying models.
References
• Models of computation and efficiency: Searching faster than O(log n), sorting
faster than O(n log n).
• Randomized algorithms in graphs and geometry: The impact of using
randomization for designing algorithms that are simpler and often more
efficient than the deterministic counterparts for several fundamental problems
like MST, mincuts, spanners, convex hulls, triangulations, etc. Typically
analysis is often harder than design.
• Approximation algorithms: A set of rapidly evolving techniques that lead to
provable approximation guarantees for hard optimization problems within
polynomial running times. Unlike other communities dealing with the same
problems the emphasis here is on provability of general instances and goes
hand-in-hand with the "hardness of approximation" theory.
Each of the topics on their own could be easily a full semester course, so depending
on the class response, we may pick and choose from the above list of topics.
Elliptic curves: The elliptic curve group, elliptic curves over finite fields, Schoof's
point counting algorithm.
Integer factoring algorithms: Trial division, Pollard rho method, p-1 method,
CFRAC method, quadratic sieve method, elliptic curve method.
References
Assumptions for Public Key Signature Schemes: One way functions Imply Secure
One-time Signatures
Socket programming, database creation and update, building large client server
applications. Basics of compiler writing using lex and yacc.
Prerequsites: None