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Simulation practice using a PLD
NAME: EVELIN AMÉRICA BELMARES RUBALCAVA
UP200958
it focuses on describing the function of the entity and
the architecture.
Resumen—During this project we worked on 4 different circuits in Quartus II is a software tool produced by Altera for the
VHDL, which were Multiplexer MUX 74x151, Decoder 74x138, Decoder analysis and synthesis of designs made in HDL. Quartus
74x49 (7 segments), Custom decoder, we describe their operation, II allows the developer to compile their designs,
according to truth tables and gate diagrams, the process It was concise perform temporal analysis, examine RTL diagrams, and
with the programming, we implemented the necessary libraries in configure the target device with the scheduler.
addition to that step by step according to the programming, it was
commented. After finishing the programming, each of the VHDLs was
simulated in Behavioral, comparing the results of the simulation with Multiplexers are combinational circuits with several
the truth table, and analyzing what was described in the code. The two inputs and one data output, and are provided with
processes were completed, all the results were successfully obtained, control inputs capable of selecting one of the data
then the report was prepared, explaining in detail for a better inputs to allow its transmission from the selected input
understanding of the project. to the single output.

I. INTRODUCTION
Intel's Quartus is a Hardware description language, very useful
for working with absolutely everything internal to an integrated
circuit, because you work directly with the design that was
given to the hardware, you can work with both combinational
and sequential circuits, in this In this project we describe
several types of integrated circuits that are very useful in
common use, finally we know how they behave internally, the
quartus program has the option of simulating how the circuits
that we describe are going to work, and thus we can modify any
anomaly in relation to the truth table, this is very useful to us
because when working with these integrated you have to be
exact in the behavior of both inputs and outputs
The selected input is determined by the combination
of logic zeros (0) and logic ones (1) on the control
II. THEORETICAL FRAMEWORK
inputs. The number of control inputs that we will need
to select will be the result of raising the 2 to a power
VHDL allows both a description of the structure of the circuit
and the specification of the functionality of a circuit using forms A decoder is a combinational circuit, whose function is
familiar to programming languages tonality of a circuit using inverse to that of the encoder, that is, it converts an
forms familiar to programming languages. input binary code (natural, BCD, etc.) of N input bits
The most important mission of a hardware description and M output lines (N can be any integer and M is an
language is that it be able to perfectly simulate the integer less than or equal to 2N), such that each output
logical behavior of a circuit without the line will be activated for only one of the possible input
programmer need to impose restrictions combinations. Normally, these circuits are usually
found as a decoder / demultiplexer. This is because a
demultiplexer can behave like a decoder.

VHDL is not a programming language, therefore knowing its

syntax does not imply necessarily knowing how to design with
it. VHDL is a hardware description language, which
It allows to describe synchronous and asynchronous circuits.
Within the structure of a program, the Entity and Architecture
units Together they form the backbone of this language. For their
part, the remaining modules, not necessarily used in the search
for a solution, serve, among other things, to optimize and
generalize the application in
future developments, as will be seen when the
opportunity arises. However, at this time our attention III. CIRCUITS
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1.- Multiplexer MUX 74x151 and as specified in the truth table, only a part of the G
simulation can be attached but in what is attached the E
results are well appreciated. 1

2.- Decoder 74x138

Figure 1.1 Multiplexer MUX 74x151 true table.

Figure 2.1 Decoder 74x138 true table.
The SN74LS151N is an 8 to 1 line data selector or The SN74LS138N is a 3 to 8 line, TTL Schottky-clamped
multiplexer with on-chip binary decoding to select the decoder/demultiplexer designed for use in high
desired data source, this truth table helped us perfectly performance memory decoding or data routing
to know what the circuit should do and be able to applications requiring very short propagation delay
describe it in the program. times.

Figure 1.2 Multiplexer MUX 74x151 VHDL code. Figure 2.2 Decoder 74X138 VHDL code.

During the description of the circuit, we commented and several From this circuit you can see how we put each case of
versions were made to reach the final, in addition to adding certain how it will behave according to the truth table, but
extra functions for future modifications. when it already exceeds numbers that are not in it, we
put the option to return a specific result which is very
easy to realize when that case occurs.

Figure 1.2 Multiplexer MUX 74x151 VHDL simulation.

The simulation gave the perfect results as described Figure 2.3 Decoder 74x138 VHDL simulation.
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The simulation gave the perfect results as described
and as specified in the truth table, only a part of the 1
simulation can be attached but in what is attached the
results are well appreciated.

3.- 74x49 Decoder (7 segments)

Figure 3.3 Decoder 74x49 VHDL simulation.

The simulation gave the perfect results as described

Figure 3.1 Decoder 74x49 true table. and as specified in the truth table, only a part of the
simulation can be attached but in what is attached the
ABCD to 7-segment decoders are widely used to results are well appreciated.
simplify the use of 7-segment displays, commonly
used to show the decimal digits from 0 to 9 on a small 3.- Custom decoder.
screen made up of LEDs..

Figure 4.1 Custom Decoder true table.

This modification to the decoder is interesting since
we apply some logic gates to the outputs and it is also
interesting how the description worked.

Figure 3.2 Decoder 74x49 VHDL code.

For this code a description for a common cathode

display was used and it is perfectly specified there and
we also added several settings for later modifications.

Figure 4.2 Custom Decoder VHDL code.

The modifications are clear, the code is correctly
described and the necessary logical operations are
applied to agree on how the circuit behaves.
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Figure 4.3 Custom Decoder VHDL simulation.

The simulation gave the perfect results as described

and as specified in the truth table, only a part of the
simulation can be attached but in what is attached the
results are well appreciated.

IV. CONCLUSION
V. I considerthat the most
important thing of all is to carry out first
of all a planning of whatwhat is wanted to
be done and what is expected to be
obtained when a project is carried out,
thereforemust develop a correct
evaluation of the possible alternatives
that are had beforeto start anything,
both the product to be purchased as well
as thepossible paths to implementation.

VI. BIBLIOGRAPHIES
https://selinc.com/es/mktg/133751/?creative=5
18028975578&keyword=multiplexor%20mux
&matchtype=b&network=g&device=c&gclid=
Cj0KCQiAu62QBhC7ARIsALXijXRSlvXW_
KMBXthYJRmtd_MM_Qk3fWVJ640gHiG68
V-fTJipsR2EqBoaAsLeEALw_wcB
https://unicrom.com/decodificador/