E2O0009-16-81

¡ Semiconductor
¡ Semiconductor MSM80C85AHRS/GS/JS

MSM80C85AHRS/GS/JS
8-Bit CMOS MICROPROCESSOR

GENRAL DESCRIPTION

The MSM80C85AH is a complete 8-bit parallel; central processor implemented in silicon gate C-MOS
technology and compatible with MSM80C85A.
It is designed with higher processing speed (max.5 MHz) and lower power consumption compared
with MSM80C85A and power down mode is provided, thereby offering a high level of system
integration.
The MSM80C85AH uses a multiplexed address/data bus. The address is split between the 8-bit
address bus and the 8-bit data bus. The on-chip address latch : of a MSM81C55-5 memory product
allows a direct interface with the MSM80C85AH.

FEATURES

• Power down mode (HALT-HOLD)

• Low Power Dissipation: 50mW(Typ)
• Single + 3 to + 6 V Power Supply
• –40 to + 85°C, Operating Temperature
• Compatible with MSM80C85A
• 0.8 ms instruction Cycle (VCC = 5V)
• On-Chip Clock Generator (with External Crystal)
• On-Chip System Controller; Advanced Cycle Status Information Available for Large System
Control
• Bug operation in MSM80C85AH is fixed
• Four Vectored interrupt (One is non-maskable) Plus the 8080A-compatible interrupt. 5
• Serial, In/Serial Out Port
• Decimal, Binary and Double Precision Arithmetic
• Addressing Capability to 64K Bytes of Memory
• TTL Compatible
• 40-pin Plastic DIP(DIP40-P-600-2.54): (Product name: MSM80C85AHRS)
• 44-pin Plastic QFJ(QFJ44-P-S650-1.27): (Product name: MSM80C85AHJS)
• 44-pin Plastic QFP(QFP44-P-910-0.80-2K): (Product name: MSM80C85AHGS-2K)

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 MSM80C85AHRS/GS/JS ¡ Semiconductor

FUNCTIONAL BLOCK DIAGRAM

RST

INTR INTA 5.5 6.5 7.5 TRAP SID SOD

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus

Accumulator Temporary Register Flag (5) Instruction

(8) (8) Flip Flops Register (8)

Instruction B REG (8) C REG (8)

Arithmetic
Logic Unit Decoder
And D REG (8) E REG (8)
ALU(8)
Machine
H REG (8) C REG (8)
Cycle Register
Encoding Stack Pointer (16) Array

Power Program Counter (16)

+5V
Supply GND Incrementer/Decrementer
Address Latch (16)

Power Down
Timing And Control
X1 CLK
GEN Control Status DMA Reset Data/Address
X2 Address Buffer (8)
Buffer (8)

CLK READY RD WR ALE S0 S1 IO / M HOLD HLDA RESET IN RESET OUT A15 - A8 AD7 - AD0
OUT Address Bus Address/Data Bus

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¡ Semiconductor MSM80C85AHRS/GS/JS

PIN CONFIGURATION (TOP VIEW)

40 pin Plastic DIP
X1 1 40 VCC
X2 2 39 HOLD
RESET OUT 3 38 HLDA
SOD 4 37 CLK(OUT)
SID 5 36 RESET IN
TRAP 6 35 READY
RST7.5 7 34 IO/M
RST6.5 8 33 S1
RST5.5 9 32 RD
INTR 10 31 WR
INTA 11 30 ALE
AD0 12 29 S0
44 pin Plastic QFP AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
42 RESET OUT

AD4 16 25 A12
35 CLK(OUT)
34 RESET IN

AD5 17 24 A11
37 HOLD
36 HLDA
43 SOD

AD6 18 23 A10
38 VCC
44 SID

39 NC
41 X2
40 X1

AD7 19 22 A9
GND 20 21 A8

TRAP 1 33 READY
RST7.5 2 32 IO/M
RST6.5 3 31 S1
RST5.5 4 30 RD
INTR 5 29 WR
INTA 6 28 ALE
AD0 7 27 S0
AD1 8 26 A15
AD2 9 25 A14
AD3 10 24 A13 44 pin Plastic QFJ
NC 11 23 A12

5
4 RESET OUT
AD4 12
AD5 13
AD6 14
AD7 15
GND 16
VCC 17
A8 18
A9 19
A10 20
A11 21
NC 22

41 CLK(OUT)
40 RESET IN
43 HOLD
42 HLDA
5 SOD

44 VCC
6 SID

1 NC
3 X2
2 X1

TRAP 7 39 READY
RST7.5 8 38 IO/M
RST6.5 9 37 S1
RST5.5 10 36 RD
INTR 11 35 WR
NC 12 34 NC
INTA 13 33 ALE
AD0 14 32 S0
AD1 15 31 A15
AD2 16 30 A14
AD3 17 29 A13
AD4 18
NC 19
AD5 20
AD6 21
AD7 22
GND 23
A8 24
A9 25
A10 26
A11 27
A12 28

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 MSM80C85AHRS/GS/JS ¡ Semiconductor

MSM80C85AH FUNCTIONAL PIN DEFINITION

The following describes the function of each pin:

Symbol Function
A8 - A15 Address Bus: The most significant 8-bits of the memory address or the 8-bits of the I/O address,
(Output, 3-state) 3-stated during Hold and Halt modes and during RESET.
A0 - A7 Multiplexed Address/Data Bus: Lower 8-bits of the memory address (or I/O address) appear on
(Input/Output) the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during
3-state the second and third clock cycles.
ALE Address Latch Enable: It occurs during the first clock state of a machine cycle and enables address to
(Output) get latched into the on-chip latch peripherals. The falling edge of ALE is set to guarantee setup and
hold times for the address information. The falling edge ALE can also be used to strobe the status
information ALE is never 3-state.
S0 , S1 , IO/M Machine cycle status:
(Output) IO/M S1 S0 States IO/M S1 S0 States
0 0 1 Memory write 1 1 1 Interrupt Acknowledge
0 1 0 Memory read . 0 0 Halt = 3-state
1 0 1 I/O write . ¥ ¥ Hold (high impedance)
1 1 0 I/O read . ¥ ¥ Reset ¥ = unspecified
0 1 1 Opcode fetch
S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of
a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch
the state of these lines.
RD READ control: A low level on RD indicates the selected memory or I/O device is to be read that
(Output, 3-state) the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and during RESET.
WR WRITE control: A low level on WR indicates the data on the Data Bus is to be written into the selected
(Output, 3-state) memory or I/O location. Data is set up at the trailing edge of WR, 3-stated during Hold and Halt
modes and during RESET.
READY If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to
(Input) send or receive data. If READY is low, the cpu will wait an integral number of clock cycles for READY
to go high before completing the read or write cycle READY must conform to specified setup and
hold times.

5 HOLD
(Input)
HOLD indicates that another master is requesting the use of the address and data buses.
The cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion
of the current bus transfer. Internal processing can continue. The processor can regain the bus only
after the HOLD is removed. When the HOLD is acknowledged, the Address, Data, RD, WR, and IO/M
lines are 3-stated. And status of power down is controlled by HOLD.
HLDA HOLD ACKNOWLEDGE: Indicates that the cpu has received the HOLD request and that it will
(Output) relinquish the bus in the next clock cycle. HLDA goes low after the Hold request is removed.
The cpu takes the bus one half clock cycle after HLDA goes low.
INTR INTERRUPT REQUEST: Is used as a general purpose interrupt. It is sampled on during the next to
(Output) the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program
Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle
a RESTART or CALL instruction can be inserted to jump to the interrupt service routine.
The INTR is enabled and disabled by software. It is disabled by Reset and immediately after
an interrupt is accepted. Power down mode is reset by INTR.
INTA INTERRUPT ACKNOWLEDGE: Is used instead of (and has the same timing as) RD during
(Output) the instruction cycle after an INTR is accepted.
RST 5.5 RESTART INTERRUPTS: These three inputs have the same timing as INTR except they cause
RST 6.5 an internal RESTART to be automatically inserted.
RST 7.5 The priority of these interrupts is ordered as shown in Table 1. These interrupts have a higher priority
(Input) than INTR. In addition, they may be individually masked out using the SIM instruction.
Power down mode is reset by these interrupts.
TRAP Trap interrupt is a nonmaskable RESTART interrupt. It is recognized at the same timing as INTR or
(Input) RST 5.5 - 7.5. It is unaffected by any mask or Interrupt Disable. It has the highest priority of any
interrupt. (See Table 1.) Power down mode is reset by input of TRAP.

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Symbol Function
Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops and release
power down mode. The data and address buses and the control lines are 3-stated during RESET and
RESET IN because of the asynchronous nature of RESET IN, the processor's internal registers and flags may be
(Input) altered by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing
connection to an R-C network for power-on RESET delay. The cpu is held in the reset condition as
long as RESET IN is applied.
RESET OUT Indicated cpu is being reset. Can be used as a system reset. The signal is synchronized to
(Output) the processor clock and lasts an integral number of clock periods.
X1 and X2 are connected to a crystal to drive the internal clock generator. X1 can also be an external
X1, X2
clock input from a logic gate. The input frequency is divided by 2 to give the processor's internal
(Input)
operating frequency.
CLK
Clock Output for use as a system clock. The period of CLK is twice the X1, X2 input period.
(Output)
SID Serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM instruction
(Input) is executed.
SOD
(Output) Serial output data line. The output SOD is set or reset as specified by the SIM instruction.

VCC + 5 Volt supply

GND Ground Reference.

Table 1 Interrupt Priority, Restart Address, and Sensitivity

Address Branched To (1)
Name Priority Type Trigger
When Interrupt Occurs
TRAP 1 24H Rising edge and high level unit sampled.
RST 7.5 2 3CH Rising edge (latched).
RST 6.5 3 34H High level unitl sampled.
RST 5.5 4 2CH High level until sampled. 5
INTR 5 (2) High level until sampled.

Notes: (1) The processor pushes the PC on the stack before branching to the indicated
address.
(2) The address branched to depends on the instruction provided to the cpu when
the interrupt is acknowledged.

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 MSM80C85AHRS/GS/JS ¡ Semiconductor

FUNCTIONAL DESCRIPTION

The MSM80C85AH is a complete 8-bit parallel central processor. It is designed with silicon gate C-
MOS technology and requires a single +5 volt supply. Its basic clock speed is 5 MHz, thus improving
on the present MSM80C85A's performance with higher system speed and power down mode. Also
it is designed to fit into a minimum system of two IC's: The CPU (MSM80C85AH), and a RAM/IO
(MSM81C55-5)

The MSM80C85AH has twelve addressable 8-bit register pairs. Six others can be used interchangeably
as 8-bit registers or 16-bit register pairs. The MSM80C85AH register set is as follows:

Mnemonic Register Contents

ACC or A Accumulator 8-bits
PC Program Counter 16-bit address
BC, DE, HL General-Purpose Registers; data pointer (HL) 8-bit ¥ 6 or 16-bits ¥ 3
SP Stack Pointer 16-bit address
Flags or F Flag Register 5 flags (8-bit space)

The MSM80C85AH uses a multiplexed Data Bus. The address is spilt between the higher 8-bit
Address Bus and the lower 8-bit Address/Data Bus. During the first T state (clock cycle) of a machine
cycle the low order address is sent out on the Address/Data Bus. These lower 8-bits may be latched
externally by the Address Latch Enable signal (ALE). During the rest of the machine cycle the data
bus is used for mamory or I/O data.

The MSM80C85AH provides RD, WR, S0, S1, and IO/M signals for bus control. An Interrupt
Acknowledge signal (INTA) is also provided. Hold and all Interrupts are synchronized with the
processor's internal clock. The MSM80C85AH also provides Serial Input Data (SID) and Serial
Output Data (SOD) lines for a simple serial interface.
5 In addition to these features, the MSM80C85AH has three maskable, vector interrupt pins, one
nonmaskable TRAP interrupt and power down mode with HALT and HOLD.

INTERRUPT AND SERIAL I/O

The MSM80C85AH has 5 interrupt inputs: INTR, RST 5.5 RST 6.5, RST 7.5, and TRAP. INTR is
identical in function to the 8080A INT. Each of the three RESTART inputs, 5.5, 6.5, and 7.5, has a
programmable mask. TRAP is also a RESTART interrupt but it is nonmaskable.

The three maskable interrupts cause the internal execution of RESTART ( saving the program
counter in the stack branching to the RESTART address) it the interrupts are enable and if the
interrupt mask is not set. The nonmaskable TRAP causes the internal execution of a RESTART vector
independent of the state of the interrupt enable or masks. (See Table 1.)

There are two different types of inputs in the restart interrupt. RST 5.5 and RST 6.5 are high level-
sensitive like INTR (and INT on the 8080A) and are recognized with the same timing as INTR. RST
7.5 is rising edge-sensitive.

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For RST 7.5, only a pulse is required to set an internal flip-flop which generates the internal interrupt
request. The RST 7.5 request flip-flop remains set until the request is serviced. Then it is reset
automatically, This flip-flop may also be reset by using the SIM instruction or by issuing a RESET IN
to the MSM80C85AH. The RST 7.5 internal flip-flop will be set by a pulse on the RST 7.5 pin even
when the RST 7.5 interrupt is masked out.

The interrupts are arranged in a flixed priority that determines which interrupt is to be recognized
if more than one is pending, as follows: TRAP-highest priority, RST 7.5, RST 6.5, RST 5.5, INTR-
lowest priority. This priority scheme does not take into account the priority of a routine that was
started by a higher priority interrupt. RST 5.5 can interrupt an RST 7.5 routine if the interrupt are re-
enabled before the end of the RST 7.5 routine.

The TRAP interrupt is useful for catastrophic evens such as power failure or bus error. The TRAP
input is recognized just as any other interrupt but has the highest priority. It is not affected by any
flag or mask. The TRAP input is both edge and level sensitive. The TRAP input must go high and
remain high until it is acknowledged. It will not be recognized again until it goes low, then high again.
This avoids any false triggering due to noise or logic glitches. Figure 3 illustrates the TRAP interrupt
request circuitry within the MSM80C85AH. Note that the servicing of any interrupt (TRAP, RST 7.5,
RST 6.5, RST 5.5,INTR) disables all future interrupts (except TRAPs) until an El instruction is
executed.

The TRAP interrupt is special in that it disables interrupts, but preserves the previous interrupt
enable status. Performing the first RIM instruction following a TRAP interrupt allows you to
determine whether interrupts were enabled or disabled prior to the TRAP. All subsequent RIM
instructions provide current interrupt enable status. Performing a RIM instruction following INTR
or RST 5.5-7.5 will provide current interrupt Enable status, revealing that Interrupts are disabled.

The serial I/O system is also controlled by the RIM and SIM instructions. SID is read by RIM, and
SIM sets the SOD data.

External TRAP Inside the MSM80C85AH 5

Interrupt Request TRAP

RESET
RESET IN Schmitt TRAP
Trigger
+5 V D CLK Interrupt
Request
Q
D
F/F
Clear
Internal
TRAP F.F
TRAP
Acknowledge

Figure 3 Trap and RESET IN Circuit

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 MSM80C85AHRS/GS/JS ¡ Semiconductor

DRIVING THE X1 AND X2 INPUTS

You may drive the clock inputs of the MSM80C85AH with a crystal, or an external clock source. The
driving frequency must be at least 1 MHz, and must be twice the desired internal clock frequency;
hence, the MSM80C85AH is operated with a 6 MHz crystal (for 3 MHz clock). If a crystal is used,
it must have the following characteristics:

Parallel resonance at twice the clock frequency desired

CL (load capacitance) £ 30 pF
CS (shunt capacitance) £ 7 pF
RS (equivalent shunt resistance) £ 75 ohms
Drive level: 10 mW
Frequency tolerance: ±0.05% (suggested)

Note the use of the capacitors between X1, X2 and ground. These capacitors are required to assure
oscillator startup at the correct frequency.
Figure 4 shows the recommended clock driver circuits. Note in B that a pull-up resistor is required
to assure that the high level voltage of the input is at least 4 V.
For driving frequencies up to and including 6 MHz you may supply the driving signal to X, and leave
X2 open-circuited (Figure 4B). To prevent self-oscillation of the MSM80C85AH, be sure that X2 is not
coupled back to X1 through the driving circuit.

A. Quartz Crystal Clock Driver B. 1 - 10 MHz Input Frequency External

Clock Drive Circuit

X1 MSM80C85AH
X1
C1
CINT = 15 pF VIH > 0.8 VCC
High time > 40 ns
C2
Low time > 40 ns
5 X2 * X2

33 pF Capacitor required for crystal frequency 10 to 6.25 MHz

50 pF Capacitor required for crystal frequency 6.25 to 4 MHz * X2 Left Floating
100 pF Capacitor required for crystal frequency <4 MHz
Note: Since the constant values may vary depending on oscillator, consult the manufacturer of
the oscillator used when designing a circuit.

Figure 4 Clock Driver Circuits

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¡ Semiconductor MSM80C85AHRS/GS/JS

BASIC SYSTEM TIMING

The MSM80C85AH has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8-bits
of address on the Data Bus. Figure 5 shows an instruction fetch, memory read and I/O write cycle
(as would occur during processing of the OUT instruction). Note that during the I/O write and read
cycle that the I/O port address is copied on both the upper and lower half of the address.

There are seven possible types of machine cycles. Which of these seven takes place is defined by the
status of the three status lines (IO/M, S1, S0) and the three control signals (RD, WR,and INTA). (See
Table 2.) The status line can be used as advanced controls (for device selection, for example), since
they become active at the T1 state, at the outset of each machine cycle. Control lines RD and WR
become active later, at the time when the transfer of data is to take place, so are used as command
lines.

A machine cycle normally consists of three T states, with the exception of OPCODE FETCH, which
normally has either four or six T states (unless WAIT or HOLD states are forced by the receipt of
READY or HOLD inputs). Any T state must be one of ten possible states, shown in Table 3.

Table 2 MSM80C85AH Machine Cycle Chart

Status Control
Machine Cycle
IO/M S1 S0 RD WR INTA
Opcode Fetch (OF) 0 1 1 0 1 1
Memory Read (MR) O 1 O O 1 1
Memory Write (MW) O 0 1 1 0 1
I/O Read (IOR) 1 1 O O 1 1
I/O Write (IOW) 1 0 1 1 0 1
Acknowledge of INTR (INA) 1 1 1 1 1 0 5
Bus Idle (BI): DAD 0 1 0 1 1 1
ACK. OF
RST, TRAP 1 1 1 1 1 1
HALT TS 0 0 TS TS 1

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Table 3 MSM80C85AH Machine State Chart

Status & Buses Control

Machine State
S1, S0 IO/M A8 – A15 AD0 – AD7 RD, WR INTA ALE
T1 ¥ ¥ ¥ ¥ 1 1 1 (1)
T2 ¥ ¥ ¥ ¥ ¥ ¥ 0
TWAIT ¥ ¥ ¥ ¥ ¥ ¥ 0
T3 ¥ ¥ ¥ ¥ ¥ ¥ 0
T4 1 0 (2) ¥ TS 1 1 0
T5 1 0 (2) ¥ TS 1 1 0
T6 1 0 (2) ¥ TS 1 0
1
TRESET ¥ TS TS TS TS 1 0
THALT 0 TS TS TS TS 1 0
THOLD ¥ TS TS TS TS 1 0
0 = Logic "0"
1 = Logic "1"
TS = High Impedance
¥ = Unspecified
Notes: (1) ALE not generated during 2nd and 3rd machine cycles of DAD instruction.
(2) IO/M = 1 during T4 - T6 of INA machine cycle.

M1 M2 M3
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3 T
CLK
5
A8-15 PCH (High Order Address) (PC+1)H IO Port

AD0-7 PCL (PC+1)L1 IO Port

(Low Order Data from Memory Data from Memory Data to Memory
Address) (Instruction) (I/O Port Address) or Peripheral
ALE

RD

WR

IO/M

STATUS S1S0(Fetch) 10 (Read) 01 Write 11

Figure 5 MSM80C85AH Basic System Timing

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¡ Semiconductor MSM80C85AHRS/GS/JS

POWER DOWN Mode

The MSM80C85AH is compatible with the MSM80C85A in function and POWER DOWN mode.
This reduces power consumption further.
There are two methods available for starting this POWER DOWN mode. One is through software
control by using the HALT command and the other is under hardware control by using the pin
HOLD. This mode is released by the HOLD, RESET, and interrupt pins (TRAP, RST7.5, RST6.5
RST5.5, or INTR). (See Table 4.)

Since the sequence of HALT, HOLD, RESET, and INTERRUPT is compatible with MSM80C85A,
every the POWER DOWN mode can be used with no special attention.

Table 4 POWER DOWN Mode Releasing Method

Start by means of Halt command Released by using pins RESET and INTERRUPT (not by pin HOLD)
Start by means of HOLD pin Released by using RESET and HOLD pins (not by interrupt pins)

(1) Start by means of HALT command (See Figures 6 and 7.)

The POWER DOWN mode can be started by executing the HALT command.
At this time, the system is put into the HOLD status and therefore the POWER DOWN mode cannot
be released even when the HOLD is released later.
In this case, the POWER DOWN mode can be released by means of the RESET or interrupt.

(2) Start by means of HOLD pin (See Figure 8.)

During the execution of commands other than the HALT, the POWER DOWN mode is started when
the system is put into HOLD status by means of the HOLD pin.
Since no interrupt works during the execution of the HOLD, the POWER DOWN mode cannot be 5
released by means of interrupt pins. In this case, the POWER DOWN mode can be released either
by means of the RESET pin or by releasing the HOLD status by means of HOLD pin.

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 MSM80C85AHRS/GS/JS ¡ Semiconductor

M1 M2 M1
T1 T2 T3 T4 T1 THLT TRESET T1 T2

CLK (OUT)

ALE

AD0-7 Address 76H Address Address

CPU MODE Run Power Down Run

RESET IN

Figure 6 Started by HALT and Released by RESET IN

M1 M2 M1
T1 T2 T3 T4 T1 THLT T1 T2

CLK (OUT)

ALE

RST5.5

CPU MODE Run Power Down Run

5
Figure 7 Started by HALT and Released by RST5.5

M1 M1
T1 T2 T3 T4 THOLD T1 T2

CLK (OUT)

ALE

HOLD

HLDA

CPU MODE Run Power Down RUN

Figure 8 Started and Released by HOLD

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¡ Semiconductor MSM80C85AHRS/GS/JS

ABSOLUTE MAXIMUM RATINGS

Limits
Parameter Symbol Condition Units
MSM80C85AHRS MSM80C85AHGS MSM80C85AHJS

Power Supply Voltage VCC –0.5 - 7 V

With respect
Input Voltage VIN –0.5 - VCC +0.5 V
to GND
Output Voltage VOUT –0.5 - VCC +0.5 V
Storage Temperature TSTG — –55 - +150 °C
Power Dissipation PD Ta = 25°C 1.0 0.7 1.0 W

OPERATING RANGE

Parameter Symbol Limits Unit

Power Supply Voltage VCC 3-6 V
Operating Temperature TOP –40 - +85 °C

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min. Typ. Max. Unit

Power Supply Voltage VCC 4.5 5 5.5 V
Operating Temperature TOP –40 +25 +85 °C
"L" Input Voltage VIL –0.3 — +0.8 V
"H" Output Voltage VIH 2.2 — VCC +0.3 V
RESET IN
"L" VILR –0.3 — +0.8 V
Input Voltage 5
RESET IN
"H" VIHR 3.0 — VCC +0.3 V
Input Voltage

DC CHARACTERISTICS

Parameter Symbol Conditions Min. Typ. Max. Unit

"L" Output Voltage VOL IOL = 2.5 mA — — 0.4 V
IOH = –2.5 mA 3.0 — — V
"H" Output Voltage VOH
IOH = –100 mA VCC - 0.4 — — V
Input Leak Current ILI 0 £ VIN £ VCC VCC = 4.5 V - 5.5 V –10 — 10 mA
Output Leak Current ILO 0 £ VOUT £ VCC Ta = –40°C - +85°C –10 — 10 mA
Tcyc = 200 ns — 10 20 mA
CL = 0 pF at reset
Operating Supply ICC
Current Tcyc = 200 ns — 5 10 mA
CL = 0 pF at power
down mode

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 MSM80C85AHRS/GS/JS ¡ Semiconductor

AC CHARACTERISTICS
(Ta = –40°C ~ 85°C, VCC = 4.5 V ~ 5.5 V)
Parameter Symbol Condition Min. Max. Unit
CLY Cycle Period tCYC 200 2000 ns
CLY Low Time t1 40 — ns
CLY High Time t2 70 — ns
CLY Rise and Fall Time tr, tf — 30 ns
X1 Rising to CLK Rising tXKR 25 120 ns
X1 Rising to CKK Falling tXKF 30 150 ns
A8~15 Valid to Leading Edge of Control (1) tAC 115 — ns
AD0~7 Valid to Leading Edge of Control tACL 115 — ns
AD0~15 Valid Data in tAD — 350 ns
Address Float After Leading Edge of RD INTA tAFR — 0 ns
A8~15 Valid Before Trailing Edge of ALE (1) tAL 50 — ns
AD0~7 Valid Before Trailing Edge of ALE tALL 50 — ns
READY Valid from Address Valid tARY — 100 ns
Address (A8~15) Valid After Control tCA 60 — ns
Width of Control Law (RD, WR, INTA) tCC 230 — ns
Trailing Edge of Control to Leading Edges of ALE tCL 25 — ns
Data Valid to Trailing Edge of WR tDW 230 — ns
HLDA to Bus Enable tHABE — 150 ns
Bus Float After HLDA tHABF tCYC=200 ns — 150 ns
HLDA Valid to Trailing Edge of CLK tHACK CL=150 pF 40 — ns
HOLD Hold Time tHDH 0 — ns
HOLD Step Up Time to Trailing Edge of CLK tHDS 120 — ns
INTR Hold Time tINH 0 — ns
5 INTR, RST and TRAP Setup Time to Falling Edge of CLK tINS 150 — ns
Address Hold Time After ALE tLA 50 — ns
Trailing Edge of ALE to Leading Edge of Control tLC 60 — ns
ALE Low During CLK High tLCK 50 — ns
ALE to Valid Data During Read tLDR — 270 ns
ALE to Valid Data During Write tLDW — 140 ns
ALE Width tLL 80 — ns
ALE to READY Stable tLRY — 30 ns
Trailing Edge of RD to Re-enabling of Address tRAE 90 — ns
RD (or INTA) to Valid Data tRD — 150 ns
Control Trailing Edge to Leading Edge of Next Control tRV 220 — ns
Data Hold Time After RD INTA (7) tRDH 0 — ns
READY Hold Time tRYH 0 — ns
READY Setup Time to Leading Edge of CLK tRYS 100 — ns
Data Valid After Trailing Edge of WR tWD 60 — ns
LEADING Edge of WR to Data Vaild tWDL — 20 ns

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¡ Semiconductor MSM80C85AHRS/GS/JS

Notes: (1) A8 - A15 address Specs apply to IO/M, S0 and S1.

(2) Test condition: tCYC=200 ns CL=150 pF
(3) For all output timing where CL=150 pF use the following correction factors:
25 pF £ CL < 150 pF : –0.10ns/pF
150 pF < CL £ 200 pF : +0.30ns/pF
(4) Output timings are measured with purely capacitive load.
(5) All timings are measured to output voltage VL=0.8 V, VH=2.2 V, and 1.5 V with
10 ns rise and fall time on inputs.
(6) To calculate timing specifications at other values of tCYC use Table 7.
(7) Data hold time is guaranteed under all loading conditions.
Input Waveform for A.C. Tests:

2.4
2.2 2.2
Test Points
0.8 0.8
0.45

Table 7 Bus Timing Specification as a TCYC Dependent

(Ta = -40°C - +85°C, VCC = 4.5 V - 5.5 V, CL = 150 pF)
MSM80C85AH
tAL — (1/2)T - 50 Min
tLA — (1/2)T - 50 Min
tLL — (1/2)T - 20 Min
tLCK — (1/2)T - 50 Min
tLC — (1/2)T - 40 Min
tAD — (5/2+N)T - 150 Max 5
tRD — (3/2+N)T - 150 Max
tRAE — (1/2)T - 10 Min
tCA — (1/2)T - 40 Min
tDW — (3/2+N)T -70 Min
tWD — (1/2)T - 40 Min
tCC — (3/2+N)T - 70 Min
tCL — (1/2)T - 75 Min
tARY — (3/2)T - 200 Max
tHACK — (1/2)T - 60 Min
tHABF — (1/2)T + 50 Max
tHABE — (1/2)T + 50 Max
tAC — (2/2)T - 85 Min
t1 — (1/2)T - 60 Min
t2 — (1/2)T - 30 Min
tRV — (3/2)T - 80 Min
tLDR — (2+N)T -130 Max

Note: N is equal to the total WAIT states.

T = tCYC

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 MSM80C85AHRS/GS/JS ¡ Semiconductor

X1 INPUT

tr t2 tf
CLK
OUTPUT
tXKR t1
tXKF tCYC

Figure 6 Clock Timing Waveform

READ OPERATION

T1 T2 T3 T1

CLK
tLCK tCA
A8-A15 Address
tAD tRAE
tRDH
AD0-AD7 Address Data In
tLL tLA
tAFR tCL
ALE tLDR
tAL tRD
tCC
RD / INTA tLC
tAC

5
WRITE OPERATION

T1 T2 T3 T1

CLK
tLCK

A8-A15 Address
tLDW tCA
AD0-AD7 Address Data Out
tLL tLA tDW tWD
tWDL
ALE
tAL
WR tLC tCC
tCL
tAC

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¡ Semiconductor MSM80C85AHRS/GS/JS

Read operation with Wait Cycle (Typical)–

same READY timing applies to WRITE operation

T1 T2 TWAIT T3 T1

CLK
tLCK tCA
A8~A15 Address
tAD tRAE
tRDH
AD0~AD7 Address Data In
tLL tLA
tAFR tCL
ALE tLDR
tAL tRD
tCC
RD / INTA tCL
tAC
tARY tRYS tRYH

READY
tLRY

Note: READY must remain stable during setup and hold times.

Figure 7 MSM80C85AH Bus Timing, With and Without Wait

HOLD OPERATION

T2 T3 THOLD THOLD T1

CLK
5
HOLD
tHDS tHACK
tHDH
HLDA
tHABF
tHABE
BUS (Address, Controls)

Figure 8 MSM80C85AH Hold Timing

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 MSM80C85AHRS/GS/JS ¡ Semiconductor

T1 T2 T4 T5 T6 THOLD T1 T2

A8-15

AD0-7 Call Inst

(1)
Bus Floating
ALE

RD

INTA
tHABE
INTR
tINS tINH
HOLD
tHDS tHDH
HLDA
tHACK tHABF

NOTE: (1) IO/M is also floating during this time.

Figure 9 MSM80C85AH Interrupt and Hold Timing

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¡ Semiconductor MSM80C85AHRS/GS/JS

Table 8 Instruction Set Summary

Instruction Code (1) Clock (2)
Mnemonic Description
D7 D6 D5 D4 D3 D2 D1 D0 Cycles
MOVE, LOAD, AND STORE
MOVr1 r2 Move register to register 0 1 D D D S S S 4
MOV M r Move register to memory 0 1 1 1 0 S S S 7
MOV r M Move memory to register 0 1 D D D 1 1 0 7
MVI r Move immediate register 0 0 D D D 1 1 0 7
MVI M Move immediate memory 0 0 1 1 0 1 1 0 10
LXI B Load immediate register Pair B & C 0 0 0 0 0 0 0 1 10
LXI D Load immediate register Pair D & E 0 0 0 1 0 0 0 1 10
LXI H Load immediate register Pair H & L 0 0 1 0 0 0 0 1 10
LXI SP Load immediate stack pointer 0 0 1 1 0 0 0 1 10
STAX B Store A indirect 0 0 0 0 0 0 1 0 7
STAX D Store A indirect 0 0 0 1 0 0 1 0 7
LDAX B Load A indirect 0 0 0 0 1 0 1 0 7
LDAX D Load A indirect 0 0 0 1 1 0 1 0 7
STA Store A direct 0 0 1 1 0 0 1 0 13
LDA Load A direct 0 0 1 1 1 0 1 0 13
SHLD Store H & L direct 0 0 1 0 0 0 1 0 16
LHLD Load H & L direct 0 0 1 0 1 0 1 0 16
XCHG Exchange D & E H & L registers 1 1 1 0 1 0 1 1 4
STACK OPS
PUSH B Push register Pair B & C on stack 1 1 0 0 0 1 0 1 12
PUSH D Push register Pair D & E on stack 1 1 0 1 0 1 0 1 12
PUSH H Push register Pair H & L on stack 1 1 1 0 0 1 0 1 12
PUSH PSW Push A and Flags on stack 1 1 1 1 0 1 0 1 12
POP B Pop register Pair B & C off stack 1 1 0 0 0 0 0 1 10
POP D Pop register Pair D & E off stack 1 1 0 1 0 0 0 1 10
POP H Pop register Pair H & L off stack 1 1 1 0 0 0 0 1 10
POP PSW Pop A and Flags off stack 1 1 1 1 0 0 0 1 10
XTHL Exchange top of stack H & L 1 1 1 0 0 0 1 1 16
SPHL H & L to stack pointer 1 1 1 1 1 0 0 1 6
JUMP
JMP Jump unconditional 1 1 0 0 0 0 1 1 10 5
JC Jump on carry 1 1 0 1 1 0 1 0 7/10
JNC Jump on no carry 1 1 0 1 0 0 1 0 7/10
JZ Jump on zero 1 1 0 0 1 0 1 0 7/10
JNZ Jump on no zero 1 1 0 0 0 0 1 0 7/10
JP Jump on positive 1 1 1 1 0 0 1 0 7/10
JM Jump on minus 1 1 1 1 1 0 1 0 7/10
JPE Jump on parity even 1 1 1 0 1 0 1 0 7/10
JPO Jump on parity odd 1 1 1 0 0 0 1 0 7/10
PCHL H & L to program counter 1 1 1 0 1 0 0 1 6
CALL
CALL Call unconditional 1 1 0 0 1 1 0 1 18
CC Call on carry 1 1 0 1 1 1 0 0 9/18
CNC Call on no carry 1 1 0 1 0 1 0 0 9/18
CZ Call on zero 1 1 0 0 1 1 0 0 9/18
CNZ Call on no zero 1 1 0 0 0 1 0 0 9/18
CP Call on positive 1 1 1 1 0 1 0 0 9/18
CM Call on minus 1 1 1 1 1 1 0 0 9/18
CPE Call on parity even 1 1 1 0 1 1 0 0 9/18
CPO Call on parity odd 1 1 1 0 0 1 0 0 9/18

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 MSM80C85AHRS/GS/JS ¡ Semiconductor

Table 8 Instruction Set Summary cont'd

Instruction Code (1) Clock (2)
Mnemonic Description
D7 D6 D5 D4 D3 D2 D1 D0 Cycles
RETURN
RET Return 1 1 0 0 1 0 0 1 10
RC Return on carry 1 1 0 1 1 0 0 0 6/12
RNC Return on no carry 1 1 0 1 0 0 0 0 6/12
RZ Return on zero 1 1 0 0 1 0 0 0 6/12
RNZ Return on no zero 1 1 0 0 0 0 0 0 6/12
RP Return on positive 1 1 1 1 0 0 0 0 6/12
RM Return on minus 1 1 1 1 1 0 0 0 6/12
RPE Return on parity even 1 1 1 0 1 0 0 0 6/12
RPO Return on parity odd 1 1 1 0 0 0 0 0 6/12
RESTART
RST Restart 1 1 A A A 1 1 1 12
INPUT/OUTPUT
IN Input 1 1 0 1 1 0 1 1 10
OUT Output 1 1 0 1 0 0 1 1 10
INCREMENT AND DECREMENT
INR r Increment register 0 0 D D D 1 0 0 4
DCR r Decrement register 0 0 D D D 1 0 1 4
INR M Increment memory 0 0 1 1 0 1 0 0 10
DCR M Decrement memory 0 0 1 1 0 1 0 1 10
INX B Increment B & C registers 0 0 0 0 0 0 1 1 6
INX D Increment D & E registers 0 0 0 1 0 0 1 1 6
INX H Increment H & L registers 0 0 1 0 0 0 1 1 6
INX SP Increment stack pointer 0 0 1 1 0 0 1 1 6
DCX B Decrement B & C 0 0 0 0 1 0 1 1 6
DCX D Decrement D & E 0 0 0 1 1 0 1 1 6
DCX H Decrement H & L 0 0 1 0 1 0 1 1 6
DCX SP Decrement stack pointer 0 0 1 1 1 0 1 1 6
ADD
ADD r Add register to A 1 0 0 0 0 S S S 4
5 ADC r
ADD M
Add register to A with carry
Add memory to A
1
1
0
0
0
0
0
0
1
0
S
1
S
1
S
0
4
7
ADC M Add memory to A with carry 1 0 0 0 1 1 1 0 7
ADI Add immediate to A 1 1 0 0 0 1 1 0 7
ACI Add immediate to A with carry 1 1 0 0 1 1 1 0 7
DAD B Add B & C to H & L 0 0 0 0 1 0 0 1 10
DAD D Add D & E to H & L 0 0 0 1 1 0 0 1 10
DAD H Add H & L to H & L 0 0 1 0 1 0 0 1 10
DAD SP Add stack pointer to H & L 0 0 1 1 1 0 0 1 10
SUBTRACT
SUB r Subtract register from A 1 0 0 1 0 S S S 4
SBB r Subtract register from A with borrow 1 0 0 1 1 S S S 4
SUB M Subtract memory from A 1 0 0 1 0 1 1 0 7
SBB M Subtract memory from A with borrow 1 0 0 1 1 1 1 0 7
SUI Subtract immediate from A 1 1 0 1 0 1 1 0 7
SBI Subtract immediate from A with borrow 1 1 0 1 1 1 1 0 7

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¡ Semiconductor MSM80C85AHRS/GS/JS

Table 8 Instruction Set Summary cont'd

Instruction Code (1) Clock (2)
Mnemonic Description
D7 D6 D5 D4 D3 D2 D1 D0 Cycles
LOGICAL
ANA r Add register with A 1 0 1 0 0 S S S 4
XRA r Exclusive Or register with A 1 0 1 0 1 S S S 4
ORA r Or register with A 1 0 1 1 0 S S S 4
CMP r Compare register with A 1 0 1 1 1 S S S 4
ANA M And memory with A 1 0 1 0 0 1 1 0 7
XRA M Exclusive Or Memory with A 1 0 1 0 1 1 1 0 7
ORA M Or memory with A 1 0 1 1 0 1 1 0 7
CMP M Compare memory with A 1 0 1 1 1 1 1 0 7
ANI And immediate with A 1 1 1 0 0 1 1 0 7
XRI Exclusive Or immediate with A 1 1 1 0 1 1 1 0 7
ORI Or immediate with A 1 1 1 1 0 1 1 0 7
CPI Compare immediate with A 1 1 1 1 1 1 1 0 7
ROTATE
RLC Rotate A left 0 0 0 0 0 1 1 1 4
RRC Rotate A right 0 0 0 0 1 1 1 1 4
RAL Rotate A left through carry 0 0 0 1 0 1 1 1 4
RAR Rotate A right through carry 0 0 0 1 1 1 1 1 4
SPECIALS
CMA Complement A 0 0 1 0 1 1 1 1 4
STC Set carry 0 0 1 1 0 1 1 1 4
CMC Complement carry 0 0 1 1 1 1 1 1 4
DAA Decimal adjust A 0 0 1 0 0 1 1 1 4
CONTROL
EI Enable Interrupts 1 1 1 1 1 0 1 1 4
DI Disable Interrupts 1 1 1 1 0 0 1 1 4
NOP No-operation 0 0 0 0 0 0 0 0 4
HLT Halt (Power down) 0 1 1 1 0 1 1 0 5
RIM Read Interrupt Mask 0 0 1 0 0 0 0 0 4
SIM Set Interrupt Mask 0 0 1 1 0 0 0 0 4
5
Notes: (1) DDD or SSS. B 000. C 001. D 010. E 011. H 100. L 101. Memory 110. A 111.
(2) Two possible cycle times, (6/12) indicate instruction cycles dependent on
condition flags.

Precautions for operation

(1) When the oscillation circuit is to be used, keep the RES input low until the oscillation is
sufficiently stabilized after power is turned on.
(2) When power is turned on, the output level (SOD etc.) is unknown before the equipment is
reset.
(3) Bug of MSM80C85A–2 at power down has fixed.
(4) Because Spike Noise would be output on HLDA, RESET OUT and CLK pins, depending on
the customers condition of usage; please take into account this issue at System Board design.

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 MSM80C85AHRS/GS/JS ¡ Semiconductor

SUPPLEMENTARY EXPLANATION

(1) SIM instruction: The execution of the SIM instruction uses the contents of the accumulator to
mask MSM80C85AH’S interrupts.

Accumulator Setting Value

Bit 7 6 5 4 3 2 1 0
— — — R7.5 MSE M7.5 M6.5 M5.5

R7.5 (Reset interrupt 7.5 Flip-flop): When this bit is set to 1, the edge detecting flip-flop of RST
7.5 interrupt is reset.
MSE (Mask Set Enable): When this bit is set to 1, the interrupt mask bits are valid.
M7.5 (Mask RST7.5): When this bit is set to 1 and MSE bit is set to 1, RST7.5 interrupt is masked.
M6.5 (Mask RST6.5): When this bit is set to 1 and MSE bit is set to 1, RST6.5 interrupt is masked.
M5.5 (Mask RST5.5): When this bit is set to 1 and MSE bit is set to 1, RST 5.5 interrupt is masked.

(2) RIM instruction: When the contents of the accumulator are read out after RIM instruction has
been executed, MSM80C85AH interrupt status can be known.

Accumulator Reading Value

Bit 7 6 5 4 3 2 1 0
— 17.5 16.5 15.5 IE M7.5 M6.5 M5.5

17.5 (Pending RST7.5): When RST7.5 interrupt is pending, "1" is read out.
16.5 (Pending RST6.5): When RST6.5 interrupt is pending, "1" is read out.
5 15.5 (Pending RST5.5): When RST5.5 interrupt is pending, "1" is read out.
IE (Interrupt Enable Flag): When interrupt is Enable, "1" is read out.
M7.5 (Mask RST7.5): When RST7.5 interrupt is masked, "1" is read out.
M6.5 (Mask RST6.5): When RST6.5 interrupt is masked, "1" is read out.
M5.5 (Mask RST5.5): When RST5.5 interrupt is masked ,"1" is read out.

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