Mni Ision: Ov7950/Ov7451 Cmos Analog NTSC C C With Omnipixel Technology

Omni ision
Advanced Information
® Preliminary Datasheet
OV7950/OV7451 CMOS Analog NTSC CAMERACHIPTM with OmniPixel® Technology
General Description Applications

• Security/Surveillance cameras
The OV7950 (color) and OV7451 (black & white) single
• Video Conferencing
chip CMOS CAMERACHIPSTM are designed to provide a
high level of functionality for all applications requiring a • Video phones
small footprint, low voltage, low power consumption and • Video e-mail
high performance color or B&W video camera. • Toys
• Finger print equipment
Both devices support NTSC composite video output and • Medical and dental equipment
can directly interface with a VCR TV monitor or other
device with 75 ohm loading.
Key Specifications
Note: The OV7950/OV7451 is available Array Size 656 x 492
Pb in a lead-free package.
Power Supply
Analog/ADC/IO 3.3 VDC + 5%
Digital Core 1.8 VDC + 5%
Power Consumption 200 mW
Features Image Area 4.080 mm x 3.102 mm
• Single chip 1/4" format video camera OV7950 1/60s - 20 µs
Exposure
• Composite video (NTSC) output Time Range OV7451 1/30s - 20 µs
• High sensitivity Optical Format 1/4"
• Automatic exposure/gain with 16 zone control S/N Ratio 48 dB
• Horizontal and vertical windowing capability Dynamic Range 49 dB
• Auto white balance control Pixel Size 6.0 µm x 6.0 µm
• Aperture/Gamma correction Dark Current 10 mW/s @ 60°C
• 50/60 Hz flicker cancellation Fixed Pattern Noise 0.22% of VPEAK-TO-PEAK
• External frame sync capability (Genlock) Package Dimensions 14.22 mm x 14.22 mm
• SPI/EEPROM used to control overlay and set other Figure 1 OV7950/OV7451 Pin Diagram (Top View)
customer variables
DOGND
HSYNC
XCLK2
XCLK1
• Two sets of dynamic overlay controls
OGND
OVDD
DVDD
CVO
NC
NC
NC
NC
• Master/slave compatible Serial Camera Control Bus 30 29 28 27 26 25 24 23 22 21 20 19
(SCCB) control interface for register programming RES 31 18 VS
• Low power consumption DOVDD 32 17 ADGND
• Extreme low dark current for high temperature PCLK 33 16 ADVDD
applications NC 34 15 SCK
• Defective pixel correction NC 35 14 ESO
NC 36 13 CS
OV7950/OV7451
Ordering Information NC 37 12 ESI
NC 38 11 FSIN
Product Package NC 39 10 RESET
NC 40 9 OVL2
OV07950-C10A (Color, NTSC) CLCC-48 NC 41 8 OVLEn
NC 42 7 PWDN
OV07451-C10A (B&W with microlens, NTSC) CLCC-48
43 44 45 46 47 48 1 2 3 4 5 6
MASTEN
MSDA
MSCL
SIO_D
SIO_C
SGND
SVDD
VREFH
VREFS
DEVDD
NVREF
VRLOW
Version 2.5, February 28, 2006 Proprietary to OmniVision Technologies 1

OV7950/OV7451 CMOS Analog NTSC (OmniPixel®) CAMERACHIP™ Omni ision
Functional Description
This section describes the various functions of the OV7950/OV7451. Refer to Figure 2 for the functional block diagram of the
OV7950/OV7451.
Figure 2 Functional Block Diagram
DAC
Video
AMP ADC DSP Overlay +CVO
Encoder
Column Sample/Hold
CS
Gain DSP Overlay
Row Image Array
Control Control Control
Select (656 x 492) SCK
SPI
Interface
ESO
ESI
CS0*
Timing/Clock Generator Register SCCB

Bank Interface
CS1*
SIO_C
SIO_D
XCLK1
XCLK2
PWDN
RESET
FSIN
OVL2
OVLEn
VS
Video Standards Image Sensor Functions
NTSC TV standards are implemented and available as

output in the OV7950/OV7451 CAMERACHIPS. Note that White Balance
the accuracy and stability of the crystal clock frequency is
important to avoid unwanted color shift in the TV video The function of white balance in the OV7950/OV7451
system. OmniVision recommends using a 12.27 MHz CAMERACHIP is to adjust and calibrate the image device
crystal when utilizing the OV7950/OV7451 CAMERACHIP. sensitivity on the primary (RGB) colors to match the color
cast of the light source. The Auto White Balance (AWB)
can be enabled or disabled by register control. If the AWB
Video Format is enabled, the image sensors continuously perform white
balancing.
The OV7950/OV7451 CAMERACHIP supports Composite
(CVBS) video format only. Composite signals are
generated from the built-in TV encoder. The OV7451 only Mirror and Vertical Flip
outputs the luminance signal.
The OV7950/OV7451 provides horizontal mirror and
vertical flip functions. These functions can be turned ON
or OFF via register settings.
2 Proprietary to OmniVision Technologies Version 2.5, February 28, 2006

Omni ision Functional Description
Multi-Chip Synchronize The receiver must pull down SIO_D during the
acknowledgement bit time. During the write cycle, the
The OV7950/OV7451 CAMERACHIP provides the OV7950/OV7451 device returns the acknowledgement
multi-chip Synchronize function where one chip works as and, during the read cycle, the master returns the
the master and all others as slave devices. The master acknowledgement, indicating to the slave that the read
chip provides the frame synchronize signal through pin VS cycle can be terminated. Note that the restart feature is
(pin 18). All slave devices then accept the frame not supported here.
synchronize signal through pin FSIN. This mode allows all
devices to synchronize together. Within each byte, the MSB is transferred first. The
read/write control bit is the LSB of the first byte. Standard
SCCB communications require only two pins, SIO_C and
Chip Configuration SIO_D. SIO_D is configured as an open drain for
bidirectional purposes. A HIGH to LOW transition on the
The OV7950/OV7451 CAMERACHIP has been designed SIO_D while SIO_C is HIGH indicates a START condition.
for ease-of-use in many stand-alone applications. Some A LOW to HIGH transition on the SIO_D while SIO_C is
functions like serial interface slave address and NTSC HIGH indicates a STOP condition. Only a master can
selection can be set by connecting appropriate pins high generate START/STOP conditions.
(logic "1") or low (logic "0") through a 10 KΩ resistor. The
OV7950/OV7451 CAMERACHIP also has a serial master Except for these two special conditions, the protocol that
and slave interface for programmable access to all SIO_D remain stable during the HIGH period of the clock,
register functions. SIO_C. Each bit is allowed to change state only when
SIO_C is LOW (see Figure 3 and Figure 4).
The OV7950/OV7451 SCCB interface supports multi-byte

Additional Picture Controls write and multi-byte read. The master must supply the
sub-address in the write cycle, but not in the read cycle.
The OV7950/OV7451 CAMERACHIP provides additional Therefore, the OV7950/OV7451 takes the read
picture control functions to enhance image quality and sub-address from the previous write cycle. In multi-byte
chip performance. These functions are listed as follows: write or multi-byte read cycles, the sub-address
• AGC gain range control automatically increments after the first data byte so that
• Gamma correction continuous locations can be accessed in one bus cycle. A
multi-byte cycle overwrites its original sub-address;
• Brightness
therefore, if a read cycle immediately follows a multi-byte
• Contrast cycle, a single byte write cycle that provides a new
• Full color bar test pattern address must be inserted.
The OV7950/OV7451 supports a single slave ID. The ID

Serial Camera Control Bus (SCCB) is preset to 60 for write and 61 for read.
Many of the functions and configuration registers in the In the write cycle, the second byte in the SCCB is the
OV7950/OV7451 image sensors are available through the sub-address for selecting the individual on-chip registers,
SCCB interface. The OV7950/OV7451 image sensor and the third byte is the data associated with this register.
operates as a slave device that supports up to 400 kbps Writing to the unimplemented sub-address is ignored.
serial transfer rate using a 7-bit address/data transfer
protocol. In the read cycle, the second byte is the data associated
with the previously stored sub-address. Reading of an
unimplemented sub-address returns unknown.
SCCB Protocol Format
Figure 3 Bit Transfer on the SCCB
In SCCB operation (see Figure 5), the master must
perform the following operations:
• Generate the Start/Stop condition SIO_D
• Provide the serial clock on SIO_C DATA DATA

• Place the 7-bit slave address (RW bit) and the 8-bit STABLE CHANGE
ALLOWED
sub-address on SIO_D
SIO_C

SCCB Master Address Value
Connect external SCCB slave-compatible storage device 0x00 Sub_add1 - first configuration register address
through the OV7950/OV7451 SCCB master interface so 0x01 Add1_value - first configuration register value
the OV7950/OV7451 can self load the configuration data
0x02 Sub_add2 - second configuration register address
from it. Data stored in the external storage device should
be arranged as follows: 0x03 Add2_value - second configuration register value
. .
. .
. .
When the sub_add = [FF] and add_value = [FF}, the

SCCB master will stop operation.
Figure 4 Data Transfer on the SCCB
SIO_D SLAVE ID RW SUB-ADDRESS DATA
A A A
SIO_C
S P
Figure 5 SCCB Protocol Format
FIRST BYTE SECOND BYTE THIRD BYTE
S SLAVE (7-BIT) RW A SUB-ADDRESS (8-BIT) A DATA (8-BIT) A P
MSB LSB=0 ACK ACK

START STOP
MASTER TRANSMIT, SLAVE RECEIVE (WRITE CYCLE)
FIRST BYTE SECOND BYTE
S SLAVE (7-BIT) RW A SUB-ADDRESS (8-BIT) A P
MSB LSB=0 ACK

START STOP
MASTER TRANSMIT, SLAVE RECEIVE (DUMMY WRITE CYCLE)
FIRST BYTE SECOND BYTE THIRD BYTE
S SLAVE (7-BIT) RW A DATA (8-BIT) A DATA (8-BIT) 1 P
MSB LSB=1 ACK STOP

START NO ACK IN
LAST BYTE
MASTER RECEIVE, SLAVE RECEIVE (READ CYCLE)
SLAVE ID – 1000000X S – START CONDITION – SLAVE TRANSMIT

X – RW BIT, 1: READ, 0: WRITE A – ACKNOWLEDGE BIT – MASTER TRANSMIT
P – STOP CONDITION – MASTER INITIATE

Omni ision Functional Description
Overlay Control Data formats are defined as follows:
The OV7950/OV7451 CAMERACHIP has an overlay Address Description

capability where the user can store an overlay bit map
Bit[7]: ON/OFF high bit
image in an external storage device with an SPI interface. 0x10
Bit[6]: ON/OFF low bit
At power up, OV7950/OV7451 will start the SPI interface Bit[7:6]: Opacity1[1:0]
when the OVLEn pin (pin 8) is set high. [Bit7, Bit0] ≠ "10" 0x11 Bit[5:4]: Resolution1[1:0]
in the first address indicates that there is no SPI slave Bit[3]: YUV1 all replaced
device attached, causing the SPI interface to stop. 0x12 Bit[7:0]: Y1
Otherwise, the OV7950/OV7451 will check bit 6 of first
0x13 Bit[7:0]: U1
byte for overwrite control. The user can define up to 15
bytes in the control register to overwrite the internal 0x14 Bit[7:0]: V1
default value (further details defining this register is not 0x15 Bit[7:0]: V1 start[9:2]
available at this time). These 15 bytes only read one time
after power up. 0x16 Bit[7:0]: V1 end[9:2]
0x17 Bit[7:0]: H1 start[9:2]
If the first byte bit[7] is “1” and bit[0] is “0”, 0x18 Bit[7:0]: H1 end[9:2]
OV7950/OV7451 will read the content in address 0x10 to
0x2B for the overlay setting. Bit[7:0]: V1 start[1:0], V1 end[1:0],
0x19
H1 start[1:0], H1 end[1:0]
0x1A Bit[7:0]: MemLine1[7:0] (unit byte)
Figure 6 SPI Overlay Process Sequence
Bit[7:0]: Overlay set 2 start address
0x20
Power-up
low 8-bit
Bit[7:0]: Overlay set 2 start address
0x21
Start SPI high 8-bit
Read content
Bit[7:6]: Opacity2[1:0]
in address
0x00~0x0F
0x22 Bit[5:4]: Resolution2[1:0]
Bit[3]: YUV2 all replaced
Do
addresses
0x00[7] = 1 &
N Stop SPI and 0x23 Bit[7:0]: Y2
0x00[0] = 0 Overlay
?
Y
0x24 Bit[7:0]: U2
Does
0x25 Bit[7:0]: V2
Read content
address
in address
0x00[6] = 1
?
0x10~0x2B 0x26 Bit[7:0]: V2 start[9:2]
Y
0x27 Bit[7:0]: V2 end[9:2]
Overwrite 15 bytes of
internal registers with the
content from addresses
Do
0x28 Bit[7:0]: H2 start[9:2]
addresses I2C Master Start
0x01~0x0F N
0x10[7] = 1 &
0x10[6] = 0
Stop Overlay
0x29 Bit[7:0]: H2 end[9:2]
?
Stop
Y
Bit[7:0]: V2 start[1:0], V2 end[1:0],
Read I2C slave content
one byte for address, 0x2A
one byte for data H2 start[1:0], H2 end[1:0]
0x2B Bit[7:0]: MemLine2[7:0] (unit byte)
Is
N Does
pin OVL2 = 1
Y
N
there no
ACK or does 0x30 ~ 0xXX Bit map 1
? address = FF
& data = FF
Read current line Read current line ? Set2 start address Bit map 2
overlay bit map 1 overlay bit map 2
data data Y ~ 0xXX
Stop I2C
Master
Overlay process Overlay process
Byte[10]
N N
Overlay function can only be enabled when bit[7] = 1 and
Field End? Field End?
bit[6] = 0.
Y Y
Reset address
Reset address to There may be two sets of overlay bitmaps in one EPROM.
the starting address of
to 0x30
overlay bit map 2 Byte [11] ~ Byte [1A] are control bytes for first bitmap.
(refer to addresses
0x21 and 0x20)

Byte [11] Byte [1A]
Resolution = 00 01 10 11 Every time when a new line is started, it is necessary to go

to a new address for memory reading. For example, if the
2x2 3x3 4x4 5x5 user specifies 500 points per line, which is not an exact
multiple of 8, they need at least 63 bytes (63 x 8 = 504) to
When choosing 3x3 or 5x5, be aware that because YUV save the information. So, they can only specify
sampling format is 4:2:2, there may be strong color MemLine[7:0] to be a number equal or larger than [3F].
aliasing around the overlay edges.
For example, If MemLine = [40]
Opacity = 00 01 10 11
Line 1 start address = [30],
25% 50% 75% 100%
reading sequence:
YUV all replaced:
Byte[20]bit7, bit6,…bit0,
Enable: Byte[21]bit7, bit6…bit0,
Byte[22]bit8, bit7……
Y overlay = Y target x q% + Y original x (1-q%) ………..
Byte[5E]bit8, bit7, bit6, bit5, bit4.
U overlay = U target x q% + U original x (1-q%) END
V overlay = V target x q% + V original x (1-q%) Line 2 start address = [70],
Disable: Reading sequence:
Y overlay = Y target x q% + Y original x (1-q%) Byte[60]bit7, bit6,…bit0,

Byte[61]bit7, bit6…bit0,
U overlay = U target Byte[62]bit8, bit7……
………..
V overlay = V target Byte[9E]bit8, bit7, bit6, bit5, bit4.
END
The q% is opacity.
So, in each line, there are 500 bits was read.
Byte [12]~[14]
Byte [20], Byte [21]
Y, U, V specifies overlay color. In BW mode, only Y
needed to be set. These two bytes indicate the 16-bit start address of the
second bitmap.
Byte [15]~[19]
Byte [22] ~ Byte [2B]
The user is allowed to specify vertical and horizontal
dimensions of their overlay bitmap. If the desired figure is These are control bytes for second bitmap (refer to
very small compared to the dimensions of the whole description for Byte [11] ~ Byte [1A]).
screen, they may save a lot of memory.

Omni ision Pin Description
Pin Description
Table 1 Pin Description
Pin Pin Default

Location Name Type (V) Function/Description
01 SVDD Power 3.3 Sensor array power supply
02 VREFH Analog – Internal reference
03 VREFS Analog – Internal reference
04 DEVDD Power 0 Sensor array decoder power supply
05 NVREF Power 0 Internal reference
06 VRLOW Analog – Internal reference
Power Down Mode ON/OFF Selection

07 PWDN Input 0 0: OFF
1: ON
Overlay ON/OFF selection
08 OVLEn Input 0 0: OFF
1: ON
Overlay bitmap file selection
09 OVL2 Input 0 0: Select first bitmap
1: Select second bitmap
Hard reset ON/OFF selection
10 RESET Input 0 0: OFF
1: ON
11 FSIN Input 0 Frame synchronizing signal input
12 ESI Input 0 SPI interface data input
13 CS Output – SPI interface chip select signal
14 ESO I/O 0 SPI interface data output
15 SCK I/O 0 SPI interface clock output
16 ADVDD Power 3.3 ADC power supply
17 ADGND Power 0 ADC ground
18 VS Output 0 Frame synchronizing signal output
19 HSYNC Output 0 Horizontal valid pixel reference signal output
20 XCLK1 Input – Crystal input
21 XCLK2 Output – Crystal output
22 DVDD Power 1.8 Digital core power supply
23 DOGND Power 0 Digital I/O interface ground
24 CVO Analog – Composite video signal output
25 OVDD Power 3.3 DAC power supply

Table 1 Pin Description
Pin Pin Default

Location Name Type (V) Function/Description
26 NC – – No connection
30 OGND Analog – DAC ground
31 RES Analog – Internal reference adjustment pin (connect to ground using a 200Ω resistor)
32 DOVDD Power 3.3 Digital I/O interface power supply
33 PCLK Output – Pixel clock output
43 MASTEN Input – Master interface enable
44 MSDA I/O – Serial master interface data I/O
45 MSCL O – Serial master interface clock output
46 SIO_D I/O – Serial slave interface data I/O
47 SIO_C Input – Serial slave interface clock input
48 SGND Power 0 Sensor array ground

Omni ision Electrical Characteristics
Electrical Characteristics
Table 2 Operating Conditions
Parameter Min Max
Operating temperature -40°C +85°C
Storage temperaturea -40°C +125°C
a. Exceeding the stresses listed may permanently damage the device. This is a stress rating only and functional operation of the sensor at
these and any other condition above those indicated in this specification is not implied. Exposure to absolute maximum rating conditions
for any extended period may affect reliability.
Table 3 DC Characteristics (-20°C < TA < 85°C, Voltages Referenced to GND)
Symbol Parameter Min Typ Max Unit
Supply
VDD1 Supply voltage (SVDD, DOVDD, EVDD) 3.15 3.3 3.45 V
VDD2 Supply voltage (DVDD) 1.70 1.8 1.90 V
IDD Supply current – 60 – mA
Digital Inputs
VIL Input voltage LOW 0.2 x DOVDD V
VIH Input voltage HIGH 0.8 x DOVDD V
CIN Input capacitor 10 pF
Digital Outputs (standard loading 25 pF, 1.2 KΩ to 3V
VOH Output voltage HIGH 2 V
VOL Output voltage LOW 0.6 V
Serial Input
VIL SIO_C and SIO_D -0.5 0 1 V
VIH SIO_C and SIO_D 2.5 3.3 VDOVDD + 0.5 V

Table 4 AC Characteristics (TA = 25°C, VDD = 5V)
Clock Input / Crystal Oscillator
fOSC Resonator frequency (NTSC) – 12.27 – MHz
Load capacitor 33 pF
Parallel resistance 1 MΩ
Rise/fall time for external clock input – 5 – ns
Duty cycle for external clock input 40 50 60 %
CVO Analog Video Output Parameters
VTO_P Video peak signal level 0.969 1.020 1.071 V
VTO_B Video black signal level 0.339 0.357 0.375 V
VVSYNC Video sync pulse amplitude 0.291 0.306 0.321 V
VSYNCLEVEL Sync level 0.017 0.022 0.027 V
IVTO Video output drive current – 30 mA
I/O Pin
ISOURCE Output pin source current (Output = 1.5V) 8 10 12 mA
ISINK Output pin sink current (Output = 3V) 8 10 12 mA
Miscellaneous Timing
tSYNC External FSIN cycle time – 2 – field
tPU Chip power-up time – – 100 μs

Omni ision Timing Specifications
Timing Specifications
NTSC Timing
Figure 7 NTSC Standard Video Timing Diagram
HSYNC HSYNC / 2
HCOUNT / 2 HCOUNT / 2 HCOUNT / 2 HCOUNT / 2
ANALOG
FIELD 1
520 521 522 523 524 525 1 2 3 4 5 6 7 13
START
OF
ANALOG VSYNC
FIELD 2
258 259 260 261 262 263 264 265 266 267 268 269 275 276
Figure 8 NTSC Composite Video Signal

MAGENTA
YELLOW
GREEN
BLACK
WHITE
CYAN
BLUE
RED
1.13 V WHITE LEVEL
100 IRE
3.58 MHZ
COLOR BURST
(9 CYCLES)
0.449 V
20 IRE
0.357 V BLACK LEVEL
7.5 IRE
0.306 V BLANK LEVEL
20 IRE
0.163 V
40 IRE
0.022 V SYNC LEVEL

Overlay Timing
Figure 9 Vertical Timing Diagram
PWUP
VS ... ... ... ...

HSYNC ... ... ... ... ... ... ... ... ... ... ... ...
CS ... ...
SCK ... ... ... ... ... ... ... ...
Read 16 System Control Bytes Read 28 Overlay Control Bytes Part II: Read Overlay Bitmap
FromEPROM [0000] ~ [000F] FromEPROM [0010] ~ [002B] From EPROM [0030] ~ [XXXX]
Available when power up. Only available when EPROM check Available in every field, If overlay
successful. function is ON.
Part I: Read Control Bytes

Only in the first Field, after Chip
Power up
In Pa rt I, SCK freq. is always 1/5 pixel clock freq;
In Pa rt II, SCK freq. can be 1/2, 1/3, 1/4 or 1/5 pixel clock freq.
according to overlay resolution (2x2, 3x3, 4x4 or 5x5).
Figure 10 Horizontal Timing Diagram
HSYNC
Overlay
312 pixels, 156 overlay bits
HREF
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 175 176 177 178 179
SCK ... ... ...
INSTRUCTION: READ BYTE ADDRESS = [0058]

ESO 15 14 13 12 11 10 ... 2 1 0
BYTE [0058] BYTE [0059] BYTE [006B]

ESI HIGH IMPEDANCE HIGH IMPEDANCE
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ... ... 0 7 6 5 4
If overlay resolution is 2x2,

overlay horizontal start = [60]
overlay horizontal end = [198]
MEMLN = [14]
So, overlay HREF includes 312 pixels.
In each line, it need to read 156 bits from overlay bitmap in EPROM.
In overlay line1 or line2, read EPROM BYTE [0030] ~ [0043];
In overlay line3 or line4, read EPROM BYTE [0044] ~ [0057];
Figure 11 shows horizontal timing of overlay line5 or line6.

Interface Timing
Figure 11 SCCB Timing Diagram
tF t HIGH tR
tLOW
SIO_C
t HD:STA t HD:DAT t SU:DAT

tSU:STA tSU:STO
SIO_D
IN
t BUF
tAA t DH
SIO_D
OUT
Table 5 SCCB Timing Specifications
fSIO_C Clock Frequency 400 KHz
tLOW Clock Low Period 1.3 μs
tHIGH Clock High Period 600 ns
tAA SIO_C low to Data Out valid 100 900 ns
tBUF Bus free time before new START 1.3 μs
tHD:STA START condition Hold time 600 ns
tSU:STA START condition Setup time 600 ns
tHD:DAT Data-in Hold time 0 μs
tSU:DAT Data-in Setup time 100 ns
tSU:STO STOP condition Setup time 600 ns
tR, tF SCCB Rise/Fall times 300 ns
tDH Data-out Hold time 50 ns

Figure 12 SPI Timing Diagram
tCS
CS
tCSS tCSH
SCK tWH tWL
tSU tH
ESO
VALID IN
tV tHO tDIS
ESI
HI-Z HI-Z
Table 6 SPI Timing Specifications
tWH SCK High Time 133 ns
tWL SCK Low Time 133 ns
tCS CS High Time 250 ns
tCSS CS Setup Time 250 ns
tCSH CS Hold Time 250 ns
tSU Data In Setup Time 50 ns
tH Data In Hold Time 50 ns
tV Output Valid 133 ns
tHO Output Hold Time 0 ns
tDIS Output Disable Time 250 ns

OV7950 Light Response
Figure 13 OV7950 Light Response
spectrum_7950
5.00E+10
4.50E+10
4.00E+10
3.50E+10
Output(mv/w.s)
3.00E+10 R
2.50E+10 G
2.00E+10 B
1.50E+10
1.00E+10
5.00E+09
0.00E+00
395 495 595 695 795 895 995 1095
w av elength

Register Set
Table 7 provides a list and description of the Device Control registers contained in the OV7950/OV7451. The device slave
addresses are 60 for write and 61 for read.
Table 7 Device Control Register List
Address Register Default

(Hex) Name (Hex) R/W Description
AGC Gain Control

Bit[7:0]: Gain setting
• Range: 1x - 32x
00 GAIN 00 RW Gain = (Bit[7]+1) x (Bit[6]+1) x (Bit[5]+1) x (Bit[4]+1) x (1+Bit[3:0]/16)
Note: This register is updated automatically when AGC is enabled. The
user can adjust the value through the serial interface if AGC is
disabled.
01 BLUE 80 RW Blue Gain Control
02 RED 80 RW Red Gain Control
03 GREEN 80 RW Green Gain Control
AEC/AGC Control
Bit[7:3]: Reserved
04 AECL 88 RW
Bit[2:1]: AGC Gain Control - high 2 bits
Bit[0]: Exposure control LSB
05 BAVG 00 RW B Channel Average
06 GAVG 00 RW G Channel Average
07 RAVG 00 RW R Channel Average
Common Control 1
Bit[7]: Mirror function
0: Normal image
1: Mirror image
Bit[6]: Vertical flip function
0: Normal image
1: Vertically flip image
08 COM1 10 RW Bit[5]: Reserved
Bit[4]: VS pin output selection
0: Output signal depends on COM7[1] (0x15)
1: Output Odd field indicator
Bit[3]: Gamma function ON/OFF
0: Gamma OFF
1: Gamma ON
Bit[2:0]: Reserved
09 RSVD XX – Reserved
0A PIDH 79 R Product ID Number MSB (Read only)
0B PIDL 50 R Product ID Number LSB (Read only)
0C-0F RSVD XX – Reserved

Omni ision Register Set
Table 7 Device Control Register List (Continued)

Automatic Exposure Control - AEC[8:1] (LSB in AECL[0] (0x04) and MSB

10 AEC 82 RW
in AECH[6:0] (0x39))
11 RSVD XX – Reserved
Common Control 4
Bit[7]: SRST
0: No change
12 COM4 50 RW 1: Initiates system reset and resets all registers to factory
default values after which the device resumes normal
operation
Bit[6:0]: Reserved
AEC, AGC, and AWB Auto/Manual Control

Bit[7]: AEC speed selection
0: Normal
1: Faster AEC correction
Bit[6]: Reserved
Bit[5]: Banding filter ON/OFF selection
0: OFF
1: ON
Bit[4]: Reserved
Bit[3]: Small exposure ON/OFF selection
13 COM5 8F RW 0: OFF (minimum exposure is 1 Tv line period (65 µs))
1: ON (minimum exposure is 20 µs)
Bit[2]: AGC auto/manual control selection
0: Manual
1: Auto
Bit[1]: AWB auto/manual control selection
0: Manual
1: Auto
Bit[0]: Exposure control
0: Manual
1: Auto


Common Control 6
Bit[7:5]: AGC max gain ceiling
000: 2x
001: 4x
010: 8x
011: 16x
100: 32x
101-111: Not allowed
Bit[4]: Reserved
14 COM6 80 RW
Bit[3:2]: Digital gain ceiling
00: 1x
01: 2x
10: 4x
11: Not allowed
Bit[1]: Reserved
Bit[0]: Exposure freeze ON/OFF
0: OFF
1: ON
Common Control 7
Bit[7:2]: Reserved
Bit[1]: VSYNC output selection
15 COM7 00 RW
0: Field VSYNC
1: Frame VSYNC
Bit[0]: Reserved
Common Control 8
Bit[7]: AEC/AGC algorithm selection
0: Average-based AEC/AGC control
1: Histogram-based AEC/AGC control
16 COM8 40 RW Bit[6]: Auto/Manual digital gain select
0: Auto digital gain
1: Manual digital gain
Bit[5:4]: Manual set digital gain [1:0]
Bit[3:0]: Reserved
17-1A RSVD XX – Reserved
1B PSHFT 6A RW Left Pixel Shift - 1 bit equals 2 pixel shift
1C MIDH 7F R Manufacturer ID Byte – High (Read only = 0x7F)
1D MIDL A2 R Manufacturer ID Byte – Low (Read only = 0xA2)
1E-20 RSVD XX – Reserved


Common Control 9
Bit[7]: Reserved
Bit[6]: VSYNC output pattern control
0: VSYNC can start at line start or half line
21 COM9 00 RW
1: VSYNC can only start at line start
Bit[5]: VSYNC output only in field one
Bit[4]: VSYNC output only in field two
Bit[3:0]: Reserved
22-23 RSVD XX – Reserved
24 AECW 78 RW Luminance Signal High Range for AEC/AGC operation
25 AECB 68 RW Luminance Signal Low Range for AEC/AGC operation
26 VWB D4 RW Fast Mode Large Step Luminance Range Threshold
27-2E RSVD XX – Reserved
2F YAVG 00 RW Luminance Average Value
33 VSFT 00 RW Vertical Window Shift
Automatic Exposure Control MSBs

39 AECH 82 RW Bit[7]: Reserved
Bit[6:0]: Automatic exposure control MSBs
3A-65 RSVD XX – Reserved
Monitor
Bit[7:4]: Register monitor control (refer to descriptions of registers
66 MNTR 00 RW COM22 (0xED), COM23 (0xEE), COM24 (0xEF) and
COM25 (0xF0)
Bit[3:0]: Reserved
67-7A RSVD XX – Reserved
Gamma Curve Highest Segment Slop

Should be calculated as follows:
7B SLOP 24 RW SLOP[7:0] = (FF - GAM15[7:0] + 1) x 40/30
Note: Use hex numbers for calculation
7C GAM1 0F RW Gamma Curve - 1st segment input end point 0x010 output value
7D GAM2 1F RW Gamma Curve - 2nd segment input end point 0x020 output value
7E GAM3 36 RW Gamma Curve - 3rd segment input end point 0x040 output value
7F GAM4 54 RW Gamma Curve - 4th segment input end point 0x080 output value
80 GAM5 5F RW Gamma Curve - 5th segment input end point 0x0A0 output value
81 GAM6 6A RW Gamma Curve - 6th segment input end point 0x0C0 output value


82 GAM7 74 RW Gamma Curve - 7th segment input end point 0x0E0 output value
83 GAM8 7C RW Gamma Curve - 8th segment input end point 0x100 output value
84 GAM9 84 RW Gamma Curve - 9th segment input end point 0x120 output value
85 GAM10 8C RW Gamma Curve - 10th segment input end point 0x140 output value
86 GAM11 9A RW Gamma Curve - 11th segment input end point 0x180 output value
87 GAM12 A7 RW Gamma Curve - 12th segment input end point 0x1C0 output value
88 GAM13 BF RW Gamma Curve - 13th segment input end point 0x240 output value
89 GAM14 D3 RW Gamma Curve - 14th segment input end point 0x2C0 output value
8A GAM15 E5 RW Gamma Curve - 15th segment input end point 0x340 output value
8B-9A RSVD XX – Reserved
9B MTX1 40 RW Color Matrix Parameter M1
9C MTX2 34 RW Color Matrix Parameter M2
9D MTX3 0C RW Color Matrix Parameter M3
9E MTX4 17 RW Color Matrix Parameter M4
9F MTX5 29 RW Color Matrix Parameter M5
A0 MTX6 40 RW Color Matrix Parameter M6
Color Matrix Control

Bit[7]: Double matrix - double M1 to M6
Bit[6]: Reserved
Bit[5]: Sign bit of M6
A1 MTX7 1E RW Bit[4]: Sign bit of M5
Brightness Control
A2 BRT 00 RW
• Range [00] to [FF}
A3 CNTR 40 RW Contrast Control
A4-BE RSVD XX – Reserved
BF BPTH1 90 RW Black Pixel Threshold Level 1
C0 BPTH2 40 RW Black Pixel Threshold Level 2
C1 WPTH1 A0 RW White Pixel Threshold Level 1
C2 WPTH2 D0 RW White Pixel Threshold Level 2
C3 BPCNT1 CC RW Black Pixel Count Number 1
C4 BPCNT2 F0 RW Black Pixel Count Number 2


C5 WPCNT1 64 RW White Pixel Count Number 1
C6 WPCNT2 80 RW White Pixel Count Number 2
C7-D0 RSVD XX – Reserved
Bit[7:6]: Zone 4 16-Zone Y average select

Bit[5:4]: Zone 3 In each zone, the two bits mean:
D1 ZONE1 FF RW
Bit[3:2]: Zone 2 00: Not selected
Bit[1:0]: Zone 1 01: Weight x1
10: Weight x2
Bit[7:6]: Zone 8
11: Weight x4
Bit[5:4]: Zone 7
D2 ZONE2 FF RW H Start
Bit[3:2]: Zone 6
V Start
Bit[1:0]: Zone 5
1 2 3 4
Bit[7:6]: Zone 12
Bit[5:4]: Zone 11
D3 ZONE3 FF RW 5 6 7 8
Bit[3:2]: Zone 10
Bit[1:0]: Zone 8
9 10 11 12
Bit[7:6]: Zone 16
Bit[5:4]: Zone 15
D4 ZONE4 FF RW 13 14 15 16
Bit[3:2]: Zone 14
Bit[1:0]: Zone 13
D5-EA RSVD XX – Reserved
EB COM21 00 RW Overlay Data Shift Select
EC RSVD XX – Reserved
Register Monitor when MNTR[7:4] are:

0000: SPI input com1
ED COM22 – R 0111: SPI input com8



0000: Overlay control register
Bit[7:6]: Overlay function ON/OFF select
0x: Overlay function OFF
10: Overlay function ON
11: Overlay function OFF
0001: Overlay bitmap 1 control register
Bit[7:6]: Overlay opacity
00: 25% overlay opacity
Bit[7:6]: Overlay resolution
00: 2x2
01: 3x3
10: 4x4
11: 5x5
EE COM23 – R 0010: Y overlay target 1
0011: U overlay target 1
0100: V overlay target 1
0101: Overlay vertical window 1 start point MSBs
0110: Overlay vertical window 1 stop point MSBs
0111: Overlay horizontal window 1 start point MSBs
1000: Overlay horizontal window 1 stop point MSBs
1001: Reserved
Bit[7:6]: Overlay vertical window 1 start point LSBs
Bit[5:4]: Overlay vertical window 1 stop point LSBs
Bit[3:2]: Overlay horizontal window 1 start point LSBs
Bit[1:0]: Overlay horizontal window 1 stop point LSBs
1010: Memory length for one line
1011: Overlay bit map 2 start address LSBs
1100: Overlay bit map 2 start address MSBs
1101: Overlay bitmap 2 control register
1110: Y overlay target 2
1111: U overlay target 2

0000: V overlay target 2
0001: Overlay vertical window 2 start point MSBs
0010: Overlay vertical window 2 stop point MSBs
0011: Overlay horizontal window 2 start point MSBs
0100: Overlay horizontal window 2 stop point MSBs
EF COM24 – R
0101: Reserved
Bit[7:6]: Overlay vertical window 2 start point LSBs
Bit[5:4]: Overlay vertical window 2 stop point LSBs
Bit[3:2]: Overlay horizontal window 2 start point LSBs
Bit[1:0]: Overlay horizontal window 2 stop point LSBs
0110: Memory length 2 for one line



0000: Y average zone 1
F0 COM25 – R 0111: Y average zone 8
F1-F2 RSVD XX – Reserved
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.

Package Specifications
The OV7950/OV7451 uses a 48-pin ceramic package (CLCC). Refer to Figure 14 and Table 8 for CLCC information and
Figure 15 for the sensor array center.
Figure 14 OV7950/OV7451 Package Specifications
.088 – .011
.560 SQ + .012 / - .005 .065 – .007
.030 – .002
.430 SQ – .005 .440 – .005 .06 +.010
-.005
.015 – .002
.040 – .003
.350 SQ – .005 .020 – .002
42 31 31 42
.040 TYP
43 42 31 30 30 43
43 30
.022 – .004
.032
.001 to .005 TYP
MIN
.488
48 48 – .004 0.029 – .001 48
1 1 Glass 1
Die
Pin 1 .037 – .007
Index Image
6 Plane
19
6 19 19 .020 TYP 6
7 18 .012 TYP
REF
7 18 18 7
R .0075 .085 TYP
R .0075
(48 PLCS)
(4 CORNERS)
Table 8 OV7950/OV7451 Package Dimensions
Dimensions Millimeters (mm) Inches (in.)
Package Size 14.22 + 0.30 / -0.13 SQ .560 + .012 / - .005 SQ
Package Height 2.23 + 0.28 .088 + .011
Substrate Base Height 0.51 + 0.05 .020 + .002
Cavity Size 8.89 + 0.13 SQ .350 + .005 SQ
Castellation Height 1.14 + 0.13 .045 + .005
Pin #1 Pad Size 0.51 x 2.16 .020 x .085
Pad Size 0.51 x 1.02 .020 x .040
Pad Pitch 1.02 + 0.08 .040 + .003
Package Edge to First Lead Center 1.524 + 0.25 / -0.13 .06 + .010 / - .005
End-to-End Pad Center-Center 11.18 + 0.13 .440 + .005
Glass Size 12.40 + 0.10 SQ / 13.00 + 0.10 SQ .488 + .004 SQ / .512 + .004 SQ
Glass Height 0.55 + 0.05 .022 + .002
Die Thickness 0.733 + 0.015 .029 + .001
Top of Glass to Image Plane 0.95 + 0.18 .037 + .007
Substrate Height 1.65 + 0.18 .065 + .007

Omni ision Package Specifications
Sensor Array Center
Figure 15 OV7950/OV7451 Sensor Array Center
A rray C enter
(-127.5 μm, 812.6 μm)
1 S c an Origin
4080 μm
3102 μm
S ens or
A rray
P ac kage C enter
(0,0)
Die
S c an E nd
P ac kage
TOP V IE W
NOT E S : 1. T his drawing is not to s cale and is for reference only.

2. As mos t optical as s emblies invert and mirror the image, the chip is typically mounted
with pin one oriented down on the P C B .

IR Reflow Ramp Rate Requirements
OV7950/OV7451 Lead-Free Packaged Devices
Figure 16 IR Reflow Ramp Rate Requirements
300.0
Z1 Z2 Z3 Z4 Z5 Z6 Z7 end
280.0
260.0
240.0
220.0
200.0
180.0
Temperature ( C )
160.0
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0 0.6 1.1 1.6 2.2 2.8 3.3 3.9
0.0
-22 -2 18 38 58 78 98 118 138 158 178 198 218 238 258 278 298 318 338 358 369
Time (sec)
-0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
Time (min.)
Table 9 Reflow Conditions
Condition Exposure
Average Ramp-up Rate (30°C to 217°C) Less than 3°C per second
> 100°C Between 330 - 600 seconds
> 150°C At least 210 seconds
> 217°C At least 30 seconds (30 ~ 120 seconds)
Peak Temperature 245°C
Cool-down Rate (Peak to 50°C) Less than 6°C per second
Time from 30°C to 245°C No greater than 390 seconds

Omni ision Package Specifications
Note:
• All information shown herein is current as of the revision and publication date. Please refer
to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all
documentation.
• OmniVision Technologies, Inc. reserves the right to make changes to their products or to
discontinue any product or service without further notice (It is advisable to obtain current product
documentation prior to placing orders).
• Reproduction of information in OmniVision product documentation and specifications is

permissible only if reproduction is without alteration and is accompanied by all associated
warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible
or liable for any information reproduced.
• This document is provided with no warranties whatsoever, including any warranty of

merchantability, non-infringement, fitness for any particular purpose, or any warranty
otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision
Technologies Inc. disclaims all liability, including liability for infringement of any proprietary
rights, relating to use of information in this document. No license, expressed or implied, by
estoppels or otherwise, to any intellectual property rights is granted herein.
• ‘OmniVision’ and ‘OmniPixel’ are trademarks of OmniVision Technologies, Inc. All other trade,
product or service names referenced in this release may be trademarks or registered trademarks of
their respective holders. Third-party brands, names, and trademarks are the property of their
respective owners.
For further information, please feel free to contact OmniVision at [email protected].
OmniVision Technologies, Inc.

1341 Orleans Drive
Sunnyvale, CA USA
(408) 542-3000


Omni ision TM
REVISION CHANGE LIST
Document Title: OV7950/OV7451 Datasheet (non-auto apps) Version: 2.3
DESCRIPTION OF CHANGES
Initial Release (created using OV7950/OV7451 ver 1.3 (for auto apps) with the following
changes):
• Deleted “for Automotive Applications” from the title.
• Under Ordering Information, changed the part number from OV07950-Q10V and
OV07451-Q10V to OV07950-C10A and OV07451-C10A.
• Changed bullet list under Applications on page 1.
• Changed Figure 1 to show pinout diagram for CLCC package.
• Under Package Specifications on page 24, changed Figure 14 and Table 8 to show CLCC
package drawing and CLCC package dimensions table.
Omni ision TM
The following changes were made to version 2.3:
• Added Figure 13 (OV7950 Light Response graph) on page 15
• Under Features on page 1, changed second bullet from “Composite video (NTSC)
differential output drive” to “Composite video (NTSC) output”
Omni ision TM
The following changes were made to version 2.4:
• Under Key Specifications on page 1, changed Power Consumption from “TBD” to
“200 mW”
• Under Key Specifications on page 1, changed S/N Ratio from “TBD” to “48 dB”
• Under Key Specifications on page 1, changed Dynamic Range from “TBD” to “49 dB”
• Under Key Specifications on page 1, changed Dark Current from “TBD” to
“10 mW/s @ 60°C”
• Under Key Specifications on page 1, changed Fixed Pattern Noise from “TBD” to
“0.22% of VPEAK-TO-PEAK”
• In Table 1 on page 7, changed Default value for pin 02 from “TBD” to “–”
• In Table 2 on page 9, changed Min and Max for Operating temperature from “TBD” and
“TBD” to “-40°C” and “+85°C”, respectively.
• In Table 2 on page 9, deleted table row for Storage Humidity.
• In Table 3 on page 9, added the table footnote: “Exceeding the stresses listed may
permanently damage the device. This is a stress rating only and functional operation of the
sensor at these and any other condition above those indicated in this specification is not
implied. Exposure to absolute maximum rating conditions for any extended period may
affect reliability.”
• In Table 3 on page 9, changed Typ for Supply current (IDD) from “TBD” to “60”
• In Figure 8 on page 11, changed callout from “1.020 V” to “1.13V”

Mni Ision: Ov7950/Ov7451 Cmos Analog NTSC C C With Omnipixel Technology

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OV7950/OV7451 CMOS Analog NTSC CAMERACHIPTM with OmniPixel® Technology

General Description Applications

• Master/slave compatible Serial Camera Control Bus 30 29 28 27 26 25 24 23 22 21 20 19

(SCCB) control interface for register programming RES 31 18 VS

• Low power consumption DOVDD 32 17 ADGND

• Extreme low dark current for high temperature PCLK 33 16 ADVDD

• Defective pixel correction NC 35 14 ESO

Product Package NC 39 10 RESET

OV07950-C10A (Color, NTSC) CLCC-48 NC 41 8 OVLEn

Version 2.5, February 28, 2006 Proprietary to OmniVision Technologies 1

Figure 2 Functional Block Diagram

Timing/Clock Generator Register SCCB

Video Standards Image Sensor Functions

NTSC TV standards are implemented and available as

2 Proprietary to OmniVision Technologies Version 2.5, February 28, 2006

The OV7950/OV7451 SCCB interface supports multi-byte

The OV7950/OV7451 supports a single slave ID. The ID

• Provide the serial clock on SIO_C DATA DATA

Version 2.5, February 28, 2006 Proprietary to OmniVision Technologies 3

SCCB Master Address Value

When the sub_add = [FF] and add_value = [FF}, the

Figure 4 Data Transfer on the SCCB

SIO_D SLAVE ID RW SUB-ADDRESS DATA

Figure 5 SCCB Protocol Format

FIRST BYTE SECOND BYTE THIRD BYTE

S SLAVE (7-BIT) RW A SUB-ADDRESS (8-BIT) A DATA (8-BIT) A P

MSB LSB=0 ACK ACK

MASTER TRANSMIT, SLAVE RECEIVE (WRITE CYCLE)

FIRST BYTE SECOND BYTE

S SLAVE (7-BIT) RW A SUB-ADDRESS (8-BIT) A P

MSB LSB=0 ACK

MASTER TRANSMIT, SLAVE RECEIVE (DUMMY WRITE CYCLE)

FIRST BYTE SECOND BYTE THIRD BYTE

S SLAVE (7-BIT) RW A DATA (8-BIT) A DATA (8-BIT) 1 P

MSB LSB=1 ACK STOP

SLAVE ID – 1000000X S – START CONDITION – SLAVE TRANSMIT

4 Proprietary to OmniVision Technologies Version 2.5, February 28, 2006

Overlay Control Data formats are defined as follows:

The OV7950/OV7451 CAMERACHIP has an overlay Address Description

Version 2.5, February 28, 2006 Proprietary to OmniVision Technologies 5

Byte [11] Byte [1A]

Resolution = 00 01 10 11 Every time when a new line is started, it is necessary to go

V overlay = V target x q% + V original x (1-q%) Line 2 start address = [70],

Disable: Reading sequence:

Y overlay = Y target x q% + Y original x (1-q%) Byte[60]bit7, bit6,…bit0,

6 Proprietary to OmniVision Technologies Version 2.5, February 28, 2006

Table 1 Pin Description

Pin Pin Default

01 SVDD Power 3.3 Sensor array power supply

02 VREFH Analog – Internal reference

03 VREFS Analog – Internal reference

04 DEVDD Power 0 Sensor array decoder power supply

05 NVREF Power 0 Internal reference

06 VRLOW Analog – Internal reference

Power Down Mode ON/OFF Selection

12 ESI Input 0 SPI interface data input

13 CS Output – SPI interface chip select signal

14 ESO I/O 0 SPI interface data output