Flexible Timing Configuration With IO-Link Master Frame Handler

Flexible Timing Configuration with IO-Link Master Frame
Handler
Thomas Schneider
to react on the different timing behaviors. This flexible

IO-Link is a serial, bi-directional, point-to-point protocol
timing configuration makes it possible to also
and interface standard for sensors and actuators in
communicate in these special use cases. Not only can
factory automation applications. An IO-Link system
the time tA and t2 be adjusted during run-time, but also
consists of an IO-Link master and IO-Link devices,
the delay time while establishing Master port
including sensors, actuators, RFID readers, I/O
communication TDMT can be adjusted as needed.
modules, and so forth. The IO-Link master enables
data exchange with IO-Link devices from different Figure 2 shows the block diagram of an 8 Port IO-Link
manufacturers. These interactions of the master and Master Reference Design (TIDA-010016) where the
its devices are characterized by several time frame handler is implemented in software using the
constraints that apply to the UART frame and the PRU.
master and device message transmission times.
Communication between a master port and its Figure 2. TIDA-010016 Block Diagram
associated device takes place in a fixed schedule
called the M-sequence time. Figure 1 demonstrates
the timings of an M-sequence consisting of a master
port message and a device message. The device
needs to respond to the master within the response
time of the device tA and not exceeding the maximum
UART frame transmission delay t2.
Figure 1. IO-Link Timing
Usually a frame handler is used to execute most of the

low level communication tasks to decrease the load on Implementation
the processor of the IO-Link master. Often, this frame
handler is implemented already in a semiconductor For the IO-Link master frame handler implementation
device together with the PHY. As the frame handler with a flexible timing configuration, one of TI's Sitara
implementation is fixed in this case in hardware, this processors with the integrated PRU-ICSS has been
makes it inflexible to react on the different timing used. The PRU-ICSS is a specialized sub-processor
behaviors of the IO-Link devices from different within some of TI’s Sitara processors. It is designed to
manufacturers. According to the IO-Link specification, complete most instructions in a single cycle and offers
the time tA needs to be less than 10 TBit and t2 needs deterministic behavior of those. This PRU-based frame
to be less than 3 TBit, where TBIT = 1 / (transmission handler enables a very flexible way of timing and time
rate). For example, this might be violated if an synchronization and is almost free of jitter. It replaces
inductive coupler device is between the master and hardware UARTs by a software implementation and
the device communication line and adding some delay eliminates the need for external processing hardware.
to the communication. A frame handler with fixed With one PRU up to 8 IO-Link master ports can be
timing limits might not be able to continue with the IO- realized. As one ICSS module of the Sitara processor
Link communication in this case. TI's solution to consists out of two PRUs, up to 16 IO-Link master
implement the frame handler in software using the ports can be realized with one ICSS module. All ports
programmable real time unit and industrial support independent cycle time from 400 µs up to 132
communications subsystem (PRU-ICSS) of the ms in 100 µs steps. At 400 µs, a maximum payload of
Sitara™ processor family makes it much more flexible eight bytes is supported. The double send buffer
SPRACM6 – March 2019 Flexible Timing Configuration with IO-Link Master Frame Handler Thomas Schneider 1
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minimizes tidle time and offloads the host timing. Test Results
Synchronous start of selected channels is supported
For test purposes, an inductive coupler device is used.
without any jitter and latency between the channels.
Inductive coupler devices are placed between an IO-
Figure 3 shows the IO-Link master PRU frame
Link master and an IO-Link device to transfer power
handler. The often available second ICSS module on
and IO-Link data contactlessly across an air gap,
the Sitara processor can be used to process
adding some delay to the response time tA of the IO-
something else, like real-time Ethernet.
Link device. In the test case, an IO-Link device with a
transmission rate of 38.4 kbit/s (COM2) is used.
Figure 3. IO-Link Master – PRU Frame Handler
Figure 5 shows the measured response time tA which
is 57 TBIT.
Figure 5. Measured Response Time tA of the IO-

Link Device
A standard IO-Link master frame handler

The IO-Link master PRU frame handler driver is part of implementation in hardware is not be able to
the RTOS Processor SDK for Sitara AM437x and communicate with an IO-Link device with a response
AMIC120 PROCESSOR-SDK-RTOS-AM437X. The time of 57 TBIT as it is not flexible enough to adjust the
driver supports the following major functionalities: timing. Only the flexible timing configuration with the
• Standard APIs to initialize, de-initialize, and control IO-Link master frame handler implemented in software
the common Software IP driver using the PRU makes it possible to still communicate
with IO-Link devices in these special use cases.
• Configuration and control of the PRU frame handler
firmware to handle the messages transferred Table 1. Alternative Device Recommendations
between the IO-Link master and device
• Timer and interrupt driven IO-Link communication OPTIMIZED PERFORMANCE
DEVICE
PARAMETERS TRADE-OFF
between IO-Link master and device to meet the
timing requirement of IO-Link master protocol ARM Cortex-A9 Up to
AM4x
1000 MHz; 2x PRU-ICSS
In addition, a sample IO-Link master stack interface ARM Cortex-A9 Up to
AMIC120 2x PRU-ICSS
layer is provided in the IO-Link master demo 300 MHz
application to provide an interface between the IO-Link ARM Cortex-A9 Up to
AMIC110
master stack and the driver. Figure 4 shows an IO-Link 300 MHz; 1x PRU-ICSS
master integration example with Profinet. ICSS0 is
used for IO-Link and ICSS1 is used for Profinet. References
Figure 4. PRU-ICSS IO-Link Master Project Texas Instruments, Sitara AM4x Processors
Example Texas Instruments, 8 Port IO-Link Master
Reference Design (TIDA-010016)
IO-Link, IO-Link Interface and System
Specification
2 Flexible Timing Configuration with IO-Link Master Frame Handler Thomas Schneider SPRACM6 – March 2019
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Flexible Timing Configuration with IO-Link Master Frame

to react on the different timing behaviors. This flexible

Figure 1. IO-Link Timing

Usually a frame handler is used to execute most of the

Figure 5. Measured Response Time tA of the IO-

A standard IO-Link master frame handler

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