Lakshya User Manual

Lakshya User Manual - Revision history

Versio Name Date Comments

n
1.0 Srinath BK 20/5/2015 Fist version

1.1 Srinath BK 10/6/2015 Locations of handoff files updated

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Table of Contents
1 -Introduction to Lakshya...................................................................................................................1
2 -Specifications of Lakshya................................................................................................................2
3 -Overview of Lakshya subsystem.....................................................................................................3
Top level pins...................................................................................................................................3
Lakshya subsystem..........................................................................................................................4
LC3..................................................................................................................................................5
dmac_mem_toplevel........................................................................................................................7
mem_data_trans_toplevel................................................................................................................9
cont_uart_toplevel.........................................................................................................................12
aes_cipher......................................................................................................................................14
aes_invcipher.................................................................................................................................16
megatron........................................................................................................................................18
4 -DFT................................................................................................................................................21
ATPG.............................................................................................................................................21
PBIST.............................................................................................................................................21
5 -Directory structure for the project..................................................................................................22
6 -Appendix........................................................................................................................................23
FSM-Based Programmable Memory BIST with Macro Command..............................................23

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Chapter -Introduction to Lakshya

1 - Introduction to Lakshya
Lakshya sub-system is an example created with intent to capture the various aspects and challenges of VLSI Physical
Design flow. It is meticulously planned to expose real world complexities in the physical design.
The gross level architecture consists of the following functional blocks:

Microprocessor core
Microprocessor core is the heart of the sub-system. It has 16-bit address and data busses. Most of the functional
blocks described below are attached to the system bus comprising of the microprocessor data and address bus.
These functional blocks’ registers and the memory are visible to the microprocessor core through the unique
address space assigned. All read/write functions to any of the peripheral cores are done through this
microprocessor core.

Image processing core

The image processing module controls the transfer of data between set of memories. It consists of a sensor
controller, histogram generator, memory controller and eleven memory cores. Respective enable signals from
microprocessor core are required to activate the controllers. It controls line scan sensor by giving expose and
capture signals and reads the data from the sensor by giving the read signal and stores the data in memory and it
reads from this memory manipulates the data and stores it in different memory.

Cryptography core
The AES cipher module reads the data from one memory as plain text and converts it into a cipher text and writes
the cipher text as the data to another memory. The module consists of a cipher logic controller module, two
memories and respective decoders to access these memories. The memory location to be accessed remains in the
address space of the microprocessor module.
The AES decipher module reads the data from one memory as cipher text, converts it into a plain text and writes
the plain text as the data to another memory. The module consists of a decipher logic controller module, two
memories and respective decoders to access these memories. The memory location to be accessed remains in the
address space of the microprocessor module.

DMAC controller
The DMAC controller module controls the transfer of data between set of memories. It consists of a controller
FSM module, four memories and respective decoders to access the memories. It reads data from a set of memory
locations and writes to a different set of memory locations in the given address space of the memory locations
module.

Data manipulation core

This module performs various data manipulation operations. It also has enough amounts of memory blocks to
assist the intermediate storage. Also, it works under two clock domains.

Communication core
Communication core is basically an UART IP with a micro processor interface. It is interfaced to the memories to
which the microprocessor core writes the data. When data is present in the memory core, the communication block
reads the data and sends it outside. At the same time, incoming data is also updated into the memory which the
microprocessor core can access.

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2 - Specifications of Lakshya
Technology 40nm
Supply voltage (nom) 1.1V
Vt of transistors svt, lvt, hvt
Area (approximate) 4.2mm2
Clock frequency 833MHz
Power consumption 600mW
Max. IR drop (VDD+VSS) 5.00%

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3 - Overview of Lakshya subsystem

Top level pins

clk

rst
16
instr_in 16
16 addr_bus
data_in 16
data_bus

read_mem uart_clk
Lakshya
Lakshya
uart_REC_dataH_in uart_XMIT_dataH_out

set_c

rclk
8
red capture
8
green expose
8
blue read

valid

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Lakshya subsystem

read_mem
clk

rst
16 clk
instr_in LC3 dmac_mem_
dmac_mem_
LC3 toplevel
16 toplevel rst
data_in
ack_complete_instr_in
ack_complete_data_in

clk
rclk aes_cypher_mem clk
aes_cypher_mem
rst toplevel
toplevel
rst
valid
8
red
8 megatron
megatron
clk
green aes_invcypher_
aes_invcypher_
8 mem_toplevel
mem_toplevel
blue rst
addr_bus

data_bus

capture
expose
read clk
mem_data_
mem_data_
trans_controller
trans_controller rst
clk _toplevel
_toplevel
uart_clk start
rst
set_c cont_uart
cont_uart
uart_REC_
dataH_in
uart_XMIT_
dataH_out

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LC3

async
asyncfetch
fetch

clk decode
decodeblock
block

rst d_macc
16 execute 16
execute
instr_in addr_bus
16 16
data_in data_bus
write
writeblock
block

memory
memoryaccess
access

Controller
Controllerm2
m2

Introduction
LC3 (Little Computer 3), is a microcontroller with a reduced instruction set.
• It acts as a main controller to the Lakshya module.
• The address space of all memories lie within the address space of LC3.
• LC3 supports ALU operations(ADD, AND, NOT).
• LC3 supports Memory operations(LD, LDR, LDI, ST, STR, etc.).
• The write to the memories is made through LC3, connected to Address and Data bus.
• It is used to set the internal registers which intern triggers a particular sub module.

Pins
Pin Name Width Direction Description
clock 1 Input It is the clock signal to all modules
reset 1 Input It is the reset signal
Instr_dout 16 Input Corresponds to the instruction from the
instruction memory
complete_data_in 1 Input Bit input from dmac_mem_toplevel
module
complete_instr_in 1 Input Bit input from dmac_mem_toplevel
module
data_dout 16 Input Corresponds to the value read from the

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data memory
Data_din 16 Output Corresponds to the value that need to be
written to data memory sent to the data
memory
Data_addr 16 Output Corresponds to the address sent to the
data memory
D_macc 1 Output To access write to data memory
I_macc 1 Output Not used by the Lakshya module
instrmem_rd 1 Output Not used by the Lakshya module
Data_rd 1 Output Not used by the Lakshya module
PC 16 Output Not used by the Lakshya module

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dmac_mem_toplevel

dmac_controller_module

Source
Sourceaddr
addrreg
reg

Decoder
Decoder
read_32
Destination
Destinationaddr
addrreg
reg 32x16
32x16
cena
wena
Number
Numberofofbytes
bytes oena

DATA BUS
ADDR BUS

wena

Addr
oena

cena

16
Write
Writemem
mem
DA Memory
Memory
Start QA 32x16
32x16
Start

ack_complete_instr_in read_64 Decoder

Decoder
64x16
64x16
ack_complete_data_in wena

Addr
oena

cena

NOTE: both CLKA & CLKB 16

ports of memories are connected
to clk DA Memory
Memory
QA 64x16
64x16

Decoder
Decoder read_256 read_128 Decoder
Decoder
256x16
256x16 128x16
128x16
wena

wena
Addr

Addr
oena

oena
cena

cena
16

16

Memory DA DA Memory
Memory Memory
256x16
256x16 QA 128x16
QA 128x16

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Introduction
The dmac_mem_toplevel module controls the transfer of data between set of memories. It consists of a
dmac_controller module, four memories and respective decoders to access the memories. It reads data from a set of
memory locations and writes to a different set of memory locations in the given address space of the LC3 module.
The pin descriptions table and the functionality of the sub modules is described in subsequent sections.

Pins
Pin Name Width Direction Description
clk 1 Input It is the clock signal to all modules
rst 1 Input It is the reset signal
start 1 Input Signal from LC3 module to start the controller process
read 1 Input A primary input signal to perform read operation on
memories
write 1 Input Signal from LC3 to perform write operations on
memories
addr_bus_dmac 16 Input Address from LC3 to access internal registers of dmac
controller module and access memories
data_bus_dmac 16 Inout Data from LC3 to be written into internal registers of
dmac controller module and memories
ack_complete_data_lc3 1 output An acknowledge signal to LC3
ack_complete_instr_lc3 1 output An acknowledge signal to LC3

dmac_controller
The DMAC Controller or dmac_controller, a controller module in dmac_mem_toplevel block, generates the
appropriate signals to transfer data between set of memories. It consists of four 16 bit registers : src_reg, dest_reg ,
num_bytes_reg and start_reg. These registers have unique address given in the address space of LC3. A write to
these registers happen when start signal is high and the address and data are given at the inputs. The controller reads
data from memory location given by the content of src_reg and writes the data into memory location given by the
content in the dest_reg, this process is repeated for number of times given by num_bytes_reg. The whole operation of
transferring data starts when a non zero value is written into start_reg.

Memories
The module has four dual port memories, SRAM_32x16_M4, SRAM_64x16_M4, SRAM_128x16_M4,
SRAM_256x16_M4. The access to the memories is through Port A . Port B pins are reserved for future use.
The address and data to write to the memories are from LC3 but to read from memories is through inout ports
address_bus and data_bus.

Decoders
It has four decoder modules, address_decoder1_32x16, address_decoder1_64x16, address_decoder_128x16,
address_decoder1_256x16. Address from address bus is given to memories through decoders and the respective
read or write operations are triggered.

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mem_data_trans_toplevel

inst2_
inst2_
256x16
256x16
(C)
(C)
ADDR BUS

DATA BUS

16 Level1
Level1
MSB
MSBCC→ →AA
LSB
LSBCC→→BB
8

L1 done
inst1_
inst1_ inst2_
inst2_
256x8
256x8 256x8
256x8
(A)
(A) (B)
(B)
Level2
Level2
8

(MSN
(MSN A)(LSNB)
A)(LSN B)→
→PP
(MSN
(MSN A)(MSN B) →QQ
A)(MSN B) →
(LSN
(LSNA)(MSN
A)(MSNB) B)→
→RR
8

(LSN
(LSN A)(LSN B) →SS
A)(LSN B) →
inst3_
inst3_ inst4_
inst4_ inst5_
inst5_ inst6_
inst6_

L2 done
256x8
256x8 256x8
256x8 256x8
256x8 256x8
256x8
(P)
(P) (Q)
(Q) (R)
(R) (S)
(S)
8

Level3
Level3
(P+Q)/2
(P+Q)/2→→XX
(R+S)/2
(R+S)/2→
→YY
8

L3 done

inst7_
inst7_ inst8_
inst8_
256x8
256x8 256x8
256x8
(X)
(X) (Y)
(Y)
Level4
Level4
8

(MSB
(MSB X)(LSBY)
X)(LSB Y)→
→ZZ
16

done

inst3_
inst3_
256x16
256x16
(Z)
(Z)

start L1 done
mem_data_
mem_data_ L2 done
clk trans_controller
trans_controller L3 done
rst L4 done
done

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Introduction
The mem_data_trans_controller_toplevel module reads the data from one or more memories , perform some
transformation on the data and writes the transformed data to another memory. The toplevel module consists of ten
memories. The memory location to be accessed remains in the address space of the LC3 module.
The pin descriptions table and the functionality of the sub modules is described in subsequent sections.

Pins
Pin Name Width Direction Description
clk 1 Input It is the clock signal to all modules
rst 1 Input It is the reset signal
do 1 Input Signal to start the controller process
rd 1 Input A primary input signal to perform read operation on
memories
wr 1 Input Signal from LC3 to perform write operations on memories
mem_data_trans_addr 16 Input Address from LC3 to access memories
mem_data_trans_data 16 Inout Data from LC3 to write into memories
mem_data_trans_finis 1 Output This signal is logic high when the memory data transfer
h function for all memory locations is complete

Memory data transfer controller

The transformations on data in the memories are controlled by the mem_data_trans_controller_toplevel module. The
transformations happen in four levels.
Level 1 : 1. Read the 16 bits data from memory C.
2. Write the MSB byte to memory A and the LSB byte to memory B.
Level 2 : 1. Read the 8 bits data from memories A and B.
2. Write the MSN of memory A and LSN of memory B to memory P.
3. Write the MSN of memory A and MSN of memory B to memory Q.
4. Write the LSN of memory A and MSN of memory B to memory R.
5. Write the LSN of memory A and LSN of memory B to memory S.
Level 3 : 1. Read the 8 bits data from memories P and Q.
2. Write the average of the two 8 bits data in memory X.
3.Read the 8 bits data from memories R and S.
4. Write the average of the two 8 bits data in memory Y.
Level 4 : 1. Read the 8 bits data from memories X and Y.
2. Write the 8 bits data from memory X as MSB byte and the 8 bits data from memory Y as LSB byte to
memory Z.

Memories
The module has eight SRAM_256x8_M4 dual port memories and two SRAM_256x16_M4 dual port memories. The
two SRAM_256x16_M4 memories are named as C and Z and the eight SRAM_256x8_M4 memories are named as
A, B, P, Q, R, S, X and Y. The direct access to the memories is through Port A . Port B pins are used by the invcipher
module to read and write into the two memories.
The address and data to write to the memories (through Port A) are from LC3 but to read from memories is through
inout ports address_bus and data_bus.

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Decoders
It has two decoder modules, address_decoder2_256x16, address_decoder5_256x16. Address from address bus is
given to two SRAM_256x16_M4 memories through these decoders and the respective read or write operations are
triggered.

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cont_uart_toplevel

Address_
Address_ Address_
Address_

ADDR
decoder2_ decoder3_

BUS
decoder2_ decoder3_
32x16
32x16 32x16
32x16 cena_mem
wena_mem
oena_mem

wenb

oenb
cenb
QB

wenb

oenb
cenb

QB
inst_SRAM_ inst_SRAM_ inst_SRAM_ inst_SRAM_
32x16_1 32x16_1 32x16_2 32x16_2
/inst_memory1 /inst_memory2 /inst_memory1 /inst_memory2
wena

wena
cena
oena

oena
cena
DA

DA

cont_uart
cont_uart
wenb

oenb
cenb
QB

cont_uart
inst_SRAM_
inst_SRAM_
64x16
64x16
wena

oena
cena
DA

clk uart_clk
rst cont_uart_mem
cont_uart_mem xmit
set_c
rec

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Introduction
The Cont_uart module controls the transfer of data between set of memories. It consists of
control_ram32x16to64x16, mem_uart_contl modules and three memories. The lc3 writes the data to first two
memories and the controller controls the data flow between the first two memories and the third memory.
The pin descriptions table and the functionality of the sub modules is described in subsequent sections.

Pins
Signal Width Direction Description
clk 1 Input It is the clock signal to this module
rst 1 Input Reset signal to the module
set_c 1 Input Set signal to the module
CENa, CENb 1 Input Chip select signal for the memories SRAM_ 32x16_M4
and SRAM_32x16_M4
WENa, WENb 1 Input Read or write signal for the memories SRAM_ 32x16_M4
and SRAM_32x16_M4
OENb, OENa 1 Input Output enable signal to the memories SRAM_
32x16_M4 and SRAM_32x16_M4
uart_REC_data 1 Input Input to the UART from the external world
H
Da, Db 8 Input Carries data which is to be written to the memories
SRAM_ 32x16_M4_1 and SRAM_32x16_M4_2
Aa , Ab 5 Input Address input to the memory
uart_clk 1 Output Output of the baud rate clock, baud rate is 9600 bps
Qa , Qb 8 Output Output of the memories

Memories
This module has two SRAM_32x16_M4 memories and one SRAM_64x8_M4 memory giving rise to three memories.
The memories are named as SRAM_32x16_1,SRAM_32x16_2 and SRAM_64x6_M4 memories. The port B of
SRAM_32x16_1 , SRAM_32x16_2 memories are connected to the memories. The SRAM_64x6_M4 is connected
between the two controllers control_ram32x16to64x16 , mem_uart_contl.

control_ram32x16to64x16
This is the first controller of the cont_uart block. This controller gets activated when ever data is written to memories
SRAM_32x16_1 , SRAM_32x16_2 from the lc3 controller. As name indicates this controller reads the data from
SRAM_32x16_1 memory and SRAM_32x16_2 memory and writes it to the memory SRAM_64x6_M4. This process is
repeated until the SRAM_64x6_M4 is filled.

mem_uart_contl
This is the second controller of the cont_uart block. This controller gets activated when ever the data is written to the
memory SRAM_64x6_M4. It transfers the data written to the memory to the uart. Only 8 bits are written to the uart at
a time and rest 8 bits are written to the uart after the transmission of the first 8 bits. When uart receives any data it is
stored in the memory SRAM_64x6_M4 starting from location 20h.

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aes_cipher

read_mem
clk
rst

clk

wr
rst
address_decoder2
address_decoder2
64x16
ADDR BUS

64x16
DATA BUS

cena_mem
mem_addr

oena_mem
128_1

wena
oena
cena

wena_mem
16
DA QB mem_in
QA 16
AB
inst2_ addr_r_mem
inst2_ aes_cipher_
64x16
64x16 cenb_r aes_cipher_
controller_
controller_
oenb_r module
module
wenb_r

cenb_w
oenb_w
inst3_
inst3_
64x16 wenb_w
64x16 16
DA DB mem_out
QA AB 6
addr_w_mem
mem_addr

cypher_key_out
plain_text_out

cipher_text_in
128_2

wena
oena
cena

key_load

ready
start
128

128

128

address_decoder3
address_decoder3
64x16
64x16

aes_cipher_module
aes_cipher_module
clk
rst

clk
rst

NOTE: CLKA/CLKB ports of

memories are connected to clk
Introduction
The aes_cipher_toplevel module reads the data from one memory as plain text, converts it into a cipher text and
writes the cipher text as the data to another memory. The toplevel module consists of a aes_cipher_controller module,
a aes_cipher module, two memories and respective decoders to access these memories. The memory location to be
accessed remains in the address space of the LC3 module.
The pin descriptions table and the functionality of the sub modules is described in subsequent sections.

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Pins
Pin Name Width Direction Description
clk 1 Input It is the clock signal to all modules
rst 1 Input It is the reset signal
start 1 Input Signal to start the controller process
read 1 Input A primary input signal to perform read operation on memories
write 1 Input Signal from LC3 to perform write operations on memories
addr_bus_aescip 16 Input Address from LC3 to access memories
h
data_bus_aescip 16 Inout Data from LC3 to write into memories
h

aes_cipher_controller
The AES cipher controller module reads the data from one SRAM_64x16_M4 memory as plain text and provides it
as the input to the cipher module, then the cipher text output from the cipher module is written into another
SRAM_64x16_M4 memory. The controller generates appropriate start signals to the cipher module and read and
write signals to the two memories.

aes_cipher
The aes_cipher module takes in the plain text and key and produces the cipher text using the key. The conversion of a
plain text to cipher text begins when the start signal is given from the controller to the module. A ready signal is given
from cipher module to controller when ever a cipher text is generated.

Memories
The module has two SRAM_64x16_M4 dual port memories. The direct access to the memories is through Port A .
Port B pins are used by the cipher module to read and write into the two memories.
The address and data to write to the memories (through Port A) are from LC3 but to read from memories is through
inout ports address_bus and data_bus.

Decoders
It has two decoder modules, address_decoder2_64x16, address_decoder3_64x16. Address from address bus is
given to memories through decoders and the respective read or write operations are triggered.

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aes_invcipher

read_mem
clk
rst

clk

wr
rst
address_decoder2
address_decoder2
64x16
ADDR BUS

64x16
DATA BUS

cena_mem
mem_addr

oena_mem
128_1

wena
oena
cena

wena_mem
16
DA QB mem_in
QA 16
AB
inst2_ addr_r_mem
inst2_ aes_invcipher_
64x16
64x16 cenb_r aes_invcipher_
controller_
controller_
oenb_r module
module
wenb_r

cenb_w
oenb_w
inst3_
inst3_
64x16 wenb_w
64x16 16
DA DB mem_out
QA AB 6
addr_w_mem
mem_addr

cypher_key_out

cipher_text_out
plain_text_in
128_2

wena
oena
cena

key_load

ready
start
128

128

128

address_decoder3
address_decoder3
64x16
64x16

aes_invcipher_module
aes_invcipher_module
clk
rst

clk
rst

NOTE: CLKA/CLKB ports of

memories are connected to clk

Introduction
The aes_invcipher_toplevel module reads the data from one memory as cipher text, converts it into a plain text and
writes the plain text as the data to another memory. The toplevel module consists of a aes_invcipher_controller

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module, a aes_invcipher module, two memories and respective decoders to access these memories. The memory
location to be accessed remains in the address space of the LC3 module.
The pin descriptions table and the functionality of the sub modules is described in subsequent sections.

Pins
Pin Name Width Direction Description
clk 1 Input It is the clock signal to all modules
rst 1 Input It is the reset signal
start 1 Input Signal to start the controller process
read 1 Input A primary input signal to perform read operation on
memories
write 1 Input Signal from LC3 to perform write operations on memories
addr_bus_aesinvciph 16 Input Address from LC3 to access memories
data_bus_aesinvciph 16 Inout Data from LC3 to write into memories

aes_invcipher_controller
The AES invcipher controller module reads the data from one SRAM_64x16_M4 memory as cipher text and provides
it as the input to the invcipher module, then the plain text output from the invcipher module is written into another
SRAM_64x16_M4 memory. The controller generates appropriate start signals to the invcipher module and read and
write signals to the two memories.

aes_invcipher
The aes_invcipher module takes in the cipher text and key and produces the plain text using the key. The conversion
of a cipher text to plain text begins when the start signal is given from the controller to the module. A ready signal is
given from invcipher module to controller when ever a plain text is generated.

Memories
The module has two SRAM_64x16_M4 dual port memories. The direct access to the memories is through Port A .
Port B pins are used by the invcipher module to read and write into the two memories.
The address and data to write to the memories (through Port A) are from LC3 but to read from memories is through
inout ports address_bus and data_bus.

Decoders
It has two decoder modules, address_decoder4_64x16, address_decoder5_64x16. Address from address bus is
given to memories through decoders and the respective read or write operations are triggered.

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megatron

capture
expose
valid

read

clk
rst
G
R

B
sen_control
sen_control DA, cena,
oena, wena
DA, cena,
oena, wena

RR GG BB MM NN OO
256x8
256x8 256x8
256x8 256x8
256x8 256x8
256x8 256x8
256x8 256x8
256x8
QB, cenb,
oenb, wenb histena

clk histogram
histogram
rst
DA, cena,
DA, cena,
oena, wena
oena, wena from ?
ena_fifo
control_
control_ average
average
XX YY ZZ mem
mem 256x8
256x8
done

256x8
256x8 256x8
256x8 256x8
256x8
QB, cenb,
QB, cenb,
oenb, wenb
oenb, wenb
QB
xyz
xyz
clk mem_control
mem_control 1024x8
1024x8
rst
DA, cena,
rclk

oena, wena

NOTE:

CLKA/CLKB ports of all memories

except those connected to
fifo_control_mem are connected to
clk.

Memories connected to
fifo_control_mem are using rclk.

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Chapter -Overview of Lakshya subsystem

Introduction
The Megatron module controls the transfer of data between set of memories. It consists of a Sen_controller,
Histogram, Mem_control, Control_mem modules and eleven memories and respective enable signals from lc3 are
required to activate the controllers . It controls line scan sensor by giving expose and capture signals and reads the
data from the sensor by giving the read signal and stores the data in memory and it reads from this memory
manipulates the data and stores it in different memory.
The pin descriptions table and the functionality of the sub modules is described in subsequent sections.

Pins
Signal Width Direction Description
clk 1 Input It is the clock signal to this module
rclk 1 Input It is another clock signal to this module
rst 1 Input Reset to the module
red 8 Input Inputs from the sensor
green 8 Input Inputs from the sensor
blue 8 Input Inputs from the sensor
valid 1 Input Inputs from the sensor
capture 1 Output Outputs to the sensor
expose 1 Output Outputs to the sensor
read 1 Output Outputs to the sensor

Memories
This module has ten SRAM_256x8_M4 memories and one SRAM_1024x8_M16 memory giving rise to eleven
memories. The memories are named as RED, GREEN, BLUE, M, N, O, X, Y, Z, XYZ, average memories. Port A of
M, N, O memories are for further use and all the ports of remaining memories are in use.

Sen_control
This is the first controller of the megatron block, which when enabled from the lc3 through the signal ena_lc3,the
controller gets activated and perform the following operations.
1. It sets the expose signal high and after ten clock cycles it sets capture signal high. Both these signals are
active for one clock cycle only.
2. It then sets read signal high for one clock cycle and reads red,green,blue data if valid is set high and stores it
in respective memories R,G,B which stands for Red,Green,Blue memories.
3. Step 2. is repeated 256 times to get different shades of red,blue,green colours. When done it sets hist_ena
signal high to enable the next controller which is histogram

Histogram
This is the second controller of the megatron block which when enabled from the sen_control controller through the
signal hist_ena, the controller gets activated and performs the following operations.
1. It resets M,N,O memories i.e. writes zeros to all the locations of the memories M,N,O.
2. It then reads R memory and counts the repeated number of shades in red pattern and stores it in respective
location of M memory.
3. Step 2. is repeated for G,B memories and stored in N,O memories.
4. Then it stores (R+G )/2 data in X memory and (R+B)/2 data in Y memory and (G+B)/2 data in Z memory in

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Lakshya User Manual

respective location.
5. Then it gives a done signal,which then enables mem_control.

Mem_control
This is the third controller of the megatron block which when enabled from the histogrm controller through the signal
done_his and an enable signal from lc3 through ena_fifo_lc3 , the controller gets activated and performs the following
operations.
1. It reads the X,Y,Z memories and stores it in SRAM 1024x8
2. It repeats the above step, 256 times to read all the locations of the memories X,Y,Z.
3. It then gives a done_ff signal to enable control_mem controller.

Control_mem
This is the fourth controller of the megatron block which when enabled from the Mem_control controller through the
signal done_ff and an enable signal from lc3 through ena_fi_cont_mem_lc3, the controller gets activated and
performs the following operations.
1. It reads 3 consecutive locations of the SRAM 1024x8 and averages it and stores it in memory 256x8.
2. It repeats the above process until the end of memory.

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Chapter -DFT

4 - DFT
Lakshya DFT implementation consists of ATPG and PBIST modules. ATPG is used to test core logic and PBIST is
used to check SRAM modules post manufacturing.

ATPG
ATPG (Automatic Test Program Generation) involves designing with scan enabled registers that enable testing of core
logic with scan-chains. Lakshya has two scan chains to one each to test core logic controlled by two functional clocks.
Below diagram shows interaction between scan_clock and functional clocks.

sys_clk
clk Core
scan_clk logic

test_mode

rclk Core
sys_rclk logic

PBIST
PBIST (Programmable Built-in Self Test) is a DFT technique used to test pre-designed blocks like SRAM. This
technique requires a on-board controller that when in test mode, can write and read to each memory to check it's
functionality. Once the check is completed, controller outputs a pass/fail state on one of the configured output pins of
the chip to show the status.
PBIST implementation in Lakshya is based on paper “FSM-Based Programmable Memory BIST with Macro
Command”. See Appendix for more details.

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Lakshya User Manual

5 - Directory structure for the project

Home
Homedirectory/
directory/

lakshya
lakshya

Run directory run1

run1 run2
run2

PD
PD run1
PV
run1
PV STA
STA

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Chapter -Appendix

6 - Appendix

FSM-Based Programmable Memory BIST with Macro Command

Proceedings of the 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT’05)
FSM_based_programmable_memory_BIST.pdf

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