CD4094BMS

CMOS 8-Stage Shift-and-Store

December 1992
Bus Register

Features Pinout
• High Voltage Type (20V Rating) CD4094BMS
TOP VIEW
• 3-State Parallel Outputs for Connection to Common
Bus
• Separate Serial Outputs Synchronous to Both Positive
and Negative Clock Edges for Cascading STROBE 1 16 VDD
• Medium Speed Operation - 5MHz at 10V (typ) DATA 2 15 OUTPUT ENABLE

• Standardized Symmetrical Output Characteristics CLOCK 3 14 Q5

• 100% Tested for Quiescent Current at 20V Q1 4 13 Q6

• Maximum Input Current of 1µA at 18V Over Full Pack- Q2 5 12 Q7

age Temperature Range; 100nA at 18V and +25oC Q3 6 11 Q8
• Noise Margin (Over Full Package/Temperature Range) Q4 7 10 Q’S
- 1V at VDD = 5V VSS 8 9 QS
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices” Functional Diagram
Applications SERIAL
OUTPUTS
• Serial-to-Parallel Data Conversion DATA 2 10 Q’S
8-STAGE
• Remote Control Holding Register CLOCK 3 SHIFT 9 QS
• Dual-Rank Shift, Hold, and Bus Applications REGISTER

Description
CD4094BMS is a 8-stage serial shift register having a storage STROBE 1
8-BIT
latch associated with each stage for strobing data from the serial STORAGE
REGISTER
input to parallel buffered 3-state outputs. The parallel outputs
may be connected directly to common bus lines. Data is shifted
on positive clock transitions. The data in each shift register stage
OUTPUT
is transferred to the storage register when the STROBE input is ENABLE 15 VDD = 16
3-STATE
high. Data in the storage register appears at the outputs when- OUTPUTS VSS = 8
ever the OUTPUT-ENABLE signal is high.
Two serial outputs are available for cascading a number of
CD4094BMS devices. Data is available at the QS serial output
terminal on positive clock edges to allow for high-speed opera- PARALLEL OUTPUTS Q1 - Q8
tion in cascaded systems in which the clock rise time is fast. The
same serial information, available at the Q’S terminal on the next (TERMINALS 4, 5, 6, 7, 14, 13, 12, 11, RESPECTIVELY)
negative clock edge, provides a means for cascading
CD4094BMS devices when the clock rise time is slow.
The CD4094BMS is supplied in these 16 lead outline packages:

Braze Seal DIP H4X

Frit Seal DIP H1F
Ceramic Flatpack H6W

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 3194
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
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 Specifications CD4094BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
(Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Maximum Package Power Dissipation (PD) at +125 C o

Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
Package Types D, F, K, H For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Linearity at 12mW/oC to 200mW
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for For TA = Full Package Temperature Range (All Package Types)
10s Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP A LIMITS
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 10 µA
2 +125 C o
- 1000 µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VOL < V
VDD = 20V, VIN = VDD or GND 7 +25oC VDD/2 VDD/2

VDD = 18V, VIN = VDD or GND 8A +125oC

VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2)
Input Voltage High VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
(Note 2)
Input Voltage Low VIL VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC - 4 V
(Note 2) VOL < 1.5V
Input Voltage High VIH VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC 11 - V
(Note 2) VOL < 1.5V
Tri-State Output IOZL VIN = VDD or GND VDD = 20V 1 +25oC -0.4 - µA
Leakage VOUT = 0V 2 +125oC -12 - µA
VDD = 18V 3 -55oC -0.4 - µA
Tri-State Output IOZH VIN = VDD or GND VDD = 20V 1 +25oC - 0.4 µA
Leakage VOUT = VDD 2 +125oC - 12 µA
VDD = 18V 3 -55oC - 0.4 µA
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented. is 0.050V max.
2. Go/No Go test with limits applied to inputs.

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 Specifications CD4094BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS SUBGROUPS TEMPERATURE MIN MAX UNITS
Propagation Delay TPHL1 VDD = 5V, VIN = VDD or GND 9 +25oC - 600 ns
Clock to Serial Output QS TPLH1 (Note 1, 2)
10, 11 +125oC, -55oC - 810 ns
Propagation Delay TPHL2 VDD = 5V, VIN = VDD or GND 9 +25oC - 460 ns
Clock to Serial Output TPLH2 (Note 1, 2)
10, 11 +125oC, -55oC - 621 ns
Q’S
Propagation Delay TPHL3 VDD = 5V, VIN = VDD or GND 9 +25oC - 840 ns
Clock to Parallel Output TPLH3 (Note 1, 2)
10, 11 +125oC, -55oC - 1134 ns
Propagation Delay TPHL4 VDD = 5V, VIN = VDD or GND 9 +25oC - 580 ns
Strobe to Parallel Output TPLH4 (Note 1, 2) o o
10, 11 +125 C, -55 C - 783 ns
o
Propagation Delay TPHZ VDD = 5V, VIN = VDD or GND 9 +25 C - 280 ns
Output Enable to Parallel TPZH (Note 2, 3)
10, 11 +125oC, -55oC - 378 ns
Output
Propagation Delay TPLZ VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
Output Enable to Parallel TPZL (Note 2, 3)
10, 11 +125oC, -55oC - 270 ns
Output
Transition Time TTHL VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
TTLH (Note 1, 2)
10, 11 +125oC, -55oC - 270 ns
Maximum Clock Input FCL VDD = 5V, VIN = VDD or GND 9 +25oC 1.25 - MHz
Frequency (Note 1, 2)
10, 11 +125oC, -55oC .93 - MHz
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
3. CL = 50pF, RL = 1K, Input TR, TF < 20ns.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA
+125oC - 150 µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA
+125oC - 300 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA
+125oC - 600 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, 4.95 - V
-55oC
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, 9.95 - V
-55oC
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA

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 Specifications CD4094BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
o
-55 C 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
oC
-55 - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.1 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55o C - -2.6 mA
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
oC
-55 - - mA
Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, - 3 V
-55oC
Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, 7 - V
-55oC
Propagation Delay TPHL1 VDD = 10V 1, 2, 3 +25oC - 250 ns
Clock to Serial Output Qs TPLH1
VDD = 15V 1, 2, 3 +25oC - 190 ns
Propagation Delay TPHL2 VDD = 10V 1, 2, 3 +25oC - 220 ns
Clock to Serial Output Q’s TPLH2 oC
VDD = 15V 1, 2, 3 +25 - 150 ns
Propagation Delay TPHL3 VDD = 10V 1, 2, 3 +25oC - 390 ns
Clock to Parallel Output TPLH3 o
VDD = 15V 1, 2, 3 +25 C - 270 ns
oC
Propagation Delay TPHL4 VDD = 10V 1, 2, 3 +25 - 290 ns
Strobe to Parallel Output TPLH4
VDD = 15V 1, 2, 3 +25oC - 200 ns
oC
Propagation Delay TPHZ VDD = 10V 1, 2, 4 +25 - 120 ns
Output Enable to Parallel TPZH
VDD = 15V 1, 2, 4 +25oC - 90 ns
Output
Propagation Delay TPLZ VDD = 10V 1, 2, 4 +25oC - 100 ns
Output Enable to Parallel TPZL
VDD = 15V 1, 2, 4 +25oC - 80 ns
Output
Transition Time TTLH VDD = 10V 1, 2, 3 +25oC - 100 ns
TTHL oC
VDD = 15V 1, 2, 3 +25 - 80 ns
Maximum Clock Input FCL VDD = 10V 1, 2, 3 +25oC 2.5 - MHz
Frequency
VDD = 15V 1, 2, 3 +25oC 3 - MHz
Minimum Data Setup TS VDD = 5V 1, 2, 3 +25oC - 125 ns
Time
VDD = 10V 1, 2, 3 +25oC - 55 ns
VDD = 15V 1, 2, 3 +25oC - 35 ns
Maximum Clock Input TRCL VDD = 5V 1, 2, 3, 5 +25oC - 15 µs
Rise and Fall Time TFCL
VDD = 10V 1, 2, 3, 5 +25oC - 5 µs
VDD = 15V 1, 2, 3, 5 +25oC - 5 µs
Minimum Clock Pulse TW VDD = 5V 1, 2, 3 +25oC - 200 ns
Width
VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 83 ns

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 Specifications CD4094BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Minimum Strobe Pulse TW VDD = 5V 1, 2, 3 +25oC - 200 ns
Width o
VDD = 10V 1, 2, 3 +25 C - 80 ns
VDD = 15V 1, 2, 3 +25oC - 70 ns
oC
Input Capacitance CIN Any Input 1, 2 +25 - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V
Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V
Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

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 Specifications CD4094BMS

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

MIL-STD-883
CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
Static Burn-In 1 4 - 7, 9 - 14 1 - 3, 8, 15 16
(Note 1)
Static Burn-In 2 4 - 7, 9 - 14 8 1 - 3, 15, 16
(Note 1)
Dynamic Burn- - 8 1, 15, 16 4 - 7, 9 - 14 3 2
In (Note 1)
Irradiation 4 - 7, 9 - 14 8 1 - 3, 15, 16
(Note 2)
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V

7-1088
 CD4094BMS

SERIAL
CL
IN p SERIAL
* OUT
2 D Q D Q D Q 10
n
CL CL CL Q’S
1 2 8
CL CL CL Q CL
CL

p
p n
CLOCK n
* TR TR
STAGES
TR SERIAL
3 CL 3-7 CL
OUT
p
STROBE CL
9
n
* TR QS
1 TR TR LATCH
TR 2 TR
TR LATCH
OUTPUT LATCH TR
* VDD
8
ENABLE 1
*
15

3-STATE
1 3- 3- VSS
STATE STATE
2 8 * ALL INPUTS
PROTECTED BY
p n CMOS PROTECTION
NETWORK
VDD VSS

4 5 6 7 14 13 12 11

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8

FIGURE 1. LOGIC DIAGRAM

TRUTH TABLE

PARALLEL OUTPUTS SERIAL OUTPUTS

OUTPUT
CL∆ ENABLE STROBE DATA Q1 QN QS* Q’S
0 X X OC OC Q7 NC
0 X X OC OC NC Q7
1 0 X NC NC Q7 NC
1 1 0 0 QN-1 Q7 NC
1 1 1 1 QN-1 Q7 NC
1 1 1 NC NC NC Q7
∆ = Level Change Logic 1 = High
X = Don’t Care Logic 0 = Low
NC = No Change
OC = Open Circuit
* At the positive clock edge information in the 7th shift register stage is transferred to the 8th register stage
and the QS output

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 CD4094BMS

Typical Performance Characteristics

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

30 15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25 12.5

20 10.0

10V
15 7.5
10V

10 5.0

5 2.5
5V 5V

0 5 10 15 0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
TRANSFER CHARACTERISTICS CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-15 -10 -5 0 -15 -10 -5 0
0 0
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10 -5

-15

-10V -10V
-20 -10

-25

-15V -15V
-30 -15

FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS CHARACTERISTICS

300
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

250

SUPPLY VOLTAGE (VDD) = 5V

400 200

SUPPLY VOLTAGE (VDD) = 5V

300 150
10V

200 100
10V
15V
100 15V 50

0 20 40 60 80 100 0 20 40 60 80 100
LOAD CAPACITANCE (CL) (pF) LOAD CAPACITANCE (CL) (pF)

FIGURE 6. CLOCK-TO-SERIAL OUTPUT QS PROPAGATION FIGURE 7. CLOCK-TO-SERIAL OUTPUT Q’S PROPAGATION

DELAY vs CL DELAY vs CL

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 CD4094BMS

Typical Performance Characteristics (Continued)

600

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

500

400 SUPPLY VOLTAGE (VDD) = 5V 400

SUPPLY VOLTAGE (VDD) = 5V

300 300

10V
200 200
10V
15V
100 100
15V

0 20 40 60 80 100 0 20 40 60 80 100
LOAD CAPACITANCE (CL) (pF) LOAD CAPACITANCE (CL) (pF)
FIGURE 8. CLOCK-TO-PARALLEL OUTPUT PROPAGATION FIGURE 9. STROBE-TO-PARALLEL OUTPUT PROPAGATION
DELAY vs CL DELAY vs CL
300
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

tPHL
TRANSITION TIME (tTHL, tTLH) (ns)
250
tPLH
SUPPLY VOLTAGE (VDD) = 5V
200 200
15V
15V
10V
10V
5V SUPPLY VOLTAGE (VDD) = 5V
150 150

100 100
10V
5V
50 50

0
0 20 40 60 80 100 0 20 40 60 80 100
LOAD CAPACITANCE (CL) (pF) LOAD CAPACITANCE (CL) (pF)

FIGURE 10. OUTPUT ENABLE-TO-PARALLEL OUTPUT FIGURE 11. TYPICAL TRANSITION TIME vs LOAD
PROPAGATION DELAY vs CL CAPACITANCE
MAXIMUM CLOCK FREQUENCY (fCL MAX) (MHz)

POWER DISSIPATION /PACKAGE (PD) (µW)

AMBIENT TEMPERATURE (TA) = +25oC

106
AMBIENT TEMPERATURE (TA) = +25oC ALTERNATING 0 AND 1 PATTERN
OUTPUT ENABLE HIGH
15 LOAD CAPACITANCE (CL) = 50PF
STROBE HIGH EVERY 8 CLOCK PULSES
105
SUPPLY VOLTAGE (VDD) = 15V

10 104

10V
103 10V
5V
5
102
CL = 50pF
CL = 15pF
10
0 5 10 15 20 1 10 102 103 104 105
SUPPLY VOLTAGE (VDD) (V) INPUT FREQUENCY (fI) (kHz)

FIGURE 12. TYPICAL MAXIMUM-CLOCK-FREQUENCY vs FIGURE 13. DYNAMIC POWER DISSIPATION vs INPUT CLOCK
SUPPLY VOLTAGE FREQUENCY

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 CD4094BMS

CLOCK

DATA IN

STROBE

OUTPUT
ENABLE

INTERNAL Q1

3 - STATE
3
OUTPUT Q1 STATE

INTERNAL Q7
3 - STATE
3

OUTPUT Q7 STATE

SERIAL QS
OUTPUT

SERIAL Q’S
OUTPUT

FIGURE 14. TIMING DIAGRAM

DIGITALLY CONTROLLED
EQUIPMENT DIGITALLY CONTROLLED DIGITALLY CONTROLLED
(REQUIRES CONTINUOUS EQUIPMENT EQUIPMENT
DIGITAL CONTROL)

D Q’S D QS D
CD4094BMS CD4094BMS CD4094BMS

STROBE CLOCK STROBE CLOCK STROBE CLOCK

CONTROL
AND
SYNC
CIRCUITRY

DATA CLOCK

FROM REMOTE
CONTROL PANEL

FIGURE 15. REMOTE CONTROL HOLDING REGISTER

7-1092
 CD4094BMS

Chip Dimensions and Pad Layout

Dimensions in parenthesis are in millimeters and are

derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office Headquarters

NORTH AMERICA EUROPE ASIA
Intersil Corporation Intersil SA Intersil (Taiwan) Ltd.
P. O. Box 883, Mail Stop 53-204 Mercure Center Taiwan Limited
Melbourne, FL 32902 100, Rue de la Fusee 7F-6, No. 101 Fu Hsing North Road
TEL: (321) 724-7000 1130 Brussels, Belgium Taipei, Taiwan
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FAX: (32) 2.724.22.05 TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029

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