Proworx 32: Ladder Logic Block Library

31007523 8/2010
ProWORX 32
Ladder Logic Block Library
8/2010
31007523.01
www.schneider-electric.com
The information provided in this documentation contains general descriptions and/or
technical characteristics of the performance of the products contained herein. This
documentation is not intended as a substitute for and is not to be used for
determining suitability or reliability of these products for specific user applications. It
is the duty of any such user or integrator to perform the appropriate and complete
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© 2010 Schneider Electric. All rights reserved.
2 31007523 8/2010
Table of Contents
Safety Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
About the Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Part I General Information . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 1 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Parameter Assignment of Instuctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Chapter 2 Instruction Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Instruction Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ASCII Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Counters and Timers Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Fast I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Loadable DX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Matrix Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Skips/Specials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Special Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Coils, Contacts, and Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Chapter 3 Closed Loop Control / Analog Values . . . . . . . . . . . . . . 43
Closed Loop Control / Analog Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PCFL Subfunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
A PID Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PID2 Level Control Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Chapter 4 Formatting Messages for ASCII READ/WRIT Operations 57
Formatting Messages for ASCII READ/WRIT Operations . . . . . . . . . . . . 58
Format Specifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Special Set-up Considerations for Control/Monitor Signals Format . . . . . 62
Chapter 5 Coils, Contacts, and Interconnects. . . . . . . . . . . . . . . . . 65
Coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Interconnects (Shorts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Chapter 6 Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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Chapter 7 Subroutine Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Subroutine Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Chapter 8 Installation of DX Loadables. . . . . . . . . . . . . . . . . . . . . . . 75
Installation of DX Loadables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Part II Instruction Descriptions (A to D) . . . . . . . . . . . . . . . 77
Chapter 9 1X3X - Input Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Chapter 10 AD16: Ad 16 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Chapter 11 ADD: Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Chapter 12 AND: Logical And . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Chapter 13 BCD: Binary to Binary Code . . . . . . . . . . . . . . . . . . . . . . . 91
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Chapter 14 BLKM: Block Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Chapter 15 BLKT: Block to Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Chapter 16 BMDI: Block Move with Interrupts Disabled . . . . . . . . . . 101
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Chapter 17 BROT: Bit Rotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Chapter 18 CALL: Activate Immediate or Deferred DX Function . . . 107
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
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Chapter 19 CANT - Interpret Coils, Contacts, Timers, Counters, and
the SUB Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Chapter 20 CCPF - Configure Cam Profile with Variable Instruments 121
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Chapter 21 CCPV - Configure Cam Profile with Variable Increments 125
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Chapter 22 CFGC - Configure Coordinated Set. . . . . . . . . . . . . . . . . 129
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Chapter 23 CFGF - Configure Follower Set . . . . . . . . . . . . . . . . . . . . 133
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Chapter 24 CFGI – Configure Imaginary Axis . . . . . . . . . . . . . . . . . . 137
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Chapter 25 CFGR – Configure Remote Axis . . . . . . . . . . . . . . . . . . . 141
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Chapter 26 CFGS – Configure SERCOS Axis . . . . . . . . . . . . . . . . . . 145
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Chapter 27 CHS: Configure Hot Standby. . . . . . . . . . . . . . . . . . . . . . 149
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Chapter 28 CKSM: Check Sum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Chapter 29 CMPR: Compare Register . . . . . . . . . . . . . . . . . . . . . . . . 159
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Chapter 30 Coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
General Usage Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
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Chapter 31 COMM - ASCII Communications Function . . . . . . . . . . . 167
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Chapter 32 COMP: Complement a Matrix . . . . . . . . . . . . . . . . . . . . . . 171
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Chapter 33 Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Chapter 34 CONV - Convert Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Chapter 35 CTIF - Counter, Timer, and Interrupt Function . . . . . . . . 185
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Chapter 36 DCTR: Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Chapter 37 DIOH: Distributed I/O Health . . . . . . . . . . . . . . . . . . . . . . . 197
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Chapter 38 DISA - Disabled Discrete Monitor . . . . . . . . . . . . . . . . . . 201
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Chapter 39 DIV: Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Chapter 40 DLOG: Data Logging for PCMCIA Read/Write Support . 211
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Run Time Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Chapter 41 DMTH - Double Precision Math. . . . . . . . . . . . . . . . . . . . . 217
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Chapter 42 DRUM: DRUM Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . 225
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
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Chapter 43 DV16: Divide 16 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Part III Instruction Descriptions (E) . . . . . . . . . . . . . . . . . . . 237
Chapter 44 EARS - Event/Alarm Recording System . . . . . . . . . . . . . 239
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Chapter 45 EMTH: Extended Math . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Floating Point EMTH Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Chapter 46 EMTH-ADDDP: Double Precision Addition . . . . . . . . . . 253
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Chapter 47 EMTH-ADDFP: Floating Point Addition . . . . . . . . . . . . . 259
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Chapter 48 EMTH-ADDIF: Integer + Floating Point Addition . . . . . . 263
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Chapter 49 EMTH-ANLOG: Base 10 Antilogarithm . . . . . . . . . . . . . . 267
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Chapter 50 EMTH-ARCOS: Floating Point Arc Cosine of an Angle
(in Radians) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Chapter 51 EMTH-ARSIN: Floating Point Arcsine of an Angle (in
Radians). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
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Chapter 52 EMTH-ARTAN: Floating Point Arc Tangent of an Angle
(in Radians) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Chapter 53 EMTH-CHSIN: Changing the Sign of a Floating Point
Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Chapter 54 EMTH-CMPFP: Floating Point Comparison. . . . . . . . . . . 293
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Chapter 55 EMTH-CMPIF: Integer-Floating Point Comparison . . . . . 299
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Chapter 56 EMTH-CNVDR: Floating Point Conversion of Degrees to
Radians . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Chapter 57 EMTH-CNVFI: Floating Point to Integer Conversion . . . 311
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Runtime Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Chapter 58 EMTH-CNVIF: Integer to Floating Point Conversion . . . 317
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Runtime Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Chapter 59 EMTH-CNVRD: Floating Point Conversion of Radians to
Degrees. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Chapter 60 EMTH-COS: Floating Point Cosine of an Angle (in
Radians) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
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Chapter 61 EMTH-DIVDP: Double Precision Division. . . . . . . . . . . . 333
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Runtime Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Chapter 62 EMTH-DIVFI: Floating Point Divided by Integer . . . . . . . 339
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Chapter 63 EMTH-DIVFP: Floating Point Division. . . . . . . . . . . . . . . 343
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Chapter 64 EMTH-DIVIF: Integer Divided by Floating Point. . . . . . . 347
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Chapter 65 EMTH-ERLOG: Floating Point Error Report Log . . . . . . 351
Representation: EMTH - ERLOG - Floating Point Math - Error Report Log 353
Chapter 66 EMTH-EXP: Floating Point Exponential Function . . . . . 357
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Chapter 67 EMTH-LNFP: Floating Point Natural Logarithm . . . . . . . 363
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Chapter 68 EMTH-LOG: Base 10 Logarithm . . . . . . . . . . . . . . . . . . . 369
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Chapter 69 EMTH-LOGFP: Floating Point Common Logarithm. . . . 375
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Chapter 70 EMTH-MULDP: Double Precision Multiplication . . . . . . 381
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
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Chapter 71 EMTH-MULFP: Floating Point Multiplication. . . . . . . . . . 387
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Chapter 72 EMTH-MULIF: Integer x Floating Point Multiplication . . 391
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Chapter 73 EMTH-PI: Load the Floating Point Value of "Pi" . . . . . . . 397
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Chapter 74 EMTH-POW: Raising a Floating Point Number to an
Integer Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Representation: EMTH - POW - Raising a Floating Point Number to an
Integer Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Chapter 75 EMTH-SINE: Floating Point Sine of an Angle (in
Radians) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Representation: EMTH - SINE - Floating Point Math - Sine of an Angle (in
Radians) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Chapter 76 EMTH-SQRFP: Floating Point Square Root. . . . . . . . . . . 413
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Chapter 77 EMTH-SQRT: Floating Point Square Root . . . . . . . . . . . . 419
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Chapter 78 EMTH-SQRTP: Process Square Root. . . . . . . . . . . . . . . . 425
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Chapter 79 EMTH-SUBDP: Double Precision Subtraction . . . . . . . . 431
Representation: EMTH - SUBDP - Double Precision Math - Subtraction 433
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Chapter 80 EMTH-SUBFI: Floating Point - Integer Subtraction . . . . 437
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Chapter 81 EMTH-SUBFP: Floating Point Subtraction . . . . . . . . . . . 443
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Chapter 82 EMTH-SUBIF: Integer - Floating Point Subtraction . . . . 449
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
Chapter 83 EMTH-TAN: Floating Point Tangent of an Angle (in
Radians). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Chapter 84 ESI: Support of the ESI Module. . . . . . . . . . . . . . . . . . . . 457
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
READ ASCII Message (Subfunction 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
WRITE ASCII Message (Subfunction 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 467
GET DATA (Subfunction 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
PUT DATA (Subfunction 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
ABORT (Middle Input ON). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Run Time Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Chapter 85 EUCA: Engineering Unit Conversion and Alarms . . . . . 475
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Part IV Instruction Descriptions (F to N) . . . . . . . . . . . . . . . 487
Chapter 86 FIN: First In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
Chapter 87 FOUT: First Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
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Chapter 88 FTOI: Floating Point to Integer . . . . . . . . . . . . . . . . . . . . . 499
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Chapter 89 GD92 - Gas Flow Function Block . . . . . . . . . . . . . . . . . . . 503
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Parameter Description - Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Parameter Description - Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Parameter Description - Optional Outputs . . . . . . . . . . . . . . . . . . . . . . . . 514
Chapter 90 GFNX AGA#3 ‘85 and NX19 ‘68 Gas Flow Function Block 515
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Chapter 91 GG92 AGA #3 1992 Gross Method Gas Flow Function
Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Chapter 92 GM92 AGA #3 and #8 1992 Detail Method Gas Flow
Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Chapter 93 G392 AGA #3 1992 Gas Flow Function Block . . . . . . . . . 553
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
Chapter 94 HLTH: History and Status Matrices . . . . . . . . . . . . . . . . . 565
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Parameter Description Top Node (History Matrix) . . . . . . . . . . . . . . . . . . 569
Parameter Description Middle Node (Status Matrix) . . . . . . . . . . . . . . . . 574
Parameter Description Bottom Node (Length). . . . . . . . . . . . . . . . . . . . . 578
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Chapter 95 HSBY - Hot Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
Representation: HSBY - Hot Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
Parameter Description Top Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
Parameter Description Middle Node: HSBY - Hot Standby. . . . . . . . . . . . 584
Chapter 96 IBKR: Indirect Block Read . . . . . . . . . . . . . . . . . . . . . . . . 585
Representation: IBKR - Indirect Block Read . . . . . . . . . . . . . . . . . . . . . . . 587
Chapter 97 IBKW: Indirect Block Write . . . . . . . . . . . . . . . . . . . . . . . 589
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
Chapter 98 ICMP: Input Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Representation: ICMP - Input Compare . . . . . . . . . . . . . . . . . . . . . . . . . . 595
Cascaded DRUM/ICMP Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
Chapter 99 ID: Interrupt Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Chapter 100 IE: Interrupt Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Chapter 101 IMIO: Immediate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Run Time Error Handling: IMIO - Immediate I/O . . . . . . . . . . . . . . . . . . . . 612
Chapter 102 IMOD: Interrupt Module Instruction . . . . . . . . . . . . . . . . 613
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Chapter 103 INDX – Immediate Incremental Move . . . . . . . . . . . . . . . 621
Parameters Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
Chapter 104 ITMR: Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
Chapter 105 ITOF: Integer to Floating Point . . . . . . . . . . . . . . . . . . . . 631
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
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Chapter 106 JOGS – JOG Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Chapter 107 JSR: Jump to Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . 639
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Chapter 108 LAB: Label for a Subroutine . . . . . . . . . . . . . . . . . . . . . . . 643
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Chapter 109 LOAD: Load Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Chapter 110 MAP3: MAP Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . 651
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Chapter 111 MATH - Integer Operations . . . . . . . . . . . . . . . . . . . . . . . . 659
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Chapter 112 MBIT: Modify Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Chapter 113 MBUS: MBUS Transaction . . . . . . . . . . . . . . . . . . . . . . . . 671
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
The MBUS Get Statistics Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
Chapter 114 MMFB – Modicon Motion Framework Bits Block . . . . . . 681
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
Chapter 115 MMFE – Modicon Motion Framework Extended
Parameters Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Chapter 116 MMFI – Modicon Motion Framework Initialize Block . . . 689
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Chapter 117 MMFS – Modicon Motion Framework Subroutine Block 695
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
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Chapter 118 MOVE – Absolute Move . . . . . . . . . . . . . . . . . . . . . . . . . . 699
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
Chapter 119 MRTM: Multi-Register Transfer Module . . . . . . . . . . . . . 703
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Chapter 120 MSPX (Seriplex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
Chapter 121 MSTR: Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
Write MSTR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
READ MSTR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Get Local Statistics MSTR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
Clear Local Statistics MSTR Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Write Global Data MSTR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
Read Global Data MSTR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
Get Remote Statistics MSTR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 732
Clear Remote Statistics MSTR Operation. . . . . . . . . . . . . . . . . . . . . . . . . 734
Peer Cop Health MSTR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
Reset Option Module MSTR Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 738
Read CTE (Config Extension Table) MSTR Operation . . . . . . . . . . . . . . . 740
Write CTE (Config Extension Table) MSTR Operation . . . . . . . . . . . . . . . 742
Modbus Plus Network Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
TCP/IP Ethernet Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
Run Time Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
Modbus Plus and SY/MAX Ethernet Error Codes . . . . . . . . . . . . . . . . . . . 751
SY/MAX-specific Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
TCP/IP Ethernet Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
CTE Error Codes for SY/MAX and TCP/IP Ethernet. . . . . . . . . . . . . . . . . 758
Chapter 122 MU16: Multiply 16 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
Chapter 123 MUL: Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
Chapter 124 NBIT: Bit Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
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Chapter 125 NCBT: Normally Closed Bit. . . . . . . . . . . . . . . . . . . . . . . . 771
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Chapter 126 NOBT: Normally Open Bit . . . . . . . . . . . . . . . . . . . . . . . . . 775
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
Chapter 127 NOL: Network Option Module for Lonworks . . . . . . . . . . 779
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
Part V Instruction Descriptions (O to Q) . . . . . . . . . . . . . . . 785
Chapter 128 OR: Logical OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Chapter 129 PCFL: Process Control Function Library . . . . . . . . . . . . 793
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
Chapter 130 PCFL-AIN: Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . 799
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
Chapter 131 PCFL-ALARM: Central Alarm Handler . . . . . . . . . . . . . . . 805
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
Chapter 132 PCFL-AOUT: Analog Output . . . . . . . . . . . . . . . . . . . . . . . 811
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
Chapter 133 PCFL-AVER: Average Weighted Inputs Calculate . . . . . 815
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
Chapter 134 PCFL-CALC: Calculated Preset Formula. . . . . . . . . . . . . 821
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
Chapter 135 PCFL-DELAY: Time Delay Queue. . . . . . . . . . . . . . . . . . . 827
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
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Chapter 136 PCFL-EQN: Formatted Equation Calculator. . . . . . . . . . 831
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
Chapter 137 PCFL-INTEG: Integrate Input at Specified Interval . . . . 837
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
Chapter 138 PCFL-KPID: Comprehensive ISA Non Interacting PID . 841
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Chapter 139 PCFL-LIMIT: Limiter for the Pv . . . . . . . . . . . . . . . . . . . . 847
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
Chapter 140 PCFL-LIMV: Velocity Limiter for Changes in the Pv . . . 851
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
Chapter 141 PCFL-LKUP: Look-up Table. . . . . . . . . . . . . . . . . . . . . . . 855
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
Chapter 142 PCFL-LLAG: First-order Lead/Lag Filter . . . . . . . . . . . . 861
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
Chapter 143 PCFL-MODE: Put Input in Auto or Manual Mode . . . . . . 865
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
Chapter 144 PCFL-ONOFF: ON/OFF Values for Deadband . . . . . . . . 869
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
Chapter 145 PCFL-PI: ISA Non Interacting PI . . . . . . . . . . . . . . . . . . . 873
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
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Chapter 146 PCFL-PID: PID Algorithms . . . . . . . . . . . . . . . . . . . . . . . . 879
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
Chapter 147 PCFL-RAMP: Ramp to Set Point at a Constant Rate . . . 885
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
Chapter 148 PCFL-RATE: Derivative Rate Calculation over a
Specified Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
Chapter 149 PCFL-RATIO: Four Station Ratio Controller . . . . . . . . . . 893
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
Chapter 150 PCFL-RMPLN: Logarithmic Ramp to Set Point . . . . . . . . 897
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899
Chapter 151 PCFL-SEL: Input Selection . . . . . . . . . . . . . . . . . . . . . . . . 901
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903
Chapter 152 PCFL-TOTAL: Totalizer for Metering Flow . . . . . . . . . . . 907
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
Chapter 153 PEER: PEER Transaction . . . . . . . . . . . . . . . . . . . . . . . . . 913
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
Chapter 154 PID2: Proportional Integral Derivative . . . . . . . . . . . . . . . 917
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
Run Time Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
18 31007523 8/2010
Part VI Instruction Descriptions (R to Z) . . . . . . . . . . . . . . . 929
Chapter 155 R --> T: Register to Table . . . . . . . . . . . . . . . . . . . . . . . . . 931
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
Chapter 156 RBIT: Reset Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Chapter 157 READ: Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Chapter 158 RET: Return from a Subroutine. . . . . . . . . . . . . . . . . . . . 945
Representation: RET - Return to Scheduled Logic . . . . . . . . . . . . . . . . . . 947
Chapter 159 RTTI - Register to Input Table . . . . . . . . . . . . . . . . . . . . . 949
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
Chapter 160 RTTO - Register to Output Table. . . . . . . . . . . . . . . . . . . 953
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
Chapter 161 RTU - Remote Terminal Unit . . . . . . . . . . . . . . . . . . . . . . 957
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
Chapter 162 SAVE: Save Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
Chapter 163 SBIT: Set Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
Chapter 164 SCIF: Sequential Control Interfaces . . . . . . . . . . . . . . . . 971
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
Chapter 165 SENS: Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
Chapter 166 Shorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
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Chapter 167 SKP - Skipping Networks . . . . . . . . . . . . . . . . . . . . . . . . . 983
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
Chapter 168 SRCH: Search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989
Chapter 169 STAT: Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
Description of the Status Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
Controller Status Words 1 - 11 for Quantum and Momentum . . . . . . . . . 1001
I/O Module Health Status Words 12 - 20 for Momentum . . . . . . . . . . . . . 1006
I/O Module Health Status Words 12 - 171 for Quantum . . . . . . . . . . . . . 1008
Communication Status Words 172 - 277 for Quantum . . . . . . . . . . . . . . 1010
Controller Status Words 1 - 11 for TSX Compact and Atrium . . . . . . . . . 1015
I/O Module Health Status Words 12 - 15 for TSX Compact. . . . . . . . . . . 1018
Global Health and Communications Retry Status Words 182 ... 184 for
TSX Compact. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
Chapter 170 SU16: Subtract 16 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
Chapter 171 SUB: Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
Chapter 172 SWAP - VME Bit Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
Chapter 173 TTR - Table to Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
Representation: TTR - Table to Register . . . . . . . . . . . . . . . . . . . . . . . . . 1039
Chapter 174 T --> R Table to Register . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
Chapter 175 T --> T: Table to Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
Chapter 176 T.01 Timer: One Hundredth of a Second Timer . . . . . . . 1047
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
20 31007523 8/2010
Chapter 177 T0.1 Timer: One Tenth Second Timer . . . . . . . . . . . . . . . 1051
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
Chapter 178 T1.0 Timer: One Second Timer . . . . . . . . . . . . . . . . . . . . 1055
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
Chapter 179 T1MS Timer: One Millisecond Timer. . . . . . . . . . . . . . . . 1059
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
Chapter 180 TBLK: Table to Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Chapter 181 TEST: Test of 2 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
Chapter 182 UCTR: Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
Chapter 183 VMER - VME Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
Chapter 184 VMEW - VME Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
Chapter 185 WRIT: Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
Chapter 186 XMIT - Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
XMIT Modbus Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
Chapter 187 XMIT Communication Block . . . . . . . . . . . . . . . . . . . . . . 1103
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
31007523 8/2010 21
Chapter 188 XMIT Port Status Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
Chapter 189 XMIT Conversion Block. . . . . . . . . . . . . . . . . . . . . . . . . . . 1123
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
Chapter 190 XMRD: Extended Memory Read . . . . . . . . . . . . . . . . . . . . 1131
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133
Chapter 191 XMWT: Extended Memory Write. . . . . . . . . . . . . . . . . . . . 1137
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139
Chapter 192 XOR: Exclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
22 31007523 8/2010
Safety Information
§
Important Information
NOTICE
Read these instructions carefully, and look at the equipment to become familiar with
the device before trying to install, operate, or maintain it. The following special
messages may appear throughout this documentation or on the equipment to warn
of potential hazards or to call attention to information that clarifies or simplifies a
procedure.
31007523 8/2010 23
PLEASE NOTE
Electrical equipment should be installed, operated, serviced, and maintained only by
qualified personnel. No responsibility is assumed by Schneider Electric for any
consequences arising out of the use of this material.
A qualified person is one who has skills and knowledge related to the construction
and operation of electrical equipment and the installation, and has received safety
training to recognize and avoid the hazards involved.
24 31007523 8/2010
About the Book
At a Glance
Document Scope
This documentation will help you configure the ladder logic instructions from
ProWORX 32.
Validity Note
This documentation is valid for ProWORX 32 under Microsoft Windows 98, Microsoft
Windows 2000, and Microsoft Windows NT 4.x.
NOTE: For additional up-to-date notes, please refer to the Read Me file in
ProWORX 32.
Related Documents
Title of Documentation Reference Number

XMIT Function Block User Guide 840 USE 113
Quantum Hot Standby Planning and Installation Guide 840 USE 106
Modbus Plus Network Planning and Installation Guide 890 USE 100
Quantum 140 ESI 062 10 ASCII Interface Module User Guide 840 USE 108
Modicon S980 MAP 3.0 Network Interface Controller User Guide GM-MAP3-001
You can download these technical publications and other technical information from
our website at www.schneider-electric.com.
User Comments
We welcome your comments about this document. You can reach us by e-mail at
[email protected].
31007523 8/2010 25
26 31007523 8/2010
General Information
31007523 8/2010
General Information
I
At a Glance
In this part you will find general information about the instruction groups and the use
of instructions.
What's in this Part?

This part contains the following chapters:
Chapter Chapter Name Page
1 Instructions 29
2 Instruction Groups 31
3 Closed Loop Control / Analog Values 43
4 Formatting Messages for ASCII READ/WRIT Operations 57
5 Coils, Contacts, and Interconnects 65
6 Interrupt Handling 71
7 Subroutine Handling 73
8 Installation of DX Loadables 75
31007523 8/2010 27
General Information
28 31007523 8/2010
Instructions
31007523 8/2010
Instructions
1
Parameter Assignment of Instuctions
General
Programming for electrical controls involves a user who implements Operational
Coded instructions in the form of visual objects organized in a recognizable ladder
form. The program objects designed, at the user level, is converted to computer
usable OP codes during the download process. the Op codes are decoded in the
CPU and acted upon by the controllers firmware functions to implement the desired
control.
Each instruction is composed of an operation, nodes required for the operation and
in- and outputs.
Parameter Assignment
Parameter assignment with the instruction DV16 as an example:
31007523 8/2010 29
Instructions
Operation
The operation determines which functionality is to be executed by the instruction,
e.g. shift register, conversion operations.
Nodes, In- and Outputs

The nodes and in- and outputs determines what the operation will be executed with.
30 31007523 8/2010
Instruction Groups
31007523 8/2010
Instruction Groups
2
Introduction
In this chapter you will find an overview of the instruction groups.
What's in this Chapter?

This chapter contains the following topics:
Topic Page
Instruction Groups 32
ASCII Functions 32
Counters and Timers Instructions 33
Fast I/O Instructions 34
Loadable DX 35
Math Instructions 36
Matrix Instructions 38
Miscellaneous 39
Move Instructions 40
Skips/Specials 41
Special Instructions 41
Coils, Contacts, and Interconnects 42
31007523 8/2010 31
Instruction Groups
Instruction Groups
General
All instructions are attached to one of the following groups.
z ASCII Functions (see page 32)
z Counters/Timers (see page 33)
z Fast I/O Instructions (see page 34)
z Loadable DX (see page 35)
z Math (see page 36)
z Matrix (see page 38)
z Miscellaneous (see page 39)
z Move (see page 40)
z Skips/Specials (see page 41)
z Special (see page 41)
z Coils, Contacts and Interconnects (see page 42)
ASCII Functions
ASCII Functions
This group provides the following instructions.
Instruction Meaning Available at PLC family

Quantum Compact Momentum Atrium
READ Read ASCII messages yes no no no
WRIT Write ASCII messages yes no no no
PLCs that support ASCII messaging use instructions called READ and WRIT to
handle the sending of messages to display devices and the receiving of messages
from input devices. These instructions provide the routines necessary for
communication between the ASCII message table in the PLC’s system memory and
an interface module at the remote I/O drops.
For further information, see Formatting Messages for ASCII READ/WRIT
Operations, page 57.
32 31007523 8/2010
Instruction Groups
Counters and Timers Instructions
Counters and Timers Instructions

The table shows the counters and timers instructions.

UCTR Counts up from 0 to a yes yes yes yes
preset value
DCTR Counts down from a yes yes yes yes
preset value to 0
T1.0 Timer that increments in yes yes yes yes
seconds
T0.1 Timer that increments in yes yes yes yes
tenths of a second
T.01 Timer that increments in yes yes yes yes
hundredths of a second
T1MS Timer that increments in yes yes yes yes
one millisecond (See note.)
NOTE: The T1MS instruction is available only on the B984-102, the Micro 311, 411,
512, and 612, and the Quantum 424 02.
31007523 8/2010 33
Instruction Groups
Fast I/O Instructions
Fast I/O Instructions

The following instructions are designed for a variety of functions known generally as
fast I/O updating.

BMDI Block move with interrupts yes yes no yes
disabled
ID Disable interrupt yes yes no yes
IE Enable interrupt yes yes no yes
IMIO Immediate I/O instruction yes yes no yes
IMOD Interrupt module yes no no yes
instruction
ITMR Interval timer interrupt no yes no yes
For more information, see Interrupt Handling, page 71.

NOTE: The fast I/O instructions are only available after configuring a CPU without
extension.
34 31007523 8/2010
Instruction Groups
Loadable DX
Loadable DX

CHS Hot standby (Quantum) yes no no no
DRUM DRUM sequenzer yes yes no yes
ESI Support of the ESI module yes no no no
140 ESI 062 10
EUCA Engineering unit yes yes no yes
conversion and alarms
HLTH History and status yes yes no yes
matrices
ICMP Input comparison yes yes no yes
MAP3 MAP 3 Transaction no no no no
MBUS MBUS Transaction no no no no
MRTM Multi-register transfer yes yes no yes
module
NOL Transfer to/from the NOL yes no no no
Module
PEER PEER Transaction no no no no
XMIT RS 232 Master Mode yes yes yes no
For more information, see Installation of DX Loadables, page 75.
31007523 8/2010 35
Instruction Groups
Math Instructions
Math Instructions
Two groups of instructions that support basic math operations are available. The first
group comprises four integer-based instructions: ADD, SUB, MUL and DIV.
The second group contains five comparable instructions, AD16, SU16, TEST, MU16
and DV16, that support signed and unsigned 16-bit math calculations and
comparisons.
Three additional instructions, ITOF, FTOI and BCD, are provided to convert the
formats of numerical values (from integer to floating point, floating point to integer,
binary to BCD and BCD to binary). Conversion operations are usful in expanded
math.
Integer Based Instructions

This part of the group provides the following instructions.

ADD Addition yes yes yes yes
DIV Division yes yes yes yes
MUL Multiplication yes yes yes yes
SUB Subtraction yes yes yes yes
36 31007523 8/2010
Instruction Groups
Comparable Instructions

AD16 Add 16 bit yes yes yes yes
DV16 Divide 16 bit yes yes yes yes
MU16 Multiply 16 bit yes yes yes yes
SU16 Subtract 16 bit yes yes yes yes
TEST Test of 2 values yes yes yes yes
Format Conversion

BCD Conversion from binary to yes yes yes yes
binary code or binary code
to binary
FTOI Conversion from floating yes yes yes yes
point to integer
ITOF Conversion from integer to yes yes yes yes
floating point
31007523 8/2010 37
Instruction Groups
Matrix Instructions
Matrix Instructions
A matrix is a sequence of data bits formed by consecutive 16-bit words or registers
derived from tables. DX matrix functions operate on bit patterns within tables.
Just as with move instructions, the minimum table length is 1 and the maximum table
length depends on the type of instruction you use and on the size of the CPU (24-
bit) in your PLC.
Groups of 16 discretes can also be placed in tables. The reference number used is
the first discrete in the group, and the other 15 are implied. The number of the first
discrete must be of the first of 16 type 000001, 100001, 000017, 100017, 000033,
100033, ... , etc..

AND Logical AND yes yes yes yes
BROT Bit rotate yes yes yes yes
CMPR Compare register yes yes yes yes
COMP Complement a matrix yes yes yes yes
MBIT Modify bit yes yes yes yes
NBIT Bit control yes yes no yes
NCBT Normally open bit yes yes no yes
NOBT Normally closed bit yes yes no yes
OR Logical OR yes yes yes yes
RBIT Reset bit yes yes no yes
SBIT Set bit yes yes no yes
SENS Sense yes yes yes yes
XOR Exclusive OR yes yes yes yes
38 31007523 8/2010
Instruction Groups
Miscellaneous
Miscellaneous

CKSM Check sum yes yes yes yes
DLOG Data Logging for PCMCIA no yes no no
Read/Write Support
EMTH Extended Math Functions yes yes yes yes
LOAD Load flash yes yes yes no
(CPU (CCC
434 12/53 960 x0/980
4 14 only) x0 only)
MSTR Master yes yes yes yes
SAVE Save flash yes yes yes no
(CPU (CCC
434 12/53 960 x0/980
4 14 only) x0 only)
SCIF Sequential control yes yes no yes
interfaces
XMRD Extended memory read yes no no yes
XMWT Extended memory write yes no no yes
31007523 8/2010 39
Instruction Groups
Move Instructions
Move Instructions

BLKM Block move yes yes yes yes
BLKT Table to block move yes yes yes yes
FIN First in yes yes yes yes
FOUT First out yes yes yes yes
IBKR Indirect block read yes yes no yes
IBKW Indirect block write yes yes no yes
R→T Register to tabel move yes yes yes yes
SRCH Search table yes yes yes yes
T→R Table to register move yes yes yes yes
T→T Table to table move yes yes yes yes
TBLK Table to block move yes yes yes yes
40 31007523 8/2010
Instruction Groups
Skips/Specials
Skips/Specials
DANGER
UNINTENTIONAL I/O SKIPPING
Take precaution when using the SKP· instruction. If inputs and outputs that
normally effect control are unintentionally skipped (or not skipped), the result can
create hazardous conditions for personnel and application equipment.
Failure to follow these instructions will result in death or serious injury.

JSR Jump to subroutine yes yes yes yes
LAB Label for a subroutine yes yes yes yes
RET Return from a subroutine yes yes yes yes
SKPC Skip (constant) yes yes yes yes
SKPR Skip (register) yes yes yes yes
The SKP instruction is a standard instruction in all PLCs. It should be used with
caution.
Special Instructions
Special Instructions
These instructions are used in special situations to measure statistical events on the
overall logic system or create special loop control situations.

DIOH Distributed I/O health yes no no yes
PCFL Process control function yes yes no yes
library
PID2 Proportional integral yes yes yes yes
derivative
STAT Status yes yes yes yes
31007523 8/2010 41
Instruction Groups
Coils, Contacts, and Interconnects

Coils, contacts, and interconnects are available at all PLC families.
z normal coil
z memory-retentive, or latched, coil
z normally open (N.O.) contact
z normally closed (N.C.) contact
z positive transitional (P.T.) contact
z negative transitional (N.T.) contact
z horizontal short
z vertical short
42 31007523 8/2010
Closed Loop Control / Analog Values
31007523 8/2010
Closed Loop Control /

Analog Values
3
Introduction
This chapter provides general information about configuring closed loop control and
using analog values.

Topic Page
Closed Loop Control / Analog Values 44
PCFL Subfunctions 45
A PID Example 49
PID2 Level Control Example 53
31007523 8/2010 43
General
An analog closed loop control system is one in which the deviation from an ideal
process condition is measured, analyzed and adjusted in an attempt to obtain and
maintain zero error in the process condition. Provided with the Enhanced Instruction
Set is a proportional-integral-derivative function block called PID2, which allows you
to establish closed loop (or negative feedback) control in ladder logic.
Definition of Set Point and Process Variable

The desired (zero error) control point, which you will define in the PID2 block, is
called the set point (SP). The conditional measurement taken against SP is called
the process variable (PV). The difference between the SP and the PV is the
deviation or error (E). E is fed into a control calculation that produces a manipulated
variable (Mv) used to adjust the process so that PV = SP (and, therefore, E = 0).
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PCFL Subfunctions
General
The PCFL instruction gives you access to a library of process control functions
utilizing analog values.
PCFL operations fall into three major categories.
z advanced calculations
z signal processing
z regulatory control
Advanced Calculations
Advanced calculations are used for general mathematical purposes and are not
limited to process control applications. With advanced calculations, you can create
custom signal processing algorithms, derive states of the controlled process, derive
statistical measures of the process, etc.
Simple math routines have already been offered in the EMTH instruction. The
calculation capability included in PCFL is a textual equation calculator for writing
custom equations instead of programming a series of math operations one by one.
Signal Processing
Signal processing functions are used to manipulate process and derived process
signals. They can do this in a variety of ways; they linearize, filter, delay and
otherwise modify a signal. This category would include functions such as an analog
input/output, limiters, lead/lag and ramp generators.
Regulatory Control
Regulatory functions perform closed loop control in a variety of applications.
Typically, this is a PID (proportional integral derivative) negative feedback control
loop. The PID functions in PCFL offer varying degrees of functionality. Function PID
has the same general functionality as the PID2 instruction but uses floating point
math and represents some options differently. PID is beneficial in cases where PID2
is not suitable because of numerical concerns such as round-off.
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Explanation of Formula Elements

Meaning of formula elements in the following formulas:
Formula Elements Meaning

Y Manipulated variable output
YP Proportional part of the calculation
YI Integral part of the calculation
YD Derivative part of the calculation
Bias Constant added to input
BT Bumpless transfer register
SP Set point
KP Proportional gain
Dt Time since last solve
TI Integral time constant
TD Derivative time constant
TD1 Derivative time lag
XD Error term, deviation
XD_1 Previous error term
X Process input
X_1 Previous process input
General Equations
The following general equations are valid.
Equation Condition/Requirement
Integral bit ON
Integral bit OFF
High/low limits
with
Gain reduction
Gain reduction zone not used
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Proportional Calculations
The following equations are valid.
Proportional bit ON
Integral Calculation
Integral bit ON
Derivative Calculation
Base derivative or PV
Derivative bit ON
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Structure Diagram
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A PID Example
Description
This example illustrates how a typical PID loop could be configured using PCFL
function PID. The calculation begins with the AIN function, which takes raw input
simulated to cause the output to run between approximately 20 and 22 when the
engineering unit scale is set to 0 ... 100.
984LL Diagram
The process variable over time should look something like this.
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Main PID Ladder Logic

The AIN output is block moved to the LKUP function, which is used to scale the input
signal. We do this because the input sensor is not likely to produce highly linear
readings; the result is an ideal linear signal.
The look-up table output is block moved to the PID function. RAMP is used to control
the rise (or fall) of the set point for the PID controller with regard to the rate of ramp
and the solution interval. In this example, the set point is established in another logic
section to simulate a remote setting. The MODE function is placed after the RAMP
so that we can switch between the RAMP-generated set point or a manual value.
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Simulated Process
The PID function is actually controlling the process simulated by this logic [value in
400100: 878(Dec)].
The process simulator is comprised of two LLAG functions that act as a filter and
input to a DELAY queue that is also a PCFL function block. This arrangement is the
equivalent of a second-order process with dead time.
The solution intervals for the LLAG filters do not affect the process dynamics and
were chosen to give fast updates. The solution interval for the DELAY queue is set
at 1000 ms with a delay of 5 intervals,i.e. 5 s. The LLAG filters each have lead terms
of 4 s and lag terms of 10 s. The gain for each is 1.0.
In process control terms the transfer function can be expressed as:
The AOUT function is used only to convert the simulated process output control
value into a range of 0 ... 4 095, which simulates a field device. This integer signal
is used as the process input in the first network.
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PID Parameters
The PID controller is tuned to control this process at 20.0, using the Ziegler-Nichols
tuning method. The resulting controller gain is 2.16, equivalent to a proportional
band of 46.3%.
The integral time is set at 12.5 s/repeat (4.8 repeats/ min). The derivative time is
initially 3 s, then reduced to 0.3 s to de-emphasize the derivative effect.
An AOUT function is used after the PID. It conditions the PID control output by
scaling the signal back to an integer for use as the control value.
The entire control loop is preceded by a 0.1 s timer. The target solution interval for
the entire loop is 1 s, and the full solve is 1 s. However, the nontime-dependent
functions that are used (AIN, LKUP, MODE, and AOUT) do not need to be solved
every scan. To reduce the scan time impact, these functions are scheduled to solve
less frequently. The example has a loop solve every 3 s, reducing the average scan
time dramatically.
NOTE: It is still important to be aware of the maximum scan impact. When
programming other loops, you will not want all of the loops to solve on the same
scan.
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PID2 Level Control Example
Description
Here is a simplified P&I diagram for an inlet separator in a gas processing plant.
There is a 2-phase inlet stream: liquid and gas.
LT-1 4 ... 20 mA level transmitter

I/P-1 4 ... 20 mA current to pneumatic converter
LV-1 control valve, fail CLOSED
LSH-1 high level switch, normally closed
LSL-1 low level switch, normally open
LC-1 level controller
I/P-1 Mv to control the flow into tank T-1
The liquid is dumped from the tank to maintain a constant level. The control objective
is to maintain a constant level in the separator. The phases must be separated
before processing; separation is the role of the inlet separator, PV-1. If the level
controller, LC-1, fails to perform its job, the inlet separator could fill, causing liquids
to get into the gas stream; this could severely damage devices such as gas
compressors.
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Ladder Logic Diagram

The level is controlled by device LC-1, a Quantum controller connected to an analog
input module; I/P-1 is connected to an analog output module. We can implement the
control loop with the following 984LL.
The first SUB block is used to move the analog input from LT-1 to the PID2 analog
input register, 40113. The second SUB block is used to move the PID2 output Mv to
the I/O mapped output I/P-1. Coil 00101 is used to change the loop from auto to
manual mode, if desired. For auto mode, it should be on.
Register Content
Specify the set point in mm for input scaling (E.U.). The full input range will be 0 ...
4000 mm (for 0 ... 4095 raw analog). Specify the register content of the top node in
the PID2 block as follows.
Register Content Content Comments

Numeric Meaning
400100 Scaled PV (mm) PID2 writes this
400101 2000 Scaled SP (mm) Set to 2000 mm (half full) initially
400102 0000 Loop output (0 ... 4095 PID2 writes this; keep it set to 0 to be
safe
400103 3500 Alarm High Set Point (mm) If the level rises above 3500 mm, coil
000102 goes ON
400104 1000 Alarm Low Set Point (mm) If the level drops below 1000 mm,
coil 000103 goes ON
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Register Content Content Comments

Numeric Meaning
400105 0100 PB (%) The actual value depends on the
process dynamics
400106 0500 Integral constant (5.00 The actual value depends on the
repeats/min) process dynamics
400107 0000 Rate time constant (per min) Setting this to 0 turns off the
derivative mode
400108 0000 Bias (0 ... 4095) This is set to 0, since we have an
integral term
400109 4095 High windup limit (0 ... 4095) Normally set to the maximum
400110 0000 Low windup limit (0 ... 4095) Normally set to the minimum
400111 4000 High engineering range (mm) The scaled value of the process
variable when the raw input is at
4095
400112 0000 Low engineering range (mm) The scaled value of the process
variable when the raw input is at 0
400113 Raw analog measure A copy of the input from the analog
(0 ... 4095) input module register (300001)
copied by the first SUB
400114 0000 Offset to loop counter register Zero disables this feature.
Normally, this is not used
400115 0000 Max loops solved per scan See register 400114
400116 0102 Pointer to reset feedback If you leave this as zero, the PID2
function automatically supplies a
pointer to the loop output register. If
the actual output (400500) could be
changed from the value supplied by
PID2, then this register should be set
to 500 (400500) to calculate the
integral properly
400117 4095 Output clamp high (0 ... 4095) Normally set to maximum
400118 0000 Output clamp low (0 ... 4095) Normally set to minimum
400119 0015 Rate Gain Limit Constant Normally set to about 15. The actual
(2 ... 30) value depends on how noisy the
input signal is. Since we are not
using derivative mode, this has no
effect on PID2
400120 0000 Pointer to track input Used only if the PRELOAD feature is
used. If the PRELOAD is not used,
this is normally zero
The values in the registers in the 400200 destination block are all set by the PID2
block.
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Formatting Messages for ASCII READ/WRIT Operations
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Formatting Messages for ASCII

READ/WRIT Operations
4
Introduction
This chapter provides general information about formatting messages for ASCII
READ/WRIT operations.

Topic Page
Formatting Messages for ASCII READ/WRIT Operations 58
Format Specifiers 59
Special Set-up Considerations for Control/Monitor Signals Format 62
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General
The ASCII messages used in the READ and WRIT instructions can be created via
your panel software using the format specifiers described below. Format specifiers
are character symbols that indicate:
z The ASCII characters used in the message
z Register content displayed in ASCII character format
z Register content displayed in hexadecimal format
z Register content displayed in integer format
z Subroutine calls to execute other message formats
Overview Format Specifiers

The following format specifiers can be used.
Specifier Meaning
/ ASCII return (CR) and linefeed (LF)
" " Enclosure for octal control code
‘ ´ Enclosure for ASCII text characters
X Space indicator
() Repeat contents of the parentheses
I Integer
L Leading zeros
A Alphanumeric
O Octal
B Binary
H Hexadecimal
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Format Specifiers
Format Specifier /
ASCII return (CR) and linefeed (LF)
Field width None (defaults to 1)

Prefix None (defaults to 1)
Input format Outputs CR, LF; no ASCII characters accepted
Output format Outputs CR, LF
Format Specifier " "

Enclosure for octal control code
Field width Three digits enclosed in double quotes

Prefix None
Input format Accepts three octal control characters
Output format Outputs three octal control characters
Format Specifier ‘ ´
Enclosure for ASCII text characters
Field width 1 ... 128 characters

Prefix None (defaults to 1)
Input format Inputs number of upper and/or lower case printable characters
specified by the field width
Output format Outputs number of upper and/or lower case printable characters
specified by the field width
Format Specifier X
Space indicator, e.g., 14X indicates 14 spaces left open from the point where the
specifier occurs.

Prefix 1 ... 99 spaces
Input format Inputs specified number of spaces
Output format Outputs specified number of spaces
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Format Specifier ( )
Repeat contents of the parentheses, e.g., 2 (4X, I5) says repeat 4X, I5 two
times
Field width None

Prefix 1 ... 255
Input format Repeat format specifiers in parentheses the number of times
specified by the prefix
Output format Repeat format specifiers in parentheses the number of times
specified by the prefix
Format Specifier I
Integer, e.g., I5 specifies five integer characters

Prefix 1 ... 99
Input format Accepts ASCII characters 0 ... 9. If the field width is not satisfied, the
most significant characters in the field are padded with zeros
Output format Outputs ASCII characters 0 ... 9. If the field width is not satisfied, the
most significant characters in the field are padded with zeros. The
overflow field consists of asterisks.
Format Specifier L
Leading zeros, e.g., L5 specifies five leading zeros

Prefix 1 ... 99
most significant characters in the field are padded with zeros
most significant characters in the field are padded with zeros. The
overflow field consists of asterisks.
Format Specifier A
Alphanumeric, e.g., A27 specifies 27 alphanumeric characters, no suffix allowed

Prefix 1 ... 99
Input format Accepts any 8-bit character except reserved delimiters such as CR,
LF, ESC, BKSPC, DEL.
Output format Outputs any 8-bit character
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Format Specifier O
Octal, e.g., O2 specifies two octal characters

Prefix 1 ... 99
most significant characters are padded with zeros.
most significant characters are padded with zeros. No overflow
indicators.
Format Specifier B
Binary, e.g., B4 specifies four binary characters

Prefix 1 ... 99
Input format Accepts ASCII characters 0 and 1. If the field width is not satisfied,
the most significant characters are padded with zeros.
Output format Outputs ASCII characters 0 and 1. If the field width is not satisfied,
the most significant characters are padded with zeros. No overflow
indicators.
Format Specifier H
Hexadecimal, e.g., H2 specifies two hex characters

Prefix 1 ... 99
Input format Accepts ASCII characters 0 ... 9 and A ... F. If the field width is not
satisfied, the most significant characters are padded with zeros.
Output format Outputs ASCII characters 0 ... 9 and A ... F. If the field width is not
satisfied, the most significant characters are padded with zeros. No
overflow indicators.
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Special Set-up Considerations for Control/Monitor Signals Format
General
To control and monitor the signals used in the messaging communication, specify
code 1002 in the first register of the control block (the register displayed in the top
node). Via this format, you can control the RTS and CTS lines on the port used for
messaging.
NOTE: In this format, only the local port can be used for messaging, i.e., a parent
PLC cannot monitor or control the signals on a child port. Therefore, the port number
specified in the fifth implied node of the control block must always be 1.
The first three registers in the data block (the displayed register and the first and
second implied registers in the middle node) have predetermined content.
Register Content
Displayed Stores the control mask word
First implied Stores the control data word
Second implied Stores the status word
These three data block registers are required for this format, and therefore the
allowable range for the length value (specified in the bottom node) is 3 ... 255.
Control Mask Word

Usage of word:
Bit Function
1 1 = port can be taken
0 = port cannot be taken
2 - 15 Not used
16 1 = control RTS
0 = do not control RTS
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Control Data Word

Usage of word:
Bit Function
1 1 = take port
0 = return port
2 - 15 Not used
16 1 = activate RTS
0 = deactivate RTS
Status Word
Usage of word:
Bit Function
1 1 = port taken
2 1 = port ACTIVE as Modbus slave
3 - 13 Not used
14 1 = DSR ON
15 1 = CTS ON
16 1 = RTS ON
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Coils, Contacts, and

Interconnects
5
Introduction
This chapter provides information about coils, contacts, and interconnects, also
called shorts. Details of all the elements in the ladder logic instruction set appear in
an alphabetical listing.

Topic Page
Coils 66
Contacts 68
Interconnects (Shorts) 70
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Coils
Definition of Coils
A coil is a discrete output that is turned ON and OFF by power flow in the logic
program. A single coil is tied to a 0x reference in the PLC’s state RAM. Because
output values are updated in state RAM by the PLC, a coil may be used internally in
the logic program or externally via the I/O map to a discrete output unit in the control
system. When a coil is ON, it either passes power to a discrete output circuit or
changes the state of an internal relay contact in state RAM.
There are two types of coils.
z A normal coil
z A memory-retentive, or latched, coil
Normal Coil
WARNING
Forcing of Coils
When a discrete input (1x) is disabled, signals from its associated input field device
have no control over its ON/OFF state. When a discrete output (0x) is disabled, the
PLC’s logic scan has no control over the ON/OFF state of the output. When a
discrete input or output has been disabled, you can change its current ON/OFF
state with the Force command.
There is an important exception when you disable coils. Data move and data
matrix instructions that use coils in their destination node recognize the current
ON/OFF state of all coils in that node, whether they are disabled or not. If you are
expecting a disabled coil to remain disabled in such an instruction, you may cause
unexpected or undesirable effects in your application.
When a coil or relay contact has been disabled, you can change its state using the
Force ON or Force OFF command. If a coil or relay is enabled, it cannot be forced.
Failure to follow these instructions can result in death, serious injury, or
equipment damage.
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A normal coil is a discrete output shown as a 0x reference.

A normal coil is ON or OFF, depending on power flow in the program.
A ladder logic network can contain up to seven coils, no more than one per row.
When a coil is placed in a row, no other logic elements or instruction nodes can
appear to the right of the coil’s logic-solve position in the row. Coils are the only
ladder logic elements that can be inserted in column 11 of a network.
To define a discrete reference for the coil, select it in the editor and click to open a
dialog box called Coil.
Symbol
Retentive Coil
If a retentive (latched) coil is energized when the PLC loses power, the coil will come
back up in the same state for one scan when the PLC’s power is restored.
To define a discrete reference for the coil, select it in the editor and click to open a
dialog box called Retentative coil (latch).
Symbol
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Contacts
Definition of Contacts
Contacts are used to pass or inhibit power flow in a ladder logic program. They are
discrete, i.e., each consumes one I/O point in ladder logic. A single contact can be
tied to a 0x or 1x reference number in the PLC’s state RAM, in which case each
contact consumes one node in a ladder network.
Four kinds of contacts are available.
z normally open (N.O.) contacts
z normally closed (N.C.) contacts
z positive transitional (P.T.) contacts
z negative transitional (N.T.) contacts
Contact Normally Open

A normally open (NO) contact passes power when it is ON.
To define a discrete reference for the NO contact, select it in the editor and click to
open a dialog called Normally open contact.
Symbol
Contact Normally Closed

A normally closed (NC) contact passes power when it is OFF.
To define a discrete reference for the NC contact, double ckick on it in the ladder
node to open a dialog called Normally closed contact.
Symbol
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Contact Pos Trans

A positive transitional (PT) contact passes power for only one scan as it transitions
from OFF to ON.
To define a discrete reference for the PT contact, select it in the editor and click to
open a dialog called Positive transition contact.
Symbol
Contact Neg Trans

A negative transitional (NT) contact passes power for only one scan as it transitions
from ON to OFF.
To define a discrete reference for the NT contact, select it in the editor and click to
open a dialog called Contact negative transition .
Symbol
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Interconnects (Shorts)
Definition of Interconnects (Shorts)

Shorts are simply straight-line connections between contacts and/or instructions in
a ladder logic network. Shorts may be inserted horizontally or vertically in a network.
Two kinds of shorts are available.
z horizontal short
z vertical short
Horizontal Short
A short is a straight-line connection between contacts and/or nodes in an instruction
through which power flow can be controlled.
A horizontal short is used to extend logic out across a row in a network without
breaking the power flow. Each horizontal short consumes one node in the network,
and uses a word of memory in the PLC.
Symbol
Vertical Short
A vertical short connects contacts or nodes in an instruction positioned one above
the other in a column. Vertical shorts can also connect inputs or outputs in an
instruction to create either-or conditions. When two contacts are connected by a
vertical short, power is passed when one or both contacts receive power.
The vertical short is unique in two ways.
z It can coexist in a network node with another element or nodal value.
z It does not consume any PLC memory.
Symbol
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Interrupt Handling
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Interrupt Handling
6
Interrupt Handling
Interrupt-related Performance
The interrupt-related instructions operate with minimum processing overhead. The
performance of interrupt-related instructions is especially critical. Using a interval
timer interrupt (ITMR) instruction adds about 6% to the scan time of the scheduled
ladder logic, this increase does not include the time required to execute the interrupt
handler subroutine associated with the interrupt.
Interrupt Latency Time

The following table shows the minimum and maximum interrupt latency times you
can expect.
ITMR overhead No work to do 60 ms/ms

Response time Minimum 98 ms
Maximum during logic solve and 400 ms
Modbus command reception
Total overhead (not counting normal logic solve time) 155 ms
These latency times assume only one interrupt at a time.
Interrupt Priorities
The PLC uses the following rules to choose which interrupt handler to execute in the
event that multiple interrupts are received simultaneously.
z An interrupt generated by an interrupt module has a higher priority than an
interrupt generated by a timer.
z Interrupts from modules in lower slots of the local backplane have priority over
interrupts from modules in the higher slots.
If the PLC is executing an interrupt handler subroutine when a higher priority
interrupt is received, the current interrupt handler is completed before the new
interrupt handler is begun.
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Interrupt Handling
Instructions that Cannot Be Used in an Interrupt Handler

The following (nonreenterant) ladder logic instructions cannot be used inside an
interrupt handler subroutine.
z MSTR
z READ / WRIT
z PCFL / EMTH
z T1.0, T0.1, T.01, and T1MS timers (will not set error bit 2, timer results invalid)
z equation networks
z user loadables (will not set error bit 2)
If any of these instructions are placed in an interrupt handler, the subroutine will be
aborted, the error output on the ITMR or IMOD instruction that generated the
interrupt will go ON, and bit 2 in the status register will be set.
Interrupt with BMDI/ID/IE

Three interrupt mask/unmask control instructions are available to help protect data
in both the normal (scheduled) ladder logic and the (unscheduled) interrupt handling
subroutine logic. These are the Interrupt Disable (ID) instruction, the Interrupt
Enable (IE) instruction, and the Block Move with Interrupts Disabled (BMDI)
instruction.
An interrupt that is executed in the timeframe after an ID instruction has been solved
and before the next IE instruction has been solved is buffered. The execution of a
buffered interrupt takes place at the time the IE instruction is solved. If two or more
interrupts of the same type occur between the ID ... IE solve, the mask interrupt
overrun error bit is set, and the subroutine initiated by the interrupts is executed only
one time
The BMDI instruction can be used to mask both a timer-generated and local I/O-
generated interrupts, perform a single block data move, then unmask the interrupts.
It allows for the exchange of a block of data either within the subroutine or at one or
more places in the scheduled logic program.
BMDI instructions can be used to reduce the time between the disable and enable
of interrupts. For example, BMDI instructions can be used to protect the data used
by the interrupt handler when the data is updated or read by Modbus, Modbus Plus,
Peer Cop or Distributed I/O (DIO).
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Subroutine Handling
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Subroutine Handling
7
Subroutine Handling
JSR / LAB Method

The example below shows a series of three user logic networks, the last of which is
used for an up-counting subroutine. Segment 32 has been removed from the order-
of-solve table in the segment scheduler.
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Subroutine Handling
When input 100001 to the JSR block in network 2 of segment 1 transitions from OFF
to ON, the logic scan jumps to subroutine #1 in network 1 of segment 32.
The subroutine will internally loop on itself ten times, counted by the ADD block. The
first nine loops end with the JSR block in the subroutine (network 1 of segment 32)
sending the scan back to the LAB block. Upon completion of the tenth loop, the RET
block sends the logic scan back to the scheduled logic at the JSR node in network
2 of segment 1.
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Installation of DX Loadables
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8
How to install the DX Loadables

The DX loadable instructions are only available if you have installed them. With the
installation of the Concept software, DX loadables are located on your hard disk.
Now you have to unpack and install the loadables you want to use as follows.
Step Action
1 With the menu command Project → Configurator you open the
configurator.
2 With Configure → Loadables... you open the dialog box Loadables.
3 Press the command button Unpack... to open the standard Windows dialog
box Unpack Loadable File where the multifile loadables (DX loadables) can
be selected. Select the loadable file you need, click the button OK and it is
inserted into the list box Available:.
4 Now press the command button Install=> to install the loadable selected in
the list box Available:. The installed loadable will be displayed in the list box
Installed:.
5 Press the command button Edit... to open the dialog box Loadable
Instruction Configuration. Change the opcode if necessary or accept
the default. You can assign an opcode to the loadable in the list box Opcode in
order to enable user program access through this code. An opcode that is
already assigned to a loadable, will be identified by a *. Click the button OK.
6 Click the button OK in the dialog box Loadables.
Configuration loadables count is adjusted. The installed loadable is available for
programming at the menu Objects → List Instructions → DX
Loadable.
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Instruction Descriptions (A to D)
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II
Introduction
In this part instruction descriptions are arranged alphabetically from A to D.

9 1X3X - Input Simulation 79
10 AD16: Ad 16 Bit 81
11 ADD: Addition 83
12 AND: Logical And 85
13 BCD: Binary to Binary Code 91
14 BLKM: Block Move 93
15 BLKT: Block to Table 97
16 BMDI: Block Move with Interrupts Disabled 101
17 BROT: Bit Rotate 103
18 CALL: Activate Immediate or Deferred DX Function 107
19 CANT - Interpret Coils, Contacts, Timers, Counters, and the SUB Block 115
20 CCPF - Configure Cam Profile with Variable Instruments 121
21 CCPV - Configure Cam Profile with Variable Increments 125
22 CFGC - Configure Coordinated Set 129
23 CFGF - Configure Follower Set 133
24 CFGI – Configure Imaginary Axis 137
25 CFGR – Configure Remote Axis 141
26 CFGS – Configure SERCOS Axis 145
27 CHS: Configure Hot Standby 149
28 CKSM: Check Sum 155
29 CMPR: Compare Register 159
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30 Coils 163
31 COMM - ASCII Communications Function 167
32 COMP: Complement a Matrix 171
33 Contacts 177
34 CONV - Convert Data 181
35 CTIF - Counter, Timer, and Interrupt Function 185
36 DCTR: Down Counter 193
37 DIOH: Distributed I/O Health 197
38 DISA - Disabled Discrete Monitor 201
39 DIV: Divide 205
40 DLOG: Data Logging for PCMCIA Read/Write Support 211
41 DMTH - Double Precision Math 217
42 DRUM: DRUM Sequencer 225
43 DV16: Divide 16 Bit 231
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1X3X - Input Simulation
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9
Introduction
This chapter describes the instruction 1X3X.

Topic Page
Short Description 80
Representation 80
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Short Description
Function Description
The Input Simulation instruction provides a simple method to simulate 1xxxx and
3xxx input data values. This block is similar to a Block Move, the BLKM instruction.
When the control input receives power, the source table is copied to the destination
(input) table.
Representation
Symbol
Representation of the instruction
Parameter Description
Description of the instruction’s parameters
Parameters State RAM Data Meaning

Reference Type
Top input 0x, 1x None
destination table 1x, 3x INT
(top node)
source table 4x INT Contains source to be moved to destination
(middle node)
length INT (Length: NNN if 3X)
(bottom node) Length: 16* if 4x
Top output 0x None Passes power when top input receives power.
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AD16: Ad 16 Bit
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AD16: Ad 16 Bit
10
Introduction
This chapter describes the instruction AD16.

Topic Page
Representation 82
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AD16: Ad 16 Bit
Short Description
The AD16 instruction performs signed or unsigned 16-bit addition on value 1 (its top
node) and value 2 (its middle node), then posts the sum in a 4x holding register in
the bottom node.
Representation
Symbol

Reference Type
Top input 0x, 1x None ON = add value 1 and value 2
Bottom input 0x, 1x None ON = signed operation
OFF = unsigned operation
value 1 (top node) 3x, 4x INT, Addend, can be displayed explicitly as an
UINT integer (range 1 ... 65 535) or stored in a register
value 2 (middle node) 3x, 4x INT, Addend, can be displayed explicitly as an
UINT integer (range 1 ... 65 535) or stored in a register
sum (bottom node) 4x INT, Sum of 16 bit addition
UINT
Top output 0x None ON = successful completion of the operation
Bottom output 0x None ON = overflow in the sum
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ADD: Addition
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ADD: Addition
11
Introduction
This chapter describes the instruction ADD.

Topic Page
Representation 84
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ADD: Addition
Short Description
The ADD instruction adds unsigned value 1 (its top node) to unsigned value 2 (its
middle node) and stores the sum in a holding register in the bottom node.
Representation
Symbol
Parameters State RAM Reference Data Type Meaning

Top input 0x, 1x None ON = add value 1 and value 2
value 1 (top node) 3x, 4x INT, UINT sum > 999 - 16 bit PLC
sum > 9999 - 24 bit PLC
65535 - 785L PLC
value 2 (middle node) 3x, 4x INT, UINT sum > 999 - 16 bit PLC
sum > 9999 - 24 bit PLC
65535 - 785L PLC
sum (bottom node) 4x INT, UINT Sum
Top output 0x None ON = overflow in the sum
sum > 999 in 16 bit PLC
sum > 9999 in 24 bit PLC
65535 in 785L PLC
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AND: Logical And
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AND: Logical And
12
Introduction
This chapter describes the instruction AND.

Topic Page
Representation 87
Parameter Description 89
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AND: Logical And
Short Description
WARNING
DISABLED COILS
Before using the AND instruction, check for disabled coils. AND will override any
disabled coils within the destination matrix without enabling them.This can cause
personal injury if a coil has disabled an operation for maintenance or repair
because the coil’s state can be changed by the AND operation.
equipment damage.
The AND instruction performs a Boolean AND operation on the bit patterns in the
source and destination matrices.
The ANDed bit pattern is then posted in the destination matrix, overwriting its
previous contents.
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AND: Logical And
Representation
Symbol
Parameters State RAM Data Type Meaning

Reference
Top input 0x, 1x None Initiates AND
source matrix 0x, 1x, 3x, 4x BOOL, First reference in the source matrix
(top node) WORD
destination 0x, 4x BOOL, First reference in the destination matrix
matrix WORD
(middle node)
length INT, UINT Matrix length; range 1 ... 100.
(bottom node)
Top output 0x None Echoes state of the top input
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AND: Logical And
An AND Example
When contact 10001 passes power, the source matrix formed by the bit pattern in
registers 40600 and 40601 is ANDed with the destination matrix formed by the bit
pattern in registers 40604 and 40605. The ANDed bits are then copied into registers
40604 and 40605, overwriting the previous bit pattern in the destination matrix.
NOTE: If you want to retain the original destination bit pattern of registers 40604 and
40605, copy the information into another table using the BLKM instruction before
performing the AND operation.
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AND: Logical And
Matrix Length (Bottom Node)

The integer entered in the bottom node specifies the matrix length, i.e. the number
of registers or 16-bit words in the two matrices. The matrix length can be in the range
1 ... 100. A length of 2 indicates that 32 bits in each matrix will be ANDed.
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AND: Logical And
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BCD: Binary to Binary Code
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13
Introduction
This chapter describes the instruction BCD.

Topic Page
Representation 92
31007523 8/2010 91
Short Description
The BCD instruction can be used to convert a binary value to a binary coded decimal
(BCD) value or a BCD value to a binary value. The type of conversion to be
performed is controlled by the state of the bottom input.
Representation
Symbol

Reference
Top input 0x, 1x None ON = enable conversion
Bottom input 0x, 1x None ON = BCD → binary conversion
OFF = binary → BCD conversion
source register 3x, 4x INT, UINT Source register where the numerical
(top node) value to be converted is stored
destination register 4x INT, UINT Destination register where the
(middle node) converted numerical value is posted
#1 bottom node) INT, UINT Constant value, can not be changed
Top output 0x None Echoes the state of the top input
Bottom output 0x None ON = error in the conversion operation
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BLKM: Block Move
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BLKM: Block Move
14
Introduction
This chapter describes the instruction BLKM.

Topic Page
Representation 95
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BLKM: Block Move
Short Description
WARNING
DISABLED COILS
Before using the BLKM instruction, check for disabled coils. BLKM will override any
disabled coils within a destination table without enabling them. This can cause
injury if a coil has been disabled for repair or maintenance because the coil’s state
can change as a result of the BLKM instruction.
equipment damage.
The BLKM (block move) instruction copies the entire contents of a source table to a
destination table in one scan.
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BLKM: Block Move
Representation
Symbol

Reference
Top input 0x, 1x None ON = initiates block move
source table 0x, 1x, 3x, 4x ANY_BIT Source table that will have its contents
(top node) copied in the block move
destination 0x, 4x ANY_BIT Destination table where the contents of the
table source table will be copied in the block
(middle node) move
table length INT, UINT Table size (number of registers or 16-bit
(bottom node) words) for both the source and destination
tables; they are of equal length.
Range: 1 ... 100
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BLKM: Block Move
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BLKT: Block to Table
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15
Introduction
This chapter describes the instruction BLKT.

Topic Page
Representation 99
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Short Description
WARNING
4x REGISTER CORRUPTION
Use external logic in conjunction with the middle or bottom input to confine the
value in the pointer to a safe range. BLKT is a powerful instruction that can corrupt
all the 4x registers in your PLC with data copied from the source block.
equipment damage.
The BLKT (block-to-table) instruction combines the functions of R→T and BLKM in
a single instruction. In one scan, it can copy data from a source block to a destination
block in a table. The source block is of a fixed length. The block within the table is of
the same length, but the overall length of the table is limited only by the number of
registers in your system configuration.
98 31007523 8/2010
Representation
Symbol

Reference
Top input 0x, 1x None ON = initiates the DX move
middle input 0x, 1x None ON = hold pointer
bottom input 0x, 1x None ON = reset pointer to zero
source block 4x BYTE, WORD First holding register in the block of
(top node) contiguous registers whose content will be
copied to a block of registers in the
destination table
pointer 4x BYTE, WORD Pointer to the destination table
(middle node)
block length INT, UINT Block length (number of 4x registers) of
(bottom node) the source block and of the destination
block
Range: 1 ... 100
Top output 0x None ON = operation successful
Middle output 0x None ON = error / move not possible
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Middle and Bottom Input

The middle and bottom input can be used to control the pointer so that source data
is not copied into registers that are needed for other purposes in the logic program.
When the middle input is ON, the value in the pointer register is frozen while the
BLKT operation continues. This causes new data being copied to the destination to
overwrite the block data copied on the previous scan.
When the bottom input is ON, the value in the pointer register is reset to zero. This
causes the BLKT operation to copy source data into the first block of registers in the
destination table.
Pointer (Middle Node)

The 4x register entered in the middle node is the pointer to the destination table. The
first register in the destination table is the next contiguous register after the pointer,
e.g. if the pointer register is 400107, then the first register in the destination table is
400108.
NOTE: The destination table is segmented into a series of register blocks, each of
which is the same length as the source block. Therefore, the size of the destination
table is a multiple of the length of the source block, but its overall size is not
specifically defined in the instruction. If left uncontrolled, the destination table could
consume all the 4x registers available in the PLC configuration.
The value stored in the pointer register indicates where in the destination table the
source data will begin to be copied. This value specifies the block number within the
destination table.
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BMDI: Block Move with Interrupts Disabled
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BMDI: Block Move with

Interrupts Disabled
16
Introduction
This chapter describes the instruction BMDI.

Topic Page
Representation 102
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BMDI: Block Move with Interrupts Disabled
Short Description
The BMDI instruction masks the interrupt, initiates a block move (BLKM) operation,
then unmasks the interrupts.
Representation
Symbol

Reference
Top input 0x, 1x None ON = masks interrupt, initiates a block move,
then unmasks the interrupts
source table 0x, 1x, 3x, 4x INT, UINT, Source table that will have its contents copied
(top node) WORD in the block move
destination table 0x, 4x INT, UINT, Destination table where the contents of the
(middle node) WORD source table will be copied in the block move
table length INT, UINT Integer value, specifies the table size, i.e. the
(bottom node) number of registers, in the source and
destination tables (they are of equal length)
Range: 1 ... 100
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BROT: Bit Rotate
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BROT: Bit Rotate
17
Introduction
This chapter describes the instruction BROT.

Topic Page
Representation 105
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BROT: Bit Rotate
Short Description
WARNING
DISABLED COILS
Before using the BROT instruction, check for disabled coils. BROT will override
any disabled coils within a destination matrix without enabling them. This can
cause injury if a coil has been disabled for repair or maintenance if BROT
unexpectedly changes the coil’s state.
equipment damage.
The BROT (bit rotate) instruction shifts the bit pattern in a source matrix, then posts
the shifted bit pattern in a destination matrix. The bit pattern shifts left or right by one
position per scan.
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BROT: Bit Rotate
Representation
Symbol

Reference Type
Top input 0x, 1x None ON = shifts bit pattern in source matrix by one
Middle input 0x, 1x None ON= shift left
OFF = shift right
Bottom input 0x, 1x None OFF = exit bit falls out of the destination
matrix
ON = exit bit wraps to start of the destination
matrix
source matrix 0x, 1x, 3x, 4x ANY_BIT First reference in the source matrix, i.e. in the
(top node) matrix that will have its bit pattern shifted
destination 0x, 4x ANY_BIT First reference in the destination matrix, i.e. in
matrix the matrix that shows the shifted bit pattern
(middle node)
length 0x INT, UINT Matrix length; range: 1 ... 100
(bottom node)
Middle output 0x None OFF = exit bit is 0
ON = exit bit is 1
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BROT: Bit Rotate

The integer value entered in the bottom node specifies the matrix length, i.e. the
number of registers or 16-bit words in each of the two matrices. The source matrix
and destination matrix have the same length. The matrix length can range from 1 ...
100, e.g. a matrix length of 100 indicates 1600 bit locations.
Result of the Shift (Middle Output)

The middle output indicates the sense of the bit that exits the source matrix (the
leftmost or rightmost bit) as a result of the shift.
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CALL: Activate DX Function
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CALL: Activate Immediate or

Deferred DX Function
18
Introduction
This chapter describes the instruction CALL.

Topic Page
Representation 109
Representation 112
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Short Description
A CALL instruction activates an immediate or deferred DX function from a library of
functions defined by function codes. The Copro copies the data and function code
into its local memory, processes the data, and copies the results back to controller
memory.
Function Codes:
z 0-499: User Immediate/Deferred DXs
z 500-9999: System Immediate/Deferred DXs
The two MSBs of the top register are the Copro# in a multiple Copro system.
108 31007523 8/2010

Representation
Overview
The content in this section applies specifically to the Immediate DX function of the
CALL instruction.
Symbol
Representation of the instruction for an Immediate DX CALL
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Description of the instruction’s parameters for an Immediate DX CALL

Reference
Top input 0x, 1x None ON initiates the CALL.
Bottom input 0x, 1x None The input to the bottom node is used with an
immediate DX function to keep scanning the
instruction regardless of the state of the top
input.
A list of the codes, their names, and their
function is detailed in the table below named
Immediate DX Functions.
value 0x, 3x INT, UINT The top node is used to specify the function
(top node) code to be executed. It may be entered
explicitly as a constant or as a value in a
4xxxx holding register. The codes fall into
two ranges:
z 0 through 499 are for user-definable DXs
z 500 through 9999 are for system DXs
Both User-definable and System-definable

codes apply to both immediate and deferred.
Both User-definable and System-definable
are provided by Schneider Electric.
register 4x INT, UINT The 4xxxx register in the middle node is the
(middle node) first in a block of registers to be passed to the
Copro for processing.
length INT, UINT The number of registers in the block is
(bottom node) defined in the bottom node.
Top output 0x None ON when the function completes
successfully.
Bottom output 0x None The output from the bottom node will go ON
if an error is detected in the function.
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Immediate DX Functions
This table lists the Immediate DX functions
Name Code Function

f_config 500 Obtain Copro configuration data
f_2md_fl 501 Convert a two-register long integer to 64-bit floating point
f_fl_2md 502 Convert floating point to two-register long integer
f_4md_fl 503 Convert a four-register long integer to floating point
f_fl_4md 504 Convert floating point to four-register long integer
f_1md_fl 505 Convert a one-register long integer to floating point
f_fl_1m 506 Convert floating point to one-register long integer
f_exp 507 Exponential function
f_log 508 Natural logarithm
f_log10 509 Base 10 logarithm
f_pow 510 Raise to a power
f_sqrt 511 Square root
f_cos 512 Cosine
f_sin 513 Sine
f_tan 514 Tangent
f_atan 515 Arc tangent x
f_atan2 516 Arc tangent y/x
f_asin 517 Arc sine
f_acos 518 Arc cosine
f_add 519 Add
f_sub 520 Subtract
f_mult 521 Multiply
f_div 522 Divide
f_deg_rad 523 Convert degrees to radians
f_rad_deg 524 Convert radians to degrees
f_swap 525 Swap byte positions within a register
f_comp 526 Floating point compare
f_dbwrite 527 Write Copro register database from PLC
f_dbread 528 Read Copro register database from PLC
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Representation
Overview
The content in this section applies specifically to the Deferred DX function of the
CALL instruction.
Symbol
Representation of the instruction for a Deferred DX CALL
Description of the instruction’s parameters for a Deferred DX CALL

Reference Type
Top input 0x, 1x None ON initiates the CALL.
Middle input 0x, 1x None The instruction calls a deferred DX when the input to
the middle node is enabled.
A list of the codes, their names, and their function is
detailed in the table below named Deferred DX
functions.
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Reference Type
value 0x, 3x INT, The top node is used to specify the function code to be
(top node) UINT executed. It may be entered explicitly as a constant or
as a value in a 4xxxx holding register. The codes fall
into two ranges:
z 0 through 499 are for user-definable DXs
z 500 through 9999 are for system DXs
Both User-definable and System-definable codes

apply to both immediate and deferred. Both User-
definable and System-definable are provided by
Schneider Electric.
register 4x INT, The 4xxxx register in the middle node is the first in a
(middle node) UINT block of registers to be passed to the Copro for
processing.
length INT, The number of registers in the block is defined in the
(bottom node) UINT bottom node.
Top output 0x None ON when the function completes successfully.
Middle output 0x None The output from the middle node, which is used only
with deferred DX functions, goes ON to indicate that
the function s in process.
Bottom output 0x None The output from the bottom node will go ON if an error
is detected in the function.
Deferred DX Functions
This table lists the Deferred DX Functions
Name Code Function

f_config 500 Obtain Copro configuration data
f_d_dbwr 501 Write Copro register database from PLC
f_d_dbrd 502 Read Copro register database from PLC
f_dgets 515 Issue dgets() on comm line
f_dputs 516 Issue dputs() on comm line
f_sprintf 518 Generate a character string
f_sscanf 519 Interpret a character string
f_egets 520 IEEE-488 gets() function
f_eputs 521 IEEE-488 puts() function
f_ectl 522 IEEE-488 error control function
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CANT - Interpret Coils, Contacts, Timers, Counters, and the SUB Block
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CANT - Interpret Coils,

Contacts, Timers, Counters, and
the SUB Block 19
Introduction
This chapter describes the instruction CANT.

Topic Page
Representation 117
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Short Description
This DX Loadable function block, upon initializing a triggering contact, analyzes your
ladder logic to extract the specific column and the corresponding contact IDs where
power flow has stopped. The CANT block contains 20 registers. A MSTR block is
used to export data from the CANT's 20 registers to a PC running the Action Monitor
program.
The CANT block is specifically used to interpret coils, contacts, timers, counters, and
the SUB block. You may not use any other types of ladder logic instructions in a
network. Otherwise, you receive incorrect results. If, however, you must use one of
the other ladder logic instructions you may place them in a separate network linked
to a coil that is referenced to the network containing the CANT block.
NOTE: Only 24-bit logic Quantum and 984 PLCs support the DX Loadable function
block. 16-bit controllers will not work with this particular block.
116 31007523 8/2010

CANT - Interpret Coils, Contacts, Timers, Counters, and the SUB
Representation
Symbol

Reference Type
Top input 0x, 1x None Action contact 3
Please see the Note below.
Middle input 0x, 1x None Action contact 2
Bottom input 0x, 1x None Action contact 1
register # 4x INT, Each CANT block contains a block of 10 setup registers,
top node UINT which will automatically fill these 10 registers with internal
data.
data register 4x INT, This node is the start of the 4x output data registers.
middle node UINT (For expanded and detailed information please see
page 118.)
delay INT, A delay timer value with 10ms increments. The value 1 is
bottom node UINT assigned to OFF.
NOTE: When any of the above inputs are activated, the CANT function block begins
to solve the routine. The bottom node specifies a delay time in 10ms increments
that the block uses to delay the start of the solve routine.
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Output Data Registers Table (Middle Node)
Output Data Register Description (Purpose)

4x Contains the address of the "CANT in use flag" coil number
Coil must be programmed with NO POWER CONNECTED FROM
THE LEFT in the last network of your ladder logic
4x + 01 CANT version number in hexadecimal format (for example, 0105 for
v1.05)
4x + 02 Hi Byte = Internal operational flags
Lo Byte = MB+ address of a PLC
4x + 03 Output coil number (a variable that is dependent on the block's state)
4x + 04 The Id of the trigger contact or coil
Bit 15 → 0 - if a coil; 1 - if a contact
Bit 14-00 → coil or contact number (1 based)
4x + 05 Hi 12 bits = network number where logic fails (1 based)
Lo 4 bits = column number where logic fails (1 based)
4x + 06 Rung #1:
Hi Byte = node state
Lo Byte = node type (opcode from node database)
4x + 07 Rung #1: Contact number (1 based)
4x + 08 Rung #2: Refer to 4x + 06
4x + 09 Rung #2: Refer to 4x + 07
4x + 10 Rung #3: Refer to 4x + 06
4x + 11 Rung #3: Refer to 4x + 07
4x + 12 Rung #4: Refer to 4x + 06
4x + 13 Rung #4: Refer to 4x + 07
4x + 14 Rung #5: Refer to 4x + 06
4x + 15 Rung #5 Refer to 4x + 07
4x + 16 Rung #6: Refer to 4x + 06
4x + 17 Rung #6: Refer to 4x + 07
4x + 18 Rung #7: Refer to 4x + 06
4x + 19 Rung #7: Refer to 4x + 07
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CANT - Interpret Coils, Contacts, Timers, Counters, and the SUB
Programming
Each network can only contain one COIL and one CANT block, which must be
located in column 10, row 5. Column 9 of the bottom rung contains the power input
for the triggers (action contacts) to the CANT block, which will provide more space
for your ladder logic programming.
NOTE: This is not at the top of the block as it usually is with DX blocks.
In any of the available row positions 5, 6, or 7, you may have up to 3 triggers that
must be a transitional type of either [P] or [N]. The CANT block node number will
default to 22 (hexadecimal) and not be changed.
Ladder Node Setup
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MSTR Write Data Setup

The purpose of the MSTR block is to send the 20 4x CANT registers to a PC-based
Action Monitor program. This transmittal of registers is done using either Modbus
Plus or an Ethernet TCP/IP Modbus.
Example:
MSTR statistics control registers
Register Value Description

400121 1 Write data function
400122 ? MSTR error register
400123 20 # of data registers to send
400124 40001 Start of data registers
400125 22 Destination MB+ address
400126 1 MB+ routing
NOTE: It is necessary to program a MSTR block for each receiving (PC) address if
you want to transmit data to more than one PC running Action Monitor.
MSTR Setup
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CCPF
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CCPF - Configure Cam Profile

with Variable Instruments
20
Introduction
This chapter describes the CCPF instruction.

Topic Page
Representation 123
31007523 8/2010 121

CCPF
Short Description
The CCPF function block configures a Cam Profile with fixed master increments. A
CamProfile relates the position of a follower axis for a given position of a master axis.
The CamProfile is a table of master and follower position coordinates. Position
points that are not explicitly listed in the table are derived by interpolating between
the given points. Linear and cubic interpolations are supported.
CamProfile Type
The CamProfile type is used to execute electronic cams in the motion controller.
electronic cams simplify programming of complex moves. They can be applied in
winding applications, flying cutoff applications, thermoforming machines, press
feeds, and many other complex control situations.
NOTE: A CamProfile configuration block can be re-executed to change the profile.
A CMD_NOT_ALLOWED error will be generated if a FollowerSet is already using
the CamProfile and following is turned on.
Related Information
See the MMFStart Loadables for ProWORX 32 file in the Programs\Lib\Quantum
folder on the ProWORX 32 installation CD for more detailed information on using
motion loadables.
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CCPF
Representation
Symbol
The following diagram shows a representation of the instruction.
The following table describes the instruction’s parameters.

Reference Type
Top input 0x None ON initiates the configuration function. When this input
goes off, the function is reset and can be initiated again.
Top node 4x INT, Address of the MMFSTART 200 Register
UINT communications table. This is normally 401001. This
address can be configured by modifying the
MMFSTART.CFG file on the QUANTUM SERCOS
controller.
Middle node 4x INT, This register points to a block of registers that define all
UINT the arguments and returns for a generic subrouting call.
The last two registers are for state control.
Bottom Node 4x INT The integer value entered in the bottom node specifies
the table length. In this case, the number of registers in
the table must be 18.
Top Output 0x None Turned on when the cam configuration call is complete
without error.
Middle Output 0x None Turned on when the cam configuration call is complete
and an error code is generated in register 4xxx15.
Bottom Output 0x None Turned on when the register length is not set at 18.
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CCPF
Registers
The following table shows the registers.
Register Data Type Description

4xxxxx Short The CamProfile ID to be configured
4xxxx1 Short The number of points in the Cam Table
4xxxx2 Unsigned Interpolation Type: Linear = 1 or Cubic = 2
4xxxx4 Unsigned Position units of the master (Rev, Deg, etc.)
4xxxx6 Float First Master Position
4xxxx8 Float Fixed master position increment
4xxx10 Unsigned Position units of the follower (Inch, Rev, etc.)
4xxx12 Float Pointer to first register of follower cam table
4xxx14 Register Block Pointer to address of cam configuration block
4xxx15 Short Error code generated by configuration block
4xxx16 Short Current operating state number
4xxx17 Short Current state entry count
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CCPV
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CCPV - Configure Cam Profile

with Variable Increments
21
Introduction
This chapter describes the CCPV instruction.

Topic Page
Representation 127
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CCPV
Short Description
The CCPV function block configures a CamProfile with variable master increments.
A CamProfile relates the position of a follower axis for a given position of a master
axis. The CamProfile is a table of master and follower position coordinates. Position
points that are not explicitly listed in the table are derived by interpolating between
the given points. Linear and cubic interpolation are supported. See CamProfile
Type, page 122 for more information on a CamProfile type.
Related Information
motion loadables.
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CCPV
Representation
Symbol
The following diagram shows a representation of the CCPV instruction.

Reference
Top input 0x None ON initiates the configuration function. When
this input goes off, the function is reset and can
be initiated again.
Top node 4x INT, UINT Address of the MMFSTART 200 Register
communications table. This is normally
401001. This address can be configured by
modifying the MMFSTART.CFG file on the
QUANTUM SERCOS controller.
Middle node 4x INT, UINT This register points to a block of registers that
define all the arguments and returns for a
generic subrouting call. The last two registers
are for state control.
Bottom node 4x INT The integer value entered in the bottom node
specifies the table length. In this case, the
number of registers in the table must be 16.
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CCPV

Reference
Top output 0x None Turned on when the cam configuration call is
complete without error.
Middle output 0x None Turned on when the cam configuration call is
complete and an error code is generated in
register 4xxx13.
Bottom output 0x None Turned on when the register length is not set
at 16.
Registers
The following table describes the instruction’s registers.

4xxxxx Short The CamProfile ID to be configured
4xxxx1 Short The number of points in the Cam Table
4xxxx2 Unsigned Interpolation Type: Linear = 1 or Cubic = 2
4xxxx4 Unsigned Position units of the master (Rev, Deg, etc.)
4xxxx6 Float Pointer to first register of the master cam table
4xxxx8 Unsigned Position units of the follower (Inch, Rev, etc.)
4xxx10 Float Pointer to first register of follower cam table
4xxx12 Register Block Pointer to first register of cam configuration block
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CFGC
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CFGC - Configure Coordinated Set
22
Introduction
This chapter describes the CFGC instruction.

Topic Page
Representation 131
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CFGC
Short Description
The CFGC function block configures a Coordinated Set. Each motion axis object
has a set of motion parameters that must be configured before the motion axis
object may be used. The configure function provides the default value for these
parameters. The default values are placed into a block of holding registers in a
specified order.
Related Information
motion loadables.
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CFGC
Representation
Symbol
The following diagram shows a representation of the CFGC instruction.

Reference Type
Top input 0x None ON initiates the configuration function. When this
input goes off, the function is reset and can be
initiated again.
UINT communications table. This is normally 401001.
This address can be configured by modifying the
MMFSTART.CFG file on the QUANTUM
SERCOS controller.
Middle node 4x INT, This register points to a block of registers that
UINT define all the arguments and returns for a
generic subrouting call. The last two registers
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CFGC

Reference Type
Middle output 0x None Turned on when the cam configuration call is
complete and an error code is generated in
register 4xxx10.
Bottom output 0x None Turned on when the register length is not set at
13.
Registers

4xxxxx Short Axis id of the Coordinated Set to be configured
4xxxx1 Short Axis id of axis member to be included in the set
4xxxx9 Register Block Pointer to register address of configuration block
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CFGF
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CFGF - Configure Follower Set
23
Introduction
This chapter describes the CFGF instruction.

Topic Page
Representation 135
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CFGF
Short Description
The CFGF function block configures a Follower Set. Each motion axis object has a
set of motion parameters that must be configured before the motion axis object may
be used. The configure function provides the default value for these parameters.
The default values are placed into a block of holding registers in a specified order.
Related Information
motion loadables.
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CFGF
Representation
Symbol
The following diagram shows a representation of the CFGF instruction.

Reference Type
Top input 0x None ON initiates the configuration function. When tthis
initiated again.
controller.
UINT define all the arguments for the configuration. The
last two registers are for state control.
specifies the table length. In this case, the number
of registers in the table must be 14.
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CFGF

Reference Type
Middle output 0x None Turned on when the subroutine call is complete
Bottom output 4x None Turned on when the register length is not set at 14.
Registers

4xxxxx Short Axis id of the Follower Set to be configured
4xxxx1 Short Axis id of Master Axis of the Follower Set
4xxx10 Register Block Pointer to register address of configuration block
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CFGI
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CFGI – Configure Imaginary Axis
24
Introduction
This chapter describes the CFGI instruction.

Topic Page
Representation 139
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CFGI
Short Description
The CFGI function block configures an ImaginaryAxis. Each motion axis object has
a set of motion parameters that must be configured before the motion axis object
may be used. The configure function provides the default value for these
parameters. The default values are placed into a block of holding registers in a
specified order.
Related Information
motion loadables.
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CFGI
Representation
Symbol
The following diagram shows a CFGI instruction.
Parameter Descriptions

Reference Type
initiated again.
SERCOS controller.
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CFGI

Reference Type
20.
Registers

4xxxxx Short Axis id for Imaginary Axis to be configured
4xxxx1 Unsigned Velocity units for the axis
4xxxx2 Float Numerator of the gear ratio
4xxxx4 Float Denominator of the gear ratio1
4xxxx6 Float Positive position limit (optional)
4xxxx8 Float Negative position limit (optional)
4xxx10 Float Velocity limit (optional)
4xxx12 Float Default acceleration (optional)
4xxx14 Float Default deceleration (optional)
4xxx16 Register Block Pointer to register of axis configuration block
1
The units associated with this value are revolutions of the feedback device. Typically the
feedback device is directly coupled to the shaft of the motor, and, therefore, this parameter
specifies the number of motor revolutions required to produce the physical travel specified by
the numerator.
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CFGR
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CFGR – Configure Remote Axis
25
Introduction
This chapter describes the CFGR instruction.

Topic Page
Representation 143
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CFGR
Short Description
The CFGR function block configures a Remote Axis. Each motion axis object has a
Related Information
motion loadables.
142 31007523 8/2010

CFGR
Representation
Symbol
The following diagram shows a representation of the CFGR instruction.

Reference Type
Top input 0x None ON initiates the configuration function. When
this input goes off, the function is reset and can
be initiated again.
SERCOS controller.
UINT define all the arguments for the configuration.
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CFGR

Reference Type
and an error code is generated in register
4xxx10.
13.
Registers

4xxxxx Short Axis id of the Remote Axis to be configured
4xxxx1 Short Velocity units for the axis
4xxxx2 Short Number of position units per
4xxxx4 Short Number of motor revolutions
4xxxx6 Short Axis id of the SERCOS Axis with secondary feedback basis
4xxxx7 Short SERCOS identification number of secondary feedback
device—default is 53
4xxxx9 Short Pointer to register of axis configuration block
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CFGS
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CFGS – Configure SERCOS Axis
26
Introduction
This chapter describes the CFGS instruction.

Topic Page
Representation 147
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CFGS
Short Description
The CFGS function block configures a Sercos Axis. Each motion axis object has a
Related Information
motion loadables.
146 31007523 8/2010

CFGS
Representation
Symbol
The following diagram shows a representation of the CFGS instruction.
Parameters Description

Reference Type
initiated again.
SERCOS controller.
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CFGS

Reference Type
20.
Registers

4xxxxx Short Axis id for SERCOS Axis to be configured
4xxxx1 Unsigned Velocity units for the axis
4xxxx2 Float Numerator of the gear ratio
4xxxx4 Float Denominator of the gear ratio1
4xxxx6 Float Positive position limit (optional)
4xxxx8 Float Negative position limit (optional)
4xxx10 Float Velocity limit (optional)
4xxx12 Float Default acceleration (optional)
4xxx14 Float Default deceleration (optional)
4xxx16 Register Block Pointer to register of axis configuration block
1
The units associated with this value are revolutions of the feedback device. Typically the
feedback device is directly coupled to the shaft of the motor, and, therefore, this parameter
specifies the number of motor revolutions required to produce the physical travel specified by
the numerator.
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CHS: Configure Hot Standby
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27
Introduction
This chapter describes the instruction CHS.

Topic Page
Representation 151
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Short Description
NOTE: This instruction is only available if you have unpacked and installed the DX
Loadables. For further information, see "Installation of DX Loadables, page 75."
The logic in the CHS loadable is the engine that drives the Hot Standby capability in
a Quantum PLC system. Unlike the HSBY instruction, the use of the CHS instruction
in the ladder logic program is optional. However, the loadable software itself must
be installed in the Quantum PLC in order for a Hot Standby system to be
implemented.
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Representation
Symbol

Reference Type
Top input 0x, 1x None Execute Hot Standby (unconditionally)
Middle input 0x, 1x None ON = Enable command register
Bottom input 0x, 1x None ON = Enable non transfer area
OFF = non transfer area will not be used and the Hot
Standby status register will not exist
command 4x INT, Hot Standby command register
register UINT, (For expanded and detailed information please see
(top node) WORD Parameter Description Command Register (Top
Node), page 153).)
nontransfer 4x INT, First register in the nontransfer area of state RAM
area UINT, (For expanded and detailed information please see
(middle node) WORD Parameter Description Nontransfer Area (Middle
Node), page 154.)
length INT, Number of registers of the Hot Standby nontransfer
(bottom node) UINT area in state RAM; range 4 ... 8000
Middle output 0x None ON = System detects interface error
Bottom output 0x None ON = System configuration set by configuration
extension
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Hot Standby System Configuration via the CHS Instruction

Program the CHS instruction in network 1, segment 1 of your ladder logic program
and unconditionally connect the top input to the power rail via a horizontal short (as
the HSBY instruction is programmed in a 984 Hot Standby system).
This method is particularly useful if you are porting Hot Standby code from a 984
application to a Quantum application. The structure of the CHS instruction is almost
exactly the same as the HSBY instruction. You simply remove the HSBY instruction
from the 984LL and replace it with a CHS instruction in the Quantum logic.
If you are using the CHS instruction in ladder logic, the only difference between it
and the HSBY instruction is the use of the bottom output. This output senses
whether or not method 2 has been used. If the Hot Standby configuration extension
screens have been used to define the Hot Standby configuration, the configuration
parameters in the screens will override any different parameters defined by the CHS
instruction at system startup.
For a detailed discussion of the issues related to the configuration extension
capabilities of a Quantum Hot Standby system, refer to the Modicon Quantum Hot
Standby System Planning and Installation Guide.
Parameter Description Execute Hot Standby (Top Input)
WARNING
ERRATIC BEHAVIOR IN THE HOT STANDBY SYSTEM
Do not enable or disable the non-transfer area while the Hot Standby system is
running.
Although it is legal to do so, we strongly discourage this practice because it can
lead to erratic behavior in the Hot Standby system.
equipment damage.
When the CHS instruction is inserted in ladder logic to control the Hot Standby
configuration parameters, its top input must be connected directly to the power rail
by a horizontal short. No control logic, such as contacts, should be placed between
the rail and the input to the top node.
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Parameter Description Command Register (Top Node)

The 4x register entered in the top node is the Hot Standby command register; 8 bits
in this register are used to configure and control Hot Standby system parameters:
Usage of command word:
Bit Function
1-5 Not used
6 0 = swap Modbus port 3 address during switchover
1 = no swap
1 = no swap
1 = no swap
9 - 11 Not used
12 0 = allow exec upgrade only after application stops
1 = allow the upgrade without stopping the application
13 0 = force standby offline if there is a logic mismatch
1 = do not force
14 0 = controller B is in OFFLINE mode
1 = controller B is in RUN
15 0 = controller A is in OFFLINE mode
1 = controller A is in RUN
16 0 = disable keyswitch override
1 = enable the override
NOTE: The Hot Standby command register must be outside of the nontransfer area
of state RAM.
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Parameter Description Nontransfer Area (Middle Node)

The 4x register entered in the middle node is the first register in the non-transfer area
of state RAM. The non-transfer area must contain at least 4 registers, the first 3 of
which have a predefined usage:
Register Content
Displayed and first implied Reverse transfer registers for passing information from the
standby to the primary PLC
Second implied CHS status register
The content of the remaining registers is application-specific; the length is defined

in the parameter length (bottom node).
The 4x registers in the non-transfer area are never transferred from the primary to
the standby PLC during the logic scans. One reason for scheduling additional
registers in the non-transfer area is to reduce the impact of state RAM transfer on
the total system scan time.
CHS Status Register

Usage of status word:
Bit Function
1 1 = the top output is ON (indicating Hot Standby system is active)
2 1 = the middle output is ON (indicating an error condition)
3 - 10 Not used
11 0 = PLC switch is set to A
1 = PLC switch is set to B
12 0 = PLC logic is matched
1 = there is a logic mismatch
13 - 14 The 2 bit value is:
z 0 1 if the other PLC is in OFFLINE mode
z 1 0 if other PLC is running in primary mode
z 1 1 if other PLC is running in standby mode
15 - 16 The 2 bit value is:

z 0 1 if this PLC is in OFFLINE mode
z 1 0 if this PLC is running in primary mode
z 1 1 if this PLC is running in standby mode
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CKSM: Check Sum
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CKSM: Check Sum
28
Introduction
This chapter describes the instruction CKSM.

Topic Page
Representation 157
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CKSM: Check Sum
Short Description
Several PLCs that do not support Modbus Plus come with a standard checksum
(CKSM) instruction. CKSM has the same opcode as the MSTR instruction and is not
provided in executive firmware for PLCs that support Modbus Plus.
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CKSM: Check Sum
Representation
Symbol

Reference Type
Top input 0x, 1x None Initiates checksum calculation of source table
(For expanded and detailed information please see
Parameter Description: Inputs, page 158.)
Middle input 0x,1x None CKSM select 1
Bottom input 0x, 1x None CKSM select 2
source 4x INT, First holding register in the source table. The checksum
(top node) UINT calculation is performed on the registers in this table.
result/count 4x INT, First of two contiguous registers
(middle node) UINT (For expanded and detailed information please see
Result / Count (Middle Node), page 158.)
length INT Number of 4x registers in the source table; range: 1 ...
(bottom node) 255
Top output 0x None ON = Checksum calculation successful
Middle output 0x None ON = implied register count > length or implied register
count =0
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CKSM: Check Sum
Inputs
The states of the inputs indicate the type of checksum calculation to be performed:
CKSM Calculation Top Input Middle Input Bottom Input

Straight Check ON OFF ON
Binary Addition Check ON ON ON
CRC-16 ON ON OFF
LRC ON OFF OFF
Result / Count (Middle Node)

The 4x register entered in the middle node is the first of two contiguous 4x registers:
Register Content
Displayed Stores the result of the checksum calculation
First implied Posts a value that specifies the number of registers selected from
the source table as input to the calculation. The value posted in the
implied register must be ≤ length of source table.
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CMPR: Compare Register
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29
Introduction
This chapter describes the instruction CMPR.

Topic Page
Representation 161
31007523 8/2010 159

Short Description
The CMPR instruction compares the bit pattern in matrix a against the bit pattern in
matrix b for miscompares. In a single scan, the two matrices are compared bit
position by bit position until a miscompare is found or the end of the matrices is
reached (without miscompares).
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Representation
Symbol

Reference
Top input 0x, 1x None ON = initiates compare operation
Middle input 0x, 1x None OFF = restart at last miscompare
ON = restart at the beginning
matrix a 0x, 1x, 3x, 4x ANY_BIT First reference in matrix a, one of the two
(top node) matrices to be compared
pointer register 4x WORD Pointer to matrix b: the first register in
(middle node) matrix b is the next contiguous 4x register
following the pointer register
length INT, UINT Matrix length; range: 1 ... 100
(bottom node)
Middle output 0x None ON = miscompare detected
Bottom output 0x None ON = miscompared bit in matrix a is 1
OFF = miscompared bit in matrix a is 0
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Pointer Register (Middle Node)

The pointer register entered in the middle node must be a 4x holding register. It is
the pointer to matrix b, the other matrix to be compared. The first register in matrix
b is the next contiguous 4x register following the pointer register.
The value stored inside the pointer register increments with each bit position in the
two matrices that is being compared. As bit position 1 in matrix a and matrix b is
compared, the pointer register contains a value of 1; as bit position 2 in the matrices
are compared, the pointer value increments to 2; etc.
When the outputs signal a miscompare, you can check the accumulated count in the
pointer register to determine the bit position in the matrices of the miscompare.

The integer value entered in the bottom node specifies a length of the two matrices,
i.e. the number of registers or 16-bit words in each matrix. (Matrix a and matrix b
have the same length.) The matrix length can range from 1 ... 100, i.e. a length of 2
indicates that matrix a and matrix b contain 32 bits.
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Coils
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Coils
30
Introduction
This chapter describes the instruction element Coils.

Topic Page
General Usage Guidelines 165
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Coils
Short Description
A coil is a discrete output that is turned ON and OFF by power flow in the logic
program. A single coil is tied to a 0xxxx reference in the PLC’s state RAM. Because
output values are updated in state RAM by the PLC, a coil may be used internally in
the logic program or externally via the I/O map to a discrete output unit in the control
system. When a coil is ON, it either passes power to a discrete output circuit or
changes the state of an internal relay contact in state RAM.
Coil Types
There are two types of coils:
z Normal coil -( )-
A normal or non-retentive or normal coil looses state when power to controller is
lost.
When power is removed from a PLC, a normal coil will be turned OFF. Once
power is restored, the coil will always be in the OFF state on the first logic scan.
z Memory-retentive or latched coil -(M)- or -(L)-
A memory-retentive or latched coil does NOT loose state when power to
controller is lost.
If a memory-retentive (or latched) coil is ON at the time a PLC loses power, the
coil will come back up in an ON state when power is restored. The coil will
maintain that ON state for the first logic scan, and then the logic program will take
control.
Coils are referenced as 0xxxx. They may be disabled and forced ON or OFF.
Disabling a coil stops the user programmed logic from changing the state of the coil.
NOTE: Disabled Coils used as destinations in DX function blocks may have their
state overwritten by the function.
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Coils
General Usage Guidelines
Overview
Once a 0x reference number has been assigned to a coil, it cannot be assigned to
any other coils in the logic program.
An 0x reference number can be referenced to any number of relay contacts, which
can then be controlled via the state of the coil with same reference number. Most
panel software packages have a feature called tracing with which you can locate the
positions in ladder logic of the contacts controlled by a coil. Refer to your software
user manual for more details.
Enable/Disable Capabilities for Discrete Values

Via panel software, you may disable a logic coil or a discrete input in your logic
program.
A disable condition will cause the following:
z Input field device to have no control over its assigned 1x logic
z Logic to have no control over the disable 9x value
Memory protection in the PLC must be OFF before you disable or enable a coil or a
discrete input.
NOTE: There is an important exception that you need to be aware of when disabling
coils:
Data transfer functions allow coils in their destination nodes to recognize the current
ON/OFF state of ALL coils, whether those coils are disabled or not, and this
recognition causes the logic to respond accordingly—maybe producing unexpected
and undesirable effects.
If you are expecting a disabled coil to remain disabled in the DX function, your
application may experience unexpected and undesirable effects.
Forcing Discretes ON and OFF

Most panel software also provides FORCE ON and FORCE OFF capabilities. When
a coil or discrete input is disabled, you can change its state from OFF to ON with
FORCE ON, and from ON to OFF with FORCE OFF.
When a coil or discrete input is enabled, it cannot be forced ON or OFF.
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Coils
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COMM - ASCII Communications Function
31007523 8/2010
COMM -
ASCII Communications Function
31
Introduction
This chapter describes the COMM instruction.

Topic Page
Representation 169
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Short Description
The ASCII Communications Function (COMM) block is used to transmit/receive
ASCII data (in the form of a single ASCII character, 1 to 4 integers or 1 to 4
hexadecimal numbers) to or from the simple ASCII port. The COMM instruction
gives you the ability to read and write canned messages to/from ASCII character
input/output devices via one of the built-in communication ports on a Micro PLC or,
if the PLC is a parent, via a comm port on one of the child PLCs on the expansion
link.
NOTE: Available only on the Micro 311, 411, 512, and 612 controllers.
168 31007523 8/2010

Representation
Symbol

Reference Type
Top input 0x, 1x None ON starts the COMM operation
Bottom input 0x, 1x None ON aborts the operation and sets the middle out.
control block 4x INT, The 4xxxx register entered in the top node is the
(top node) UINT first of 10 contiguous holding registers in the
control block.
(For the register usage please see the Register
Usage Table below.
data block 4x INT, The middle node contains the first 4xxxx register
(middle node) UINT of the data block - a table where variable
message data is placed. In a read operation, the
data block is a destination table. In a write
operation the data block is a source table.
length INT, The integer value entered in the bottom node
(bottom node) UINT specifies the length, which is the number of
registers in the data block. The length can range
from 3 through 255.
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Reference Type
(Top output) 0x None Echoes the state of the top input.
Middle output 0x None ON = error detected (for one scan).
Bottom output 0x None ON = operation complete (for one scan).
Register Usage Table

This table details the register usage for the top node.
Register Usage
4xxxx + 0 Operation Code
4xxxx + 1 Error Status
4xxxx + 2 Number of data fields provided/expected
4xxxx + 3 Number of data fields processed
4xxxx + 4 Reserved
4xxxx + 5 Port Number (1 for local, 2 for child #1, 3 for child #2, etc.
4xxxx + 6 Reserved
4xxxx + 7 Reserved
4xxxx + 8 Reserved
4xxxx + 9 Active Status Timer
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COMP: Complement a Matrix
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32
Introduction
This chapter describes the instruction COMP.

Topic Page
Representation 173
31007523 8/2010 171

Short Description
WARNING
DISABLED COILS
Before using the COMP instruction, check for disabled coils. COMP will override
any disabled coils in the destination matrix without enabling them. This can cause
can be changed by the COMP operation.
equipment damage.
The COMP instruction complements the bit pattern, i.e. changes all 0s to 1s and all
1s to 0s, of a source matrix, then copies the complemented bit pattern into a
destination matrix. The entire COMP operation is accomplished in one scan.
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Representation
Symbol

Reference
Top input 0x, 1x None ON = initiates the complement operation
source 0x, 1x, 3x, 4x ANY_BIT First reference in the source matrix, which
(top node) contains the original bit pattern before the
complement operation
destination 0x, 4x ANY_BIT First reference in the destination matrix
(middle node) where the complemented bit pattern will
be posted
length INT, UINT Matrix length; range: 1 ... 100.
(bottom node)
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A COMP Example
When contact 10001 passes power, the bit pattern in the source matrix (registers
40600 and 40601) is complemented, then the complemented bit pattern is posted in
the destination matrix (registers 40602 and 40603). The original bit pattern is
maintained in the source matrix.
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The integer value entered in the bottom node specifies a matrix length, i.e. the
number of registers or 16-bit words in the matrices. Matrix length can range from
1 ... 100. A length of 2 indicates that 32 bits in each matrix will be complemented.
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176 31007523 8/2010

Contacts
31007523 8/2010
Contacts
33
Introduction
This chapter describes the instruction element Contacts.

Topic Page
Representation 179
31007523 8/2010 177

Contacts
Short Description
Contacts are used to pass or inhibit power flow in a ladder logic program.
178 31007523 8/2010

Contacts
Representation
They are discrete, which means each consumes one I/O point in ladder logic. A
single contact can be tied to a 0x or 1x reference number in the PLC’s state RAM,
in which case each contact consumes one node in a ladder network.
Four kinds of contacts are available:
z normally open (N.O.) contacts
z normally closed (N.C.) contacts
z positive transitional (P.T.) contacts
z negative transitional (N.T.) contacts
Referencing Normally Open/Normally Closed Contacts

Normally open -| |- and normally closed -|\|- contacts may be referenced by inputs
(1xxxx) or coils (0xxxx).
Field Device state vs. Programmed Contact Flow

Field Device Programmed Contact Field Contact Closed Field Contact Open
-| |- -| |- Passes Power
-|\|- Passes Power
-|\|- -| |- Passes Power
Passes Power
Referencing Transitional Contacts

Transitional contacts positive -| ↑ |- and negative -| ↓ |- contacts may be referenced
by inputs (1xxxx) or coils (0xxxx).
State Table Transition Power Flow at Transition

-|↑|- Off to On On 1 Scan Power
-|↓|- On to Off Off Flow Pulse
NOTE: A transitional contact will pass power continuously if the referenced coil is
skipped by a SKP instruction or by the segment scheduler. A transitional contact
may not pass power if it is referenced to an input that has been scheduled to read
from the I/O drop more than once per scan via the segment scheduler.
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Contacts
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CONV - Convert Data
31007523 8/2010
CONV - Convert Data
34
Introduction
This chapter describes the instruction CONV.

Topic Page
Representation 183
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CONV - Convert Data
Short Description
The Convert block is a 484-replacement instruction, and it is one of four replacement
instructions. The CONV block is used to convert:
z discrete data to a holding register
z holding-register data to discrete data
The conversion can be either:
z binary to binary
z BCD to binary (discrete to register)
z binary to BCD (register to discrete)
This block uses 12 bits in 12 bits out, but if the conversion is straight binary to binary,
bits 11 and 12 are forced off.
In converting discretes to a holding register, the source is specified as a constant
which implies a 1xxxx and the destination is specified as a constant which implies
a 4xxxx (for example, 00049 implies 40049).
In converting a register to output discretes, the source is specified as a holding
register (4xxxx) and the destination is specified as a constant which implies a 0xxxx.
For example 00032 implies 12 coils with 00032.
NOTE: Take precaution when converting register data to discretes as coils may
inadvertently be activated.
NOTE: Available only on the 984-351 and 984-455 PLCs.
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CONV - Convert Data
Representation
Symbol
Parameters State RAM Reference Data Type Meaning

Top input 0x, 1x None ON initiates specified operation
Bottom input 0x, 1x None ON = Binary
OFF = BCD
source 4x INT, UINT Converts content of register
(top node)
register 3x INT, UINT
(bottom node)
Top output 0x None Operation successful
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CONV - Convert Data
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CTIF - Counter, Timer, and Interrupt Function
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CTIF - Counter, Timer, and

Interrupt Function
35
Introduction
This chapter describes the CTIF instruction.

Topic Page
Representation 187
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Short Description
The CTIF block is used by a parent PLC to access child functions over an I/O
expansion bus. The parent function block will complete in the same scan. If multiple
blocks exist, the last one executed will be used.
The CTIF instruction is used with the Micro PLCs to set up the inputs for hard-wired
interrupt and/or hard-wired counter/timer operations. This instruction always starts
and finishes in the same scan. The CTIF instruction is a configuration/operation tool
for Modicon Micro PLCs that contain hardware interrupts (all models except the
110CPU311 models). The actual counter/timer and interrupts are in the PLC
hardware, and the CTIF instruction is used to set up this hardware.
NOTE: The counter, timer, interrupt function (CTIF) is only available on Micro 311,
411, 512, and 612 controllers.
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Representation
Symbol

Reference Type
Top input 0x, 1x None ON initiates specified operation
register # 4x INT The 4xxxx register entered in the top node is the
(top node) first of four contiguous holding registers in the
CTIF parameter block.
(For expanded and detailed information about
the four registers please see the section named
Parameter Description, page 188.)
drop number INT The integer value entered in the bottom node
(bottom node) indicates the drop number where the operation
will be performed. The drop number is in the
range of 1 through 5.
Bottom output 0x None Error
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Overview
The top node holds four contiguous registers, 4x through 4x+3. This topic describes
how those registers are used and configured in the top node.
First Register (4x) Usage

The first register, 4x, gives you information either about the type of error generated
or about the type of operation being performed. When you configure the register you
need to consider both how the bits will be used, Bit Usage, and the results of
ON/OFF Combinations.
Here is a graphic demonstrating the Bit Usage for the first register (4x),
and the following table describes the Bit Usage for the first register (4x).
Bit Usage
1-4 Reserved
5-8 Error/Operation type messages
9 - 14 Reserved
15 Set Mode
16 Get Mode
The following table describes the ON/OFF Combinations for bits 5 through 8 and
the error/operation type message generated by the first register (4x).
Bit 5 6 7 8 Description
0 0 0 0 No error detected
0 0 0 1 Unsupported operation type specified
0 0 1 0 Interrupt 2 not supported in this model
0 0 1 1 Interrupt 3 not supported while counter is selected
0 1 0 0 Counter value of 0 specified
0 1 0 1 Counter value too big (counter value > 16,383)
0 1 1 0 Operation type supported only on local drop
0 1 1 1 Specified drop not in I/O map
1 0 0 0 No subroutine for enabled interrupt
1 0 0 1 Remote drop is unhealthy
1 0 1 0 Function not supported remotely
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The following table describes Bit Usage and the ON/OFF Combinations for bits 15
and 16 of the first register (4x).
Bit 15 16 Description
0 0 Set Mode
0 1 Get Mode
Second Register (4x+1) Usage

The second register, 4x+1, allows you to control the set-up for the Set Mode
operation. When you configure the register you need to consider both how the bits
will be used, Bit Usage, and the results of the ON/OFF Combinations.
Here is a graphic demonstrating the Bit Usage for the second register (4x+1).
The following tables describe both Bit Usage and the ON/OFF Combinations for
bits 1 through 16 of the second register (4x+1).
The following table describes Bit Usage and ON/OFF Combinations for bits 1 and
2 of the second register (4x+1).
Bit Usage
1 Terminal-count loading
0 - Disable
1 - Enable
2 Reserved
Bit 3 4 Description
0 1 Disable interrupt service for Interrupt 3
1 0 Enable interrupt service for Interrupt 3
Bit 5 6 Description
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Bit 7 8 Description
0 1 Disable interrupt service for timer/counter interrupt
1 0 Enable interrupt service for timer/counter interrupt
0 1 Disable auto-restart operation
1 0 Enable auto-restart operation
0 1 Stop counter/timer operation
1 0 Start counter/timer operation
0 1 Counter Mode
1 0 Timer Mode
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Third Register (4x+2) Usage

The third register, 4x+2, gives you the status for the Get Mode operation. When you
configure the register you need to consider both how the bits will be used, Bit
Usage, and the results of the ON/OFF Combinations.
Here is a graphic demonstrating the Bit Usage for the third register (4x+2).
The following table describes Bit Usage and ON/OFF Combinations for bits 1
through 16 for the third register (4x+2).
Bit Usage
1 No subroutine for Interrupt 3
4 No subroutine for timer/counter interrupt
5-9 Reserved
10 Interrupt 3
0 - Disabled
1 - Enabled
11 Interrupt 2
0 - Disabled
1 - Enabled
12 Interrupt 1
0 - Disabled
1 - Enabled
13 Interrupt serve for time/counter input
0 - Disabled
1 - Enabled
14 Auto restart operation
0 - Disabled
1 - Enabled
15 Counter/timer operation
0 - Stopped
1 - Started
16 0 - Counter Mode
1 - Timer Mode
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Fourth Register (4x+3) Usage

The fourth register marks the current count value of the timer/counter interrupt. The
count value can be set either by the instruction block (set automatically) or by the
user.
z Get Mode
Instruction block sets the current count.
z Set Mode
User sets the counter/timer.
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DCTR: Down Counter
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DCTR: Down Counter
36
Introduction
This chapter describes the instruction DCTR.

Topic Page
Representation 195
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DCTR: Down Counter
Short Description
The DCTR instruction counts control input transitions from OFF to ON down from a
counter preset value to zero.
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DCTR: Down Counter
Representation
Symbol
*Available on the following:

z E685/785 PLCs
z L785 PLCs
z Quantum Series PLCs

Reference Type
Top input 0x, 1x None OFF → ON = initiates the counter operation
Bottom input 0x, 1x None OFF = accumulated count is reset to preset value
ON = counter accumulating
counter preset 3x, 4x INT, Preset value, can be displayed explicitly as an
(top node) UINT integer (range 1 ... 65 535) or stored in a register
Preset Value: Max. 999 - 16-bit PLC Max. 9999
- 24-bit PLC Max. 65535 - *PLC
accumulated 4x INT, Count value (actual value); which decrements by
count UINT one on each transition from OFF to ON of the top
(bottom node) input until it reaches zero.
Top output 0x None ON = accumulated count = 0
Bottom output 0x None ON = accumulated count > 0
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DCTR: Down Counter
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DIOH: Distributed I/O Health
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37
Introduction
This chapter describes the instruction DIOH.

Topic Page
Representation 199
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Short Description
The DIOH instruction lets you retrieve health data from a specified group of drops
on the distributed I/O network. It accesses the DIO health status table, where health
data for modules in up to 189 distributed drops is stored.
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Representation
Symbol

Reference Type
Top input 0x, 1x None ON = initiates the retrieval of the specified status words from the DIO health table
into the destination table
source INT, The source value entered in the top node is a four-digit constant in the form
(top node) UINT xxyy, where:
z xx is a decimal value in the range 00 ... 16, indicating the slot number in which
the relevant DIO processor resides. The value 00 can always be used to
indicate the Modbus Plus ports on the PLC, regardless of the slot in which it
resides.
z yy is a decimal value in the range 1 ... 64, indicating the drop number on the
appropriate token ring.
For example, if you are interested in retrieving drop status starting at distributed
drop #1 on a network being handled by a DIO processor in slot 3, enter 0301 in
the top node.
destination 4x INT, First holding register in the destination table, i.e. in a block of contiguous
(middle node) UINT, registers where the retrieved health status information is stored
WORD
length INT, Length of the destination table, range 1 ... 64
(bottom node) UINT
Bottom output 0x None ON = invalid source entry
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Source Value (Top Node)

The source value entered in the top node is a four-digit constant in the form xxyy,
where:
Digits Meaning
xx Decimal value in the range 00 ... 16, indicating the slot number in which the
relevant DIO processor resides. The value 00 can always be used to indicate the
Modbus Plus ports on the PLC, regardless of the slot in which it resides.
yy Decimal value in the range 1 ... 64, indicating the drop number on the appropriate
token ring
For example, if you are interested in retrieving drop status starting at distributed drop
#1 on a network being handled by a DIO processor in slot 3, enter 0301 in the top
node.
Length of Destination Table (Bottom Node)

The integer value entered in the bottom node specifies the length, i.e. the number of
4x registers, in the destination table. The length is in the range 1 ... 64.
NOTE: If you specify a length that excedes the number of drops available, the
instruction will return status information only for the drops available. For example, if
you specify the 63rd drop number (yy) in the top node register and then request a
length of 5, the instruction will give you only two registers (the 63rd and 64th drop
status words) in the destination table.
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DISA - Disabled Discrete Monitor
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38
Introduction
This chapter describes the instruction DISA.

Topic Page
Representation 203
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Short Description
The Disabled Discrete Monitor (DISA) is a loadable function, an instruction that
monitors disabled coils and inputs. Therefore, DISA monitors the disabled states of
all 0xxxx and 1xxxx addresses.
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Representation
Symbol
NOTE: The NSUP loadable must be loaded prior to loading the DISA loadable.

Reference Type
Top input 0x, 1x None Disabled coils table
coils 4x INT, UINT Number of disabled coils found (even if > NNN)
(top node)
4x+# INT, UINT Address of ‘#’ disabled coil found
inputs 4y INT, UINT Number of disabled input discretes found
(middle node) (even if > NNN)
4y+# INT, UINT Address of ‘#’’ disabled discrete found
length INT, UINT Passes power when top input receives power
(bottom node)
Top output 0x None ON if disabled coils are found
Middle output 0x None ON if disabled inputs are found
Bottom output 0x None Echoes state of top input
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DIV: Divide
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DIV: Divide
39
Introduction
This chapter describes the instruction DIV.

Topic Page
Representation 207
Example 209
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DIV: Divide
Short Description
The DIV instruction divides unsigned value 1 (its top node) by unsigned value 2 (its
middle node) and posts the quotient and remainder in two contiguous holding
registers in the bottom node.
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DIV: Divide
Representation
Symbol
*Available on the following:

z E685/785 PLCs
z L785 PLCs
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DIV: Divide

Reference
Top input 0x, 1x None ON = value 1 divided by value 2
Middle input 0x, 1x None ON = decimal remainder
OFF = fraction remainder
value 1 3x, 4x INT, UINT Dividend, can be displayed explicitly as an
(top node) integer (range 1 ... 9999)* or stored in two
contiguous registers (displayed for high-
order half, implied for low-order half)
*Max. 999 - 16 bit Max. 9999 - 24 bit Max.
65535 - *PLC (See availability list above.)
value 2 3x, 4x INT, UINT Divisor, can be displayed explicitly as an
(middle node) integer (range 1 ... 9999) or stored in a
register
result 4x INT, UINT First of two contiguous holding registers:
/remainder displayed: result of division
(bottom node) implied: remainder (either a decimal or a
fraction, depending on the state of middle
input)
Top output 0x None ON = division successful
Middle output 0x None ON = overflow:
if result > 9999*, a 0 value is returned
Bottom output 0x None ON = value 2 = 0
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DIV: Divide
Example
Quotient of Instruction DIV

The state of the middle input indicates whether the remainder will be expressed
as a decimal or as a fraction. For example, if value 1 = 8 and value 2 = 3, the decimal
remainder (middle input ON) is 6666; the fractional remainder (middle input OFF)
is 2.
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DIV: Divide
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DLOG: Data Logging for PCMCIA Read/Write Support
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DLOG: Data Logging for

PCMCIA Read/Write Support
40
Introduction
This chapter describes the instruction DLOG.

Topic Page
Representation 213
Run Time Error Handling 216
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Short Description
NOTE: This instruction is only available with the PLC family TSX Compact.
PCMCIA read and write support consists of a configuration extension to be
implemented using a DLOG instruction. The DLOG instruction provides the facility
for an application to copy data to a PCMCIA flash card, copy data from a PCMCIA
flash card, erase individual memory blocks on a PCMCIA flash card, and to erase
an entire PCMCIA flash card. The data format and the frequency of data storage are
controlled by the application.
NOTE: The DLOG instruction will only operate with PCMCIA linear flash cards that
use AMD flash devices.
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Representation
Symbol

Reference Type
Top input 0x, 1x None ON = DLOG operation enabled, it should remain ON
until the operation has completed successfully or an
error has occurred.
Middle input 0x, 1x None ON = stops the currently active operation
control block 4x INT, First of five contiguous registers in the DLOG control
(top node) UINT block
Control Block (Top Node), page 214.)
data area 4x INT, First 4x register in a data area used for the source or
(middle node) UINT destination of the specified operation
(For expanded and detailed information please see Data
Area (Middle Node), page 215.)
length INT, Maximum number of registers reserved for the data
(bottom node) UINT area, range: 0 ... 100.
Middle output 0x None ON = error during DLOG operation (operation
terminated unsuccessfully)
Bottom output 0x None ON = DLOG operation finishes successfully (operation
successful)
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Control Block (Top Node)

The 4x register entered in the top node is the first of five contiguous registers in the
DLOG control block.
The control block defines the function of the DLOG command, the PCMCIA flash
card window and offset, a return status word, and a data word count value.
Register Function Content

Displayed Error Status Displays DLOG errors in HEX values
First implied Operation Type 1 = Write to PCMCIA Card
2 = Read to PCMCIA Card
3 = Erase One Block
4 = Erase Entire Card Content
Second Window This register identifies a particular block (PCMCIA
implied (Block Identifier) memory window) located on the PCMCIA card
(1 block=128k bytes)
The number of blocks are dependent on the memory
size of the PCMCIA card. (e.g.. 0 ... 31 Max. for a 4Meg
PCMCIA card).
Third implied Offset Particular range of bytes located within a particular
(Byte Address block on the PCMCIA card.
within the Block) Range: 1 ... 128k bytes
Fourth implied Count Number of 4x registers to be written or read to the
PCMCIA card. Range: 0 ... 100.
NOTE: PCMCIA Flash Card address are address on a Window:Offset basis.

Windows have a set size of 128k bytes (65 535 words (16-bit values)). No Write or
Read operation can cross the boundary from one window to the next. Therefore,
offset (third implied register) plus length (fourth implied register) must always be less
or equal to 128k bytes (65 535 words).
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Data Area (Middle Node)

The 4x register entered in the middle node is the first register in a contiguous block
of 4x word registers, that the DLOG instruction will use for the source or destination
of the operation specified in the top node’s control block.
Operation State Ram Reference Function

Write 4x Source Address
Read 4x Destination Address
Erase Block none None
Erase Card none None
Length (Bottom Node)

The integer value entered in the bottom node is the length of the data area, i.e., the
maximum number of words (registers) allowed in a transfer to/from the PCMCIA
flash card. The length can range from 0 ... 100.
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Run Time Error Handling
Error Codes
The displayed register of the control block contains the following DLOG errors in
Hex-code.
Error Code in Hex Content

1 The count parameter of the control block > the DLOG block length
during a WRITE operation (01)
2 PCMCIA card operation failed when intially started
(write/read/erase)
3 PCMCIA card operation failed during execution (write/read/erase)
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DMTH - Double Precision Math
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41
Introduction
This chapter describes the four double precision math operations executed by the
instruction DMTH. The four operations are addition, subtraction, multiplication, and
division.

Topic Page
Representation 219
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Short Description
The Double Precision Math (DMTH) instruction performs double precision addition,
subtraction, multiplication, or division (set by bottom node). DMTH uses 2 registers
appended together to form one operand.
Each DMTH instruction operates on the same two operands.
z OP1 = 4x, 4x + 1 (top node)
z OP2 = 4y, 4y + 1 (middle node)
Function Codes
The DMTH instruction performs any one of four possible double precision math
operations. DMTH performs the operation by calling a function. To call the desired
function enter a function code in the bottom node. Function codes range from 1 ... 4.
Code DMTH Function Function Performed Result Registers

1 Double Precision Add (OP1) + (OP 2) (4y + 3, 4y + 4)
Addition
2 Double Precision Subtract (OP1) - (OP 2) (4y + 2, 4y + 3)
Subtraction
3 Double Precision Multiply (OP1) * (OP 2) (4y + 2, 4y + 3)
Multiplication
(4y + 4, 4y + 5)
4 Double Precision Divide (OP1)\(OP 2) (4y + 2, 4y + 3) quotient
Division (4y + 4, 4y + 5) remainder
Notes:
z For numbers spread over more than one register, the least significant 4 digits are
stored in the highest holding register.
z Results, flags, and remainders are stored in the registers following OP2.
z Registers not used by the chosen math function may be used for other purposes.
z The Subtract Function uses the outputs to indicate the result of comparison
between Operands OP1 and OP2.
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Representation
Overview
This topic describes the addition, subtraction, multiplication, and division operations,
which are the four operations performed by the instruction DMTH. Each operations
has a symbol, which is a graphical representation of the instruction, and a
parameter description, which is a table-format representation of the instruction.
Symbol -Addition
Representation of the instruction for the addition operation
Parameter Description - Addition

Description of the instruction’s parameters for the addition operation

Reference Type
Top input 0x, 1x None ON adds operands and posts sum in designated registers.
operand 1 4x INT, The first of two contiguous 4xxxx registers is entered in the top node. The
(top node) UINT second 4xxxx register is implied. Operand 1 is stored here.
Each register holds a value in the range 0000 through 9999, for a
combined double precision value in the range 0 through 99,999,999. The
high-order half of operand 1 is stored in the displayed register, and the low-
order half is stored in the implied register.
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Reference Type
operand 2 and 4x INT, The first of six contiguous 4x registers is entered in the middle node.
sum UINT The remaining five registers are implied:
(middle node) z The displayed register and the first implied register store the high-order
and low-order halves of operand 2, respectively, for a combined double
precision value in the range 0 through 99,999,999
z The value stored in the second implied register indicates whether an
overflow condition exists (a value of 1 = overflow)
z The third and fourth implied registers store the high-order and low-order
halves of the double precision sum, respectively
z The fifth implied register is not used in the calculation but must exist in
state RAM
Middle output 0x None On = operand out of range or invalid
Symbol - Subtraction
Representation of the instruction for the subtraction operation
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Parameter Description - Subtraction

Description of the instruction’s parameters for the subtraction operation

Reference Type
Top input 0x, 1x None ON subtracts operand 2 from operand 1 and posts difference in designated
registers.
(top node) UINT second 4xxxx register is implied. Operand 1 is stored here.
Each register holds a value in the range 0000 through 9999, for a combined
double precision value in the range 0 through 99,999,999. The high-order half of
operand 1 is stored in the displayed register, and the low-order half is stored in
the implied register.
operand 2 4x INT, The first of six contiguous 4xxxx registers is entered in the middle node.
difference UINT The remaining five registers are implied:
(middle node) z The displayed register and the first implied register store the high-order and
low-order halves of operand 2, respectively, for a combined double precision
value in the range 0 through 99,999,999
z The value stored in the second implied register indicates whether an overflow
condition exists (a value of 1 = overflow)
z The third and fourth implied registers store the high-order and low-order
halves of the double precision sum, respectively
z The fifth implied register is not used in the calculation but must exist in state
RAM
Top output 0x None ON = operand 1 > operand 2
Middle output 0x None ON = operand 1 = operand 2
Bottom output 0x None ON = operand 1 < operand 2
Symbol - Multiplication
Representation of the instruction for the multiplication operation
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Parameter Description - Multiplication

Description of the instruction’s parameters for the multiplication operation

Reference Type
Top input 0x, 1x None ON = operand 1 x operand 2 and product posted in designated registers.
(top node) UINT second 4xxxx register is implied. Operand 1 is stored here. The second 4x
register is implied.
Each register holds a value in the range 0000 through 9999, for a combined
double precision value in the range 0 through 99,999,999. The high-order
half of operand 1 is stored in the displayed register, and the low-order half
is stored in the implied register.
operand 4x INT, The first of six contiguous 4xxxx registers is entered in the middle node.
2/product UINT The remaining five registers are implied:
(middle node) z The displayed register and the first implied register store the high-order
and low-order halves of operand 2, respectively, for a combined double
z The last four implied registers store the double precision product in the
range 0 through 9,999,999,999,999,999
Middle output 0x None ON = operand out of range
Symbol - Division
Representation of the instruction for the division operation
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Parameter Description - Division

Description of the instruction’s parameters for the division operation

Reference Type
Top input 0x, 1x None ON = operand 1 divided by operand 2 and result posted in designated
registers.
OFF = fractional remainder
(top node) UINT second 4xxxx register is implied. Operand 1 is stored here. The second 4x
Each register holds a value in the range 0000 through 9999, for a
combined double precision value in the range 0 through 99,999,999. The
high-order half of operand 1 is stored in the displayed register, and the low-
operand 2 4x INT, The first of six contiguous 4x registers is entered in the middle node.
quotient UINT The remaining five registers are implied:
remainder z The displayed register and the first implied register store the high-order
(middle node) and low-order halves of operand 2, respectively, for a combined double
Note: Since division by 0 is illegal, a 0 value causes an error; an error
trapping routine sets the remaining middle-node registers to 0000 and
turns the bottom output ON.
z The second and third implied registers store an eight-digit quotient
z The fourth and fifth implied registers store the remainder. If the
remainder is expressed as a fraction, it is eight digits long and both
registers are used, if the remainder is expressed as a decimal, it is four
digits long and only the fourth implied register is used
Middle output 0x None ON = an operand out of range
Bottom output 0x None On = operand 2 is 0
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DRUM: DRUM Sequencer
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42
Introduction
This chapter describes the instruction DRUM.

Topic Page
Representation 227
31007523 8/2010 225

Short Description
Loadables. For further information, see Installation of DX Loadables, page 75."
The DRUM instruction operates on a table of 4x registers containing data
representing each step in a sequence. The number of registers associated with this
step data table depends on the number of steps required in the sequence. You can
pre-allocate registers to store data for each step in the sequence, thereby allowing
you to add future sequencer steps without having to modify application logic.
DRUM incorporates an output mask that allows you to selectively mask bits in the
register data before writing it to coils. This is particularly useful when all physical
sequencer outputs are not contiguous on the output module. Masked bits are not
altered by the DRUM instruction, and may be used by logic unrelated to the
sequencer.
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Representation
Symbol
*Available on the following

z E685/785 PLCs
z L785 PLCs
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Reference Type
Top input 0x, 1x None ON = initiates DRUM sequencer
Middle input 0x, 1x None ON = step pointer increments to next step
Bottom input 0x, 1x None ON = reset step pointer to 0
step pointer 4x INT, Current step number
(top node) UINT
step data table 4x INT, First register in a table of step data information
(middle node) UINT (For expanded and detailed information please
see Step Data Table (Middle Node), page 229.)
length INT, Number of application-specific registers used in
(bottom node) UINT the step data table, range: 1 .. 999
Length:Max. 255 - 16-bit PLC Max. 999 - 24-bit
PLC Max. 65535 - *PLC
Middle output 0x None ON = step pointer value = length
Bottom output 0x None ON = Error
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Step Pointer (Top Node)

The 4x register entered in the top node stores the current step number. The value
in this register is referenced by the DRUM instruction each time it is solved. If the
middle input to the block is ON, the contents of the register in the top node are
incremented to the next step in the sequence before the block is solved.
Step Data Table (Middle Node)

The 4x register entered in the middle node is the first register in a table of step data
information.
The first six registers in the step data table hold constant and variable data required
to solve the block:
Register Name Content

Displayed masked output data Loaded by DRUM each time the block is solved;
contains the contents of the current step data
register masked with the outputmask register
First implied current step data Loaded by DRUM each time the block is solved;
contains data from the step pointer, causes the
block logic to automatically calculate register
offsets when accessing step data in the step data
table
Second implied output mask Loaded by user before using the block, DRUM will
not alter output mask contents during logic solve;
contains a mask to be applied to the data for each
sequencer step
Third implied machine ID number Identifies DRUM/ICMP blocks belonging to a
specific machine configuration; value range: 0 ... 9
999 (0 = block not configured); all blocks belonging
to same machine configuration have the same
machine ID number
Fourth implied profile ID number Identifies profile data currently loaded to the
sequencer; value range: 0... 9 999 (0 = block not
configured); all blocks with the same machine ID
number must have the same profile ID number
Fifth implied steps used Loaded by user before using the block, DRUM will
not alter steps used contents during logic solve;
contains between 1 ... 999 for 24 bit CPUs,
specifying the actual number of steps to be solved;
the number must be greater or less than the table
length in the bottom node
The remaining registers contain data for each step in the sequence.
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The integer value entered in the bottom node is the length, i.e., the number of
application-specific registers used in the step data table. The length can range from
1 ... 999 in a 24-bit CPU.
The total number of registers required in the step data table is the length + 6. The
length must be greater or equal to the value placed in the steps used register in the
middle node.
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DV16: Divide 16 Bit
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DV16: Divide 16 Bit
43
Introduction
This chapter describes the instruction DV16.

Topic Page
Representation 233
Example 235
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DV16: Divide 16 Bit
Short Description
The DV16 instruction performs a signed or unsigned division on the 16-bit values in
the top and middle nodes (value 1 / value 2), then posts the quotient and remainder
in two contiguous 4x holding registers in the bottom node.
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DV16: Divide 16 Bit
Representation
Symbol
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DV16: Divide 16 Bit

Reference
Top input 0x, 1x None ON = enables value 1 / value 2
value 1 3x, 4x INT, UINT Dividend, can be displayed explicitly as an
(top node) integer (range 1 ... 65 535) or stored in two
contiguous registers (displayed for high-
order half, implied for low-order half)
value 2 3x, 4x INT, UINT Divisor, can be displayed explicitly as an
(middle node) integer (range 1 ... 65 535, enter e.g.
#65535) or stored in a register
quotient 4x INT, UINT First of two contiguous holding registers:
(bottom node) displayed: result of division
implied: remainder (either a decimal or a
fraction, depending on the state of middle
input)
Top output 0x None ON = Divide operation completed
successfully
Middle output 0x None ON = overflow:
quotient > 65 535 in unsigned operation
-32 768 > quotient > 32 767 in signed
operation
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DV16: Divide 16 Bit
Example
Quotient of Instruction DV16

The state of the middle input indicates whether the remainder will be expressed as
a decimal or as a fraction. For example, if the middle input is ON and value 1 = 8 and
value 2 = 3, the quotient has a value of 2 in the Result register and a value of 6666
in the Remainder register.
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DV16: Divide 16 Bit
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Instruction Descriptions (E)
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III
Introduction
In this part all instruction descriptions start with E.

44 EARS - Event/Alarm Recording System 239
45 EMTH: Extended Math 247
46 EMTH-ADDDP: Double Precision Addition 253
47 EMTH-ADDFP: Floating Point Addition 259
48 EMTH-ADDIF: Integer + Floating Point Addition 263
49 EMTH-ANLOG: Base 10 Antilogarithm 267
50 EMTH-ARCOS: Floating Point Arc Cosine of an Angle 271
(in Radians)
51 EMTH-ARSIN: Floating Point Arcsine of an Angle (in Radians) 277
52 EMTH-ARTAN: Floating Point Arc Tangent of an Angle 281
(in Radians)
53 EMTH-CHSIN: Changing the Sign of a Floating Point Number 287
54 EMTH-CMPFP: Floating Point Comparison 293
55 EMTH-CMPIF: Integer-Floating Point Comparison 299
56 EMTH-CNVDR: Floating Point Conversion of Degrees to 305
Radians
57 EMTH-CNVFI: Floating Point to Integer Conversion 311
58 EMTH-CNVIF: Integer to Floating Point Conversion 317
59 EMTH-CNVRD: Floating Point Conversion of Radians to 323
Degrees
60 EMTH-COS: Floating Point Cosine of an Angle (in Radians) 329
61 EMTH-DIVDP: Double Precision Division 333
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62 EMTH-DIVFI: Floating Point Divided by Integer 339
63 EMTH-DIVFP: Floating Point Division 343
64 EMTH-DIVIF: Integer Divided by Floating Point 347
65 EMTH-ERLOG: Floating Point Error Report Log 351
66 EMTH-EXP: Floating Point Exponential Function 357
67 EMTH-LNFP: Floating Point Natural Logarithm 363
68 EMTH-LOG: Base 10 Logarithm 369
69 EMTH-LOGFP: Floating Point Common Logarithm 375
70 EMTH-MULDP: Double Precision Multiplication 381
71 EMTH-MULFP: Floating Point Multiplication 387
72 EMTH-MULIF: Integer x Floating Point Multiplication 391
73 EMTH-PI: Load the Floating Point Value of "Pi" 397
74 EMTH-POW: Raising a Floating Point Number to an Integer 403
Power
75 EMTH-SINE: Floating Point Sine of an Angle (in Radians) 407
76 EMTH-SQRFP: Floating Point Square Root 413
77 EMTH-SQRT: Floating Point Square Root 419
78 EMTH-SQRTP: Process Square Root 425
79 EMTH-SUBDP: Double Precision Subtraction 431
80 EMTH-SUBFI: Floating Point - Integer Subtraction 437
81 EMTH-SUBFP: Floating Point Subtraction 443
82 EMTH-SUBIF: Integer - Floating Point Subtraction 449
83 EMTH-TAN: Floating Point Tangent of an Angle (in Radians) 453
84 ESI: Support of the ESI Module 457
85 EUCA: Engineering Unit Conversion and Alarms 475
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EARS - Event/Alarm Recording System
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EARS - Event/Alarm
Recording System
44
Introduction
This chapter describes the instruction EARS.

Topic Page
Representation 241
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Short Description
The EARS block is loaded to a PLC used in an alarm/event recording system. An
EARS system requires that the PLC work in conjunction with a human-machine
interface (HMI) host device that runs a special offline software package. The PLC
monitors a specified group of events for changes in state and logs change data into
a buffer. The data is then removed by the host over a high speed network such as
Modbus Plus. The two devices comply with a defined handshake protocol that
ensures that all data detected by the PLC is accurately represented in the host.
PLC Functions in an Event/Alarm Recording System

When a PLC is employed in an EARS environment, it is set up to maintain and
monitor two tables of 4xxxx registers, one containing the current state of a set of
user-defined events and one containing the history of the most recent state of these
events. Event states are stored as bit representations in the 4xxxx registers; a bit
value of 1 signifying an ON state and a bit value of 0 signifying an OFF state. Each
table can contain up to 62 registers, allowing you to monitor the states of up to 992
events.
When the PLC detects a change between the current state bit and the history bit for
an event, the EARS instruction prepares a two word message and places it in a
buffer where they can be off-loaded to a host HMI.
This message contains:
z a time stamp representing the time span from midnight to 24:00 hours in tenths
of a second
z a transition flag indicating that the event is either a positive or negative transition
with respect to the event state
z a number indicating which event has occurred
Host to PLC Interaction

The host HMI device must be able to read and write PLC data registers via the
Modbus protocol. A handshake protocol maintains integrity between the host and
the circular buffer running in the PLC. This enables the host to receive events
asynchronously from the buffer at a speed suitable to the host while the PLC detects
event changes and load the buffer at its faster scan rate.
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Representation
Symbol

Reference Type
Top input 0x, 1x None ON = Handshake performed (if needed), validation
check performed, and EARS operations proceeds
OFF = Handshake performed (if needed) and
outstanding transactions are completed
Bottom input 0x, 1x None Buffer Reset: Event table and top node pointers cleared
to 0
state table 4x INT, The 4xxxx register entered in the top node is the first of
pointer / UINT 64 contiguous registers. The first two registers contain
history table values that specify the location and size of the current
(top node) state table.
(For expanded and detailed information please see the
sectionRegister Table (Top Node), page 243.)
The remaining 61 registers are available to store history
data. If all the remaining registers are not required for
the history table, those registers may be used
elsewhere in the program for other purposes, but they
will still be found (by a Modbus search) in the top node
of the EARS block.
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Reference Type
buffer table 4x INT, The 4xxxx register entered in the middle node is the first
(middle node) UINT in a series of contiguous registers uses as a buffer table.
The first five registers are used as follows, and the rest
contain the circular buffer. The circular buffer uses an
even number of registers in the range 2 through 100.
(For expanded and detailed information please see the
topic Data Register Table (Middle Node), page 244.)
The time stamp is encoded in 20 bits as a binary
weighted value that represents the time in an increment
of 0.1 s, starting from midnight of the day on which the
status change was detected:
z 1 hour = 3,600 seconds = 36,000 tenths of a second
z 24 hours = 86,400 seconds = 864,000 tenths of a
second
Note: The real time clock in the chassis mount
controllers has a tenth-of-a-second resolution, but the
other 984s have real time clock chips that resolve only
to a second. An algorithm is used in EARS to provide a
best estimate of tenth-of-a-second resolution; it is
accurate in the relative time intervals between events,
but it may vary slightly from the real time clock.
length INT, The integer value entered in the bottom node is the
(bottom node) UINT length - i.e., actual number of registers allocated for the
circular buffer. The length can range from 2 through
100. Each event requires two registers for data storage.
Therefore, if you wish to trap up to 25 events at any
given time in the buffer, assign a length of 50 in the
bottom node.
Top output 0x None ON = Data in the buffer
Passes power when data is in the queue
Middle output 0x None ON for one scan following communications
acknowledgment from host
Passes power for one scan after getting a host
response
Bottom output 0x None Buffer full: No events can be added until host off-loads
some or until Buffer Reset
Passes power when queue is full. No more events can
be added
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Overview
This topic provides detailed and expanded information in table form for the top and
middle nodes, and the middle node provides further information, which is detailed in
three additional tables.
Therefore, there are five tables in this topic.
z register table (top node)
z data register table (middle node)
z status/error codes table
z event-change data table
z binary weighted value table
Register Table (Top Node)

This is the register table for the top node of EARS.
Register Content
4x Indirect pointer to the current state table for example if the register contains a
value of 5, then the state table begins at register 40005; the indirect pointer
register must be hard-coded by the programmer
4x+1 Contains a value in the range 1 through 62 that specifies the number of
registers in the current state table; this value must be hard-coded by the
programmer
4x+2 First register of the history table, and the remaining registers allocated to the
top node may be used in the table as required; the history table can provide
monitoring for as many as 992 contiguous events (if 16 bits in all the 62
available registers are used)
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Data Register Table (Middle Node)

This is the data register table for the middle node of EARS.
Register Content
4x A value that defines the maximum number of registers the circular buffer may
occupy
4x+1 The Q_take pointer - the pointer to the next register where the host will go to
remove data
4x+2 The low byte contains the Q_put pointer - the pointer to the register in the
circular buffer where the EARS block will begin to place the next state-change
data. The high byte contains the last transaction number received.
4x+3 The Q+count is a value indicating the number of words currently in the circular
buffer.
4x+4 The 4x+4 register gives Status/Error information
For an explanation of the codes and the status/error messages that the code
represents please see the Status/Error Codes Table below.
4x+5 The 4x+5 register
z Gives Event-change data
z Is the first register in a circular buffer
z Is where Event-change data are stored
Each change in event status produces two contiguous registers, and those
registers are explained in the Event-change Data Table below.
Status/Error Codes Table

This is the status/error codes table for the 4x+4 register of the middle node. The
information below provides detailed and expanded information for the 4x+4 register
of the middle node. The code number displayed represents an existing condition.
Code Condition
1 Invalid block length
2 Invalid clock request
3 Invalid clock configuration
4 Invalid state length
5 Invalid queue put
6 Invalid queue take
7 Invalid state
8 Invalid queue count
9 Invalid sequence number
10 Count removed
255 Bad clock chip
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Event-change Data Table

When a change occurs in the 4x+5 register, this register then produces two
contiguous registers. This topic explains how these contiguous registers are used.
Event Data Register 1
The following table describes the Bit Usage.
Bit Usage
1-4 Four most significant bits of Event Time Stamp
5 Transition Event Type
0 = Negative
1 = Positive
6 Reserved
7 - 16 Event Number (1 ... 992)
The following table describes the Bit Usage.
Bit Usage
1 - 16 Sixteen least significant bits of Event Time Stamp
The time stamp is encoded in 20 bits as a binary weighted value that represents the
time in an increment of 0.1 s (tenths of a second), starting from midnight of the day
on which the status change was detected.
z 1 hour = 3600 seconds = 36000 tenths of a second
z 24 hours = 86,400 seconds = 864,000 tenths of a second
For expanded and detailed information on binary weighted values for the time stamp
see the Binary Weighted Values Table below.
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Binary Weighted Values Table

Event Data Register 1 (Most significant nibble (4 bits))
The following table shows binary weighted values for the time stamp, where n is the
relative bit position in the 20-bit time scheme.
2n n 2n n 2n n
1 0 256 8 65536 16
2 1 512 9 131072 17
4 2 1024 10 262144 18
8 3 2048 11 524288 19
16 4 4096 12
32 5 8192 13
64 6 16384 14
128 7 32768 15
NOTE: The real time clock in chassis mount controllers has a tenth-of-a-second
resolution, but the other 984s have real time clock chips that resolve only to a
second. An algorithm is used in EARS to provide a best estimate of tenth-of-a-
second resolution. The algorithmic estimate is accurate in relative time intervals
between events, but the estimate may vary slightly from the real time clock.
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EMTH: Extended Math
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EMTH: Extended Math
45
Introduction
This chapter describes the instruction EMTH.

Topic Page
Representation 249
Floating Point EMTH Functions 252
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EMTH: Extended Math
Short Description
This instruction accesses a library of double-precision math, square root and
logarithm calculations and floating point (FP) arithmetic functions.
The EMTH instruction allows you to select from a library of 38 extended math
functions. Each of the functions has an alphabetical indicator of variable
subfunctions that can be selected from a pulldown menu in your panel software and
appears in the bottom node. EMTH control inputs and outputs are function-
dependent.
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EMTH: Extended Math
Representation
Symbol

Reference Type
Top input 0x, 1x None Depends on the selected EMTH function, see
"Inputs, Outputs and Bottom Node, page 250"
Middle input 0x, 1x None Depends on the selected EMTH function
Bottom input 0x, 1x None Depends on the selected EMTH function
top node 3x, 4x DINT, Two consecutive registers, usually 4x holding
UDINT, registers but, in the integer math cases, either 4x
REAL or 3x registers
middle node 4x DINT, Two, four, or six consecutive registers,
UDINT, depending on the function you are implementing.
REAL
subfunction An alphabetical label, identifying the EMTH
(bottom node) function, see "Inputs, Outputs and Bottom Node,
page 250"
Top output 0x None Depends on the selected EMTH function, see
"Inputs, Outputs and Bottom Node, page 250"
Middle output 0x None Depends on the selected EMTH function
Bottom output 0x None Depends on the selected EMTH function
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EMTH: Extended Math
Inputs, Outputs and Bottom Node

The implementation of inputs to and outputs from the block depends on the EMTH
subfunction you select. An alphabetical indicator of variable subfunctions appears in
the bottom node identifing the EMTH function you have chosen from the library.
You will find the EMTH subfunctions in the following tables.
z Double Precision Math
z Integer Math
z Floating Point Math
Subfunctions for Double Precision Math

Double Precision Math
EMTH Function Subfunction Active Inputs Active Outputs

Addition ADDDP Top Top and Middle
Subtraction SUBDP Top Top, Middle and Bottom
Multiplication MULDP Top Top and Middle
Division DIVDP Top and Middle Top, Middle and Bottom
Subfunctions for Integer Math

Integer Math

Square root SQRT Top Top and Middle
Process square root SQRTP Top Top and Middle
Logarithm LOG Top Top and Middle
Antilogarithm ANLOG Top Top and Middle
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EMTH: Extended Math
Subfunctions for Floating Point Math

Integer-to-FP conversion CNVIF Top Top
Integer + FP ADDIF Top Top
Integer - FP SUBIF Top Top
Integer x FP MULIF Top Top
Integer / FP DIVIF Top Top
FP - Integer SUBFI Top Top
FP / Integer DIVFI Top Top
Integer-FP comparison CMPIF Top Top
FP-to-Integer conversion CNVFI Top Top and Middle
Addition ADDFP Top Top
Subtraction SUBFP Top Top
Multiplication MULFP Top Top
Division DIVFP Top Top
Comparison CMPFP Top Top, Middle and Bottom
Square root SQRFP Top Top
Change sign CHSIN Top Top
Load Value of p PI Top Top
Sine in radians SINE Top Top
Cosine in radians COS Top Top
Tangent in radians TAN Top Top
Arcsine in radians ARSIN Top Top
Arccosine in radians ARCOS Top Top
Arctangent in radians ARTAN Top Top
Radians to degrees CNVRD Top Top
Degrees to radians CNVDR Top Top
FP to an integer power POW Top Top
Exponential function EXP Top Top
Natural log LNFP Top Top
Common log LOGFP Top Top
Report errors ERLOG Top Top and Middle
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EMTH: Extended Math
Floating Point EMTH Functions
Use of Floating Point Functions

To make use of the floating point (FP) capability, the four-digit integer values used
in standard math instructions must be converted to the IEEE floating point format.
All calculations are then performed in FP format and the results must be converted
back to integer format.
The IEEE Floating Point Standard

EMTH floating point functions require values in 32-bit IEEE floating point format.
Each value has two registers assigned to it, the eight most significant bits
representing the exponent and the other 23 bits (plus one assumed bit) representing
the mantissa and the sign of the value.
NOTE: Floating point calculations have a mantissa precision of 24 bits, which
guarantees the accuracy of the seven most significant digits. The accuracy of the
eighth digit in an FP calculation can be inexact.
It is virtually impossible to recognize a FP representation on the programming panel.
Therefore, all numbers should be converted back to integer format before you
attempt to read them.
Dealing with Negative Floating Point Numbers

Standard integer math calculations do not handle negative numbers explicitly. The
only way to identify negative values is by noting that the SUB function block has
turned the bottom output ON.
If such a negative number is being converted to floating point, perform the Integer-
to-FP conversion (EMTH subfunction CNVIF), then use the Change Sign function
(EMTH subfunction CHSIN) to make it negative prior to any other FP calculations.
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EMTH-ADDDP: Double Precision Addition
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EMTH-ADDDP:
Double Precision Addition
46
Introduction
This chapter describes the EMTH subfunction EMTH-ADDDP.

Topic Page
Representation 255
31007523 8/2010 253

Short Description
This instruction is a subfunction of the EMTH instruction. It belongs to the category
"Double Precision Math."
254 31007523 8/2010

Representation
Symbol
31007523 8/2010 255


Reference Type
Top input 0x, 1x None ON = adds operands and posts sum in
designated registers
operand 1 4x DINT, Operand 1 (first of two contiguous registers)
(top node) UDINT The first of two contiguous 4xxxx registers is
entered in the top node. The second 4xxxx
register is implied. Operand 1 is stored here.
Each register holds a value in the range 0000
through 9999, for a combined double precision
value in the range of 0 through 99,999,999. The
high-order half of operand 1 is stored in the
displayed register, and the low-order half is
stored in the implied register.
operand 2 and 4x DINT, Operand 2 and sum (first of six contiguous
sum UDINT registers)
(middle node) The first of six contiguous 4xxxx registers is
entered in the middle node.
The remaining five registers are implied:
z The displayed register and the first implied
register store the high-order and low-order
halves of operand 2, respectively, for a
combined double precision value in the range
0 through 99,999,999
z The value stored in the second implied
register indicates whether an overflow
z The third and fourth implied registers store the
high-order and low-order halves of the double
precision sum, respectively
z The fifth implied register is not used in the
calculation but must exist in state RAM
ADDDP Selection of the subfunction ADDDP
(bottom node)
Middle output 0x None ON = operand out of range or invalid
256 31007523 8/2010

Operand 1 (Top Node)

The first of two contiguous 4x registers is entered in the top node. The second 4x
Register Content
Displayed Register stores the low-order half of operand 1
Range 0 000 ... 9 999, for a combined double precision value in the
range 0 ... 99 999 999
First implied Register stores the high-order half of operand 1
range 0 ... 99 999 999
Operand 2 and Sum (Middle Node)

The first of six contiguous 4x registers is entered in the middle node. The remaining
five registers are implied:
Register Content
Displayed Register stores the low-order half of operand 2, respectively, for a
combined double precision value in the range 0 ... 99 999 999
First implied Register stores the high-order half of operand 2, respectively, for a
Second implied The value stored in this register indicates whether an overflow
Third implied Register stores the low-order half of the double precision sum.
Fourth implied Register stores the high-order half of the double precision sum.
Fifth implied Register is not used in the calculation but must exist in state RAM
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258 31007523 8/2010

EMTH-ADDFP: Floating Point Addition
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EMTH-ADDFP:
Floating Point Addition
47
Introduction
This chapter describes the EMTH subfunction EMTH-ADDFP.

Topic Page
Representation 261
31007523 8/2010 259

Short Description
"Floating Point Math."
260 31007523 8/2010

Representation
Symbol

Reference Type
Top input 0x, 1x None ON = enables FP addition
value 1 4x REAL Floating point value 1 (first of two contiguous
(top node) registers)
The first of two contiguous 4xxxx registers is
entered in the top node. The second register is
implied. FP value 1 in the addition is stored here.
value 2 and sum 4x REAL Floating point value 2 and the sum (first of four
(middle node) contiguous registers)
The first of four contiguous 4xxxx registers is
entered in the middle node. The remaining three
registers are implied. FP value 2 is stored in the
displayed register and the first implied register.
The sum of the addition is stored in FP format in
the second and third implied registers.
ADDFP Selection of the subfunction ADDFP
(bottom node)
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Floating Point Value 1 (Top Node)

The first of two contiguous 4x registers is entered in the top node. The second
Register Content
Displayed Registers store the FP value 1.
First implied
Floating Point Value 2 and Sum (Middle Node)

The first of four contiguous 4x registers is entered in the middle node. The remaining
three registers are implied
Register Content
Displayed Registers store the FP value 2.
First implied
Second implied Registers store the sum of the addition in FP format.
Third implied
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EMTH-ADDIF: Integer + Floating Point Addition
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EMTH-ADDIF:
Integer + Floating Point Addition
48
Introduction
This chapter describes the EMTH subfunction EMTH-ADDIF.

Topic Page
Representation 265
31007523 8/2010 263

Short Description
264 31007523 8/2010

Representation
Symbol

Reference Type
Top input 0x, 1x None ON = initiates integer + FP operation
integer 4x DINT, Integer value (first of two contiguous registers)
implied. The double precision integer value to be
added to the FP value is stored here.
FP and sum 4x REAL FP value and sum (first of four contiguous registers)
(middle node) The first of four contiguous 4xxxx registers is
registers are implied. The displayed register and
the first implied register store the FP value to be
added in the operation, and the sum is posted in the
second and third implied registers. The sum is
posted in FP format.
ADDIF Selection of the subfunction ADDIF
(bottom node)
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Integer Value (Top Node)

Register Content
Displayed The double precision integer value to be added to the FP value is
First implied stored here.
FP Value and Sum (Middle Node)

Register Content
Displayed Registers store the FP value to be added in the operation.
First implied
Second implied The sum is posted here in FP format.
Third implied
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EMTH-ANLOG: Base 10 Antilogarithm
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EMTH-ANLOG:
Base 10 Antilogarithm
49
Introduction
This chapter describes the EMTH subfunction EMTH-ANLOG.

Topic Page
Representation 269
31007523 8/2010 267

Short Description
"Integer Math."
268 31007523 8/2010

Representation
Symbol

Reference Type
Top input 0x, 1x None ON = enables antilog(x) operation
source 3x, 4x INT, Source value
(top node) UINT The top node is a single 4xxxx holding register or 3xxxx input register. The
source value (the value on which the antilog calculation will be performed)
is stored here in the fixed decimal format 1.234 . It must be in the range
of 0 through 7999, representing a source value up to a maximum of 7.999.
result 4x DINT, Result (first of two contiguous registers
(middle node) UDINT The first of two contiguous 4xxxx registers is entered in the middle node.
The second register is implied. The result of the antilog calculation is
posted here in the fixed decimal format 12345678.
The most significant bits are posted in the displayed register, and the least
significant bits are posted in the implied register. The largest antilog value
that can be calculated is 99770006 (9977 posted in the displayed register
and 0006 posted in the implied register).
ANLOG Selection of the subfunction ANLOG
(bottom node)
Middle output 0x None ON = an error or value out of range
31007523 8/2010 269


The top node is a single 4x holding register or 3x input register. The source value,
i.e. the value on which the antilog calculation will be performed, is stored here in the
fixed decimal format 1.234. It must be in the range 0 ... 7 999, representing a source
value up to a maximum of 7.999.
Result (Middle Node)

The first of two contiguous 4x registers is entered in the middle node. The second
register is implied. The result of the antilog calculation is posted here in the fixed
decimal format 12345678:
Register Content
Displayed Most significant bits
First implied Least significant bits
The largest antilog value that can be calculated is 99770006 (9977 posted in the
displayed register and 0006 posted in the implied register).
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EMTH-ARCOS: Floating Point Arc Cosine of an Angle (in Radians)
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EMTH-ARCOS: Floating Point Arc

Cosine of an Angle (in Radians)
50
Introduction
This chapter describes the EMTH subfunction EMTH-ARCOS.

Topic Page
Representation 273
31007523 8/2010 271

Short Description
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Representation
Symbol
31007523 8/2010 273


Reference Type
Top input 0x, 1x None ON = calculates arc cosine of the value
value 4x REAL FP value indicating the cosine of an angle (first of
(top node) two contiguous registers)
implied. An FP value indicating the cosine of an
angle between 0 through Pi radians is stored
here.
This value must be in the range of -1.0 through
+1.0; if not:
z The arc cosine is not computed
z An invalid result is returned
z An error is flagged in the EMTH ERLOG
function
arc cosine of 4x REAL Arc cosine in radians of the value in the top node
value (first of four contiguous registers)
entered in the middle node.The remaining three
registers are implied.
The arc cosine in radians of the FP value in the
top node is posted in the second and third implied
registers. The displayed register and the first
implied register are not used but their allocation in
state RAM is required.
Tip: To preserve registers, you can make the 4x
reference numbers assigned to the displayed
register and the first implied register in the middle
node equal to the register references in the top
node, since the first two middle-node registers are
not used.
ARCOS Selection of the subfunction ARCOS
(bottom node)
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Value (Top Node)

Register Content
Displayed An FP value indicating the cosine of an angle between 0 ... p radians
First implied is stored here.
This value must be in the range of -1.0 ... +1.0;
If the value is not in the range of -1.0 ... +1.0:

z The arc cosine is not computed
z An error is flagged in the EMTH-ERLOG function
Arc Cosine of Value (Middle Node)

Register Content
Displayed Registers are not used but their allocation in state RAM is required.
First implied
Second implied The arc cosine in radians of the FP value in the top node is posted
Third implied here.
NOTE: To preserve registers, you can make the 4x reference numbers assigned to
the displayed register and the first implied register in the middle node equal to the
register references in the top node, since the first two middle-node registers are not
used.
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276 31007523 8/2010

EMTH-ARSIN: Floating Point Arcsine of an Angle (in Radians)
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EMTH-ARSIN: Floating Point

Arcsine of an Angle (in Radians)
51
Introduction
This chapter describes the EMTH subfunction EMTH-ARSIN.

Topic Page
Representation 279
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Short Description
278 31007523 8/2010

Representation
Symbol

Reference Type
Top input 0x, 1x None ON = calculates the arcsine of the value
value 4x REAL FP value indicating the sine of an angle (first of two
(top node) contiguous registers)
The first of two contiguous 4xxxx registers is entered
in the top node. The second register is implied. An FP
value indicating the sine of an angle between -Pi/2
through +Pi/2 radians is stored here.
This value, the sine of an angle, must be in the range
of -1.0 through +1.0; if not:
z The arcsine is not computed
z An error is flagged in the EMTH ERLOG function
arcsine of value 4x REAL Arcsine of the value in the top node (first of four
ARSIN Selection of the subfunction ARSIN
(bottom node)
Top output 0x None ON = operation successful*
*Error is flagged in the EMTH ERLOG function.
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Value (Top Node)

Register Content
Displayed An FP value indicating the sine of an angle between -π/2 ... π/2
First implied radians is stored here. This value (the sine of an angle) must be in
the range of -1.0 ... +1.0;
If the value is not in the range of -1.0 ... +1.0:

z The arcsine is not computed
Arcsine of Value (Middle Node)

Register Content
First implied
Second implied The arcsine of the value in the top node is posted here in FP format.
Third implied
used.
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EMTH-ARTAN: Floating Point Arc Tangent of an Angle (in Radians)
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EMTH-ARTAN: Floating Point Arc

Tangent of an Angle (in Radians)
52
Introduction
This chapter describes the EMTH subfunction EMTH-ARTAN.

Topic Page
Representation 283
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Short Description
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Representation
Symbol
31007523 8/2010 283


Reference Type
Top input 0x, 1x None ON = calculates the arc tangent of the value
value 4x REAL FP value indicating the tangent of an angle (first
(top node) of two contiguous registers)
implied. An FP value indicating the tangent of an
angle between -Pi/2 through +Pi/2 radians is
stored here. Any valid FP value is allowed.
arc tangent of 4x REAL Arc tangent of the value in the top node (first of
value four contiguous registers)
The arc tangent in radians of the FP value in the
implied register are not used but their allocation in
Tip: To preserve registers, you can make the
4xxxx reference numbers assigned to the
displayed register and the first implied register in
the middle node equal to the register references
in the top node, since the first two middle-node
registers are not used.
ARTAN Selection of the subfunction ARTAN
(bottom node)
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Value (Top Node)

Register Content
Displayed An FP value indicating the tangent of an angle between -π/2 ... π/2
First implied radians is stored here. Any valid FP value is allowed.;
Arc Tangent of Value (Middle Node)

Register Content
First implied
Second implied The arc tangent in radians of the FP value in the top node is posted
Third implied here.
used.
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EMTH-CHSIN: Changing the Sign of a Floating Point Number
31007523 8/2010
EMTH-CHSIN: Changing the Sign

of a Floating Point Number
53
Introduction
This chapter describes the EMTH subfunction EMTH-CHSIN.

Topic Page
Representation 289
31007523 8/2010 287

Short Description
288 31007523 8/2010

Representation
Symbol
31007523 8/2010 289


Reference Type
Top input 0x, 1x None ON = changes the sign of FP value
value 4x REAL Floating point value (first of two contiguous
implied. The FP value whose sign will be changed
is stored here.
-(value) 4x REAL Floating point value with changed sign (first of
(middle node) four contiguous registers)
registers are implied.The top node FP value in the
implied register in the middle node are not used
in the operation but their allocation in state RAM
is required.
Tip: To preserve registers, you can make the
4xxxx reference numbers assigned to the
displayed register and the first implied register in
the middle node equal to the register references
in the top node, since the first two middle-node
registers are not used.
CHSIN Selection of the subfunction CHSIN
(bottom node)
290 31007523 8/2010

Floating Point Value (Top Node)

Register Content
Displayed The FP value whose sign will be changed is stored here.
First implied
Floating Point Value with changed sign (Middle Node)

Register Content
First implied
Second implied The top node FP value with changed sign is posted here.
Third implied
used.
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292 31007523 8/2010

EMTH-CMPFP: Floating Point Comparison
31007523 8/2010
EMTH-CMPFP:
Floating Point Comparison
54
Introduction
This chapter describes the EMTH subfunction EMTH-CMPFP.

Topic Page
Representation 295
31007523 8/2010 293

Short Description
294 31007523 8/2010

Representation
Symbol
31007523 8/2010 295


Reference Type
Top input 0x, 1x None ON = initiates comparison
value 1 4x DINT, First floating point value (first of two contiguous
(top node) UDINT registers)
implied. The first FP value (value 1) to be
compared is stored here.
value 2 4x REAL Second floating point value (first of four
registers are implied. The second FP value
(value 2) to be compared is entered in the
displayed register and the first implied register;
the second and third implied registers are not
used in the comparison but their allocation in
CMPFP Selection of the subfunction CMPFP
(bottom node)
Middle output 0x None Please see the table named Middle and Bottom
Output, page 297, which indicates the
relationship created when CMFPF compares two
floating point values.
Bottom output 0x None Please see the table named Middle and Bottom
Output, page 297, which indicates the
relationship created when CMFPF compares two
floating point values.
296 31007523 8/2010

Value 1 (Top Node)

register is implied:
Register Content
Displayed The first FP value (value 1) to be compared is stored here.
First implied
Value 2 (Middle Node)

three registers are implied:
Register Content
Displayed The second FP value (value 2) to be compared is stored here.
First implied
Second implied Registers are not used but their allocation in state RAM is required.
Third implied
Middle and Bottom Output

When EMTH function CMPFP compares its two FP values, the combined states of
the middle and the bottom output indicate their relationship:
Middle Output Bottom Output Relationship

ON OFF value 1 > value 2
OFF ON value 1 < value 2
ON ON value 1 = value 2
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298 31007523 8/2010

EMTH-CMPIF: Integer-Floating Point Comparison
31007523 8/2010
EMTH-CMPIF: Integer-Floating
Point Comparison
55
Introduction
This chapter describes the EMTH subfunction EMTH-CMPIF.

Topic Page
Representation 301
31007523 8/2010 299

Short Description
300 31007523 8/2010

Representation
Symbol
31007523 8/2010 301


Reference
Top input 0x, 1x None ON = initiates comparison
integer 4x DINT, UDINT Integer value (first of two contiguous
The first of two contiguous 4xxxx registers
is entered in the top node. The second
register is implied. The double precision
integer value to be compared is stored
here.
FP 4x REAL Floating point value (first of four
The first of four contiguous 4xxxx registers
is entered in the middle node. The
remaining three registers are implied. The
FP value to be compared is entered in the
displayed register and the first implied
register; the second and third implied
registers are not used in the comparison
but their allocation in state RAM is
required.
CMPIF Selection of the subfunction CMPIF
(bottom node)
Middle output 0x None Please see the table named Middle and
Bottom Output, page 303, which indicates
the relationship created when CMPIF
compares two floating point values.
Bottom output 0x None Please see the table named Middle and
Bottom Output, page 303, which indicates
the relationship created when CMPIF
compares two floating point values.
302 31007523 8/2010


Register Content
Displayed The double precision integer value to be compared is stored here.
First implied
Floating Point Value (Middle Node)

Register Content
Displayed The FP value to be compared is stored here.
First implied
Second implied Registers are not used but their allocation in state RAM is required.
Third implied
Middle and Bottom Output

When EMTH function CMPIF compares its integer and FP values, the combined
states of the middle and the bottom output indicate their relationship:
Middle Output Bottom Output Relationship

ON OFF integer > FP
OFF ON integer < FP
ON ON integer = FP
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304 31007523 8/2010

EMTH-CNVDR: Floating Point Conversion of Degrees to Radians
31007523 8/2010
EMTH-CNVDR: Floating Point

Conversion of Degrees to Radians
56
Introduction
This chapter describes the EMTH subfunction EMTH-CNVDR.

Topic Page
Representation 307
31007523 8/2010 305

Short Description
306 31007523 8/2010

Representation
Symbol
31007523 8/2010 307


Reference
Top input 0x, 1x None ON = initiates conversion of value 1 to
value 2 (result)
value 4x REAL Value in FP format of an angle in degrees
(top node) (first of two contiguous registers)
register is implied. The value in FP format
of an angle in degrees is stored here.
result 4x REAL Converted result (in radians) in FP format
(middle node) (first of four contiguous registers)
remaining three registers are implied.
The converted result in FP format of the
top-node value (in radians) is posted in the
second and third implied registers. The
register are not used but their allocation in
Tip: To preserve registers, you can make
the 4xxxx reference numbers assigned to
the displayed register and the first implied
register in the middle node equal to the
register references in the top node, since
the first two middle-node registers are not
used.
CNVDR Selection of the subfunction CNVDR
(bottom node)
*Error is flagged in the EMTH ERLOG
function.
308 31007523 8/2010

Value (Top Node)

Register Content
Displayed The value in FP format of an angle in degrees is stored here.
First implied
Result in Radians (Middle Node)

Register Content
First implied
Second implied The converted result in FP format of the top-node value (in radians)
Third implied is posted here.
used.
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310 31007523 8/2010

EMTH-CNVFI: Floating Point to Integer Conversion
31007523 8/2010
EMTH-CNVFI: Floating Point to

Integer Conversion
57
Introduction
This chapter describes the EMTH subfunction EMTH-CNVFI.

Topic Page
Representation 313
Runtime Error Handling 315
31007523 8/2010 311

Short Description
312 31007523 8/2010

Representation
Symbol
31007523 8/2010 313


Reference
Top input 0x, 1x None ON = initiates FP to integer conversion
FP 4x REAL Floating point value to be converted (first
(top node) of two contiguous registers)
integer value to be converted to 32-bit FP
format is stored here.
Note: If an invalid integer value ( > 9999)
is entered in either of the two top-node
registers, the FP conversion will be
performed but an error will be reported and
logged in the EMTH ERLOG function (see
page 138). The result of the conversion
may not be correct.
integer 4x DINT, UDINT Integer value (first of four contiguous
(middle node) registers)
FP result of the conversion is posted in the
register are not used in the function but
their allocation in state RAM is required.
the 4x reference numbers assigned to the
used.
CNVFI Selection of the subfunction CNVFI
(bottom node)
function.
Bottom output 0x None OFF = positive integer value
ON = negative integer value
314 31007523 8/2010

Integer Value (Middle Node)

Register Content
First implied
Second implied The double precision integer result of the conversion is stored here.
Third implied This value should be the largest integer value possible that is ≤ the
FP value.
For example, the FP value 3.5 is converted to the integer value 3,
while the FP value -3.5 is converted to the integer value -4.
used.
Runtime Error Handling
Runtime Errors
If the resultant integer is too large for double precision integer format (> 99 999 999),
the conversion still occurs but an error is logged in the EMTH_ERLOG function.
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316 31007523 8/2010

EMTH-CNVIF: Integer to Floating Point Conversion
31007523 8/2010
EMTH-CNVIF: Integer to
Floating Point Conversion
58
Introduction
This chapter describes the EMTH subfunction EMTH-CNVIF.

Topic Page
Representation 319
31007523 8/2010 317

Short Description
318 31007523 8/2010

Representation
Symbol
31007523 8/2010 319


Reference
Top input 0x, 1x None ON = initiates FP to integer conversion
register is implied. The FP value to be
converted is stored here.
result 4x REAL Result (first of four contiguous registers)
(middle node) The first of four contiguous 4xxxx registers
The double precision integer result of the
conversion is stored in the second and
third implied registers. This value should
be the largest integer value possible that is
<= the FP value. For example, the FP
value 3.5 is converted to the integer value
3, while the FP value -3.5 is converted to
the integer value -4.
Note: If the resultant integer is too large for
984 double precision integer format (>
99,999,999), the conversion still occurs
but an error is logged in the EMTH ERLOG
function (see page 138).
The displayed register and the first implied
register in the middle node are not used in
the conversion but their allocation in state
RAM is required.
used.
CNVIF Selection of the subfunction CNVIF
(bottom node)
function.
320 31007523 8/2010


Register Content
Displayed The double precision integer value to be converted to 32-bit FP
First implied format is stored here.

three registers are implied.
Register Content
First implied
Second implied The FP result of the conversion is posted here.
Third implied
used.
Runtime Errors
If an invalid integer value ( > 9 999) is entered in either of the two top-node registers,
the FP conversion will be performed but an error will be reported and logged in the
EMTH_ERLOG function. The result of the conversion may not be correct.
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322 31007523 8/2010

EMTH-CNVRD: Floating Point Conversion of Radians to Degrees
31007523 8/2010
EMTH-CNVRD: Floating Point

Conversion of Radians to Degrees
59
Introduction
This chapter describes the EMTH subfunction EMTH-CNVRD.

Topic Page
Representation 325
31007523 8/2010 323

Short Description
324 31007523 8/2010

Representation
Symbol
31007523 8/2010 325


Reference
Top input 0x, 1x None ON = initiates conversion of value 1 to
value 2
value 4x REAL Value in FP format of an angle in radians
(top node) (first of two contiguous registers)
register is implied. The value in FP format
of an angle in radians is stored here.
result 4x REAL Converted result (in degrees) in FP format
The converted result in FP format of the
top-node value (in degrees) is posted in
the second and third implied registers. The
used.
CNVRD Selection of the subfunction CNVRD
(bottom node)
function.
326 31007523 8/2010

Value (Top Node)

Register Content
Displayed The value in FP format of an angle in radians is stored here.
First implied
Result in Degrees (Middle Node)

Register Content
First implied
Second implied The converted result in FP format of the top-node value (in degrees)
Third implied is posted here.
used.
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328 31007523 8/2010

EMTH-COS: Floating Point Cosine of an Angle (in Radians)
31007523 8/2010
EMTH-COS: Floating Point Cosine

of an Angle (in Radians)
60
Introduction
This chapter describes the EMTH subfunction EMTH-COS.

Topic Page
Representation 331
31007523 8/2010 329

Short Description
330 31007523 8/2010

Representation
Symbol

Reference Type
Top input 0x, 1x None ON = calculates the cosine of the value
value 4x REAL FP value indicating the value of an angle in
(top node) radians (first of two contiguous registers)
implied. An FP value indicating the value of an
angle in radians is stored here.
The magnitude of this value must be < 65536.0; if
not:
z The cosine is not computed
z An error is flagged in the EMTH ERLOG
function
cosine of value 4x REAL Cosine of the value in the top node (first of four
COS Selection of the subfunction COS
(bottom node)
31007523 8/2010 331

Value (Top Node)

Register Content
Displayed An FP value indicating the value of an angle in radians is stored
First implied here. The magnitude of this value must be < 65 536.0.
If the magnitude of this value is ≥ 65 536.0:

z The cosine is not computed
Cosine of Value (Middle Node)

Register Content
First implied
Second implied The cosine of the value in the top node is posted here in FP format.
Third implied
used.
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EMTH-DIVDP: Double Precision Division
31007523 8/2010
EMTH-DIVDP:
Double Precision Division
61
Introduction
This chapter describes the EMTH subfunction EMTH-DIVDP.

Topic Page
Representation 335
31007523 8/2010 333

Short Description
334 31007523 8/2010

Representation
Symbol
31007523 8/2010 335


Reference Type
Top input 0x, 1x None ON = operand 1 divided by operand 2 and result
posted in designated registers.
top node UDINT The first of two contiguous 4xxxx registers is entered
in the top node. The second register is implied. The
top node is stored here. Each register holds a value
in the range of 0000 through 9999, for a combined
double precision value in the range of 0 through
99,999,999. The high-order half of operand 1 is
stored in the displayed register, and the low-order
half is stored in the implied register.
operand 2 4x DINT, Operand 2, quotient and remainder (first of six
quotient UDINT contiguous registers)
remainder The first of six contiguous 4xxxx registers is entered
middle node in the middle node.
halves of operand 2, respectively, for a combined
double precision value in the range of 0 through
99,999,999
Note: Since division by 0 is illegal, a 0 value causes
an error. An error trapping routine sets the remaining
middle-node registers to 0000 and turns the bottom
output ON.
z The second and third implied registers store an
eight-digit quotient
z The fourth and fifth implied registers store the
remainder. If the remainder is expressed as a
fraction, it is eight digits long and both registers
are used; if the remainder is expressed as a
decimal, it is four digits long and only the fourth
implied register is used
DIVDP Selection of the subfunction DIVDP"
(bottom node)
Middle output 0x None ON = an operand out of range or invalid
Bottom output 0x None ON = operand 2 = 0
336 31007523 8/2010


Register Content
Displayed Low-order half of operand 1 is stored here.
First implied High-order half of Operand 1 is stored here.
Each register holds a value in the range 0000 ... 9 999, for a combined double
precision value in the range 0 ... 99 999 999.
Operand 2, Quotient and Remainder (Middle Node)

five registers are implied
Register Content
combined double precision value in the range 0 ... 99 999 999.
Second implied Registers store an eight-digit quotient.
Third implied
Fourth implied Registers store the remainder.
Fifth implied z f it is expressed as a decimal, it is four digits long and only the
fourth implied register is used.
z If it is expressed as a fraction, it is eight digits long and both
registers are used
Runtime Errors
Since division by 0 is illegal, a 0 value causes an error, an error trapping routine sets
the remaining middle-node registers to 0000 and turns the bottom output ON.
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338 31007523 8/2010

EMTH-DIVFI: Floating Point Divided by Integer
31007523 8/2010
EMTH-DIVFI: Floating Point

Divided by Integer
62
Introduction
This chapter describes the EMTH subfunction EMTH-DIVFI.

Topic Page
Representation 341
31007523 8/2010 339

Short Description
340 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = initiates FP / integer operation
FP 4x REAL Floating point value (first of two contiguous registers)
(top node) The first of two contiguous 4xxxx registers is entered in the top
node. The second register is implied. The FP value to be divided
by the integer value is stored here.
integer and 4x DINT, UDINT Integer value and quotient (first of four contiguous registers)
quotient The first of four contiguous 4xxxx registers is entered in the middle
(middle node) node. The remaining three registers are implied. The double
precision integer value that divides the FP value is posted in the
displayed register and the first implied register, and the quotient is
posted in the second and third implied registers. The quotient is
posted in FP format.
DIVFI Selection of the subfunction DIVFI
(bottom node)
31007523 8/2010 341


Register Content
Displayed The FP value to be divided by the integer value is stored here.
First implied
Integer Value and Quotient (Middle Node)

Register Content
Displayed The double precision integer value that divides the FP value is
First implied posted here.
Second implied The quotient is posted here in FP format.
Third implied
342 31007523 8/2010

EMTH-DIVFP: Floating Point Division
31007523 8/2010
EMTH-DIVFP:
Floating Point Division
63
Introduction
This chapter describes the instrcution EMTH-DIVFP.

Topic Page
Representation 345
31007523 8/2010 343

Short Description
344 31007523 8/2010

Representation
Symbol

Reference Type
Top input 0x, 1x None ON = initiates value 1 / value 2 operation
implied. FP value 1, which will be divided by the
value 2, is stored here.
value 2 and 4x REAL Floating point value 2 and the quotient (first of four
quotient contiguous registers)
registers are implied. FP value 2, the value by
which value 1 is divided, is stored in the displayed
register and the first implied register. The quotient
is posted in FP format in the second and third
implied registers.
DIVFP Selection of the subfunction DIVFP
(bottom node)
31007523 8/2010 345


Register Content
Displayed FP value 1, which will be divided by the value 2, is stored here.
First implied
Floating Point Value 2 and Quotient (Middle Node)

Register Content
Displayed FP value 2, the value by which value 1 is divided, is stored here
First implied
Third implied
346 31007523 8/2010

EMTH-DIVIF: Integer Divided by Floating Point
31007523 8/2010
EMTH-DIVIF: Integer
Divided by Floating Point
64
Introduction
This chapter describes the instruction EMTH-DIVIF.

Topic Page
Representation 349
31007523 8/2010 347

Short Description
348 31007523 8/2010

Representation
Symbol

Reference Type
Top input 0x, 1x None ON = initiates integer / FP operation
implied. The double precision integer value to be
divided by the FP value is stored here.
FP and quotient 4x REAL FP value and quotient (first of four contiguous
registers are implied. The displayed register and
the first implied register store the FP value to be
divided in the operation, and the quotient is
posted in the second and third implied registers.
The quotient is posted in FP format.
DIVIF Selection of the subfunction DIVIF
(bottom node)
31007523 8/2010 349


Register Content
Displayed The double precision integer value to be divided by the FP value is
Floating Point Value and Quotient (Middle Node)

Register Content
Displayed The FP value to be divided in the operation is posted here.
First implied
Third implied
350 31007523 8/2010

EMTH-ERLOG: Floating Point Error Report Log
31007523 8/2010
EMTH-ERLOG: Floating
Point Error Report Log
65
Introduction
This chapter describes the instrcution EMTH-ERLOG.

Topic Page
Representation: EMTH - ERLOG - Floating Point Math - Error Report Log 353
31007523 8/2010 351

Short Description
352 31007523 8/2010

Representation: EMTH - ERLOG - Floating Point Math - Error Report Log
Symbol
31007523 8/2010 353


Reference
Top input 0x, 1x None ON = retrieves a log of error types since
last invocation
not used 4x INT, UINT, Not used in the operation (first of two
(top node) DINT, UDINT, contiguous registers)
REAL The first of two contiguous 4xxxx registers
register is implied. These two registers are
not used in the operation but their
allocation in state RAM is required.
error data 4x INT, UINT, Error log register (first of four contiguous
(middle node) DINT, UDINT, registers)
REAL The first of four contiguous 4xxxx registers
is entered in the middle node.
The remaining three registers are implied.
The second implied register is used as the
error log register.
(For expanded and detailed information
about the error log please see the table
Error Log Register, page 355 in the
section Parameter Description.
The third implied register has all its bits
cleared to zero. The displayed register and
the first implied register are not used but
these registers must be allocated but none
are used.
ERLOG Selection of the subfunction ERLOG
(bottom node)
Top output 0x None ON = retrieval successful
Middle output 0x None ON = nonzero values in error log register
OFF = all zeros in error log register
354 31007523 8/2010

Not used (Top Node)

Register Content
Displayed These two registers are not used in the operation but their allocation
First implied in state RAM is required.
Error Data (Middle Node)

Register Content
Displayed Error log register, see table.
First implied This register has all its bits cleared to zero.
Second implied These two registers are not used but their allocation in state RAM is
Third implied required.
register references in the top node, since these registers must be allocated but none
are used.
Error Log Register

Usage of error log register:
Bit Function
1-8 Function code of last error logged
9 - 11 Not used
12 Integer/FP conversion error
13 Exponential function power too large
14 Invalid FP value or operation
15 FP overflow
16 FP underflow
If the bit is set to 1, then the specific error condition exists for that bit.
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356 31007523 8/2010

EMTH-EXP: Floating Point Exponential Function
31007523 8/2010
EMTH-EXP: Floating Point

Exponential Function
66
Introduction
This chapter describes the EMTH subfunction EMTH-EXP.

Topic Page
Representation 359
31007523 8/2010 357

Short Description
358 31007523 8/2010

Representation
Symbol
31007523 8/2010 359


Reference
Top input 0x, 1x None ON = calculates exponential function of
the value
value 4x REAL Value in FP format (first of two contiguous
register is implied. A value in FP format in
the range -87.34 through +88.72 is stored
here.
If the value is out of range, the result will
either be 0 or the maximum value. No error
will be flagged.
result 4x REAL Exponential of the value in the top node
The exponential of the value in the top
node is posted in FP format in the second
and third implied registers. The displayed
register and the first implied register are
not used but their allocation in state RAM
is required.
used.
EXP Selection of the subfunction EXP
(bottom node)
360 31007523 8/2010

Value (Top Node)

Register Content
Displayed A value in FP format in the range -87.34 ... +88.72 is stored here.
First implied If the value is out of range, the result will either be 0 or the maximum
value. No error will be flagged.

Register Content
Displayed These registers are not used but their allocation in state RAM is
First implied required
Second implied The exponential of the value in the top node is posted here in FP
Third implied format.
used.
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362 31007523 8/2010

EMTH-LNFP: Floating Point Natural Logarithm
31007523 8/2010
EMTH-LNFP: Floating Point

Natural Logarithm
67
Introduction
This chapter describes the EMTH subfunction EMTH-LNFP.

Topic Page
Representation 365
31007523 8/2010 363

Short Description
364 31007523 8/2010

Representation
Symbol
31007523 8/2010 365


Reference
Top input 0x, 1x None ON = calculates the natural log of the
value
value 4x REAL Value > 0 in FP format (first of two
register is implied. A value > 0 is stored
here in FP format.
If the value <= 0, an invalid result will be
returned in the middle node and an error
will be logged in the EMTH ERLOG
function.
result 4x REAL Natural logarithm of the value in the top
(middle node) node (first of four contiguous registers)
The natural logarithm of the value in the
top node is posted in FP format in the
used.
LNFP Selection of the subfunction LNFP
(bottom node)
366 31007523 8/2010

Value (Top Node)

Register Content
Displayed A value > 0 is stored here in FP format.
First implied If the value ≤ 0, an invalid result will be returned in the middle node
and an error will be logged in the EMTH-ERLOG function.

Register Content
Second implied The natural logarithm of the value in the top node is posted here in
Third implied FP format.
used.
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368 31007523 8/2010

EMTH-LOG: Base 10 Logarithm
31007523 8/2010
68
Introduction
This chapter describes the EMTH subfunction EMTH-LOG.

Topic Page
Representation 371
31007523 8/2010 369

Short Description
"Integer Math."
370 31007523 8/2010

Representation
Symbol
31007523 8/2010 371


Reference
Top input 0x, 1x None ON = enables log(x) operation
source 3x, 4x DINT, UDINT Source value (first of two contiguous
The first of two contiguous 3xxxx or 4xxxx
registers is entered in the top node. The
second register is implied. The source
value upon which the log calculation will
be performed is stored in these registers.
If you specify a 4xxxx register, the source
value may be in the range of 0 through
99,999,99. The low-order half of the value
is stored in the implied register, and the
high-order half is stored in the displayed
register.
9,999. The log calculation is done on only
the value in the displayed register; the
implied register is required but not used.
result 4x INT, UINT Result
(middle node) The middle node contains a single 4xxxx
holding register where the result of the
base 10 log calculation is posted. The
result is expressed in the fixed decimal
format 1.234 , and is truncated after the
third decimal position. The largest result
that can be calculated is 7.999, which
would be posted in the middle register as
7999.
LOG Selection of the subfunction LOG
(bottom node)
Middle output 0x None ON = an error or value out of range
372 31007523 8/2010


The first of two contiguous 3x or 4x registers is entered in the top node. The second
register is implied. The source value upon which the log calculation will be
performed is stored in these registers.
If you specify a 4x register, the source value may be in the range 0 ... 99 999 99:
Register Content
Displayed The high-order half of the value is stored here.
First implied The low-order half of the value is stored here.
If you specify a 3x register, the source value may be in the range 0 ... 9 999:
Register Content
Displayed The source value upon which the log calculation will be performed is
stored here
First implied This register is required but not used.

The middle node contains a single 4x holding register where the result of the base
10 log calculation is posted. The result is expressed in the fixed decimal format
1.234, and is truncated after the third decimal position.
The largest result that can be calculated is 7.999, which would be posted in the
middle register as 7999.
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374 31007523 8/2010

EMTH-LOGFP: Floating Point Common Logarithm
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EMTH-LOGFP: Floating Point

Common Logarithm
69
Introduction
This chapter describes the EMTH subfunction EMTH-LOGFP.

Topic Page
Representation 377
31007523 8/2010 375

Short Description
376 31007523 8/2010

Representation
Symbol
31007523 8/2010 377


Reference
Top input 0x, 1x None ON = calculates the common log of the
value
value 4x REAL Value > 0 in FP format (first of two
register is implied. A value > 0 is stored
here in FP format.
If the value <= 0, an invalid result will be
returned in the middle node and an error
will be logged in the EMTH ERLOG
function.
result 4x REAL Common logarithm of the value in the top
(middle node) node (first of four contiguous registers)
The common logarithm of the value in the
top node is posted in FP format in the
used.
LOGFP Selection of the subfunction LOGFP
(bottom node)
378 31007523 8/2010

Value (Top Node)

Register Content
Displayed A value > 0 is stored here in FP format.
First implied If the value ≤ 0, an invalid result will be returned in the middle node
and an error will be logged in the EMTH-ERLOG function.

Register Content
Second implied The common logarithm of the value in the top node is posted here in
Third implied FP format.
used.
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380 31007523 8/2010

EMTH-MULDP: Double Precision Multiplication
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EMTH-MULDP:
Double Precision Multiplication
70
Introduction
This chapter describes the EMTH subfunction EMTH-MULDP.

Topic Page
Representation 383
31007523 8/2010 381

Short Description
382 31007523 8/2010

Representation
Symbol
31007523 8/2010 383


Reference
Top input 0x, 1x None ON = Operand 1 x Operand 2
Product posted in designated registers
operand 1 4x DINT, UDINT Operand 1 (first of two contiguous
The first of two contiguous 4x registers is
entered in the top node. The second 4x
register is implied. Operand 1 is stored
here. The second 4x register is implied.
Each register holds a value in the range of
0000 through 9999, for a combined double
precision value in the range of 0 through
99,999,999. The high-order half of
operand 1 is stored in the displayed
register, and the low-order half is stored in
the implied register.
operand 2 / 4x DINT, UDINT Operand 2 and product (first of six
product contiguous registers)
(middle node) The first of six contiguous 4xxxx registers
is entered in the middle node.
z The displayed register and the first
implied register store the high-order
and low-order halves of operand 2,
respectively, for a combined double
precision value in the range 0 through
99,999,999
z The last four implied registers store the
double precision product in the range 0
through 9,999,999,999,999,999
MULDP Selection of the subfunction MULDP
(bottom node)
Middle output 0x None ON = operand out of range
384 31007523 8/2010


Register Content
range 0 ... 99 999 999
range 0 ... 99 999 999
Operand 2 and Product (Middle Node)

Register Content
Second implied These registers store the double precision product in the range 0 ...
Third implied 9 999 999 999 999 999
Fourth implied
Fifth implied
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386 31007523 8/2010

EMTH-MULFP: Floating Point Multiplication
31007523 8/2010
EMTH-MULFP:
Floating Point Multiplication
71
Introduction
This chapter describes the EMTH subfunction EMTH-MULFP.

Topic Page
Representation 389
31007523 8/2010 387

Short Description
388 31007523 8/2010

Representation
Symbol

Reference Type
Top input 0x, 1x None ON = initiates FP multiplication
in the top node. The second register is implied. FP
value 1 in the multiplication operation is stored here.
value 2 and 4x REAL Floating point value 2 and the product (first of four
product contiguous registers)
(middle node) The first of four contiguous 4xxxx registers is entered
in the middle node. The remaining three registers are
implied. FP value 2 in the multiplication operation is
stored in the displayed register and the first implied
register. The product of the multiplication is stored in
FP format in the second and third implied registers.
MULFP Selection of the subfunction MULFP
(bottom node)
31007523 8/2010 389


Register Content
Displayed FP value 1 in the multiplication operation is stored here.
First implied
Floating Point Value 2 and Product (Middle Node)

Register Content
Displayed FP value 2 in the multiplication operation is stored here.
First implied
Second implied The product of the multiplication is stored here in FP format.
Third implied
390 31007523 8/2010

EMTH-MULIF: Integer x Floating Point Multiplication
31007523 8/2010
EMTH-MULIF: Integer x
Floating Point Multiplication
72
Introduction
This chapter describes the EMTH subfunction EMTH-MULIF.

Topic Page
Representation 393
31007523 8/2010 391

Short Description
392 31007523 8/2010

Representation
Symbol
31007523 8/2010 393


Reference
Top input 0x, 1x None ON = initiates integer x FP operation
integer value to be multiplied by the FP
value is stored here.
FP and product 4x REAL FP value and product (first of four
register store the FP value to be multiplied
in the operation, and the product is posted
in the second and third implied registers.
The product is posted in FP format.The
first of four contiguous 4xxxx registers is
entered in the middle node. The remaining
three registers are implied. The displayed
register and the first implied register store
the FP value to be multiplied in the
operation, and the product is posted in the
product is posted in FP format.
MULIF Selection of the subfunction MULIF
(bottom node)
394 31007523 8/2010


Register Content
Displayed The double precision integer value to be multiplied by the FP value
First implied is stored here.
FP Value and Product (Middle Node)

Register Content
Displayed The FP value to be multiplied in the operation is stored here.
First implied
Second implied The product of the multiplication is stored here in FP format.
Third implied
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396 31007523 8/2010

EMTH-PI: Load the Floating Point Value of "Pi"
31007523 8/2010
EMTH-PI: Load the

Floating Point Value of "Pi"
73
Introduction
This chapter describes the EMTH subfunction EMTH-PI.

Topic Page
Representation 399
31007523 8/2010 397

Short Description
398 31007523 8/2010

Representation
Symbol
31007523 8/2010 399


Reference
Top input 0x, 1x None ON = loads FP value of π to middle node
register
not used 4x REAL First of two contiguous registers
(top node) The first of two contiguous 4xxxx registers
register is implied. These registers are not
used but their allocation in state RAM is
required.
FP value of π 4x REAL FP value of π (first of four contiguous
is entered in the middle node.The
The FP value of p is posted in the second
and third implied registers. The displayed
is required.
used.
PI Selection of the subfunction PI
(bottom node)
400 31007523 8/2010

Not used (Top Node)

Register Content
First implied required.
Floating Point Value of π (Middle Node)

Register Content
First implied required.
Second implied The FP value of π is posted here.
Third implied
used.
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402 31007523 8/2010

EMTH-POW: Raising a Floating Point Number to an Integer Power
31007523 8/2010
EMTH-POW: Raising a Floating

Point Number to an Integer Power
74
Introduction
This chapter describes the EMTH subfunction EMTH-POW.

Topic Page
Representation: EMTH - POW - Raising a Floating Point Number to an Integer 405
Power
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Short Description
404 31007523 8/2010

Representation: EMTH - POW - Raising a Floating Point Number to an Integer

Power
Symbol

Reference Type
Top input 0x, 1x None ON = calculates FP value raised to the power of integer
value
FP value 4x REAL FP value (first of two contiguous registers)
(top node) The first of two contiguous 4xxxx registers is entered in
the top node. The second register is implied. The FP
value to be raised to the integer power is stored here.
integer and 4x INT, Integer value and result (first of four contiguous registers)
result UINT The first of four contiguous 4xxxx registers is entered in
(middle node) the middle node.The remaining three registers are
implied.
The bit values in the displayed register must all be
cleared to zero. An integer value representing the power
to which the top-node value will be raised is stored in the
first implied register. The result of the FP value being
raised to the power of the integer value is stored in the
second and third implied registers.
POW Selection of the subfunction POW
(bottom node)
31007523 8/2010 405

FP Value (Top Node)

Register Content
Displayed The FP value to be raised to the integer power is stored here.
First implied
Integer and Result (Middle Node)

Register Content
Displayed The bit values in this register must all be cleared to zero.
First implied An integer value representing the power to which the top-node value
will be raised is stored here.
Second implied The result of the FP value being raised to the power of the integer
Third implied value is stored here.
406 31007523 8/2010

EMTH-SINE: Floating Point Sine of an Angle (in Radians)
31007523 8/2010
EMTH-SINE: Floating Point

Sine of an Angle (in Radians)
75
Introduction
This chapter describes the EMTH subfunction EMTH-SINE.

Topic Page
Representation: EMTH - SINE - Floating Point Math - Sine of an Angle 409
(in Radians)
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Short Description
408 31007523 8/2010

Representation: EMTH - SINE - Floating Point Math - Sine of an Angle (in

Radians)
Symbol
31007523 8/2010 409


Reference
Top input 0x, 1x None ON = calculates the sine of the value
value 4x REAL FP value indicating the value of an angle in
(top node) radians (first of two contiguous registers)
register is implied. An FP value indicating
the value of an angle in radians is stored
here.
The magnitude of this value must be <
65536.0; if not:
z The sine is not computed
z An error is flagged in the EMTH
ERLOG function
sine of value 4x REAL Sine of the value in the top node (first of
(middle node) four contiguous registers)
is entered in the middle node.The
The sine of the value in the top node is
posted in the second and third implied
registers in FP format. The displayed
is required.
used.
SINE Selection of the subfunction SINE
(bottom node)
function.
410 31007523 8/2010

Value (Top Node)

Register Content
If the magnitude is ≥ 65 536.0:

z The sine is not computed
Sine of Value (Middle Node)

Register Content
First implied
Second implied The sine of the value in the top node is posted here in FP format.
Third implied
used.
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412 31007523 8/2010

EMTH-SQRFP: Floating Point Square Root
31007523 8/2010
EMTH-SQRFP:
Floating Point Square Root
76
Introduction
This chapter describes the EMTH subfunction EMTH-SQRFP.

Topic Page
Representation 415
31007523 8/2010 413

Short Description
414 31007523 8/2010

Representation
Symbol
31007523 8/2010 415


Reference
Top input 0x, 1x None ON = initiates square root on FP value
value 4x REAL Floating point value (first of two contiguous
register is implied. The FP value on which
the square root operation is performed is
stored here.
result 4x REAL Result in FP format (first of four contiguous
result of the square root operation is
posted in FP format in the second and third
implied registers. The displayed register
and the first implied register in the middle
node are not used in the operation but
used.
SQRFP Selection of the subfunction SQRFP
(bottom node)
416 31007523 8/2010


Register Content
Displayed The FP value on which the square root operation is performed is

Register Content
First implied
Second implied The result of the square root operation is posted here in FP format.
Third implied
used.
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418 31007523 8/2010

EMTH-SQRT: Floating Point Square Root
31007523 8/2010
EMTH-SQRT:
Floating Point Square Root
77
Introduction
This chapter describes the EMTH subfunction EMTH-SQRT.

Topic Page
Representation 421
31007523 8/2010 419

Short Description
"Integer Math."
420 31007523 8/2010

Representation
Symbol
31007523 8/2010 421


Reference
Top input 0x, 1x None ON = initiates a standard square root
operation
value (the value for which the square root
will be derived) is stored here.
register.
9,999. The square root calculation is done
on only the value in the displayed register;
the implied register is required but not
used.
result 4x DINT, UDINT Result (first of two contiguous registers)
(middle node) Enter the first of two contiguous 4xxxx
registers in the middle node. The second
register is implied. The result of the
standard square root operation is stored
here.
The result is stored in the fixed-decimal
format: 1234.5600. where the displayed
register stores the four-digit value to the
left of the first decimal point and the
implied register stores the four-digit value
to the right of the first decimal point.
Numbers after the second decimal point
are truncated; no round-off calculations
are performed.
SQRT Selection of the subfunction SQRT
(bottom node)
Middle output 0x None ON =source value out of range
422 31007523 8/2010


register is implied. The source value, i.e. the value for which the square root will be
derived, is stored here.
If you specify a 4x register, the source value may be in the range 0 ... 99 999 99:
Register Content
Displayed The high-order half of the value is stored here.
First implied The low-order half of the value is stored here.
If you specify a 3x register, the source value may be in the range 0 ... 9 999:
Register Content
Displayed The square root calculation is done on only the value in the
displayed register
First implied This register is required but not used.

Enter the first of two contiguous 4x registers in the middle node. The second register
is implied. The result of the standard square root operation is stored here in the
fixed-decimal format: 1234.5600.:.
Register Content
Displayed This register stores the four-digit value to the left of the first decimal
point.
First implied This register stores the four-digit value to the right of the first decimal
point.
NOTE: Numbers after the second decimal point are truncated; no round-off
calculations are performed.
31007523 8/2010 423

424 31007523 8/2010

EMTH-SQRTP: Process Square Root
31007523 8/2010
EMTH-SQRTP:
Process Square Root
78
Introduction
This chapter describes the EMTH subfunction EMTH-SQRTP.

Topic Page
Representation 427
Example 430
31007523 8/2010 425

Short Description
"Integer Math."
The process square root function tailors the standard square root function for closed
loop analog control applications. It takes the result of the standard square root result,
multiplies it by 63.9922 (the square root of 4 095) and stores that linearized result in
the middle-node registers.
The process square root is often used to linearize signals from differential pressure
flow transmitters so that they may be used as inputs in closed loop control
operations.
426 31007523 8/2010

Representation
Symbol
31007523 8/2010 427


Reference
Top input 0x, 1x None ON = initiates process square root
operation
will be derived) is stored in these two
registers. In order to generate values that
have meaning, the source value must not
exceed 4095. In a 4xxxx register group the
source value will therefore be stored in the
implied register, and in a 3xxxx register
group the source value will be stored in the
displayed register.
linearized result 4x DINT, UDINT Linearized result (first of two contiguous
is entered in the middle node. The second
register is implied. The linearized result of
the process square root operation is
stored here.
left of the first decimal point and the
implied register stores the four-digit value
to the right of the first decimal point.
Numbers after the second decimal point
are truncated; no round-off calculations
are performed.
SQRTP Selection of the subfunction SQRPT
(bottom node)
Middle output 0x None ON =source value out of range
428 31007523 8/2010


register is implied. The source value, i.e. the value for which the square root will be
derived, is stored here. In order to generate values that have meaning, the source
value must not exceed 4 095.
If you specify a 4x register:
Register Content
Displayed Not used
First implied The source value will be stored here
If you specify a 3x register:
Register Content
Displayed The source value will be stored here
First implied Not used.
Linearized Result (Middle Node)

register is implied. The linearized result of the process square root operation is
stored here n the fixed-decimal format 1234.5600..
Register Content
Displayed This register stores the four-digit value to the left of the first decimal
point.
First implied This register stores the four-digit value to the right of the first decimal
point.
NOTE: Numbers after the second decimal point are truncated; no round-off
calculations are performed.
31007523 8/2010 429

Example
Process Square Root Function

This example gives a quick overview of how the process square root is calculated.
Instruction
Suppose a source value of 2000 is stored in register 300030 of EMTH function

SQRTP.
First, a standard square root operation is performed:
Then this result is multiplied by 63.9922, yielding a linearized result of 2861.63:
The linearized result is placed in the two registers in the middle node:
Register Part of the result

400030 2861 (four-digit value to the left of the first decimal point)
400031 6300 (four-digit value to the right of the first decimal point)
430 31007523 8/2010

EMTH-SUBDP: Double Precision Subtraction
31007523 8/2010
EMTH-SUBDP:
Double Precision Subtraction
79
Introduction
This chapter describes the EMTH subfunction EMTH-SUBDP.

Topic Page
Representation: EMTH - SUBDP - Double Precision Math - Subtraction 433
31007523 8/2010 431

Short Description
432 31007523 8/2010

Representation: EMTH - SUBDP - Double Precision Math - Subtraction
Symbol
31007523 8/2010 433


Reference Type
Top input 0x, 1x None ON = subtracts operand 2 from operand 1 and posts
difference in designated registers
(top node) UDINT The first of two contiguous 4xxxx registers is entered
in the top node. The second 4xxxx register is
implied. Operand 1 is stored here. Each register
holds a value in the range 0000 through 9999, for a
combined double precision value in the range of 0
through 99,999,999. The low-order half of operand 1
is stored in the displayed register, and the high-
operand 2/ 4x DINT, Operand 2 and difference (first of six contiguous
difference UDINT registers)
(middle node) The first of six contiguous 4xxxx registers is entered
in the middle node.
halves of operand 2, respectively, for a combined
double precision value in the range 0 through
99,999,999
z The second and third implied registers store the
high-order and low-order halves, respectively, of
the absolute difference in double precision
format
z The value stored in the fourth implied register
indicates whether or not the operands are in the
valid range (1 = out of range and 0 = in range)
z The fifth implied register is not used in this
calculation but must exist in state RAM
SUBDP Selection of the subfunction SUBDP
(bottom node)
Top output 0x None ON = operand 1 > operand 2
Middle output 0x None ON = operand 1 = operand 2
Bottom output 0x None ON = operand 1 < operand 2
434 31007523 8/2010


Register Content
range 0 ... 99 999 999
range 0 ... 99 999 999
Operand 2 and Product (Middle Node)

Register Content
Displayed Register stores the low-order half of operand 2 for a combined
double precision value in the range 0 ... 99 999 999
First implied Register stores the high-order half of operand 2 for a combined
double precision value in the range 0 ... 99 999 999
Second implied This register stores the low-order half of the absolute difference in
double precision format
Third implied This register stores the high-order half of the absolute difference in
double precision format
Fourth implied 0 = operands in range
1 = operands out of range
Fifth implied This register is not used in the calculation but must exist in state
RAM.
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436 31007523 8/2010

EMTH-SUBFI: Floating Point - Integer Subtraction
31007523 8/2010
EMTH-SUBFI: Floating Point -

Integer Subtraction
80
Introduction
This chapter describes the EMTH subfunction EMTH-SUBFI.

Topic Page
Representation 439
31007523 8/2010 437

Short Description
438 31007523 8/2010

Representation
Symbol
31007523 8/2010 439


Reference
Top input 0x, 1x None ON = initiates FP - integer operation
FP 4x REAL Floating point value (first of two contiguous
register is implied. The FP value from
which the integer value is subtracted is
stored here.
integer and 4x DINT, UDINT Integer value and difference (first of four
difference contiguous registers)
register store the double precision integer
value to be subtracted from the FP value,
and the difference is posted in the second
and third implied registers. The difference
is posted in FP format.
SUBFI Selection of the subfunction SUBFI
(bottom node)
440 31007523 8/2010


Register Content
Displayed The FP value from which the integer value is subtracted is stored
First implied here.
Sine of Value (Middle Node)

Register Content
Displayed Registers store the double precision integer value to be subtracted
First implied from the FP value.
Second implied The difference is posted here in FP format.
Third implied
31007523 8/2010 441

442 31007523 8/2010

EMTH-SUBFP: Floating Point Subtraction
31007523 8/2010
EMTH-SUBFP:
Floating Point Subtraction
81
Introduction
This chapter describes the EMTH subfunction EMTH-SUBFP.

Topic Page
Representation 445
31007523 8/2010 443

Short Description
444 31007523 8/2010

Representation
Symbol
31007523 8/2010 445


Reference
Top input 0x, 1x None ON = initiates FP value 1 - value 2
subtraction
value 1 4x REAL Floating point value 1 (first of two
register is implied. FP value 1 (the value
from which value 2 will be subtracted) is
stored here.
value 2 and 4x REAL Floating point value 2 and the difference
difference (first of four contiguous registers)
remaining three registers are implied. FP
value 2 (the value to be subtracted from
value 1) is stored in the displayed register
and the first implied register. The
difference of the subtraction is stored in FP
format in the second and third implied
registers.
SUBFP Selection of the subfunction SUBFP
(bottom node)
446 31007523 8/2010


Register Content
Displayed FP value 1 (the value from which value 2 will be subtracted) is stored here.
First implied

Register Content
Displayed FP value 2 (the value to be subtracted from value 1) is stored in
First implied these registers
Second implied The difference of the subtraction is stored here in FP format.
Third implied
31007523 8/2010 447

448 31007523 8/2010

EMTH-SUBIF: Integer - Floating Point Subtraction
31007523 8/2010
EMTH-SUBIF: Integer -
Floating Point Subtraction
82
Introduction
This chapter describes the EMTH subfunction EMTH-SUBIF.

Topic Page
Representation 451
31007523 8/2010 449

Short Description
450 31007523 8/2010

Representation
Symbol

Reference Type
Top input 0x, 1x None ON = initiates integer - FP operation
(top node) UDINT The first of two contiguous 4xxxx registers is entered
in the top node. The second register is implied. The
double precision integer value from which the FP
value is subtracted is stored here.
FP and 4x REAL FP value and difference (first of four contiguous
difference registers)
registers are implied. The displayed register and the
first implied register store the FP value to be
subtracted from the integer value, and the difference
is posted in the second and third implied registers.
The difference is posted in FP format.
SUBIF Selection of the subfunction SUBIF
(bottom node)
31007523 8/2010 451


Register Content
Displayed The double precision integer value from which the FP value is
First implied subtracted is stored here.
FP Value and Difference (Middle Node)

Register Content
Displayed Registers store the FP value to be subtracted from the integer value.
First implied
Second implied The difference is posted here in FP format.
Third implied
452 31007523 8/2010

EMTH-TAN: Floating Point Tangent of an Angle (in Radians)
31007523 8/2010
EMTH-TAN: Floating Point

Tangent of an Angle (in Radians)
83
Introduction
This chapter describes the EMTH subfunction EMTH-TAN.

Topic Page
Representation 455
31007523 8/2010 453

Short Description
454 31007523 8/2010

Representation
Symbol

Reference Type
Top input 0x, 1x None ON = calculates the tangent of the value
value 4x REA FP value indicating the value of an angle in radians
(top node) L (first of two contiguous registers)
in the top node. The second register is implied. A value
in FP format indicating the value of an angle in radians
is stored here.
The magnitude of this value must be < 65536.0; if not:
z The tangent is not computed
z An error is flagged in the EMTH ERLOG function
tangent of value 4x REA Tangent of the value in the top node (first of four
(middle node) L contiguous registers)
TAN Selection of the subfunction TAN
(bottom node)
31007523 8/2010 455

Value (Top Node)

Register Content
If the magnitude is ≥ 65 536.0:

z The tangent is not computed
Tangent of Value (Middle Node)

Register Content
First implied
Second implied The tangent of the value in the top node is posted here in FP format.
Third implied
used.
456 31007523 8/2010

ESI: Support of the ESI Module
31007523 8/2010
84
Introduction
This chapter describes the instruction ESI.

Topic Page
Representation 459
READ ASCII Message (Subfunction 1) 463
WRITE ASCII Message (Subfunction 2) 467
GET DATA (Subfunction 3) 468
PUT DATA (Subfunction 4) 469
ABORT (Middle Input ON) 473
Run Time Errors 474
31007523 8/2010 457

Short Description
Loadables. For further information, see the chapter Installation of DX Loadables,
page 75.
The instruction for the ESI module 140 ESI 062 10 are optional loadable instructions
that can be used in a Quantum controller system to support operations using an ESI
module. The controller can use the ESI instruction to invoke the module. The power
of the loadable is its ability to cause a sequence of commands over one or more logic
scans.
With the ESI instruction, the controller can invoke the ESI module to:
z Read an ASCII message from a serial port on the ESI module, then perform a
sequence of GET DATA transfers from the module to the controller.
z Write an ASCII message to a serial port on the ESI module after having
performed a sequence of PUT DATA transfers to the variable data registers in the
module.
z Perform a sequence of GET DATA transfers (up to 16 384 registers of data from
the ESI module to the controller); one Get Data transfer will move up to 10 data
registers each time the instruction is solved.
z Perform a sequence of PUT DATA (up to 16 384 registers of data to the ESI
module from the controller). One PUT DATA transfer moves up to 10 registers of
data each time the instruction is solved.
z Abort the ESI loadable command sequence running.
NOTE: After placing the ESI instruction in your ladder diagram, you must enter the
top, middle, and bottom parameters. Proceed by double clicking on the instruction.
This action produces a form for the entry of the 3 parameters. This parametric must
be completed to enable the DX zoom function in the Edit menu pulldown.
458 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = enables the subfunction
Middle input 0x, 1x None Abort current message
subfunction 4x INT, UINT, Number of possible subfunction, range 1
(top node WORD ... 4
subfunction 4x INT, UINT, First of eighteen contiguous 4x holding
parameters WORD registers which contain the subfunction
(middle node) parameters
length INT, UINT Number of subfunction parameter
bottom node registers, i.e. the length of the table in the
middle node
Middle output 0x None ON = operation done
Bottom output 0x None ON = error detected
31007523 8/2010 459

Top Input
When the input to the top node is powered ON, it enables the ESI instruction and
starts executing the command indicated by the subfunction code in the top node.
Middle Input
When the input to the middle node is powered ON, an Abort command is issued. If
a message is running when the ABORT command is received, the instruction will
complete; if a data transfer is in process when the ABORT command is received, the
transfer will stop and the instruction will complete.
Subfunction # (Top Node)

The top node may contain either a 4x register or an integer. The integer or the value
in the register must be in the range 1 ... 4.
It represents one of four possible subfunction command sequences to be executed
by the instruction:
Subfunction Command Sequence

1 One command (READ ASCII Message, page 463) followed by multiple GET
DATA commands
2 Multiple PUT DATA commands followed by one command (WRITE ASCII
Message, page 467)
3 Zero or more commands (GET DATA, page 468)
4 Zero or more commands (PUT DATA, page 469)
NOTE: A fifth command, (ABORT ASCII Message (see page 473)), can be initiated
by enabling the middle input to the ESI instruction.
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Subfunction Parameters (Middle Node)

The first of eighteen contiguous 4x registers is entered in the middle node. The
ramaining seventeen registers are implied.
The following subfunction parameters are available:
Register Parameter Contents

Displayed ESI status register Returned error codes
First implied Address of the first 4x register Register address minus the leading 4 and
in the command structure any leading zeros, as specified in the I/O
Map (e.g., 1 represents register 400001)
Second Address of the first 3x register Register address minus the leading 3 and
implied in the command structure any leading zeros, as specified in the I/O
Map (e.g., 7 represents register 300007)
Third implied Address of the first 4x register Register address minus the leading 4 and
in the controller's data register any leading zeros (e.g., 100 representing
area register 400100)
Fourth implied Address of the first 3x register Register address minus the leading 3 and
in the controller's data register any leading zeros (e.g., 1000 representing
area register 301000)
Fifth implied Starting register for data Number in the range 0 ... 3FFF hex
register area in module
Sixth implied Data transfer count Number in the range 0 ... 4000 hex
Seventh ESI timeout value, in 100 ms Number in the range 0 ... FFFF hex, where
implied increments 0 means no timeout
Eighth implied ASCII message number Number in the range 1 ... 255 dec
Ninth implied ASCII port number 1 or 2
Note: The registers below are internally used by the ESI loadable. Do not write registers
while the ESI loadable is running. For best use, initialize these registers to 0 (zero) when the
loadable is inserted into logic.
10th implied ESI loadable previous scan power in state
11th implied Data left to transfer
12th implied Current ASCII module command running
13th implied ESI loadable sequence number
14th implied ESI loadable flags
15th implied ESI loadable timeout value (MSW)
16th implied ESI loadable timeout value (LSW)
17th implied Parameter Table Checksum generated by ESI loadable
NOTE: Once power has been applied to the top input, the ESI loadable starts
running. Until the ESI loadable compiles (successfully or in error), the subfunction
parameters should not be modified. If the ESI loadable detects a change, the
loadable will compile in error (Parameter Table).
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The bottom node contains the length of the table in the middle node, i.e., the number
of subfunction parameter registers. For READ/ WRITE operations, the length must
be 10 registers. For PUT/GET operations, the required length is eight registers; 10
may be specified and the last two registers will be unused.
Ouptuts
NOTE: NSUP must be loaded before ESI in order for the loadable to work properly.
If ESI is loaded before NSUP or ESI is loaded alone, all three outputs will be turned
ON.
Middle Output
The middle output goes ON for one scan when the subfunction operation specified
in the top node is completed, timed out, or aborted
Bottom Output
The bottom output goes ON for one scan if an error has been detected. Error
checking is the first thing that is performed on the instruction when it is enabled, it it
is completed before the subfunction is executed. For more details, see Run Time
Errors, page 474.
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READ ASCII Message (Subfunction 1)
READ ASCII Message

A READ ASCII command causes the ESI module to read incoming data from one of
its serial ports and store the data in internal variable data registers. The serial port
number is specified in the tenth (ninth implied) register of the subfunction
parameters table. The ASCII message number to be read is specified in the ninth
(eighth implied) register of the subfunction parameters table. The received data is
stored in the 16K variable data space in user-programmed formats.
When the top node of the ESI instruction is 1, the controller invokes the module and
causes it to execute one READ ASCII command followed by a sequence of GET
DATA commands (transferring up to 16,384 registers of data) from the module to the
controller.
Command Structure
Command Structure
Word Content (hex) Meaning

0 01PD P = port number (1 or 2); D = data count
1 xxxx Starting register number, in the range 0 ... 3FFF
2 00xx Message number, where xx is in the range 1 ... FF (1 ... 255
dec)
3 ... 11 Not used
Response Structure
Command Structure

0 01PD Echoes command word 0
1 xxxx Echoes starting register number from Command Word 1
2 00xx Echoes message number from Command Word 2
3 xxxx Data word 1
4 xxxx Data word 2
... ... ...
11 xxxx Module status or data word 9
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A Comparative READ ASCII Message/Put Data Example

Below is an example of how an ESI loadable instruction can simplify your logic
programming task in an ASCII read application. Assume that the 12-point
bidirectional ESI module has been I/O mapped to 400001 ... 400012 output registers
and 300001 ... 300012 input registers. We want to read ASCII message #10 from
port 1, then transfer four words of data to registers 400501 ... 400504 in the
controller.
Parameterizing of the ESI instruction:
The subfunction parameter table begins at register 401000 . Enter the following
parameters in the table:
Register Parameter Value Description

401000 nnnn ESI status register
401001 1 I/O mapped output starting register (400001)
401002 1 I/O mapped input starting register (300001)
401003 501 Starting register for the data transfer (400501)
401004 0 No 3x starting register for the data transfer
401005 100 Module start register
401006 4 Number of registers to transfer
401007 600 timeout = 60 s
401008 10 ASCII message number
401009 1 ASCII port number
401010-17 N/A Internal loadable variables
With these parameters entered to the table, the ESI instruction will handle the read
and data transfers automatically in one scan.
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Read and Data Transfers without ESI Instruction

The same task could be accomplished in ladder logic without the ESI loadable, but
it would require the following three networks to set up the command and transfer
parameters, then copy the data. Registers 400101 ... 400112 are used as
workspace for the output values. Registers 400201 ... 400212 are initial READ
ASCII Message command values. Registers 400501 ... 400504 are the data space
for the received data from the module.
First Network
Contents of registers
Register Value (hex) Description

400201 0114 READ ASCII Message command, Port 1, Four registers
400202 0064 Module’s starting register
400203 nnnn Not valid: data word 1
... ... ...
The first network starts up the READ ASCII Message command by turning ON coil
000011 forever. It moves the READ ASCII Message command into the workspace,
then moves the workspace to the output registers for the module.
Second Network
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400098 nnnn Workspace for response word
400099 nnnn Workspace for response word
400088 7FFF Response word mask
400089 8000 Status word valid bit mask
As long as coil 000011 is ON, READ ASCII Message response Word 0 in the input
register is tested to make sure it is the same as command Word 0 in the workspace.
This is done by ANDing response Word 0 in the input register with 7FFF hex to get
rid of the Status Word Valid bit (bit 15) in Response Word 0.
The module start register in the input register is also tested against the module start
register in the workspace to make sure that are the same.
If both these tests show matches, test the Status Word Valid bit in response Word
0. To do this, AND response Word 0 in the input register with 8000 hex to get rid of
the echoed command word 0 information. If the ANDed result equals the Status
Word Valid bit, coil 000020 is turned ON indicating an error and/or status in the
Module Status Word. If the ANDed result is not the status word valid bit, coil 000012
is turned ON indicating that the message is done and that you can start another
command in the module.
Third Network
If coil 000020 is ON, this third network will test the Module Status Word for busy
status. If the module is busy, do nothing. If the Module Status Word is greater than
1 (busy), a detected error has been logged in the high byte and coil 000099 will be
turned ON. At this point, you need to determine what the error is using some error-
handling logic that you have developed.
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WRITE ASCII Message (Subfunction 2)
WRITE ASCII Message

In a WRITE ASCII Message command, the ESI module writes an ASCII message to
one of its serial ports. The serial port number is specified in the tenth (ninth implied)
register of the subfunction parameters table. The ASCII message number to be
written is specified in the ninth (eighth implied) register of the subfunction
parameters table.
When the top node of the ESI instruction is 2, the controller invokes the module and
causes it to execute one Write ASCII command. Before starting the WRITE
command, subfunction 2 executes a sequence of PUT DATA transfers (transferring
up to 16 384 registers of data) from the controller to the module.
Command Structure
Command Structure
Word Content Meaning

(hex)
0 02PD P = port number (1 or 2); D = data count
2 00xx Message number, where xx is in the range 1 ... FF (1 ... 255 dec)
3 xxxx Data word 1
4 xxxx Data word 2
... ... ...
11 xxxx Data word 9
Response Structure
Response Structure
Word Content Meaning

(hex)
0 02PD Echoes command word 0
1 xxxx Echoes starting register number from command word 1
2 00xx Echoes message number from command word 2
3 0000 Returns a zero
... ... ...
11 xxxx Module status
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GET DATA (Subfunction 3)
GET DATA
A GET DATA command transfers up to 10 registers of data from the ESI module to
the controller each time the ESI instruction is solved in ladder logic. The total number
of words to be read is specified in Word 0 of the GET DATA command structure (the
data count). The data is returned in increments of 10 in Words 2 ... 11 in the GET
DATA response structure.
If a sequence of GET DATA commands is being executed in conjunction with a
READ ASCII Message command (via subfunction 1), up to nine registers are
transferred when the instruction is solved the first time. Additional data are returned
in groups of ten registers on subsequent solves of the instruction until all the data
has been transferred
If there is an error condition to be reported (other than a command syntax error), it
is reported in Word 11 in the GET DATA response structure. If the command has
requested 10 registers and the error needs to be reported, only nine registers of data
will be returned in Words 2 ... 10, and Word 11 will be used for error status.
NOTE: If the data count and starting register number that you specify are valid but
some of the registers to be read are beyond the valid register range, only data from
the registers in the valid range will be read. The data count returned in Word 0 of the
response structure will reflect the number of valid data registers returned, and an
error code (1280 hex) will be returned in the Module Status Word (Word 11 in the
response table).
Command Structure
Command Structure

0 030D D = data count
2 ... 11 Not used
Response Structure
Response Structure

0 030D Echoes command word 0
2 xxxx Data word 1
3 xxxx Data word 2
... ... ...
11 xxxx Module status or data word 10
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PUT DATA (Subfunction 4)
PUT DATA
A PUT DATA command writes up to 10 registers of data to the ESI module from the
controller each time the ESI instruction is solved in ladder logic. The total number of
words to be written is specified in Word 0 of the PUT DATA command structure (the
data count).
The data is returned in increments of 10 in words 2 ... 11 in the PUT DATA command
structure. The command is executed sequentially until command word 0 changes to
another command other than PUT DATA (040D hex).
NOTE: If the data count and starting register number that you specify are valid but
some of the registers to be written are beyond the valid register range, only data
from the registers in the valid range will be written. The data count returned in Word
0 of the response structure will reflect the number of valid data registers returned,
and an error code (1280 hex) will be returned in the Module Status Word (Word 11
in the response table).
Command Structure
Command Structure

0 040D D = data count
2 xxxx Data word 1
3 xxxx Data word 2
... ... ...
11 xxxx Data word 10
Response Structure
Response Structure

0 040D Echoes command word 0
... ... ...
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A Comparative PUT DATA Example

Below is an example of how an ESI loadable instruction can simplify your logic
programming task in a PUT DATA application. Assume that the 12-point
bidirectional ESI 062 module has been I/O mapped to 400001 ... 400012 output
registers and 300001 ... 300012 input registers. We want to put 30 controller data
registers, starting at register 400501, to the ESI module starting at location 100.
Parameterizing of the ESI instruction:
The subfunction parameter table begins at register 401000 . Enter the following
parameters in the table:
Register Parameter Value Description

401000 nnnn ESI status register
401001 1 I/O mapped output starting register (400001)
401002 1 I/O mapped input starting register (300001)
401003 501 Starting register for the data transfer (400501)
401004 0 No 3x starting register for the data transfer
401005 100 Module start register
401006 30 Number of registers to transfer
401007 0 timeout = never
401008 N/A ASCII message number
401009 N/A ASCII port number
401009 N/A Internal loadable variables
With these parameters entered to the table, the ESI instruction will handle the data
transfers automatically over three ESI logic solves.
Handling of Data Transfer without ESI Instruction

The same task could be accomplished in ladder logic without the ESI loadable, but
it would require the following four networks to set up the command and transfer
parameters, then copy data multiple times until the operation is complete. Registers
400101 ... 400112 are used as workspace for the output values. Registers 400201
... 400212 are initial PUT DATA command values. Registers 400501 ... 400530 are
the data registers to be sent to the module.
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First Network - Command Register Network

400201 040A PUT DATA command, 10 registers
400202 0064 Module’s starting register
... ... ...
The first network starts up the transfer of the first 10 registers by turning ON coil
000011 forever. It moves the initial PUT DATA command into the workspace, moves
the first 10 registers (400501 ... 400510) into the workspace, and then moves the
workspace to the output registers for the module.
Second Network - Command Register Network
As long as coil 000011 is ON and coil 000020 is OFF, PUT DATA response word 0
in the input register is tested to make sure it is the same as the command word in
the workspace. The module start register in the input register is also tested to make
sure it is the same as the module start register in the workspace.
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If both these tests show matches, the current module start register is tested against
what would be the module start register of the last PUT DATA command for this
transfer. If the test shows that the current module start register is greater than or
equal to the last PUT DATA command, coil 000020 goes ON indicating that the
transfer is done. If the test shows that the current module start register is less than
the last PUT DATA command, coil 000012 indicating that the next 10 registers
should be transferred.
Third Network - Command Register Network
As long as coil 000012 is ON, there is more data to be transferred. The module start
register needs to be tested from the last command solve to determine which set of
10 registers to transfer next. For example, if the last command started with module
register 400110, then the module start register for this command is 400120.
Fourth Network - Command Register Network
As long as coil 000012 is ON, add 10 to the module start register value in the
workspace and move the workspace to the output registers for the module to start
the next transfer of 10 registers.
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ABORT (Middle Input ON)
ABORT
When the middle input to the ESI instruction is powered ON, the instruction aborts
a running ASCII READ or WRITE message. The serial port buffers of the module
are not affected by the ABORT, only the message that is currently running.
Command Structure
Command Structure
Word Content (hex)

0 0900
1 ... 11 not used
Response Structure
Response Structure

0 0900 Echoes command word 0
... ... ...
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Run Time Errors
Run Time Errors

The command sequence executed by the ESI module (specified by the subfunction
value in the top node of the ESI instruction) needs to go through a series of error
checking routines before the actual command execution begins. If an error is
detected, a message is posted in the register displayed in the middle node.
The following table lists possible error message codes and their meanings:
Error Code (dec) Meaning

0001 Unknown subfunction specified in the top node
0010 ESI instruction has timed out (exceeded the time specified in the eighth
register of the subfunction parameter table)
0101 Error in the READ ASCII Message sequence
0102 Error in the WRITE ASCII Message sequence
0103 Error in the GET DATA sequence
0104 Error in the PUT DATA sequence
1000 Length (Bottom Node) is too small
1001 Nonzero value in both the 4x and 3x data offset parameters
1002 Zero value in both the 4x and 3x data offset parameters
1003 4x or 3x data offset parameter out of range
1004 4x or 3x data offset plus transfer count out of range
1005 3x data offset parameter set for GET DATA
1006 Parameter Table Checksum error
1101 Output registers from the offset parameter out of range
1102 Input registers from the offset parameter out of range
2001 Error reported from the ESI module
Once the parameter error checking has completed without finding an error, the ESI
module begins to execute the command sequence.
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EUCA: Engineering Unit Conversion and Alarms
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EUCA: Engineering Unit

Conversion and Alarms
85
Introduction
This chapter describes the instrcution EUCA.

Topic Page
Representation 477
Examples 480
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Short Description
Loadables. For further information, see "Installation of DX Loadables, page 75."
The use of ladder logic to convert binary-expressed analog data into decimal units
can be memory-intensive and scan-time intensive operation. The Engineering Unit
Conversion and Alarms (EUCA) loadable is designed to eliminate the need for extra
user logic normally required for these conversions. EUCA scales 12 bits of binary
data (representing analog signals or other variables) into engineering units that are
readily usable for display, data logging, or alarm generation.
Using Y = mX + b linear conversion, binary values between 0 ... 4095 are converted
to a scaled process variable (SPV). The SPV is expressed in engineering units in
the range 0 ... 9 999.
One EUCA instruction can perform up to four separate engineering unit conversions.
It also provides four levels of alarm checking on each of the four conversions:
Level Meaning
HA High absolute
HW High warning
LW Low warning
LA Low absolute
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Representation
Symbol

Reference Type
Top input 0x, 1x None ON initiates the conversion
Middle input 0x, 1x None Alarm input
Bottom input 0x, 1x None Error input
alarm status 4x INT, Alarm status for as many as four EUCA conversions
(top node) UINT (For more information please see Alarm Status (Top
Node), page 478.)
parameter table 4x INT, First of nine contiguous holding registers in the EUCA
(middle node) UINT, parameter table
(For more information please see Parameter Table
(Middle Node), page 479.)
nibble # (1...4) INT, Integer value, indicates which one of the four nibbles
(bottom node) UINT in the alarm status register to use
Middle output 0x None ON if the middle input is ON or if the result of the
EUCA conversion crosses a warning level
Bottom output 0x None ON if the bottom input is ON or if a parameter is out of
range
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Alarm Status (Top Node)

The 4x register entered in the top node displays the alarm status for as many as four
EUCA conversions, which can be performed by the instruction. The register is
segmented into four four-bit nibbles. Each four-bit nibble represents the four
possible alarm conditions for an individual EUCA conversion.
The most significant nibble represents the first conversion, and the least significant
nibble represents the fourth conversion:
Alarm Setting
Condition of alarm setting
Alarm type Condition

HA An HA alarm is set when the SPV exceeds the user-defined high alarm
value expressed in engineering units
HW An HW alarm is set when SPV exceeds a user-defined high warning value
expressed in engineering units
LW An LW alarm is set when SPV is less than a user-defined low warning value
LA An LA alarm is set when SPV is less than a user-defined low alarm value
Only one alarm condition can exist in any EUCA conversion at any given time. If the
SPV exceeds the high warning level the HW bit will be set. If the HA is exceeded,
the HW bit is cleared and the HA bit is set. The alarm bit will not change after
returning to a less severe condition until the deadband (DB) area has also been
exited.
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Parameter Table (Middle Node)

The 4x register entered in the middle node is the first of nine contiguous holding
registers in the EUCA parameter table:
Register Content Range

Displayed Binary value input by the user 0 ... 4 095
First implied SPV calculated by the EUCA block
Second implied High engineering unit (HEU), maximum LEU < HEU ≤ 99 999
SPV required and set by the user (top of the
scale)
Third implied Low engineering unit (LEU), minimum SPV 0 ≤ LEU < HEU
required and set by the user (bottom end of
the scale)
Fourth implied DB area in SPV units, below HA levels and 0 ≤ DB < (HEU - LEU)
above LA levels that must be crossed
before the alarm status bit will reset
Fifth implied HA alarm value in SPV units HW < HA ≤ HEU
Sixth implied HW alarm value in SPV units LW < HW < HA
Seventh implied LW alarm value in SPV units LA < LW < HW
Eighth implied LA alarm value in SPV units LEU ≤ LA < LW
NOTE: An error is generated if any value is out of the range defined above
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Examples
Overview
The following examples are shown.
z Principles of EUCA Operation (example 1)
z Use in a Drive System (example 2)
z Four EUCA conversions together (example 3)
Example 1
This example demonstrates the principles of EUCA operation. The binary value is
manually input in the displayed register in the middle node, and the result is visually
available in the SPV register (the first implied register in the middle node).
The illustration below shows an input range equivalent of a 0 ... 100 V measure,
corresponding to the whole binary 12-bit range:
A range of 0 ... 100 V establishes 50 V for nominal operation. EUCA provides a

margin on the nominal side of both warning and alarm levels (deadband). If an alarm
threshold is exceeded, the alarm bit becomes active and stays active until the signal
becomes greater (or less) than the DB setting -5 V in this example.
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Programming the EUCA block is accomplished by selecting the EUCA loadable and
writing in the data as illustrated in the figure below:
Reference Data
Register Meaning Content

400440 STATUS 0000000000000000
400450 INPUT 1871 DEC
400451 SPV 46 DEC
400452 HIGH_unit 100 DEC
400453 LOW_unit 0 DEC
400454 Dead_band 5 DEC
400455 HIGH_ALARM 70 DEC
400456 HIGH_WARN 60 DEC
400457 LOW_ALARM 40 DEC
400458 LOW_WARN 30 DEC
The nine middle-node registers are set using the reference data editor. DB is 5 V
followed by 10 V increments of high and low warning. The actual high and low alarm
is set at 20 V above and below nominal.
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On a graph, the example looks like this:
NOTE: The example value shows a decimal 46, which is in the normal range. No
alarm is set, i.e., register 400440 = 0.
You can now verify the instruction in a running PLC by entering values in register
400450 that fall into the defined ranges. The verification is done by observing the bit
change in register 400440 where:
Example 2
If the input of 0 ... 4095 indicates the speed of a drive system of 0 ... 5000 rpm, you
could set up a EUCA instruction as follows.
The binary value in 400210 results in an SPV of 4835 decimal, which exceeds the
high absolute alarm level, sets the HA bit in 400209, and powers the EUCA alarm
node.
Parameter Speed
Maximum Speed 5 000 rpm
Minimum Speed 0 rpm
DB 100 rpm
HA Alarm 4 800 rpm
HW Alarm 4 450 rpm
LW Alarm 2 000 rpm
LA Alarm 1 200 rpm
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Instruction
Reference Data

400209 STATUS 1000000000000000
400210 INPUT 3960 DEC
400211 SPV 4835 DEC
400212 MAX_SPEED 5000 DEC
400213 MIN_SPEED 0 DEC
400214 Dead_band 100 DEC
400215 HIGH_ALARM 4800 DEC
400216 HIGH_WARN 4450 DEC
400217 LOW_ALARM 2000 DEC
400218 LOW_WARN 1200 DEC
The N.O. contact is used to suppress alarm checks when the drive system is
shutdown, or during initial start up allowing the system to get above the Low alarm
RPM level.
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Varying the binary value in register 400210 would cause the bits in nibble 1 of
register 400209 to correspond with the changes illustrated above. The DB becomes
effective when the alarm or warning has been set, then the signal falls into the DB
zone.
The alarm is maintained, thus taking what would be a switch chatter condition out of
a marginal signal level. This point is exemplified in the chart above, where after
setting the HA alarm and returning to the warning level at 4700 the signal crosses in
and out of DB at the warning level (4450) but the warning bit in 400209 stays ON.
The same action would be seen if the signal were generated through the low
settings.
Example 3
You can chain up to four EUCA conversions together to make one alarm status
register. Each conversion writes to the nibble defined in the block bottom node. In
the program example below, each EUCA block writes it‘s status (based on the table
values for that block) into a four bit (nibble) of the status register 400209.
484 31007523 8/2010

Reference Data

400209 STATUS 0000001001001000
The status register can then be transferred using a BLKM instruction to a group of
discretes wired to illuminate lamps in an alarm enunciator panel.
As you observe the status content of register 400209 you see: no alarm in block 1,
an LW alarm in block 2, an HW alarm in Block 3, and an HA alarm in block 4.
The alarm conditions for the four blocks can be represented with the following table
settings:
Conversion 1 Conversion 2 Conversion 3 Conversion 4

Input 400210 = 2048 400220 = 1220 400230 = 3022 400240 = 3920
Scaled # 400211 = 2501 400221 = 1124 400231 = 7379 400241 = 0770
HEU 400212 = 5000 400222 = 3300 400232 = 9999 400242 = 0800
LEU 400213 = 0000 400223 = 0200 400233 = 0000 400243 = 0100
DB 400214 = 0015 400224 = 0022 400234 = 0100 400244 = 0006
Hi Alarm 400215 = 40000 400225 = 2900 400235 = 8090 400245 = 0768
Hi Warn 400216 = 3500 400226 = 2300 400236 = 7100 400246 = 0680
Lo Warn 400217 = 2000 400227 = 1200 400237 = 3200 400247 = 0280
Lo Alarm 400218 = 1200 400228 = 0430 400238 = 0992 400248 = 0230
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486 31007523 8/2010

Instruction Descriptions (F to N)
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IV
Introduction
In this part instruction descriptions are arranged alphabetically from F to N.

86 FIN: First In 489
87 FOUT: First Out 493
88 FTOI: Floating Point to Integer 499
89 GD92 - Gas Flow Function Block 503
90 GFNX AGA#3 ‘85 and NX19 ‘68 Gas Flow Function Block 515
91 GG92 AGA #3 1992 Gross Method Gas Flow Function Block 529
92 GM92 AGA #3 and #8 1992 Detail Method Gas Flow 541
Function Block
93 G392 AGA #3 1992 Gas Flow Function Block 553
94 HLTH: History and Status Matrices 565
95 HSBY - Hot Standby 579
96 IBKR: Indirect Block Read 585
97 IBKW: Indirect Block Write 589
98 ICMP: Input Compare 593
99 ID: Interrupt Disable 599
100 IE: Interrupt Enable 603
101 IMIO: Immediate I/O 607
102 IMOD: Interrupt Module Instruction 613
103 INDX – Immediate Incremental Move 621
104 ITMR: Interrupt Timer 625
105 ITOF: Integer to Floating Point 631
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106 JOGS – JOG Move 635
107 JSR: Jump to Subroutine 639
108 LAB: Label for a Subroutine 643
109 LOAD: Load Flash 647
110 MAP3: MAP Transaction 651
111 MATH - Integer Operations 659
112 MBIT: Modify Bit 667
113 MBUS: MBUS Transaction 671
114 MMFB – Modicon Motion Framework Bits Block 681
115 MMFE – Modicon Motion Framework Extended Parameters 685
Subroutine
116 MMFI – Modicon Motion Framework Initialize Block 689
117 MMFS – Modicon Motion Framework Subroutine Block 695
118 MOVE – Absolute Move 699
119 MRTM: Multi-Register Transfer Module 703
120 MSPX (Seriplex) 709
121 MSTR: Master 713
122 MU16: Multiply 16 Bit 759
123 MUL: Multiply 763
124 NBIT: Bit Control 767
125 NCBT: Normally Closed Bit 771
126 NOBT: Normally Open Bit 775
127 NOL: Network Option Module for Lonworks 779
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FIN: First In
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FIN: First In
86
Introduction
This chapter describes the instruction FIN.

Topic Page
Representation 491
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FIN: First In
Short Description
The FIN instruction is used to produce a first-in queue. A FOUT instruction needs to
be used to clear the register at the bottom of the queue. An FIN instruction has one
control input and can produce three possible outputs.
490 31007523 8/2010

FIN: First In
Representation
Symbol

Reference
Top input 0x, 1x None ON = copies source bit pattern into queue
source data 0x, 1x, 3x, 4x ANY_BIT Source data, will be copied to the top of the
(top node) destination queue in the current logic scan
queue pointer 4x WORD First of a queue of 4x registers, contains
(middle node) queue pointer; the next contiguous
register is the first register in the queue
queue length INT, UINT Number of 4x registers in the destination
(bottom node) queue. Range: 1 ... 100
Middle output 0x None ON = queue full, no more source data can
be copied to the queue
Bottom output 0x None ON = queue empty (value in queue pointer
register = 0)
31007523 8/2010 491

FIN: First In
Mode of Functioning
The FIN instruction is used to produce a first-in queue. It copies the source data from
the top node to the first register in a queue of holding registers. The source data is
always copied to the register at the top of the queue. When a queue has been filled,
no further source data can be copied to it.
Source Data (Top Node)

When using register types 0x or 1x:
z First 0x reference in a string of 16 contiguous coils or discrete outputs
z First 1x reference in a string of 16 discrete inputs
Queue Pointer (Middle Node)

The 4x register entered in the middle node is a queue pointer. The first register in
the queue is the next contiguous 4x register following the pointer. For example, if the
middle node displays a a pointer reference of 400100, then the first register in the
queue is 400101.
The value posted in the queue pointer equals the number of registers in the queue
that are currently filled with source data. The value of the pointer cannot exceed the
integer maximum queue length value specified in the bottom node.
If the value in the queue pointer equals the integer specified in the bottom node, the
middle output passes power and no further source data can be written to the queue
until an FOUT instruction clears the register at the bottom of the queue.
492 31007523 8/2010

FOUT: First Out
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FOUT: First Out
87
Introduction
This chapter describes the instruction FOUT.

Topic Page
Representation 495
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FOUT: First Out
Short Description
DANGER
DISABLED COILS
Before using the FOUT instruction, check for disabled coils. FOUT will override any
disabled coils within a destination register without enabling them. This can cause
can change as a result of the FOUT operation.
Failure to follow these instructions will result in death or serious injury.
The FOUT instruction works together with the FIN instruction to produce a first in-
first out (FIFO) queue. It moves the bit pattern of the holding register at the bottom
of a full queue to a destination register or to word that stores 16 discrete outputs.
An FOUT instruction has one control input and can produce three possible outputs.
494 31007523 8/2010

FOUT: First Out
Representation
Symbol
31007523 8/2010 495

FOUT: First Out

Reference
Top input 0x, 1x None ON = clears source bit pattern from the
queue
source pointer 4x WORD First of a queue of 4x registers, contains
(top node) source pointer; the next contiguous
register is the first register in the queue
In the FOUT instruction, the source data
comes from the 4xxxx register at the
bottom of a full queue. The next
contiguous 4xxxx register following the
source pointer register in the top node is
the first register in the queue. For
example, if the top node displays pointer
register 40100, then the first register in the
queue is 40101.
The value posted in the source pointer
equals the number of registers in the
queue that are currently filled. The value of
the pointer cannot exceed the integer
maximum queue length value specified in
the bottom node. If the value in the source
pointer equals the integer specified in the
bottom node, the middle output passes
power and no further FIN data can be
written to the queue until the FOUT
instruction clears the register at the bottom
of the queue to the destination register.
destination 0x, 4x ANY_BIT Destination register
register The destination specified in the middle
(middle node) node can be a 0xxxx reference or 4xxxx
register. When the queue has data and the
top control input to the FOUT passes
power, the source data is cleared from the
bottom register in the queue and is written
to the destination register.
queue length INT, UINT Number of 4x registers in the queue.
(bottom node) Range: 1 ... 100
Middle output 0x None ON = queue full, no more source data can
be copied to the queue
Bottom output 0x None ON = queue empty (value in queue pointer
re
496 31007523 8/2010

FOUT: First Out
Mode of Functioning
The FOUT instruction works together with the FIN instruction to produce a first in-
first out (FIFO) queue. It moves the bit pattern of the holding register at the bottom
of a full queue to a destination register or to word that stores 16 discrete outputs.
NOTE: The FOUT instruction should be placed before the FIN instruction in the
ladder logic FIFO to ensure removal of the oldest data from a full queue before the
newest data is entered. If the FIN block were to appear first, any attempts to enter
the new data into a full queue would be ignored.
Source Pointer (Top Node)

In the FOUT instruction, the source data comes from the 4x register at the bottom of
a full queue. The next contiguous 4x register following the source pointer register in
the top node is the first register in the queue. For example, if the top node displays
pointer register 400100, then the first register in the queue is 400101.
The value posted in the source pointer equals the number of registers in the queue
that are currently filled. The value of the pointer cannot exceed the integer maximum
queue length value specified in the bottom node. If the value in the source pointer
equals the integer specified in the bottom node, the middle output passes power and
no further FIN data can be written to the queue until the FOUT instruction clears the
register at the bottom of the queue to the destination register.
Destination Register (Middle Node)

The destination specified in the middle node can be a 0x reference or 4x register.
When the queue has data and the top input to the FOUT passes power, the source
data is cleared from the bottom register in the queue and is written to the destination
register.
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FOUT: First Out
498 31007523 8/2010

FTOI: Floating Point to Integer
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88
Introduction
This chapter describes the instruction FTOI.

Topic Page
Representation 501
31007523 8/2010 499

Short Description
The FTOI instruction performs the conversion of a floating value to a signed or
unsigned integer (stored in two contiguous registers in the top node), then stores the
converted integer value in a 4x register in the middle node.
500 31007523 8/2010

Representation
Symbol

Reference Type
Top input 0x, 1x None ON = enables conversion
FP (top node) 4x REAL First of two contiguous holding registers
where the floating point value is stored
converted integer 4x INT, Converted integer value is posted here
(middle node) UINT
1 INT, A constant value of 1 (can not be changed)
(bottom node) UINT
Top output 0x None ON = integer conversion completed
successfully
Bottom output 0x None ON = converted integer value is out of range:
unsigned integer > 65 535
-32 768 > signed integer > 32 767
31007523 8/2010 501

502 31007523 8/2010

GD92 Gas Flow Function Block
31007523 8/2010
GD92 - Gas Flow Function Block
89
Introduction
This chapter describes the instruction GD92 AGA #3 and AGA #8 1992 detail
method.

Topic Page
Representation 505
Parameter Description - Inputs 507
Parameter Description - Outputs 513
Parameter Description - Optional Outputs 514
31007523 8/2010 503

Short Description
The gas flow loadable function block allows you to run AGA 3 (1992) and AGA 8
(1992) equations. The computed flow rates agree within 1 ppm of the published AGA
standards.
The GD92 instruction uses the detail method of characterization requiring detailed
knowledge of the gas composition.
The GD92 gas flow loadable function block is available only on certain Compact and
Micro controllers.
NOTE: GD92 does not support API 21.1 audit trail. GD92 only supports a single
meter run.
NOTE: You must install the LSUP loadable before the GD92.
More Information
For detailed information about the gas flow function block loadables, especially the:
z system warning/error codes (4x+0) for each instruction
z program warning/error codes (4x+1) for each instruction
z API 21.1 Audit Trail
z GET_LOGS.EXE utility
z SET_SIZE.EXE utility
please see the Modicon Starling Associates Gas Flow Loadable Function Block
User Guide (890 USE 137).
504 31007523 8/2010

Representation
Symbol
31007523 8/2010 505


Reference Type
Top input 0x, 1x None ON = solving
This input starts the calculation of the gas flow.
The calculations are based on your parameters
entered into the input registers.
Important: Never detach the top input while the block
is running. You will generate an error 188 and the
data in this block could be corrupted.
Important: You MUST fill in all pertinent values in the
configuration table.
(For information about entering values, see
Configuration Table, page 507.)
Middle input 0x, 1x None Allows you to set a warning.
Allows you to capture any user-defined warnings or
errors as needed in your applications.
Bottom input 0x, 1x None Allows you to set an error and STOP the flow function.
Allows you to capture any user-defined warnings or
errors as needed in your applications.
constant #0001 4x INT, The top node must contain a constant, #0001.
(top node) UINT
register 4x INT, The 4x register entered in the middle node is the first
(middle node) UINT in a group of contiguous holding registers that
comprise the configuration parameters and values
associated with the Gas Flow Block.
Important: Do not attempt to change the middle node
4x register while the Gas Flow Block is running. You
will lose your data and generate an error 302. If you
need to change the 4x register, first STOP the PLC.
#0003 INT, The bottom node specifies the calculation type and
(bottom node) UINT must contain a constant, #0003.
Top output 0x None ON = Operation successful
Middle output 0x None ON = System or program warning
Bottom output 0x None ON = System or program error
506 31007523 8/2010

Parameter Description - Inputs
Configuration Table
You must fill in all pertinent values in the configuration table using the reference data
editor either in ProWORX or Concept, or the DX Zoom screens in Modsoft, or Meter
Manager. The following inputs table lists all the configuration parameters that you
must be fill in.
The outputs (Outputs Results Table) and the optional outputs (Optional Outputs
Results Table) show the calculation results of the block. Some of those parameters
are required.
NOTE: Only valid entries are allowed. Entries outside the valid ranges are not
accepted. Illegal entries result in errors or warnings.
NOTE: Concept 2.1 or higher may be used to load the gas blocks. However,
Concept and ProWORX do not provide help or DX zoom screens for configuration.
When using Concept or ProWORX panel software, we recommend you use Meter
Manager for your configuration needs.
Inputs
The following is a detailed description of configuration variables for the GD92 gas
flow function block.
Inputs Description
4xxxx+3: 1 through 2 Location of Taps
1 - Upstream
2 - Downstream
4xxxx+3: 3 through 4 Meter Tube Material
1 - Stainless Steel
2 - Monel
3 - Carbon Steel
4xxxx+3: 5 through 6 Orfice Material
1 - Stainless Steel
2 - Monel
3 - Carbon Steel
4xxxx+3: 7 through 8 Reserved for Future Use (Do not use)
4xxxx+3: 9 through 10 Optional Outputs
1 - Yes
2 - No
Note: When using only the standard outputs, the loadable uses
157 4xxxx registers. When using the optional outputs, the
loadable uses 181 4xxxx registers.
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Inputs Description
4xxxx+4: 1 Absolute/Gauge Pressure
0 - Static Pressure Measured in Absolute Units
1 - Static Pressure Measured in Gauge Units
4xxxx+4: 2 Low Flow Cut Off
0 - Do Not Use Flow Cut Off
1 - Use Flow Cut Off
4xxxx+4: 3 through 6 Load Command
0 - Ready to Accept Command
1 - CMD: Send Configuration to Internal Table from 4xxxx
2 - CMD: Read Configuration from Internal Table to 4xxxx
3 - CMD: Reset API 21.1 configuration change log
4xxxx+4: 7 through 8 Input Type
1 - 3xxxx Pointers entered in 4x+6 ... 4x+10
2 - Input Values entered in 4x+6 ... 4x+10
4xxxx+4: 9 through 10 Mole % Error Limits
1 - Enable
2 - Disable
4xxxx+4: 11 through 12 Dual Range Differential Pressure Option
1 - Yes
2 - No
4xxxx+4: 13 through 14 Compressible/Incompressible
1 - Compressible
2 - Incompressible
4xxxx+4: 15 through 16 Averaging Methods
0 - Flow Dependent Time Weighted Linear
1 - Flow Dependent Time Weighted Formulaic
2 - Flow Weighted Linear
3 - Flow Weighted Formulaic
Note: For most applications you will use 0.
4xxxx+5: 1 through 2 Measurement Units
1 - US
2 - Metric (SI)
4xxxx+6 Temperature 3xxxx Pointer or Input Value
Data type: Unsigned integer value
4xxxx+7 Pressure (absolute) 3xxxx Pointer or Input Value
4xxxx+8 Differential Pressure 1 3xxxx Pointer or Input Value
508 31007523 8/2010

Inputs Description
4xxxx+10 Analog Input Raw Value Minimum Temperature
4xxxx+11 Analog Input Raw Value Maximum Temperature
4xxxx+12 Analog Input Raw Value Minimum Pressure
Data type: Signed integer value
4xxxx+13 Analog Input Raw Value Maximum Pressure
4xxxx+14 Analog Input Raw Value Minimum Differential Pressure 1
4xxxx+15 Analog Input Raw Value Maximum Differential Pressure 1
4xxxx+18 through 19 Engineering Unit Temperature Minimum
-200 through 760°F (-128.89 through 404.4°C)
Data type: Floating point number
4xxxx+20 through 21 Engineering Unit Temperature Maximum
4xxxx+22 through 23 Engineering Unit Pressure Minimum
0 through 40,000psia (0 through 275,790.28kPa)
4xxxx+24 through 25 Engineering Unit Pressure Maximum
4xxxx+26 through 27 Engineering Unit Differential Pressure 1 Minimum
>= 0 (inches H2O or kPa)
4xxxx+28 through 29 Engineering Unit Differential Pressure 1 Maximum
> 0 (inches H2O or kPa)
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Inputs Description
4xxxx+34 through 35 Orifice Plate Diameter, d r
(0 < dr < 100in) (0 < dr < 2540mm)
4xxxx+36 through 37 Orifice Plate Diameter Measurement Temperature, T r
(32 <= Tr < 77°F) (0 <= Tr < 25°C)
4xxxx+38 through 39 Meter Tube Internal Diameter D r
(0 <Dr <100in) (0 < Dr < 2540mm)
4xxxx+40 through 41 Measured Meter Tube Internal Diameter Temperature T r
(32 <= Tr < 77°F) (0 <= Tr < 25°C)
4xxxx+42 through 43 Base Temperature, T b
(32.0 <= Tb < 77.0°F) (0 <= Tb < 25°C)
4xxxx+44 through 45 Base Pressure, P b
(13.0 <= Pb < 16.0PSIA) (89.63 <= Pb < 110.32kPa)
4xxxx+46 through 47 Reference Temperature for Relative Density, T gr
(32.0 <= Tgr < 77.0°F) (0 <= Tgr < 25°C)
4xxxx+48 through 49 Reference Pressure for Relative Density, P gr
(13.0 <= Pgr < 16.0PSIA) (89.63 <= Pgr < 110.32kPa)
4xxxx+50 through 57 Reserved for Future Use (Do not use)
4xxxx+58 through 59 User Input Correction Factor, F u
(0 < Fu < 2.0)
4xxxx+60 through 61 Absolute Viscosity of Flowing Fluid, μ c
(0.005 <= μc <= 0.5 centipoise)
4xxxx+62 through 63 Isentropic Exponent, k
(1.0 <= k < 2.0)
4xxxx+64 Beginning of Day Hour
(0 ... 23)
510 31007523 8/2010

Inputs Description
4xxxx+79 through 80 Atmospheric Pressure P at
(3 <= Pat <30psi) (20.684 <= Pat < 206.843kPa)
4xxxx+81 through 82 Low Flow Cut Off Level
(>= 0ft3/Hr) (>= 0m3/Hr)
Used if enabled in 4x+4: 2.
4xxxx+83 through 84 Mole % of Methane, x i
*(0.0 <= xi <= 100)
4xxxx+85 through 86 Mole % of Nitrogen, x i
*(0.0 <= xi <= 100)
4xxxx+87 through 88 Mole % of Carbon Dioxide, x i
*(0.0 <= xi <= 100)
4xxxx+89 through 90 Mole % of Ethane, x i
*(0.0 <= xi <= 100)
xxx+91 through 92 Mole % of Propane, x i
*(0.0 <= xi <= 12)
4xxxx+93 through 94 Mole % of Water, x i
*(0.0 <= xi <= 10)
4xxxx+95 through 96 Mole % of Hydrogen Sulfide, x i
*(0.0 <= xi <= 100)
4xxxx+97 through 98 Mole % of Hydrogen, x i
*(0.0 <= xi <= 100)
4xxxx+99 through 100 Mole % of Carbon Monoxide, x i
*(0.0 <= xi <= 3)
4xxxx+101 through 102 Mole % of Oxygen, x i
*(0.0 <= xi <= 21)
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Inputs Description
4xxxx+103 through 104 Mole % of I-Butane, x i
*(0.0 <= xi <= 6) for combined butanes
4xxxx+105 through 106 Mole % of n-Butane, x i
4xxxx+107 through 108 Mole % of I-Pentane, x i
*(0.0 <= xi <= 4) for combined pentanes
4xxxx+109 through 110 Mole % of n-Pentane, x i
4xxxx+111 through 112 Mole % of Hexane, x i
*(0.0 <= xi <= 10) for combined hexanes +
4xxxx+113 through 114 Mole % of Heptane, x i
4xxxx+115 through 116 Mole % of Octane, x i
4xxxx+117 through 118 Mole % of Nonane, x i
4xxxx+119 through 120 Mole % of Decane, x i
4xxxx+121 through 122 Mole % of Helium, x i
*(0.0 <= xi <= 30)
4xxxx+123 through 124 Mole % of Argon, x i
*(0.0 <= xi <= 100)
*Valid range
512 31007523 8/2010

Parameter Description - Outputs
Outputs Results Table

The outputs show the calculation results of the block.
Outputs Description
4xxxx+0 System Warning/Error Code (Displayed in Hex mode)
4xxxx+1 Program Warning/Error Code
4xxxx+2 Version Number (Displayed in Hex mode)
4xxxx+125 through 126 Temperature at Flowing Conditions (Tf) (F or C)
4xxxx+127 through 128 Pressure (Pf) (psia or kPa)
4xxxx+129 through 130 Differential Pressure (hw) (in H2O or kPa
4xxxx+131 through 132 Integral Value (IV)
4xxxx+133 through 134 Integral Multiplier Value (IMV)
4xxxx+135 through 136 Volume Flow Rate at Base Conditions (Tb, Pb), Qb
(ft3/hr or m3/hr)
4xxxx+137 through 138 Mass Flow Rate (Qm) (lbm/hr or Kg/hr)
4xxxx+139 through 140 Accumulated Volume Current Day
4xxxx+141 through 142 Accumulated Volume Last Hour
4xxxx+143 through 144 Accumulated Volume Last Day
4xxxx+145 through 146 Average Temperature Last Day
4xxxx+147 through 148 Average Pressure Last Day
4xxxx+149 through 150 Average Differential Pressure Last Day
4xxxx+151 through 152 Average IV Last Day
4xxxx+153 through 154 Average Volume Flow Rate at Base Conditions (Tb, Pb) for the
Last Day
4xxxx+155: 13 4xxxx Table Differs from Actual Configuration
4xxxx+155: 14 Flow Rate Solve Complete Heartbeat
4xxxx+155: 15 Block is Functioning Heartbeat
4xxxx+155: 16 End of Day Flag
31007523 8/2010 513

Parameter Description - Optional Outputs
Optional Outputs Configuration Table

The optional outputs show the calculation results of the block. These are only active
if 4x+3: 9 ... 10 is 1.
Optional Outputs Description

4xxxx+156 through 157 Compressibility at Flowing Conditions (Tf, Pf), Zf
4xxxx+158 through 159 Compressibility at Base Conditions (Tb, Pb), Zb
4xxxx+160 through 161 Compressibility at Standard Conditions (Ts, Ps), Zs
4xxxx+162 through 163 Density at Fluid Flowing Conditions (Pt,p)
4xxxx+164 through 165 Density of Fluid at Base Conditions (ρ)
4xxxx+166 through 167 Supercompressibility (Fpv)
4xxxx+168 through 169 Gas Relative Density (Gr)
4xxxx+170 through 171 Orifice Plate Coefficient of Discharge (Cd)
4xxxx+172 through 173 Expansion Factor (Y)
4xxxx+174 through 175 Velocity of Approach Factor (Ev)
4xxxx+176 through 177 Volume Flow Rate at Flowing Conditions (Tf, Pf), Qf
4xxxx+180 Orifice Plate Coefficient of Discharge Bounds Flag within
Iteration Scheme (Cd-f)
514 31007523 8/2010

GFNX Gas Flow Function Block
31007523 8/2010
GFNX AGA#3 ‘85 and NX19 ‘68

Gas Flow Function Block
90
Introduction
This chapter describes the instruction GFNX AGA#3 ‘85 and NX19 ‘68.

Topic Page
Representation 517
31007523 8/2010 515

Short Description
The GFNX AGA #3 ‘85 and NX19 API 21.1 gas flow loadable function block is
available only on certain Compact and Micro controllers.
standards.
The GFNX instruction uses the detail method of characterization requiring detailed
NOTE: You must install the LSUP loadable before the GFNX.
More Information
516 31007523 8/2010

Representation
Symbol

Reference Type
This input starts the calculation of the gas flow.
The calculations are based on your parameters
entered into the input registers.
Important: Never detach the top input while the
block is running. You will generate an error 188 and
the data in this block could be corrupted.
Important: You MUST fill in all pertinent values in
the configuration table.
31007523 8/2010 517


Reference Type
Allows you to set a warning and log peripheral
activities in the audit trail even log without stopping
the block.
Bottom input 0x, 1x None Allows you to set an error and STOP the flow
function.
Allows you to set an error, log peripheral errors in
the audit trail event log, and STOP the flow
function.
constant #0001 4x INT, The top node must contain a constant, #0001.
(top node) UINT
register 4x INT, The 4x register entered in the middle node is the
(middle node) UINT first in a group of contiguous holding registers that
comprise the configuration parameters and values
associated with the Gas Flow Block.
Important: Do not attempt to change the middle
node 4x register while the Gas Flow Block is
running. You will lose your data and generate an
error 302. If you need to change the 4x register,
first STOP the PLC.
method INT, The bottom node specifies the calculation type and
(bottom node) UINT must contain a constant.
Important: Use only valid entries. Other entries
deny access to the block’s DX zoom screens.
518 31007523 8/2010

Configuration Table
must fill in.
are required.
Inputs
The following is a detailed description of configuration variables for the GFNX gas
Inputs Description
1 - Upstream
2 - Downstream
1 - Stainless Steel
2 - Monel
3 - Carbon Steel
1 - Stainless Steel
2 - Monel
3 - Carbon Steel
1 - Yes
2 - No
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Inputs Description
1 - Enable
2 - Disable
1 - Yes
2 - No
1 - Compressible
2 - Incompressible
1 - US
2 - Metric (SI)
4xxxx+5: 15 through 16 Reserved for API 21.1
520 31007523 8/2010

Inputs Description
-40 through 240°F (-40 through 115.5556°C)
-40 through 240°F (-40 through 115.5556°C)
31007523 8/2010 521

Inputs Description
(0 < dr < 100in) (0 < dr < 2540mm)
(32 <= Tr < 77°F) (0 <= Tr < 25°C)
(0 <Dr <100in) (0 < Dr < 2540mm)
(32 <= Tr < 77°F) (0 <= Tr < 25°C)
(32.0 <= Tb < 77.0°F) (0 <= Tb < 25°C)
(13.0 <= Pb < 16.0PSIA) (89.63 <= Pb < 110.32kPa)
(0 < Fu < 2.0)
(0 ... 23)
4xxxx+65 through 78 Reserved for API 21.1
(3 <= Pat <30psi) (20.684 <= Pat < 206.843kPa)
(>= 0ft3/Hr) (>= 0m3/Hr)
522 31007523 8/2010

Inputs Detail Method 11

The following inputs apply to detail method 11.
Inputs Description
Applies when using Detail Method 11
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
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Inputs Description
Applies when using Detail Method 11
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 30)
4xxxx+123 through 124 Reserved for future use (do not use)
*Valid range
524 31007523 8/2010

Inputs Gross Methods 10, 12, and 13

The following inputs apply to gross methods 10, 12, and 13.
Inputs Description
Applies when using Gross Methods 10, 12, and 13
*(0.0 <= xi <= 100)
(Required for method 13 ONLY)
*(0.0 <= xi <= 100)
(Required for methods 10, 12, and 13)
*(0.0 <= xi <= 100)
4xxxx+93 through 94 Specific Gravity, G r
(0.07 <= Gr < 1.52
4xxxx+95 through 96 Heating Value, HV
(0.07 HV < 1800)
(Required for method 12 ONLY)
*Valid range
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Outputs Description
4xxxx+129 through 130 Differential Pressure (hw) (in H2O or kPa)
ft3/hr or m3/hr
4xxxx+153 User-definable warning/error value (Use for API 21.1)
Note: This status bit does not appear in the DX Zoom screen
but may be used in program logic.
526 31007523 8/2010


if 4x+3: 9 ... 10 is 1.

4xxxx+166 through 167 Supercompressibility, F pv
4xxxx+168 through 169 Gas Relative Density, G r
4xxxx+172 through 173 Expansion Factor, Y
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528 31007523 8/2010

GG92 Gross Method Gas Flow Function Block
31007523 8/2010
GG92 AGA #3 1992 Gross Method

Gas Flow Function Block
91
Introduction
This chapter describes the instruction GG92 AGA #3 and AGA #8 1992 gross
method gas flow function block.

Topic Page
Representation 531
31007523 8/2010 529

Short Description
The GG92 gas flow loadable function block is available only on certain Compact and
Micro controllers.
standards. The GG92 allows the API 21.1 audit trail. The GG92 permits 8 passes.
The GG92 instruction uses the detail method of characterization requiring detailed
NOTE: You must install the LSUP loadable before the GG92.
More Information
530 31007523 8/2010

Representation
Symbol

Reference
This input starts the calculation of the gas
flow.
The calculations are based on your
parameters entered into the input registers.
Important: Never detach the top input
while the block is running. You will generate
an error 188 and the data in this block could
be corrupted.
Important: You MUST fill in all pertinent
values in the configuration table.
31007523 8/2010 531


Reference
Allows you to set a warning and log
peripheral activities in the audit trail event
log without stopping the block.
Bottom input 0x, 1x None Allows you to set an error and STOP the
flow function.
Allows you to set an error, log peripheral
errors in the audit trail event log, and STOP
the flow function.
constant #0001 4x INT, UINT The top node must contain a constant,
(top node) #0001.
register 4x INT, UINT The 4x register entered in the middle node
(middle node) is the first in a group of contiguous holding
registers that comprise the configuration
parameters and values associated with the
Gas Flow Block.
Important: Do not attempt to change the
middle node 4x register while the Gas Flow
Block is running. You will lose your data. If
you need to change the 4x register, first
STOP the PLC.
method INT, UINT The bottom node specifies the calculation
(bottom node) type and must contain a constant, #0003.
The integer value entered in the bottom
node specifies the characterization
method:
z 1 - Gross Method 1 (HV-Gr-CO2)
z 2 - Gross Method 2 (Gr-CO2-N2)

532 31007523 8/2010

Configuration Table
must fill in.
are required.
Inputs
The following is a detailed description of configuration variables for the GG92 gas
Inputs Description
1 - Upstream
2 - Downstream
1 - Stainless Steel
2 - Monel
3 - Carbon Steel
1 - Stainless Steel
2 - Monel
3 - Carbon Steel
4xxxx+3: 7 through 8 Reserved for future use (do not use)
1 - Yes
2 - No
31007523 8/2010 533

Inputs Description
1 - Enable
2 - Disable
1 - Yes
2 - No
1 - Compressible
2 - Incompressible
1 - US
2 - Metric (SI)
4xxxx+5: 3 through 14 Reserved for future use (do not use)
534 31007523 8/2010

Inputs Description
14 through 149°F (-10 through 65°C)
14 through 149°F (-10 through 65°C)
0 through 1,470psia (0 through 11,996kPa)
0 through 1,470psia (0 through 11,996kPa)
31007523 8/2010 535

Inputs Description
(0 < dr < 100in) (0 < dr < 2540mm)
(32 <= Tr < 77°F) (0 <= Tr < 25°C)
(0 <Dr <100in) (0 < Dr < 2540mm)
(32 <= Tr < 77°F) (0 <= Tr < 25°C)
(32.0 <= Tb < 77.0°F) (0 <= Tb < 25°C)
(13.0 <= Pb < 16.0PSIA) (89.63 <= Pb < 110.32kPa)
(32.0 <= Tgr < 77.0°F) (0 <= Tgr < 25°C)
(13.0 <= Pgr < 16.0PSIA) (89.63 <= Pgr < 110.32kPa)
4xxxx+50 through 51 Reference Temperature for Molar Density, T d
(32.0 <= Td < 77.0°F) (0 <=Td < 25°C)
4xxxx52 through 53 Reference Pressure for Molar Density, P d
(13.0 <= Pd < 16.0PSIA) (89.63 <= Pd < 110.32kPa
4xxxx+54 through 55 Reference Temperature fo Heating Value, T h
(32.0 <= Th < 77.0) (0 <=Th < 25°C)
(0 < Fu < 2.0)
536 31007523 8/2010

Inputs Description
(0.01 <= μc <= 0.1 centipoise)
(1.0 <= k < 2.0)
(0 ... 23)
(3 <= Pat <30psi) (20.684 <= Pat < 206.843kPa)
(>= 0ft3/Hr) (>= 0m3/Hr)
*(0.0 <= xi <= 50)
(Required for method 2 only)
*(0.0 <= xi <= 30)
*(0.0 <= xi <= 10)
*(0.0 <= xi <= 3)
4xxxx+93 through 94 Specific Gravity, G r
*(.55 < Gr < 0.87))
4xxxx+95 through 96 Heating Value, HV
*(477 <= HV < 1211BTU/Ft3) (17.7725 <= HV < 45.1206Kj/dm3)
(Required for method 1 only)
*Valid range
31007523 8/2010 537


Outputs Description
(ft3/hr or m3/hr
4xxxx+153 User definable warning/error value (Use for API 21.1)
538 31007523 8/2010


if 4x+3: 9 ... 10 is 1.

31007523 8/2010 539

540 31007523 8/2010

GM92 - Gas Flow Function Block
31007523 8/2010
GM92 AGA #3 and #8 1992 Detail

Method Gas Flow Function Block
92
Introduction
This chapter describes the instruction GM92 AGA #3 and #8 1992 detail method
with API 21.1 audit trail.

Topic Page
Representation 543
31007523 8/2010 541

Short Description
The GM92 gas flow loadable function block is available only on certain Compact and
Micro controllers.
standards.
This function block allows you to run the API 21.1 audit trail. The block has 8 mether
runs.
NOTE: You must install the LSUP loadable before the GM92.
More Information
542 31007523 8/2010

Representation
Symbol

Reference
flow.
be corrupted.
31007523 8/2010 543


Reference
flow function.
the flow function.
(top node) #0001.
Gas Flow Block.
STOP the PLC.
#0003 INT, UINT The bottom node specifies the calculation
544 31007523 8/2010

Configuration Table
must fill in.
are required.
Inputs
The following is a detailed description of configuration variables for the GD92 gas
Inputs Description
1 - Upstream
2 - Downstream
1 - Stainless Steel
2 - Monel
3 - Carbon Steel
1 - Stainless Steel
2 - Monel
3 - Carbon Steel
1 - Yes
2 - No
31007523 8/2010 545

Inputs Description
1 - Enable
2 - Disable
1 - Yes
2 - No
1 - Compressible
2 - Incompressible
1 - US
2 - Metric (SI)
546 31007523 8/2010

Inputs Description
31007523 8/2010 547

Inputs Description
(0 < dr < 100in) (0 < dr < 2540mm)
(32 <= Tr < 77°F) (0 <= Tr < 25°C)
(0 <Dr <100in) (0 < Dr < 2540mm)
(32 <= Tr < 77°F) (0 <= Tr < 25°C)
(32.0 <= Tb < 77.0°F) (0 <= Tb < 25°C)
(13.0 <= Pb < 16.0PSIA) (89.63 <= Pb < 110.32kPa)
(32.0 <= Tgr < 77.0°F) (0 <= Tgr < 25°C)
(13.0 <= Pgr < 16.0PSIA) (89.63 <= Pgr < 110.32kPa)
(0 < Fu < 2.0)
(0.005 <= μc <= 0.5 centipoise)
(1.0 <= k < 2.0)
(0 ... 23)
548 31007523 8/2010

Inputs Description
(3 <= Pat <30psi) (20.684 <= Pat < 206.843kPa)
(>= 0ft3/Hr) (>= 0m3/Hr)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 12)
*(0.0 <= xi <= 10)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 100)
*(0.0 <= xi <= 3)
*(0.0 <= xi <= 21)
31007523 8/2010 549

Inputs Description
*(0.0 <= xi <= 30)
4xxxx+123 through 124 Mole % of Argon, x i
*(0.0 <= xi <= 100)
*Valid range
550 31007523 8/2010


Outputs Description
4xxxx+127 through 128 Pressure (Pf) (psia or kPa
(ft3/hr or m3/hr)
31007523 8/2010 551


if 4x+3: 9 ... 10 is 1.

552 31007523 8/2010

G392 Gas Flow Function Block
31007523 8/2010
G392 AGA #3 1992 Gas Flow

Function Block
93
Introduction
This chapter describes the instruction G392 AGA #3 1992 gross method with API
21.1 audit trail.

Topic Page
Representation 555
31007523 8/2010 553

Short Description
The G392 gas flow loadable function block is available only on certain Compact and
Micro controllers.
The gas flow loadable function block allows you to run AGA 3 (1992) equations. The
computed flow rates agree within 1 ppm of the published AGA standards.
NOTE: You must install the LSUP loadable before the G392.
More Information
554 31007523 8/2010

Representation
Symbol

Reference
flow.
be corrupted.
31007523 8/2010 555


Reference
flow function.
the flow function.
(top node) #0001.
Gas Flow Block.
STOP the PLC.
#0017 INT, UINT The bottom node specifies the calculation
556 31007523 8/2010

Configuration Table
must fill in.
are required.
Inputs
The following is a detailed description of configuration variables for the G392 gas
Inputs Description
1 - Upstream
2 - Downstream
1 - Stainless Steel
2 - Monel
3 - Carbon Steel
1 - Stainless Steel
2 - Monel
3 - Carbon Steel
4xxxx+3: 7 through 8 Compressibility User Input Type
1 - Density at flowing and base condition
2 - Compressibility factor at flowing and base conditions and
gas relative density at base conditions
1 - Yes
2 - No
31007523 8/2010 557

Inputs Description
1 - Yes
2 - No
1 - Compressible
2 - Incompressible
1 - US
2 - Metric (SI)
558 31007523 8/2010

Inputs Description
31007523 8/2010 559

Inputs Description
(0 < dr < 100in) (0 < dr < 2540mm)
(32 <= Tr < 77°F) (0 <= Tr < 25°C)
(0 <Dr <100in) (0 < Dr < 2540mm)
(32 <= Tr < 77°F) (0 <= Tr < 25°C)
(32.0 <= Tb < 77.0°F) (0 <= Tb < 25°C)
(13.0 <= Pb < 16.0PSIA) (89.63 <= Pb < 110.32kPa)
(0 < Fu < 2.0)
(0.005 <= μc <= 0.5 centipoise)
(1.0 <= k < 2.0)
(0 ... 23)
4xxxx+65 through 78 Reserved for API 21.1 configuration
(3 <= Pat <30psi) (20.684 <= Pat < 206.843kPa)
(>= 0ft3/Hr) (>= 0m3/Hr)
560 31007523 8/2010

Inputs Description
4xxxx+83 through 84 Density at Flowing Conditions, ρf
(0 < ρf < 1000.0lbm/ft3) (0 < ρf < 1601.846kg/m3)
4xxxx+85 through 86 Density at Base Conditions, ρb
(0 < ρb < 100.0lbm/ft3) (0 < ρb < 1601.846kg/m3
4xxxx+87 through 88 Compressibility Factor at Flowing Conditions, Z f
(0 < Zf < 3)
4xxxx+89 through 90 Compressibility Factor at Base Conditions, Z b
(0 < Zb < 3)
xxx+91 through 92 Gas Relative Density at Base Conditions, Gr
(0.07 <= Gr < 1.52)
31007523 8/2010 561


Outputs Description
4xxxx+125 through 126 Temperature at Flowing Conditions (Tf) ((F or C)
(ft3/hr or m3/hr)
4xxxx+137 through 138 Mass Flow Rate (Qm)
562 31007523 8/2010


if 4x+3: 9 ... 10 is 1.

31007523 8/2010 563

564 31007523 8/2010

HLTH: History and Status Matrices
31007523 8/2010
94
Introduction
This chapter describes the instruction HLTH.

Topic Page
Representation 567
Parameter Description Top Node (History Matrix) 569
Parameter Description Middle Node (Status Matrix) 574
Parameter Description Bottom Node (Length) 578
31007523 8/2010 565

Short Description
Loadables. For further information, see Installation of DX Loadables, page 75.
The HLTH instruction creates history and status matrices from internal memory
registers that may be used in ladder logic to detect changes in PLC status and
communication capabilities with the I/O. It can also be used to alert the user to
changes in a PLC System. HLTH has two modes of operation, (learn) and (monitor).
566 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON initiates the designated operation
Middle input 0x, 1x None Learn / monitor mode
(For expanded and detailed information,
see Learn / Monitor Mode (MIddle and
Bottom Input), page 568.)
Bottom input 0x, 1x None Learn / monitor mode
(For expanded and detailed information,
see Learn / Monitor Mode (MIddle and
Bottom Input), page 568.)
history (top node) 4x INT, UINT, History matrix (first in a block of contiguous
WORD registers, range: 6 ... 135)
status (middle node) 4x INT, UINT, Status matrix (first in a block of contiguous
WORD registers, range: 3 ... 132)
length (bottom node) INT, UINT length = (number of RIO drops x 4) + 3
MIddle output 0x None Echoes state of the middle input
31007523 8/2010 567

Modes of operation
The HLTH instruction has two modes of operation:
Type of Mode Meaning

Learn Mode HLTH can be initialized to learn the configuration in which it is
implemented and save the information as a point-in-time reference
called history matrix.
This matrix contains:
z A user-designated drop number for communications status
monitoring
z User logic checksum
z Disabled I/O indicator
z S911 Health
z Choice of single or dual cable system
z I/O Map display
Monitor Mode Monitor mode enables an operation that checks PLC system
conditions. Detected changes are recorded in a status matrix., which
monitors the most recent system conditions and sets bit patterns to
indicate detected changes.
The status matrix contains:
z Communication status of the drop designated in the history
matrix
z A flag to indicate when there is any disabled I/O
z Flags to indicate the "on/off" status of constant sweep and the
Memory protect key switch
z Flags to indicate a battery-low condition and if Hot Standby is
functional
z Failed module position data
z Changed user logic checksum flag
z RIO lost-communication flag
Learn / Monitor Mode (MIddle and Bottom Input)

The HLTH instruction block has three control inputs and can produce three possible
outputs.
The combined states of the middle and bottom inputs control the operating mode:
Middle Input Bottom Input Operation

ON OFF Learn Mode as Dual Cable System
ON ON Learn Mode as Single Cable System
OFF ON Monitor Mode
OFF OFF Monitor Mode Update Logic Checksum
568 31007523 8/2010

Parameter Description Top Node (History Matrix)
History Matrix (Top Node)

The 4x register entered in the top node is the first in a block of contiguous registers
that comprise the history matrix. The data for the history matrix is gathered by the
instruction during a learn mode operation and is set in the matrix when the mode
changes to monitor.
The history matrix can range from 6 ... 135 registers in length. Below is a description
of the words in the history matrix. The information from word 1 is contained in the
displayed register in the top node and the information from words 2 ... 135 is stored
in the implied registers.
Word 1
Enter drop number (range 0 ... 32) to be monitored for retries
Word 2
High word of learned checksum
Word 3
Low word of learned checksum
Word 4
The status and a counter for multiplexing the inputs. HLTH processes 16 words of
input (256 inputs) per scan. This word holds the last word location of the last scan.
The register is overwritten on every scan. The value in the counter portion of the
word increases to the maximum number of inputs, then restarts at 0.
Usage of word 4:
Bit Function
1 1 = at least one disabled input has been found
2 - 16 Count of the number of word checked for disabled inputs prior to this scan.
31007523 8/2010 569

Word 5
Status and a counter for multiplexing outputs to detect if one is disabled. HLTH looks
at 16 words (256 outputs) per scan to find one that is disabled. It holds the last word
location of the last scan. The block is overwritten on every scan. The value in the
counter portion increases to maximum outputs then restarts at 0.
Usage of word 5:
Bit Function
1 1 = at least one disabled output has been found.
2 - 16 Count of the number of word checked for disabled outputs prior to this scan.
Word 6
Hot Standby cable learned data
Usage of word 6:
Bit Function
1 1 = S911 present during learn.
2-8 Not used
9 1 = cable A is monitored.
10 1 = cable B is monitored.
11 - 16 Not used
Word 7 ... 134

These words define the learned condition of drop 1 to drop 32 as follows:
Word Drop No.

7 ... 10 1
11 ... 14 2
15 ... 18 3
: :
: :
131 ... 134 32
The structure of the four words allocated to each drop are as follows:
570 31007523 8/2010

First Word
Bit Function
1 Drop delay bit 1
Note: Drop delay bits are used by the software to delay the monitoring of the
drop for four scans after reestablishing communications with a drop. The delay
value is for internal use only and needs no user intervention.
2 Drop delay bit 2
3 Drop delay bit 3
4 Drop delay bit 4
5 Drop delay bit 5
6 Rack 1, slot 1, module found
Second Word
Bit Function
31007523 8/2010 571

Bit Function
Third Word
Bit Function
572 31007523 8/2010

Fourth Word
Bit Function
13 ... 16 not used
31007523 8/2010 573

Parameter Description Middle Node (Status Matrix)
Status Matrix (Middle Node)

The 4x register entered in the middle node is the first in a block of contiguous holding
registers that will comprise the status matrix. The status matrix is updated by the
HLTH instruction during monitor mode (top input is ON and middle input is OFF).
The status matrix can range from 3 ... 132 registers in length. Below is a description
of the words in the status matrix. The information from word 1 is contained in the
displayed register in the middle node and the information from words 2 ... 131 is
stored in the implied registers.
Word 1
This word is a counter for lost-communications at the drop being monitored.
Usage of word 1:
Bit Function
1-8 Indicates the number of the drop being monitored (0 ... 32).
9 - 16 Count of the lost communication incidents (0 ... 15).
Word 2
This word is the cumulative retry counter for the drop being monitored (the drop
number is indicated in the high byte of word 1).
Usage of word 2:
Bit Function
1-4 Not used
5 - 16 Cumulative retry count (0 ... 255).
Word 3
This word updates PLC status (including Hot Standby health) on every scan.
574 31007523 8/2010

Usage of word 3:
Bit Function
1 ON = all drops are not communicating.
2 Not used
3 ON = logic checksum has changed since last learn.
4 ON = at least one disabled 1x input detected.
5 ON = at least one disabled 0x output detected.
6 ON = constant sweep enabled.
7 - 10 Not used
11 ON = memory protect is OFF.
12 ON = battery is bad.
13 ON = an S911 is bad.
14 ON = Hot Standby not active.
15 - 16 Not used
Word 4 ... 131

These words indicate the status of drop 1 to drop 32 as follows:
Word Drop No.

4 ... 7 1
8 ... 11 2
12 ... 15 3
: :
: :
128 ... 131 32
The structure of the four words allocated to each drop is as follows:

First Word
Bit Function
1 Drop communication fault detected
2 Rack 1, slot 1, module fault
31007523 8/2010 575

Bit Function
Second Word
Bit Function
576 31007523 8/2010

Third Word
Bit Function
Fourth Word
Bit Function
9 Cable A fault
10 Cable B fault
11 ... 16 not used
31007523 8/2010 577

Parameter Description Bottom Node (Length)

The decimal value entered in the bottom node is a function of how many I/O drops
you want to monitor. Each drop requires four registers/matrix. The length value is
calculated using the following formula:
length = (# of I/O drops x 4) + 3
This value gives you the number of registers in the status matrix. You only need to
enter this one value as the length because the length of the history matrix is
automatically increased by 3 registers -i.e., the size of the history matrix is
length + 3.
578 31007523 8/2010

HSBY - Hot Standby
31007523 8/2010
HSBY - Hot Standby
95
Introduction
This chapter describes the instruction HSBY.

Topic Page
Representation: HSBY - Hot Standby 581
Parameter Description Top Node 583
Parameter Description Middle Node: HSBY - Hot Standby 584
31007523 8/2010 579

HSBY - Hot Standby
Short Description
The HSBY loadable instruction manages a 984 Hot Standby control system. This
instruction must be placed in network 1 of segment 1 in the application logic for both
the primary and standby controllers. It allows you to program a nontransfer area in
system state RAM—an area that protects a serial group of registers in the standby
controller from being modified by the primary controller.
Through the HSBY instruction you can access two registers—a command register
and a status register. Access allows you to monitor and control Hot Standby
operations. The status register is the third register in the nontransfer area you
specify.
580 31007523 8/2010

HSBY - Hot Standby
Representation: HSBY - Hot Standby
Symbol
31007523 8/2010 581

HSBY - Hot Standby

Reference
Top input 0x, 1x None Execute HSBY (unconditionally)
ON = function enabled
Middle input 0x, 1x None Enable command register
Bottom input 0x, 1x None Enable nontransfer area
command 4x INT, UINT The 4xxxx register entered in the top node
register is the HSBY command register; eight bits in
(top node) this register may be configured and
controlled via your panel software.
(For more information, see Configuring the
Register, page 583.)
nontransfer 4x INT, UINT The 4xxxx register entered in the middle
area node is the first register reserved for the
(middle node) nontransfer area in state RAM. The first
three registers in the nontransfer area are
special registers.
(For more information, see Nontransfer
Area Special Registers, page 584 or
Application Specific Registers, page 584.)
length INT, UINT The integer value entered in the bottom
(bottom node) node defines the length (the number of
registers) of the HSBY nontransfer area in
state RAM. The length must be at least four
registers; in the range from 4 through 255
registers in a 16-bit CPU, and in the range
of 4 through 8000 registers in a 24-bit CPU.
Top output 0x None Hot Standby system ACTIVE
Middle output 0x None PLC cannot communicate with its HSBY
module
582 31007523 8/2010

HSBY - Hot Standby
Parameter Description Top Node
Configuring the Register

You may configure bits six through eight and 12 through 16.
Follow these guidelines for configuring those bits.
Bit Function
6 0 = Swap Modbus port 2 address during switchover
1 = Do not swap Modbus port 3 address during switchover
1 = Do not swap Modbus port 2 address during switchover
1 = Do not swap Modbus port q address during switchover
12 0 = Allow exec upgrade only after application stops
1 = Allow exec upgrade without stopping application
13 0 = Force standby offline if there is a logic mismatch
1 = Do not force standby offline if there is a logic mismatch
14 0 = Controller B in OFFLINE mode
1 = Controller B in RUN mode
15 0 = Controller A in OFFLINE mode
1 = Controller A in RUN mode
16 0 = Disable keyswitch override
1 = Enable keyswitch override
31007523 8/2010 583

HSBY - Hot Standby
Parameter Description Middle Node: HSBY - Hot Standby
Nontransfer Area Special Registers

The first three registers in the nontransfer area are special registers.
Register Content
Displayed and first implied These two registers are reverse transfer registers for
passing information from the standby to the primary PLC
Second implied HSBY status register
Application Specific Registers

Bits 11 through 16 are application specific.
The content of the remaining registers is application specific. The length is defined
in the bottom node.
Bit Function
11 0 = This PLC’s switch set to A
1 = This PLC’s switch set to B
12 0 = PLCs have matching logic
1 = PLCs do not have matching logic
13 0 1 = The other PLC in OFFLINE mode
14 1 0 = The other PLC running in primary mode
1 1 = The other PLC running in standby mode
15 0 1 = This PLC in OFFLINE mode
16 1 0 = This PLC running in primary mode
1 1 = This PLC running in standby mode
584 31007523 8/2010

IBKR: Indirect Block Read
31007523 8/2010
96
Introduction
This chapter describes the instruction IBKR.

Topic Page
Representation: IBKR - Indirect Block Read 587
31007523 8/2010 585

Short Description
The IBKR (indirect block read) instruction lets you access non-contiguous registers
dispersed throughout your application and copy the contents into a destination block
of contiguous registers. This instruction can be used with subroutines or for
streamlining data access by host computers or other PLCs.
586 31007523 8/2010

Representation: IBKR - Indirect Block Read
Symbol

Reference
Top input 0x, 1x None ON = initiates indirect read operation
source table 4x INT, UINT First holding register in a source table:
(top node) contain values that are pointers to the
non-contiguous registers you want to
collect in the operation.
destination block 4x INT, UINT First in a block of contiguous destination
(middle node) registers, i.e. the block to which the
source data will be copied.
length (1 ... 255) INT, UINT Number of registers in the source table
(bottom node) and the destination block, range: 1 ... 255
Bottom output 0x None ON = error in source table
31007523 8/2010 587

588 31007523 8/2010

IBKW: Indirect Block Write
31007523 8/2010
97
Introduction
This chapter describes the instruction IBKW.

Topic Page
Representation 591
31007523 8/2010 589

Short Description
The IBKW (indirect block write) instruction lets you copy the data from a table of
contiguous registers into several non-contiguous registers dispersed throughout
your application.
590 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = initiates indirect write operation
source block 4x INT, UINT First in a block of source registers: contain
(top node) values that will be copied to non-
contiguous registers dispersed throughout
the logic program
destination 4x INT, UINT First in a block of contiguous destination
pointers pointer registers. Each of these registers
(middle node) contains a value that points to the address
of a register where the source data will be
copied.
length INT, UINT Number of registers in the source block
(1 ... 255) and the destination pointer block,
(bottom node) range: 1 ... 255
Bottom output 0x None ON = error in destination table
31007523 8/2010 591

592 31007523 8/2010

ICMP: Input Compare
31007523 8/2010
ICMP: Input Compare
98
Introduction
This chapter describes the instruction ICMP.

Topic Page
Representation: ICMP - Input Compare 595
Cascaded DRUM/ICMP Blocks 598
31007523 8/2010 593

ICMP: Input Compare
Short Description
The ICMP (input compare) instruction provides logic for verifying the correct
operation of each step processed by a DRUM instruction. Errors detected by ICMP
may be used to trigger additional error-correction logic or to shut down the system.
ICMP and DRUM are synchronized through the use of a common step pointer
register. As the pointer increments, ICMP moves through its data table in lock step
with DRUM. As ICMP moves through each new step, it compares-bit for bit-the live
input data to the expected status of each point in its data table.
594 31007523 8/2010

ICMP: Input Compare
Representation: ICMP - Input Compare
Symbol

Reference
Top input 0x, 1x None ON = initiates the input comparison
Middle input 0x, 1x None A cascading input, telling the block that
previous ICMP comparison were all good,
ON = compare status is passing to the
middle output
step pointer 4x INT, UINT Current step number
(top node)
step data table 4x INT, UINT First register in a table of step data
(middle node) information
length INT, UINT Number of application-specific registers-
(bottom node) used in the step data table, range: 1 .. 999
Middle output 0x None ON =this comparison and all previous
cascaded ICMPs are good
31007523 8/2010 595

ICMP: Input Compare
Step Pointer (Top Node)

The 4x register entered in the top node stores the step pointer, i.e., the number of
the current step in the step data table. This value is referenced by ICMP each time
the instruction is solved. The value must be controlled externally by a DRUM
instruction or by other user logic. The same register must be used in the top node of
all ICMP and DRUM instructions that are solved as a single sequencer.

The 4x register entered in the middle node is the first register in a table of step data
information. The first eight registers in the table hold constant and variable data
required to solve the instruction:

Displayed raw input Loaded by user from a group of sequential inputs to be used by
data ICMP for current step
First current Loaded by ICMP each time the block is solved; contains a copy of
implied step data data in the step pointer; causes the block logic to automatically
calculate register offsets when accessing step data in the step data
table
Second input mask Loaded by user before using the block; contains a mask to be
implied ANDed with raw input data for each step-masked bits will not be
compared; masked data are put in the masked input data register
Third masked Loaded by ICMP each time the block is solved; contains the result
implied input data of the ANDed input mask and raw input data
Fourth compare Loaded by ICMP each time the block is solved; contains the result
implied status of an XOR of the masked input data and the current step data;
unmasked inputs that are not in the correct logical state cause the
associated register bit to go to 1-non-zero bits cause a miscompare,
and middle output will not go ON
Fifth machine Identifies DRUM/ICMP blocks belonging to a specific machine
implied ID number configuration; value range: 0 ... 9999 (0 = block not configured); all
blocks belonging to same machine configuration have the same
machine ID
Sixth Profile ID Identifies profile data currently loaded to the sequencer; value
implied Number range: O... 9999 (0 = block not configured); all blocks with the same
machine ID number must have the same profile ID number
Seventh Steps Loaded by user before using the block, DRUM will not alter steps
implied used used contents during logic solve: contains between 1 ... 999 for 24
bit CPUs, specifying the actual number of steps to be solved; the
number must be £ the table length in the bottom node of the ICMP
block
The remaining registers contain data for each step in the sequence.
596 31007523 8/2010

ICMP: Input Compare

The integer value entered in the bottom node is the length-i.e., the number of
application-specific registers-used in the step data table. The length can range from
1 .. 999 in a 24-bit CPU.
length must be > the value placed in the steps used register in the middle node.
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ICMP: Input Compare
Cascaded DRUM/ICMP Blocks
Cascaded DRUM/ICMP Blocks

A series of DRUM and/or ICMP blocks may be cascaded to simulate a mechanical
drum up to 512 bits wide. Programming the same 4x register reference into the top
node of each related block causes them to cascade and step as a grouped unit
without the need of any additional application logic.
All DRUM/ICMP blocks with the same register reference in the top node are
automatically synchronized. The must also have the same constant value in the
bottom node, and must be set to use the same value in the steps used register in
the middle node.
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ID: Interrupt Disable
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99
Introduction
This chapter describes the instruction ID.

Topic Page
Representation 601
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Short Description
instruction.
The ID instruction masks timer-generated and/or local I/O-generated interrupts.
An interrupt that is executed in the time frame after an ID instruction has been solved
one time.
600 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = instruction masks timer-generated
and/or local I/O generated interrupts
Type INT, UINT Type of interrupt to be masked (Constant
bottom node integer)
please see the section Type (Bottom
Node), page 602.)
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Type (Bottom Node)

Enter a constant integer in the range 1 ... 3 in the node. The value represents the
type of interrupt to be masked by the ID instruction, where:
Integer Value Interrupt Type

3 Timer interrupt masked
2 Local I/O module interrupt masked
1 Both interrupt types masked
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IE: Interrupt Enable
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100
Introduction
This chapter describes the instruction IE.

Topic Page
Representation 605
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Short Description
instruction.
The IE instruction unmasks interrupts from the timer or local I/O module and
responds to the pending interrupts by executing the designated subroutines.
An interrupt that is executed in the time frame after an ID instruction has been solved
one time.
604 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = instruction unmasks interrupts and
responds pending interrupts
Type INT, UINT Type of interrupt to be unmasked
bottom node (Constant integer)
For more information, see Type (Bottom
Node), page 606.
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Top Input
When the input is energized, the IE instruction unmasks interrupts from the timer or
local I/O module and responds to the pending interrupts by executing the designated
subroutines.
Type (Bottom Node)

Enter a constant integer in the range 1 ... 3 in the node. The value represents the
type of interrupt to be unmasked by the IE instruction, where:
Integer Value Interrupt Type

3 Timer interrupt unmasked
2 Local I/O module interrupt unmasked
1 Both interrupt types unmasked
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IMIO: Immediate I/O
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IMIO: Immediate I/O
101
Introduction
This chapter describes the instruction IMIO.
NOTE: This instruction is only available after configuring a CPU without extension.

Topic Page
Representation 609
Run Time Error Handling: IMIO - Immediate I/O 612
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IMIO: Immediate I/O
Short Description
The IMIO instruction permits access of specified I/O modules from within ladder
logic. This differs from normal I/O processing, where inputs are accessed at the
beginning of the logic solve for the segment in which they are used and outputs are
updated at the end of the segment’s solution. The I/O modules being accessed must
reside in the local backplane with the Quantum PLC.
In order to use IMIO instructions, the local I/O modules to be accessed must be
designated in the I/O Map in your panel software.
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IMIO: Immediate I/O
Representation
Symbol
NOTE: This IMIO block will not work with the following Compact I/O modules due to
hardware design restrictions inherent with these modules
z AS-BADU-204
z AS-BADU-205
z AS-BADU-206
z AS-BADU-216

Reference
Top input 0x, 1x None ON = enables the immediate I/O access
control block 4x INT, UINT, Control block (first of two contiguous registers)
top node WORD For more information, see Runtime Errors,
page 612.
type INT, UINT Type of operation (constant integer in the range
bottom node of 1 ... 3)
This is the function to perform
z 1 – Input operation: Transfer data from
module to state RAM
z 2 – Output operation: Transfer date from
state RAM to module
z 3 – Bidirectional or I/O operation: Allows both
Input and Output for bidirectional modules
Bottom output 0x None Error (indicated by a code in the error status
register in the IMIO control block)
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IMIO: Immediate I/O

Register Content
Displayed This register specifies the physical address of the I/O module to be
accessed.
First implied This register logs the error status, which is maintained by the
instruction.
Physical Address of the I/O Module

The high byte of the displayed register in the control block allows you to specify
which rack the I/O module to be accessed resides in, and the low byte allow you to
specify slot number within the specified rack where the I/O module resides.
Usage of word:
Bit Function
1-5 Not used
Rack 1 only for Quantum
Local racks 1 through 4 can be used for 32-bit Compact
6-8 Rack number 1 to 4 (only rack 1 is currently supported)
9 - 11 Not used
12 - 16 Slot number
Rack Number
Bit Number Rack Number

6 7 8
0 0 1 rack 1
Rack 1 only for Quantum
Racks 1 through 4 can be used for 32-bit Compact
0 1 0 rack 2
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IMIO: Immediate I/O
Bit Number Rack Number

6 7 8
0 1 1 rack 3
1 0 0 rack 4
Slot Number
Bit Number Slot Number

12 13 14 15 16
0 0 0 0 1 slot 1
0 0 0 1 0 slot 2
0 0 0 1 1 slot 3
0 0 1 0 0 slot 4
0 0 1 0 1 slot 5
0 0 1 1 0 slot 6
0 0 1 1 1 slot 7
0 1 0 0 0 slot 8
0 1 0 0 1 slot 9
0 1 0 1 0 slot 10
0 1 0 1 1 slot 11
0 1 1 0 0 slot 12
0 1 1 0 1 slot 13
0 1 1 1 0 slot 14
0 1 1 1 1 slot 15
1 0 0 0 0 slot 16
Type (Bottom Node)

Enter a constant integer in the range 1 ... 3 in the bottom node. The value represents
the type of operation to be performed by the IMIO instruction, where:
Integer Value Type of Immediate Access

1 Input operation: transfers data from the specified module to state RAM
2 Output operation: transfers data from state RAM to the specified module
3 I/O operation: does both input and output if the specified module is
bidirectional
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IMIO: Immediate I/O
Run Time Error Handling: IMIO - Immediate I/O
Runtime Errors
The implied register in the control block will contain the following error code when
the instruction detects an error:
Error Code Meaning

2001 Invalid type specified in the bottom node
2002 Problem with the specified I/O slot, either an invalid slot number entered
in the displayed register of the control block or the I/O Map does not
contain the correct module definition for this slot
2003 A type 3 operation is specified in the bottom node, and the module is not
bidirectional
F001 Specified I/O module is not healthy
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IMOD: Interrupt Module Instruction
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IMOD:
Interrupt Module Instruction
102
Introduction
This chapter describes the instruction IMOD.

Topic Page
Representation 615
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Short Description
The IMOD instruction initiates a ladder logic interrupt handler subroutine when the
appropriate interrupt is generated by a local interrupt module and received by the
PLC. Each IMOD instruction in an application is set up to correspond to a specific
slot in the local backplane where the interrupt module resides. The IMOD instruction
can designate the same or a separate interrupt handler subroutine for each interrupt
point on the associated interrupt module.
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Representation
Symbol

Reference Type
Top input 0x, 1x None ON = initiates an interrupt
Bottom input 0x, 1x None ON = clears a previously detected error
slot number INT, Indicates the slot number where the local interrupt
(top node) UINT module resides (constant integer in the range of 1 ...
16)
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Reference Type
control block 4x INT, Control block (first of max. 19 contiguous registers,
(middle node) UINT, depending on number of interrupts)
WORD The middle node contains the first 4x register n the
IMOD control block. The control block contains
parameters required to program an IMOD
instruction. The size (number of registers) of the
control block will equal the total number of
programmed interrupt points + 3.
The first three registers in the control block contain
status information. The remaining registers provide
a means for you to specify the label (LAB) number
of the interrupt handler subroutine. The interrupt
handler subroutine is in the last (unscheduled)
segment of the ladder logic program.
For expanded and detailed information please see
Control Block (Middle Node), page 617,)
number of INT, Indicates the number of interrupts that can be
interrupts UINT generated from the associated interrupt module
(bottom node) (constant integer in the range of 1 ... 16)
The bottom node contains an integer indicating the
number of interrupts that can be generated from the
associated interrupt module. The size (number of
registers of the control block is the number of
interrupts + 3.
The PLC is able to be configured for a maximum of
64 module interrupts (from all the interrupt modules
residing in the local backplane). If the number you
enter in the bottom node of an IMOD instruction
causes the total number of module interrupts
system wide to exceed 64, an error is logged in bit
7 of the first register in the control block.
For example, if you use four interrupt modules in the
local backplane and assign 16 interrupts to each of
these modules (by entering 16 in the bottom node of
each associated 8MOD instruction, the PLC will not
be able to handle any more module interrupts. If you
attempt to create a fifth IMOD instruction, an error
will be logged in the IMOD’s control block when you
specify a value in the bottom node.
Bottom output 0x None ON = error is detected. The source of the error can
be from any one of the enabled interrupt points on
the interrupt module.
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General Information to IMOD

Up to 14 IMOD instructions can be programmed in a ladder logic application, one for
each possible option slot in a local backplane.
Each interrupting point on each interrupt module can initiate a different interrupt
handler subroutine.
A maximum of 64 interrupt points can be defined in a user logic application. It is not
necessary that all possible input points on a local interrupt module be defined in the
IMOD instruction as interrupts.
Enabling of the Instruction (Top Input)

When the input to the top node is energized, the IMOD instruction is enabled. The
PLC will respond to interrupts generated by the local interrupt module in the
designated slot number. When the top input is not energized, interrupts from the
module in the designated slot are disabled and all previously detected errors are
cleared including any pending masked interrupts.
Clear Error (Bottom Input)

This input clears previous errors.
Slot Number (Top Node)

The top node contains a decimal in the range 1 ... 16, indicating the slot number
where the local interrupt module resides. This number is used to index into an array
of control structures used to implement the instruction.
NOTE: The slot number in one IMOD instruction must be unique with respect to the
slot numbers used in all other IMOD instruction in an application. If not the next
IMOD with that particular slot number will have an error.
NOTE: The slot numbers where the PLC and the power supply reside are illegal
entries -i.e., a maximum of 14 of the 16 possible slot numbers can be used as
interrupt module slots. If the IMOD slot number is the same as the PLC, the IMOD
will have an error.
Control Block (Middle Node)

The middle node contains the first 4x register in the IMOD control block. The control
block contains parameters required to program an IMOD instruction. The size
(number of registers) of the control block will equal the total number of programmed
interrupt points + 3.
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The first three registers in the control block contain status information, of the
remaining registers provide means for you to specify the label (LAB) number of the
interrupt handler subroutine that is in the last (unscheduled) segment of the ladder
logic program.
Control Block for IMOD
Register Content
Displayed Function status bits
First implied State of inputs 1 ... 16 from the interrupt module at the time of the
interrupt
Second implied State of inputs 17 ... 32 from the interrupt module at the time of the
interrupt (invalid data for a 16-bit interrupt module)
Third implied LAB number and status for the first interrupt programmed point on
the interrupt module
... ...
Last implied LAB number and status for the last interrupt programmed point on
the interrupt
Function Status Bits

Function status bits
Bit Function
1-2 Not used
3 Error: controller slot
The slot number given in the top node of the IMOD is the CPU slot number.
4 Error: interrupt lost due to communication error in backplane
When reading the interrupting module, a computation error occurred and the
data is invalid. Because the interrupting points are cleared on the read, the
interrupt(s) are lost.
5 Module not healthy or not in I/O map
The I/O module in the slot given in the top node is not healthy (i.e., not working,
or missing) or a module has not been specified in the I/O map.
6 Error: interrupt lost because of on-line editing
While the operator was editing the ladder logic (this includes requesting a power
display of a different network, i.e., page up or page down), two or more interrupts
for the same point occurred. Only one is serviced.
7 Error: Maximum number of interrupts exceeded
More than 64 interrupts have been specified in the ladder logic and this "IMOD"
is the one that causes the count to exceed 64.
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Bit Function
8 Error: slot number used in previous network (CAUTION: see Loss of Interrupts,
page 619)
The slot number in the top node is used in another "IMOD" block with in the
ladder logic. The first block is working, but this one is ignored.
9 - 15 Not used
16 0 = IMOD disabled
1 = IMOD enabled
This bit reflects to the state of power in the top node.
Loss of Interrupts
CAUTION
LOSS OF INTERRUPTS: WORKING IMOD INSTRUCTION
An error is indicated in bit 8 when two IMOD instructions are assigned the same
slot number. When this happens, it is possible to lose interrupts from the working
IMOD instruction without an indication if the number specified in the bottom node
of the two instructions is different.
Failure to follow these instructions can result in injury or equipment damage.
Status Bits and LAB Number for each Interrupt Point

Bits 1 ... 5 of the third implied through last implied registers are status bits for each
interrupt point. Bits 7 ... 16 are used to specify the LAB number for the interrupt
handler subroutine. The LAB number is a decimal value in the range 1 ... 1023.
Function status bits
Bit Function
Interrupt Point Status
1 Execution delayed because of interrupt mask
This is not an error, but an indication that interrupts are disabled and at least one
interrupt for this point has occurred and will be serviced when interrupts are
enabled.
2 Error: invalid block in the interrupt handler subroutine
An invalid DX block has been used in the interrupt handler subroutine for this
input point (see Instructions that Cannot be Used in an Interrupt Handler for
details).
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Bit Function
3 Error: Mask interrupt overrun
Two or more interrupts for this point have occurred while the interrupt was
disabled: i.e., Use of the Interrupt Disable (ID) block without using the Interrupt
Enable (IE) block or during online editing.
4 Error: execution overrun
A second interrupt (or more) has occurred while the interrupt handler subroutine
was still running.
5 Error: invalid LAB number
The LAB number specified in bits 7...16, zero, or that LAB number is not used in
the last segment of the user logic. This error will Auto Clear.
6 not used
LAB number
7 - 16 LAB number for the associated interrupt handler
Value in the range 1 ... 1023
Whenever the input to the bottom node of the IMOD instruction is enabled, the status
bits (bits 1 ... 5) are cleared. If a LAB number is specified (in bits 7 ... 16) as 0 or an
invalid number, any interrupts generated from that point are ignored by the PLC.
Number of Interrupts (Bottom Node)

The bottom node contains an integer indicating the number of interrupts that can be
generated from the associated interrupt module. The size (number of registers) of
the control block is this number + 3.
The PLC is able to be configured for a maximum of 64 module interrupts (from all
the interrupt modules residing in the local backplane). If the number you enter in the
bottom node of an IMOD instruction causes the total number of module interrupts
system wide to exceed 64, an error is logged in bit 7 of the first register in the control
block.
For example, if you use four interrupt modules in the local backplane and assign 16
interrupts to each of these modules (by entering 16 in the bottom node of each
associated IMOD instruction, the PLC will not be able to handle any more module
interrupts. If you attempt to create a fifth IMOD instruction, an error will be logged in
that IMOD’s control block when you specify a value in the bottom node.
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INDX
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INDX –
Immediate Incremental Move
103
Introduction
This chapter describes the INDX instruction.

Topic Page
Parameters Description 623
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INDX
Short Description
The INDX function block issues an MMFStart Immediate Incremental Move on the
axis specified. The velocity and increment are specified in the associated table.
622 31007523 8/2010

INDX
Parameters Description
Symbol
The following diagram shows an INDX function.

Reference Type
Top input 0x None ON initiates the move function. When this input goes off,
the function is reset and can be initiated again.
controller.
UINT the arguments for the move. The last two registers are
for state control.
Bottom 4x INT The integer value entered in the bottom node specifies
node the table length. In this case, the number of registers in
Top output 0x None Turned on when the move start is complete without error.
Middle 0x None Turned on when the move is not started and an error
output code is generated in register 4xxxx5.
Bottom 0x None Turned on when the register length is not set at 8, the
output MMFSTART revision is not correct, or the function timed
out.
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INDX
Registers

4xxxxx Short Axis id for the incremental move.
4xxxx1 Float Length of the incremental move.
4xxxx3 Float Velocity of the incremental move.
4xxxx5 Short Error code generated when attempting to start move.
4xxxx6 Short Current operating state number
4xxxx7 Short Current state entry count.
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ITMR: Interrupt Timer
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104
Introduction
This chapter describes the instruction ITMR.

Topic Page
Representation 627
31007523 8/2010 625

Short Description
The ITMR instruction allows you to define an interval timer that generates interrupts
into the normal ladder logic scan and initiates the execution of an interrupt handling
subroutine. The user-defined interrupt handler is a ladder logic subroutine created
in the last, unscheduled segment of ladder logic with its first network marked by a
LAB instruction. Subroutine execution is asynchronous to the normal scan cycle.
Up to 16 ITMR instructions can be programmed in an application. Each interval timer
can be programmed to initiate the same or different interrupt handler subroutines,
controlled by the JSR/LAB method described in the chapter General.
Each instance of the interval timer is delayed for a programmed interval while the
PLC is running, then generates a processor interrupt when the interval has elapsed.
An interval timer can execute at any time during normal logic scan, including system
I/O updating or other system housekeeping operations. The resolution of each
interval timer is 1 ms. An interval can be programmed in units of 1 ms, 10 ms, 100
ms, or 1 s. An internal counter increments at the specified resolution.
You should be aware that if the ITMR time is less than the L/L edit time slice, there
will be no power flow display or user logic edit allowed.
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Representation
Symbol
31007523 8/2010 627


Reference
Top input 0x, 1x None ON = enables instruction
(For expanded and detailed information please
see the section Top Input.)
control block 4x INT, UINT, Control block (first of three contiguous registers)
(top node) WORD The top node contains the first of three contiguous
4xxxx registers in the ITMR control block. These
registers are used to specify the parameters
required to program each ITMR instruction.
The lower eight bits of the first (displayed) register
in the control block allow you to specify function
control parameters, and the upper eight bits are
used to display function status.
In the second register of the control block, specify
a value representing the interval at which the ITRM
instruction will generate interrupts and initiate the
execution of the interrupt handler. The interval will
be incremented in the units specified by bits 12 and
13 of the first control block register - i.e., 1 ms, 10
ms, 100 ms, or 1 s units.
In the third register of the control block, specify a
value indicating the label (LAB) number that will
start the interrupt handler subroutine. The number
must be in the range of 1 through 1023.
Note: We recommend that the size of the logic
subroutine associated with the LAB be minimized
so that the application does not become interrupt-
driven.
(For more information, see Control Block (Top
Node), page 629.)
timer number INT, UINT Timer number assigned to this ITMR instruction
(bottom node) (must be unique with respect to all other ITMR
instructions in the application); range: 1 ... 16
Bottom output 0x None Error (source of the error may be in the
programmed parameters or a runtime execution
error)
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Top Input
When the top input is energized, the ITMR instruction is enabled. It begins counting
the programmed time interval. When that interval has expired the counter is reset
and the designated error handler logic executes.
When the top input is not energized, the following events occur:
z All indicated errors are cleared
z The timer is stopped
z The time count is either reset or held, depending on the state of bit 15 of the first
register in the control block (the displayed register in the top node)
z Any pending masked interrupt is cleared for this timer

The top node contains the first of three contiguous 4x registers in the ITMR control
block. These registers are used to specify the parameters required to program each
ITMR instruction.
Control Block for ITMR
Register Content
Displayed Function status and function control bits
First implied In this register specify a value representing the interval at which the
ITMR instruction will generate interrupts and initiate the execution of
the interrupt handler.
The interval will be incremented in the units specified by bits 12 and
13 of the first control block register, i.e. 1 ms, 10 ms, 100 ms, or 1 s
units.
Second implied In this register specify a value indicating the label (LAB) number that
will start the interrupt handler subroutine.
The number must be in the range 1 ... 1023.
NOTE: We recommend that the size of the logic subroutine associated with the LAB
be minimized so that the application does not become interrupt-driven.
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Function Status and Function Control Bits

The lower eight bits of the displayed register in the control block allow you to specify
function control parameters, and the upper eight bits are used to display function
status:
Bit Function
Function Status
1 Execution delayed because of interrupt mask.
2 Invalid block in the interrupt handler subroutine.
3 Not used
4 Time = 0
5 Mask interrupt overrun.
6 Execution overrun.
7 No LAB or invalid LAB.
8 Timer number used in previous network.
Function Control
9 - 11 Not used
12 - 13 0 0 = 1 ms time base
0 1 = 10 ms time base
1 0 = 100 ms time base
1 1 = 1 s time base
14 1 = PLC stop holds counter.
0 = PLC stop resets counter.
15 1 = enable OFF holds counter.
0 = enable OFF resets counter.
16 1 = instruction enabled
0 = instruction disabled
Timer Number (Bottom Node)

Up to 16 ITMR instructions can be programmed in an application. The interrupts are
distinguished from one another by a unique number between 1 ... 16, which you
assign to each instruction in the bottom node. The lowest interrupt number has the
highest execution priority.
For example, if ITMR 4 and ITMR 5 occur at the same time, ITMR 4 is executed first.
After ITMR 4 has finished, ITMR 5 generally will begin executing.
An exception would be when another ITMR interrupt with a higher priority occurs
during ITMR 4’s execution. For example, suppose that ITMR 3 occurs while ITMR 5
is waiting for ITMR 4 to finish executing. In this case, ITMR 3 begins executing when
ITMR4 finishes, and ITMR 5 continues to wait.
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ITOF: Integer to Floating Point
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105
Introduction
This chapter describes the instruction ITOF.

Topic Page
Representation 633
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Short Description
The ITOF instruction performs the conversion of a signed or unsigned integer value
(its top node) to a floating point (FP) value, and stores the FP value in two
contiguous 4x registers in the middle node.
632 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = enables conversion
integer 3x, 4x INT, UINT Integer value, can be displayed explicitly
(top node) as an integer (range 1 ... 65 535) or stored
in a register
converted FP 4x REAL Converted FP value (first of two
(middle node) contiguous holding registers)
1 INT, UINT Constant value of 1, can not be changed
(bottom node)
Top output 0x None ON = FP conversion completed
successfully
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JOGS
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JOGS – JOG Move
106
Introduction
This chapter describes the JOGS instruction.

Topic Page
Representation 637
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JOGS
Short Description
This function block jogs an axis positive or negative using MMFStart Immediate
Continuous Move and Halt. Jog velocity is specified in the associated register table.
636 31007523 8/2010

JOGS
Representation
Symbol
The following diagram shows the JOGS function.
31007523 8/2010 637

JOGS

Reference Type
Top input 0x None ON activates a JOG positive. A HALT command is used
when the input turns off.
Middle Input 0x None ON activates a JOG negative. A HALT command is
used when the input turns off.
controller.
UINT the arguments for the jog. The last two registers are for
state control.
Bottom node 4x INT The integer value entered in the bottom node specifies
Top output 0x None Turned on when the jog has been issued without error
and reflects the state of the top or middle inputs.
Middle 0x None Turned on when the jog has been issued without error
output and reflects the state of the top or middle inputs.
Bottom 0x None Turned on when the register length is not set at 6.
output
Registers

4xxxxx Short Axis id for the incremental move.
4xxxx1 Float Velocity used for jogging the axis.
4xxxx3 Short Error code generated when attempting to start move.
4xxxx5 Short Current state entry count.
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JSR: Jump to Subroutine
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107
Introduction
This chapter describes the instruction JSR.

Topic Page
Representation 641
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Short Description
When the logic scan encounters an enabled JSR instruction, it stops the normal
logic scan and jumps to the specified source subroutine in the last (unscheduled)
segment of ladder logic.
You can use a JSR instruction anywhere in user logic, even within the subroutine
segment. The process of calling one subroutine from another subroutine is called
nesting. The system allows you to nest up to 100 subroutines; however, we
recommend that you use no more than three nesting levels. You may also perform
a recursive form of nesting called looping, whereby a JSR call within the subroutine
recalls the same subroutine.
Example to Subroutine Handling

For an example of subroutine handling, see Subroutine Handling, page 73.
640 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None Enables the source subroutine
source 4x INT, UINT Source pointer (indicator of the subroutine
(top node) to which the logic scan will jump), entered
explicitly as an integer or stored in a
register; range: 1 ... 1 023
#1 INT, UINT Always enter the constant value 1
(bottom node)
Bottom output 0x None Error in subroutine jump
On if jump cannot be executed
Label does not exist
or
Nesting level > 100
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642 31007523 8/2010

LAB: Label for a Subroutine
31007523 8/2010
108
Introduction
This chapter describes the instruction LAB.

Topic Page
Representation 645
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Short Description
The LAB instruction is used to label the starting point of a subroutine in the last
(unscheduled) segment of user logic. This instruction must be programmed in row
1, column 1 of a network in the last (unscheduled) segment of user logic. LAB is a
one-node function block.
LAB also serves as a default return from the subroutine in the preceding networks.
If you are executing a series of subroutine networks and you find a network that
begins with LAB, the system knows that the previous subroutine is finished, and it
returns the logic scan to the node immediately following the most recently executed
JSR block.
NOTE: If you need real world I/O serviced while you are in the interrupt subroutine,
you must use the IMIO (see page 607) (read/write) function block in the same
subroutine. If you do not, the real world I/O referenced in that subroutine will not get
serviced until the appropriate segment is solved.
Example to Subroutine Handling

For an example of subroutine handling, see Subroutine Handling, page 73.
644 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None Initiates the subroutine specified by the
number in the bottom node
subroutine INT, UINT Integer value, identifies the subroutine you
(top node) are about to execute
Range: 1 ... 255 16-bit PLC.
Range: 1 ... 1023 24-bit PLC.
Size = constant 1 - 255 or
Size = constant 1-1023 for 785L
Subroutine number error ON if return
cannot be executed
If more than one network begins with a
LAB instruction with the same subroutine
value, the lowest-numbered network is
used as the starting point for the
subroutine.
Top output 0x None ON = error in the specified subroutine’s
initiation
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Subroutine (Bottom Node)

The integer value entered in the node identifies the subroutine you are about to
execute. The value can range from 1 ... 255. If more than one subroutine network
has the same LAB value, the network with the lowest number is used as the starting
point for the subroutine.
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LOAD: Load Flash
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LOAD: Load Flash
109
Introduction
This chapter describes the instruction LOAD.

Topic Page
Representation 649
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LOAD: Load Flash
Short Description
NOTE: This instruction is available with the PLC family TSX Compact, with Quantum
CPUs 434 12/ 534 14 and Momentum CPUs CCC 960 x0/ 980 x0.
The LOAD instruction loads a block of 4x registers (previously saved) from state
RAM where they are protected from unauthorized modification.
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LOAD: Load Flash
Representation
Symbol

Reference
Top input 0x, 1x None Start LOAD operation: it should remain ON
until the operation has completed
successfully or an error has occurred.
register 4x INT, UINT, First of max. 512 contiguous 4x registers
(top node) WORD to be loaded from state RAM
1, 2, 3, 4 INT Integer value, which defines the specific
(middle node) buffer where the block of data is to be
loaded
length INT Number of words to be loaded, range:
(bottom node) 1 ... 512
Top output 0x None ON = LOAD is active
Middle output 0x None ON = a LOAD is requested from a buffer
where no data has been saved.
Bottom output 0x None ON = Length not equal to SAVEd length
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LOAD: Load Flash
1, 2, 3, 4 (Middle Node)
The middle node defines the specific buffer where the block of data is to be loaded.
Four 512 word buffers are allowed. Each buffer is defined by placing its
corresponding value in the middle node, that is, the value 1 represents the first
buffer, value 2 represents the second buffer and so on. The legal values are 1, 2, 3,
and 4. When the PLC is started all four buffers are zeroed. Therefore, you may not
load data from the same buffer without first saving it with the instruction SAVE.
When this is attempted the middle output goes ON. In other words, once a buffer is
used, it may not be used again until the data has been removed.
Bottom Output
The output from the bottom node goes ON when a LOAD request is not equal to the
registers that were SAVEd. This kind of transaction is allowed, however, it is your
responsibility to ensure this does not create a problem in your application.
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MAP3: MAP Transaction
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110
Introduction
This chapter describes the instruction MAP3.

Topic Page
Representation 653
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Short Description
Ladder logic applications running in the controller initiate communication with MAP
network nodes through the MAP3 instruction.
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Representation
Symbol

Reference
Top input 0x, 1x None ON = initiates a transaction
Middle input 0x, 1x None ON = new transaction to be initiated in the
same scan
control block 4x INT, UINT, Control Block (first register of a block)
(top node) WORD
data source 4x INT, UINT, Data source (starting register)
(middle node) WORD
length INT, UINT Length of local data area, range: 1 ... 255)
(bottom node)
Top output 0x None Transaction completes successfully
MIddle output 0x None Transaction is in progress
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Top Input
This input initiates a transaction. To start a transaction the input must be held ON
(HIGH) for at least one scan. If the S980 has resources to process the transaction,
the middle output passes power. If resources are not available, no outputs pass
power.
Once a transaction is started, it will run until a reply is received, a communications
error is detected, or a timeout occurs. The values in the control block, data source,
and length must not be altered, or the transaction will not be completed and the
bottom output will pass power. A second transaction cannot be started by the same
block until the first one is complete.
Middle Input
If the top input is also HIGH, the middle input going ON allows a new transaction to
be initiated in the same scan, following the completion of a previous one. A new
transaction begins when the top output passes power from the first transaction.

The top node is the starting 4x register of a block of registers that control the block’s
operation.
The contents of each register is determined by the kind of operation to be performed
by the MAP3 block:
z read or write
z information report
z unsolicited status
z conclude
z abort
Registers of the control block:
Word Meaning
1 Destination Device
2 Qualifier / Function Code
3 Network Mode / Network Type
4 Function Status
5 Register A Reference Type
This word is labeled Register A* and contains the reference type for 4 types of
Read (0x, 1x, 3x, and 4x registers) and 2 types of Write (0X or 4x).
6 Register B Reference Number
This word is labeled Register B* and contains the starting reference number in
the range 1 to 99999.
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Word Meaning
7 Register C Reference Length
This word is labeled Register C* and contains the Quantity of references
requested.
8 Register D Timeout
This word is labeled Register D* and contains the Timeout parameter. This value
sets the maximum length of time used to complete a transaction, including
retries.
Destination Device
Word 1 contains the destination device in bit position 9 through 16. The computer
works with this byte as the LSB and will accept a range of 1 to 255.
Usage of word 1:
Bit Function
1-8 Not used
9 - 16 Destination device
Qualifier / Function Code

Word 2 contains two bytes of information. The qualifier bits are 1 to 8 and the
function code is in bits 9 to 16.
Usage of word 2:
Bit Function
Qualifier
1-8 0 = addressed
>0 = named
Function Code
9 - 16 4 = read
5 = write
Network Mode / Network Type

Word 3 contains two bites of information. The mode is in bits 5 through 8 and the
type is in bits 9 through 16.
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Usage of word 3:
Bit Function
1-4 Not used
Mode
5-8 1 = association
Type
9 - 12 7 = 7 layer MAP network
13 - 16 1 = type 1 service
Function Status
Word 4 is the function status. An error code is returned if an error occurs in a block
initiated function.
The decimal codes are:
Code Meaning
1 Association request rejected
4 Message timeout application response
5 Invalid destination device
6 Message size exceeded
8 Invalid function code
17 Device not available
19 Unsupported network type
22 No channel available
23 MMS message not sent
24 Control block changed
25 Initiate failed
26 System download in progress
28 Channel not ready
99 Undetermined error
103 Access denied
105 Invalid address
110 Object nonexistent
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Function summary
The network controlling device may issue a function code that alters the control
block register assignment as given above for read/write. Those differences for
information, status, conclude and abort are identified in this summary on the bottom
of your screen.
Refer to Modicon S980 Map 3.0 Network Interface User Guide that describes the
register contents for each operation.
Data Source (Middle Node)

The middle node is the starting 4x register of the local data source (for a write
request) or local data destination (for a read).

The bottom node defines the maximum size of the local data area (the quantity of
registers) starting at 4x register of data source, in the range of 1 to 255 decimal. The
quantity of data to be actually transferred in the operation is determined by a
reference length parameter in one of the control registers.
Top Output
The top output passes power for one scan when a transaction completes
successfully.
Middle Output
The middle output passes power when a transaction is in progress. If the top input
is ON and the middle input is OFF, then the middle output will go OFF on the same
scan that the top output goes ON. If both top input and middle input are ON, then the
middle output will remain ON.
Bottom Output
The bottom output passes power for one scan when a transaction cannot be
completed. An error code is returned to the function status word (register 4x+3) in
the function’s control block.
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MATH - Integer Operations
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111
Introduction
This chapter describes the four integer operations executed by the instruction
MATH. The four operations are decimal square root, process square root, logarithm
(base 10), and antilogarithm (base 10).

Topic Page
Representation 661
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Short Description
The MATH instruction performs any one of four integer math operations, which is
called by entering a function code in the range 1 ... 4 in the bottom node.
Table with two columns:
Code MATH Function

1 Decimal square root
2 Process square root
3 Logarithm (base 10)
4 Antilogarithm (base 10)
Each MATH function operates on the contents of the top node registers and places
a result in the middle node registers.
For example, the normal square root uses registers 3/4xxxx and 3/4xxxx+1 as an 8
digit operand and stores the result in 4yyyy and 4yyyy+1. The result storage format
is XXXX.XX00 where there are 2 places of precision following an implied decimal
point.
Math performs the function indicated by the bottom node:
Code Function Operand Range Result Registers Range

Registers
1 Normal 3/4x, 3/4x + 1 8 Digits 4y, 4y + 1 xxxx.xxoo
2 Process 3/4x 4 Digits 4y, 4y + 1 xxxx.xxoo
3 Log (x) 3/4x, 3/4x + 1 8 Digits 4y 1 to 7,999
4 Antilog (x) 3/4x 1 to 7,999 4y, 4y + 1 8 Digits
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Representation
Symbol - Decimal Square Root

Representation of the instruction for the decimal square root operation
Parameter Description - Decimal Square Root

Description of the instruction’s parameters for the decimal square root operation

Reference
Top Input 0x, 1x None ON initiates a standard square root
operation.
source 3x. 4x INT, UINT The first of two contiguous 3xxxx or 4xxxx
(top node) registers is entered in the top node. The
will be derived) is stored here.
value may be in the range 0 through
register.
value may be in the range 0 through 9,999.
The square root calculation is done on only
the value in the displayed register; the
implied register is required but not used.
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Reference
result 4x INT, UINT Enter the first of two contiguous 4xxxx
(middle node) registers in the middle node. The second
register is implied. The result of the
standard square root operation is stored
here.
register stores the four-digit value to the left
of the first decimal point and the implied
right of the first decimal point. Numbers
after the second decimal point are
truncated; no round-off calculations are
performed.
Bottom output 0x None ON = top-node value out of range
Symbol - Process Square Root

Representation of the instruction for the process square root operation
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Parameter Description - Process Square Root

The process square root function tailors the standard square root function for closed
loop analog control applications. It takes the result of the standard square root result,
multiplies it by 63.9922 (the square root of 4095), and stores that linearized result in
the middle-node registers.

Reference
Top Input 0x, 1x None ON initiates process square root operation
will be derived) is stored in these two
registers.
In order to generate values that have
meaning, the source value must not
exceed 4095. In a 4xxxx register group the
source value will therefore be stored in the
implied register, and in a 3xxxx register
group the source value will be stored in the
displayed register.
result 4x INT, UINT The first of two contiguous 4xxxx registers
(middle node) is entered in the middle node. The second
register is implied. The linearized result of
the process square root operation is stored
here.
register stores the four-digit value to the left
of the first decimal point and the implied
right of the first decimal point. Numbers
after the second decimal point are
truncated; no round-off calculations are
performed.
Bottom output 0x None ON = Source value out of range
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Symbol - Logarithm (base 10)

Representation of the instruction for the Logarith (base 10) operation
Parameter Description - Logarithm (base 10 logarithm)

Description of the instruction’s parameters for the logarithm (base 10) operation

Reference
Top Input 0x, 1x None ON enables log(x) operation
second register is implied. The source value
upon which the log calculation will be
performed is stored in these registers.
value may be in the range 0 through
99,999,99. The low-order half of the value is
stored in the implied register, and the high-
order half is stored in the displayed register.
log calculation is done on only the value in
the displayed register; the implied register is
required but not used.
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Reference
result 4x INT, UINT The middle node contains a single 4xxxx
(middle node) holding register where the result of the base
10 log calculation is posted. The result is
expressed in the fixed decimal format 1.234
, and is truncated after the third decimal
position.
The largest result that can be calculated is
7.999, which would be posted in the middle
register as 7999.
Top output 0x None ON = Operation Successful
Bottom output 0x None ON = an error ar a value out of range
Symbol - Antilogarithm (base 10)

Representation of the instruction for the antilogarithm (base 10) operation
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Parameter Description - Antilogarithm (base 10)

Description of the instruction’s parameters for the antilogarithm (base 10) operation

Reference
Top Input 0x, 1x None ON enables antilog(x) operation
source 3x. 4x INT, UINT The top node is a single 4xxxx holding
(top node) register or 3xxxx input register. The source
value (the value on which the antilog
calculation will be performed) is stored here
in the fixed decimal format 1.234 . It must
be in the range 0 through 7999,
representing a source value up to a
maximum of 7.999.
result 4x INT, UINT The first of two contiguous 4xxxx registers
(middle node) is entered in the middle node. The second
register is implied. The result of the antilog
calculation is posted here in the fixed
decimal format 12345678.
The largest antilog value that can be
calculated is 99770006 (9977 posted in the
displayed register and 0006 posted in the
implied register).
Bottom output 0x None ON = An error or a value out of range
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MBIT: Modify Bit
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MBIT: Modify Bit
112
Introduction
This chapter describes the instruction MBIT.

Topic Page
Representation 669
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MBIT: Modify Bit
Short Description
WARNING
DISABLED COILS
Before using the MBIT instruction, check for disabled coils. MBIT will override any
disabled coils within a destination group without enabling them. This can cause
can change as a result of the MBIT instruction.
equipment damage.
The MBIT instruction modifies bit locations within a data matrix, i.e. it sets the bit(s)
to 1 or clears the bit(s) to 0. One bit location may be modified per scan.
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MBIT: Modify Bit
Representation
Symbol

Reference
Top input 0x, 1x None ON = implements bit modification
Middle input 0x, 1x None OFF = clear bit locations to 0
ON = set bit locations to 1
Bottom input 0x, 1x None Increment bit location by one after
modification
bit location 3x, 4x INT, UINT, Specific bit location to be set or clear in the
(top node) WORD data matrix; entered explicitly as an
integer value or stored in a register (range
1 ... 9 600)
data matrix 0x, 4x INT, UINT, First word or register in the data matrix
(middle node) WORD
length INT, UINT Matrix length; range: 1 ... 600
(bottom node)
Middle output 0x None Echoes state of the middle input
Bottom output 0x None ON = error: bit location > matrix length
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MBIT: Modify Bit
Bit Location (Top Node)

NOTE: If the bit location is entered as an integer or in a 3x register, the instruction
will ignore the state of the bottom input.

The integer value entered in the bottom node specifies a matrix length, i.e, the
number of 16-bit words or registers in the data matrix. The length can range from
1 ... 600 in a 24-bit CPU, e.g, a matrix length of 200 indicates 3200 bit locations.
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MBUS: MBUS Transaction
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113
Introduction
This chapter describes the instruction MBUS.

Topic Page
Representation 673
The MBUS Get Statistics Function 676
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Short Description
The S975 Modbus II Interface option modules use two loadable function blocks:
MBUS and PEER. MBUS is used to initiate a single transaction with another device
on the Modbus II network. In an MBUS transaction, you are able to read or write
discrete or register data.
PLCs on a Modbus II network can handle up to 16 transactions simultaneously.
Transactions include incoming (unsolicited) messages as well as outgoing
messages. Thus, the number of message initiations a PLC can manage at any time
is 16 - # of incoming messages.
A transaction cannot be initiated unless the S975 has enough resources for the
entire transaction to be performed. Once a transaction has been initiated, it runs until
a reply is received, an error is detected, or a timeout occurs. A second transaction
cannot be started in the same scan that the previous transaction completes unless
the middle input is ON. A second transaction cannot be initiated by the same MBUS
instruction until the first transaction has completed.
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Representation
Symbol

Reference Type
Top input 0x, 1x None Enable MBUS transaction
Middle input 0x, 1x None Repeat transaction in same scan
Bottom input 0x, 1x None Clears system statistics
control block 4x INT, First of seven contiguous registers in the MBUS
(top node) UINT, control block
WORD (For more information, see Control Block (Top
Node), page 674.)
data block 4x INT, First 4x register in a data block to be transmitted or
(middle node) UINT, received in the MBUS transaction.
WORD
length INT, Number of words reserved for the data block is
(bottom node) UINT entered as a constant value
(For more information, see Length (Bottom Node),
page 675.)
Top output 0x None Transaction complete
Middle output 0x None Transaction in progress or new transaction starting
Bottom output 0x None Error detected in transaction
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The 4x register entered in the top node is the first of seven contiguous registers in
the MBUS control block:
Register Content
Displayed Address of destination device (range: 0 ... 246)
First implied not used
Second implied Function code
Third implied Reference type
Fourth implied Reference number, e.g., if you placed a 4 in the third implied register
and you place a 23 in this register, the reference will be holding
register 400023
Fifth implied Number of words of discrete or register references to be read or
written
Sixth implied Time allowed for a transaction to be completed before an error is
declared; expressed as a multiple of 10 ms, e.g., 100 indicates 1 000
ms; the default timeout is 250 ms.
Function Code
This register contains the function code for requested action:
Value Meaning
01 Read discretes
02 Read registers
03 Write discrete outputs
04 Write register outputs
255 Get system statistics
Reference Type
This register contains one of 4 possible discrete or register reference types:
Value Reference type

0 Discrete output (0x)
1 Discrete input (1x)
2 Input register (3x)
3 Holding register (4x)
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Number of Words to Read or Write

Number of words of discrete or register references to be read or written; the length
limits are:
Read register 251 registers

Write register 249 registers
Read coils 7.848 discretes
Write coils 7.800 discretes

The number of words reserved for the data block is entered as a constant value in
the bottom node. This number does not imply a data transaction length, but it can
restrict the maximum allowable number of register or discrete references to be read
or written in the transaction.
The maximum number of words that may be used in the specified transaction is:
Max. Number of Transaction

Words
251 Reading registers (one register/word)
249 Writing registers (one register/word)
490 Reading discretes using 24-bit CPUs (up to 16 discretes/word)
487 Writing discretes using 24-bit CPUs (up to 16 discretes/word
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The MBUS Get Statistics Function
General
Issuing function code 255 in the second implied register of the MBUS control block
obtains a copy of the Modbus II local statistics, a series of 46 contiguous register
locations where data describing error and system conditions is stored. To use MBUS
for a get statistics operation, set the length in the bottom node to 46, a length < 46
returns an error (the bottom output will go ON), and a length > 46 reserves extra
registers that cannot be used.
Example
Parameterizing of the instruction
Register 400101 is the first register in the MBUS control block, making register
400103 the control register that defines the MBUS function code. By entering a
value of 255 in register 400103, you implement a get statistics function. Registers
401000 ... 401045 are then filled with the system statistics.
System Statistics Overview

The following system statistics are available.
z Token bus controller (TBC)
z Software-maintained receive statistics
z TBC-maintained error counters
z Software-maintained transmit errors
z Software-maintained receive errors
z User logic transaction errors
z Manufacturing message format standard
z (MMFS) errors
z Background statistics
z Software revision
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Token Bus Controller (TBC)

Registers 401000 ... 401003 are then filled with the following:
Register Content
401000 Number of tokens passed by this station
401001 Number of tokens sent by this station
401002 Number of time the TBC has failed to pass token and has not found a
successor
401003 Number of times the station has had to look for a new successor
Software-maintained Receive Statistics

Register Content
401004 TBC-detected error frames
401005 Invalid request with response frames
401006 Applications message too long
401007 Media access control (MAC) address out of range
401008 Duplicate application frames
401009 Unsupported logical link control (LLC) message types
401010 Unsupported LLC address
TBC-maintained Error Counters

Register Content
401011 Receive noise bursts (no start delimiter)
401012 Frame check sequence errors
401013 E-bit error in end delimiter
401014 Fragmented frames received (start delimiter not followed by end delimiter)
401015 Receive frames too long
401016 Discarded frames because there is no receive buffer
401017 Receive overruns
401018 Token pass failures
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Software-maintained Transmit Errors

Register Content
401019 Retries on request with response frames
401020 All retries performed and no response received from unit
Software-maintained Receive Errors

Registers 401021... 401022 are then filled with the following:
Register Content
401021 Bad transmit request
401022 Negative transmit confirmation
User Logic Transaction Errors

Register Content
401023 Message sent but no application response
401024 Invalid MBUS/PEER logic
Manufacturing Message Format Standard

Register Content
401025 Command not executable
401026 Data not available
(MMFS) Errors
Register Content
401027 Device not available
401028 Function not implemented
401029 Request not recognized
401030 Syntax error
401031 Unspecified error
401032 Data request out of bounds
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Register Content
401033 Request contains invalid controller address
401034 Request contains invalid data type
401035 None of the above
Background Statistics
Register Content
401036 Invalid MBUS/PEER request
401037 Number of unsupported MMFS message types received
401038 Unexpected response or response received after timeout
401039 Duplicate application responses received
401040 Response from unspecified device
401041 Number of responses buffered to be processed (in the least significant byte);
number of MBUS/PEER requests to be processed (in the most significant
byte)
401042 Number of received requests to be processed (in the least significant byte);
number of transactions in process (in the most significant byte)
401043 S975 scan time in 10 ms increments
Software Revision
Register Content
401044 Version level of fixed software (PROMs): major version number in most
significant byte; minor version number in least significant byte
401045 Version of loadable software (EEPROMs): major version number in most
significant byte; minor version number in least significant byte
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MMFB
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MMFB – Modicon Motion

Framework Bits Block
114
Introduction
This chapter describes the MMFB block.

Topic Page
Representation 683
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MMFB
Short Description
The MMFB function block sets control bits for an axis in the MMFSTART table area.
See Representation, page 683 for a description of the control bit functions. Most of
these functions can be accomplished with subroutines, but this is more efficient
Related Information
folder on the ProWORX 32 installation CD for detailed information on using motion
loadables.
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MMFB
Representation
Symbol
The following diagram shows the MMFB function.

Reference Type
Top input 0x None ON moves control data. Data will be moved
constantly when this input is on.
controller.
Middle node 4x INT, This register points to a block of registers that define
UINT all the arguments for the jog. The last two registers
specifies the table length. In this case, the number of
registers in the table must be 3.
Top output 0x None Echoes state of top input, except if the axis (top node
content) is incorrect or table length is not two.
output
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MMFB
Registers

4xxxxx INT Axis id.
4xxxx1 INT Low order control: bits 0-15
4xxxx2 INT High order control: bits 16-31
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MMFE
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MMFE – Modicon Motion

Framework Extended Parameters
Subroutine 115
Introduction
This chapter describes the MMFE block.

Topic Page
Representation 687
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MMFE
Short Description
The MMFE function block is designed specifically for executing moveImmed and
moveQueue subroutines with Coordinated Sets. Par1 specifies the MoveType
(Absolute or Incremental) and EPar1 through EParN take the Position for all the N
axes in the Coordinated Set. Then EparN+1 through Epar2N take the Velocity of all
N axes in the Coordinated Set, up to eight axes. For these move subroutines, Par2
is not used and there are no return values, but they are included in the function block
for future subroutines.
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MMFE
Representation
Symbol
The following diagram shows an MMFE block.

Reference Type
Top input 0x None ON initiates the subroutine. When this input goes off, the
function block is reset and can be initiated again.
controller.
UINT the arguments and routines for a generic subroutine call.
Bottom node 4x INT The integer value entered in the bottom node specifies
Top output 0x None Turned on when the subroutine call is complete without
error.
Middle 0x None Turned on when the subroutine call is complete and an
output error is code is generated in register 4xxx38.
output
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MMFE
Registers

4xxxxx Short Number of the subroutine to be executed
4xxxx1 Short Axis id for the subroutine
4xxxx2 Unsigned First parameter for the subroutine
4xxxx4 Unsigned Second parameter for the subroutine
4xxxx6 Float Third parameter for the subroutine
4xxxx8 Float Fourth parameter for the subroutine
4xxx10 Float Third parameter for the subroutine
4xxx12 Float Fourth parameter for the subroutine
4xxx38 Short Error code generated from subroutine
4xxx39 Unsigned First return value from subroutine
4xxx41 Float Second return value from subroutine
4xxx43 Float Third return value from subroutine
4xxx45 Function State Current operating state number
4xxx47 State Count Current state entry count
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MMFI
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MMFI – Modicon Motion

Framework Initialize Block
116
Introduction
This chapter describes the MMFI block.

Topic Page
Representation 691
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MMFI
Short Description
This function block defines the MMFSTART communication register table. This table
starts at 41000 length 200. It passes power from input 1 but checks the revision in
the table.
Related Information
loadables.
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MMFI
Representation
Symbol
The following diagram shows an MMFI block.

Reference
Top input 0x None ON initiates the function to check the
MMFSTART revision.
Middle node 4x INT, UINT Points to a block of 200 registers that
makeup the MMFSTART communication
area. This address is normally 401001, but
can be changed with MMFSTART
configuration in the SERCOS
CONTROLLER
Bottom node 4x INT The integer value entered in the bottom
node specifies the table length. In this case,
the number of registers in the table must be
200.
Top output 0x None Echoes the state of top input.
at 200.
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MMFI
Registers
The following table shows the instruction’s registers.
Register Information Data Description

Type
base+001:002 RingControl UDINT Indicates enabling, stopping, holding, etc.
base+003 WatchDogCont INT Used by controller and PLC to make sure the
other is allowed.
base+004 Debug INT Used to output debug messages.
base+005 SubNumber INT Indicates the subroutine number.
base+006 AxisID INT Apply subroutine to this motion axis.
base+007:010 Parameter 1...2 UDINT Indicates parameters for this subroutine (two
integers).
base+011:042 Parameter 3...18 REAL Indicates parameters for this subroutine (16
floats)
base+043:050 (Reserved) (eight words)
base+051:066 SA1..8Control UDINT Indicates control bits for each SERCOS Axis
base+067:074 IA1..4Control UDINT Indicates control bits for each Imaginary Axis
base+075:082 CS1..4Control UDINT Indicates control bits for each Coordinated
Set.
base+083:090 FS1..4Control UDINT Indicates control bits for each Follower Set.
base+091 USubNumber INT Indicates user subroutine number
base+092 UAxisID INT Apply user subroutine to this motion axis
base+93:096 UParameter1...2 UDINT Indicates user parameters for this subroutine
(two integers)
base+97:100 UParameter3...4 REAL User parameters for this subroutine (two
floats)
base+101:102 RingStatus UDINT Indicates fault, enabled, holding, profile end,
in position
base+103 WatchDogState INT Echoes what is written in WatchDogCont
base+104 NumberOfAxes INT Indicates how many SERCOS axes have
been configured
base+105 FaultAxis INT Indicates which axis faulted
base+106 FaultCode INT Indicates what fault occurred
base+107 WarnAxis INT Indicates which axis is having a problem
base+108 WarnCode INT Indicates what warning occurred
base+109 SubNumEcho INT Echoes SubNumber when subroutine code
completes
base+110 AxisIDEcho INT Echoes AxisID
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MMFI
Register Information Data Description

Type
base+111 Error INT Indicates subroutine motion error number
base+112:113 Return1 UDINT Indicates subroutine return value (one integer)
base+114:117 Return2...3 REAL Indicates subroutine return value (two floats)
base+118 Revision INT Indicates interface revision number
base+119:134 SA1..8Position REAL Indicates position for eight SERCOS axes
base+135:142 IA1..4Position REAL Indicates position for four imaginary axes
base+143:150 RA1..4Position REAL indicates position for four remote axes
base+151:166 SA1..8Status UDINT Indicates status bits for each SERCOS Axis
base+167:174 IA1..45Status UDINT Indicates status bits for each Imaginary Axis
base+175:182 CS1..45Status UDINT Indicates status bits for each Coordinated Set
base+183:190 FS1..45Status UDINT Indicates status bits for each Follower Set
base+191 USubNumEcho INT Echoes user SubNumber when subroutine
code complete
base+192 UAxisIDEcho INT Echoes user AxisID
base+193 UError INT Indicates user subroutine motion error
number
base+194 UReturn1 UDINT Indicates user subroutine return value (one
integer)
base+196:199 UReturn2..3 REAL Indicates user subroutine value (two floats)
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MMFI
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MMFS
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MMFS – Modicon Motion

Framework Subroutine Block
117
Introduction
This chapter describes the MMFS block.

Topic Page
Representation 697
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MMFS
Short Description
This function block issues an MMFSTART subroutine using standard parameters
and returns. It can be used to execute any MMFSTART standard subroutine except
moves to CoordinatedSets. These subroutines provide a common interface to
SERCOS drives.
Related Information
loadables.
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MMFS
Representation
Symbol
The following diagram shows an MMFS block.

Reference
Top input 0x None ON initiates the subroutine. When this input
goes off, the function block is reset and can be
initiated again.
define all the arguments and routines for a
generic subroutine call. The last two registers
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MMFS

Reference
Top output 0x None Turned on when the subroutine call is
Note: Top and middle outputs are reset by the
top input being turned off.
Middle output 0x None Turned on when the subroutine call is
complete and an error is code is generated in
register 4xxx10.
at 19.
Registers

4xxxxx Short Number of the subroutine to be executed
4xxxx1 Short Axis id for the subroutine
4xxxx2 Unsigned First parameter for the subroutine
4xxxx4 Unsigned Second parameter for the subroutine
4xxxx6 Float Third parameter for the subroutine
4xxxx8 Float Fourth parameter for the subroutine
4xxx10 Short Error code generated from the subroutine
4xxx11 Unsigned First return value from the subroutine
4xxx13 Float Second return value from the subroutine
4xxx15 Float Third return value from the subroutine
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MOVE
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MOVE – Absolute Move
118
Introduction
This chapter describes the MOVE block.

Topic Page
Representation 701
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MOVE
Short Description
This function block issues an MMFStart Immediate Absolute move on the axis
specified. The velocity and position are specified in the associated table.
Related Information
loadables.
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MOVE
Representation
Symbol
The following diagram shows a MOVE block.

Reference
Top input 0x None ON initiates the incremental move. When this
input goes off, the function block is reset and
can be initiated again.
define all the arguments for the configuration.
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MOVE

Reference
Top output 0x None Turned on when the move start is complete
without error.
Note: Top and middle outputs are reset by the
top input being turned off.
Middle output 0x None Turned on when the move is not started and
an error is code is generated in register
4xxxx5.
at 8.
Registers

4xxxxx Short Axis ID for the absolute move
4xxxx2 Float Target position of the absolute move
4xxxx3 Float Velocity of the absolute move
4xxxx5 Short Error generated when attempting to start move
4xxxx7 Short Current state entry count
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MRTM: Multi-Register Transfer Module
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MRTM:
Multi-Register Transfer Module
119
Introduction
This chapter describes the instruction MRTM.

Topic Page
Representation 705
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Short Description
The MRTM instruction is used to transfer blocks of holding registers from the
program table to the command block, a group of output registers. To verify each
block transfer, an echo of the data contained in the first holding register is returned
to an input register.
704 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = enables the operation
Middle input 0x, 1x None ON = one instruction block is transferred,
table pointer of control table is increased by
the value of "length"
Bottom input 0x, 1x None ON =reset
program table 0x, 1x, 3x, 4x INT, UINT, First register of the program table. The digit 4
(top node) WORD is assumed as the most significant digit.
control table 3x, 4x INT, UINT, First register of the control table. The digit 4 is
(middle node) WORD assumed as the most significant digit.
length INT, UINT Number of registers moved from the program
(bottom node) table during each transfer, range: 1 to 127
Middle output 0x None Instruction block is transferred to the
command block (stays on only for the
remainder of the current scan).
Bottom output 0x None ON = pointer value ≥ table end
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Mode of Functioning
The MRTM transfers contiguous blocks of up to 127 registers from a table of register
blocks to a block size holding register area. The MRTM function block controls the
operation of the module in the following manner:
If power is Then ...

applied to the...
Top input The function block is enabled for data transfers.
Note: On initial startup, power must be applied to the bottom input.
Middle input The function block attempts to transfer one instruction block. Before a
transfer can occur, the echo register is evaluated. The most significant
bit (MSB) of the echo register is not evaluated just bits 0 through 14.
Echo mismatch is a condition that prohibits a transfer. If a transfer is
permitted, one instruction block is transferred form the table starting at
the table pointer.
The table pointer in the control table is then advanced. If the pointer’s
new value is equal to or greater than the table end, the bottom output is
turned on. A table pointer value less than the table end turns off the
output.
Bottom input The function block resets. The table pointer in the control table is
reloaded with the start of commands value from the header of the
program table
Parameter Description Increment Step (MIddle Input)

When power is applied, this input attempts to transfer one instruction block. Before
a transfer can occur, the echo register is evaluated. The most significant bit (MSB)
of the echo register is not evaluated, just bits 0 through 14. Echo mismatch is a
condition that prohibits a transfer. If a transfer is permitted, one instruction block is
transferred from the program table starting at the table pointer. The table pointer in
the control table is then incremented by the value "Length" (displayed in the bottom
node).
NOTE: The MRTM function block is designed to accept fault indications from I/O
modules, which echo valid commands to the controller, but set a bit to indicate the
occurrence of a fault. This method of fault indication is common for motion products
and for most other I/O modules. If using a module that reports a fault condition in any
other way, especially if the echo involved is not an echo of a valid command, special
care must be taken when writing the error handler for the ladder logic to ensure the
fault is detected. Failure to do so may result in a lockup or some other undesirable
performance of the MRTM.
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Parameter Description Reset Pointer (Bottom Input)

When power is applied to this input, the function block is reset. The table pointer in
the control table is reloaded with the start of commands value from the header of the
program table.
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MSPX (Seriplex)
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MSPX (Seriplex)
120
Introduction
This chapter describes the instruction MSPX.

Topic Page
Representation 711
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MSPX (Seriplex)
Short Description
The MSPX reads and writes bits within the base unit’s registers.
The top node of the MSPX instruction represents the internal sub-function number.
This node can be assigned a decimal constant value of 32 or a 4xxxx register
containing the value of 32.
The middle node represents the starting 4xxxx register location for the SERIPLEX-
MOMENTUM interface base unit.
The bottom node is interpreted as a numeric offset from 3000 indicating the first
3xxxx input register assigned to the interface base unit. The bottom node value
specifies the location of the base unit's status register.
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MSPX (Seriplex)
Representation
Symbol

Reference Type
Top input 0x, 1x None The Block Enable/Disable input enables and
disables the operation of the MSPX block. When
the associated logic is TRUE the top input is
turned ON and the block's instructions are
executed. The values of the base unit's input and
output registers are not affected by the enabling
or disabling of the block.
Middle input 0x, 1x None The Run/Stop Bus input regulates the operation
of the Seriplex bus through the run/halt bit within
the base unit's control register. The run/halt bit is
set to 1 when the associated logic is TRUE, and
cleared to 0 when the associated logic is FALSE.
The parameters of this input are not to be altered
while it is enabled or the run/halt bit will result in
a configuration fault.
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MSPX (Seriplex)

Reference Type
32 INT, Represents the internal sub-function number.
(top node) UINT This node can be assigned a decimal constant
value of 32 or a 4xxxx register containing the
value of 32.
register 4x INT, Represents the starting 4xxxx register location
(middle node) UINT for the SERIPLEX-MOMENTUM interface base
unit.
offset 3x INT, Interpreted as a numeric offset from 3000
(bottom node) UINT indicating the first 3xxxx input register assigned
to the interface base unit. The bottom node value
specifies the location of the base unit's status
register.
Top output 0x None The Bus Running Indicator output reports
whether or not the Seriplex bus is running. If the
bus running bit is ON, the output is TRUE and the
Seriplex bus is operating normally, but, if the bus
running bit is OFF, the output will be FALSE.
Middle output 0x None The Fault output reports if the MSPX instruction
has experienced a fault condition other than a
configuration fault. This will occur if any of the
following status registers are ON: Bus fault (bit
3); MOMENTUM fault (bit 4); CDR error (bit 5).
The detailed description of the detected fault can
be determined by reading the base unit's status
register.
Bottom output 0x None The Config Error output indicates that a
configuration error has occurred, and its state is
explained in the base unit's status register. When
the config fault bit is ON the output becomes
TRUE indicating that an improper attempt was
made while writing to the base units control
register.
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MSTR: Master
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MSTR: Master
121
Introduction
This chapter describes the instruction MSTR.

Topic Page
Representation 715
Write MSTR Operation 722
READ MSTR Operation 724
Get Local Statistics MSTR Operation 726
Clear Local Statistics MSTR Operation 728
Write Global Data MSTR Operation 730
Read Global Data MSTR Operation 731
Get Remote Statistics MSTR Operation 732
Clear Remote Statistics MSTR Operation 734
Peer Cop Health MSTR Operation 736
Reset Option Module MSTR Operation 738
Read CTE (Config Extension Table) MSTR Operation 740
Write CTE (Config Extension Table) MSTR Operation 742
Modbus Plus Network Statistics 744
TCP/IP Ethernet Statistics 749
Run Time Errors 750
Modbus Plus and SY/MAX Ethernet Error Codes 751
SY/MAX-specific Error Codes 753
TCP/IP Ethernet Error Codes 755
CTE Error Codes for SY/MAX and TCP/IP Ethernet 758
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MSTR: Master
Short Description
PLCs that support networking communications capabilities over Modbus Plus and
Ethernet have a special MSTR (master) instruction with which nodes on the network
can initiate message transactions.
The MSTR instruction allows you to initiate one of 12 possible network
communications operations over the network.
z Read MSTR Operation
z Write MSTR Operation
z Get Local Statistics MSTR Operation
z Clear Local Statistics MSTR Operation
z Write Global Data MSTR Operation
z Read Global Data MSTR Operation
z Get Remote Statistics MSTR Operation
z Clear Remote Statistics MSTR Operation
z Peer Cop Health MSTR Operation
z Reset Option Module MSTR Operation
z Read CTE (Config Extension) MSTR Operation
z Write CTE (Config Extension) MSTR Operation
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MSTR: Master
Representation
Symbol
For more information, see Parameter Description, page 718.

Reference
Top input 0x, 1x None ON = enables selected MSTR operation
Middle input 0x, 1x None ON = terminates active MSTR operation
Bottom input 0x, 1x None Note: Only available for M1E:
ON = TCP port will be held open
control block 4x INT, UINT Control block (first of several (network-
(top node) dependant) contiguous holding registers)
data area 4x INT, UINT Data area (source or destination
(middle node) depending on selected operation)
length INT Length of data area (maximum number of
(bottom node) registers), range: 1 ... 100
Top output 0x None ON while the instruction is active (echoes
state of the top input)
MIddle output 0x None ON if the MSTR operation is terminated
prior to completion (echoes state of the
middle input)
Bottom output 0x None ON = operation successful
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MSTR: Master
Bottom Input
With 984LL exec. versions 1.20 and later, power is asserted to the bottom input of
the MSTR block. Along with the top enable input, this assertion causes the TCP
connection to remain open. Once the connection has been established, only
Modbus command and response packets are transmitted onto the Ethernet. The
repetition rate, however, cannot be specified. It transmits as fast as the scan and the
target served can accomodate. No dynamic changes to the control block are
accepted until the enable (top) input is pulsed.
984LL function block example for open connection operation
IEC MSTR Function Block

A new feature has been added to IEC exec. versions 1.21 and later by setting a bit
in the Slot_ID of the EFB TCP_IP_ADR. Asserting this go-again bit, along with the
TCP/IP operation, bit causes the TCP connection to remain open. Once the
connection has been established, only Modbus command and response packets are
transmitted onto the Ethernet. The only difference is that the repetition rate cannot
be specified. It goes as fast as the scan and the target server can acomodate.
The Slot_ID of the EFB TCP_IP_ADR has extended usage:
z Bit 0 = 0 MBP operation
z Bit 0 = 1 TCP/IP operation
z Bit 1 = 0 The TCP port will be closed after the transaction has completed (as
before).
z Bit 1 = 1 The TCP port will be held open.
z Bits 2 through 7 are reserved and must remain at 0.
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MSTR: Master
NOTE: Map_idx = 0 for Momentum M1E processors

IEC EFB example for open connection operation: Register 400050 = 3 hex
This feature is only usable for the following EFBs:

z CREAD_REG
z CREADREG
z CWRITE_REG
z CWRITERREG
z MBP_MSTR (needs to be always kept active: ENABLE=1)
Do not use this feature with the following EFBs
z READREG
z WRITEREG
z READ_REG
z WRITE_REG
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MSTR: Master
Mode of Functioning
The MSTR instruction allows you to initiate one of 12 possible network
communications operations over the network. Each operation is designated by a
code.
Up to four MSTR instructions can be simultaneously active in a ladder logic program.
More than four MSTRs may be programmed to be enabled by the logic flow; as one
active MSTR block releases the resources it has been using and becomes
deactivated, the next MSTR operation encountered in logic can be activated.
Master Operations
Certain MSTR operations are supported on some networks and not on others.
Code Type of Operation Modbus TCP/IP SY/MAX

Plus Ethernet Ethernet
1 Write Data x x x
2 Read Data x x x
3 Get Local Statistics x x -
4 Clear Local Statistics x x -
5 Write Global Database x - -
6 Read Global Database x - -
7 Get Remote Statistics x x -
8 Clear Remote Statistics x x -
9 Peer Cop Health x - -
10 Reset Option Module - x x
11 Read CTE (config extension) - x x
12 Write CTE (config extension) - x x
Legend
x supported
- not supported
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MSTR: Master

The 4x register entered in the top node is the first of several (network-dependant)
holding registers that comprise the network control block.
The control block structure differs according to the network in use.
z Modbus Plus
z TCP/IP Ethernet
z SY/MAX Ethernet
NOTE: You need to understand the routing procedures used by the network you are
using when you program an MSTR instruction. A full discussion of Modbus Plus
routing path structures is given in Modbus Plus Planning and Installtion Guide. If
TCP/IP or SY/MAX Ethernet routing is being implemented, it must be accomplished
via standard third-party Ethernet IP router products.
Control Block for Modbus Plus

The first of twelve contiguous 4x registers is entered in the top node. The remaining
eleven registers are implied:
Register Content
Displayed Identifies one of the nine MSTR operations legal for Modbus Plus
(1 ... 9)
First implied Displays error status
Second implied Displays length (number of registers transferred)
Third implied Displays MSTR operation-dependent information
Fourth implied The Routing 1 register, used to designate the address of the
destination node for a network transaction. The register display is
implemented physically for the Quantum PLCs
Fifth implied The Routing 2 register
Sixth implied The Routing 3 register
Seventh implied The Routing 4 register
Eighth implied The Routing 5 register
Ninth implied not applicable
Tenth implied not applicable
Eleventh implied not applicable
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MSTR: Master
Routing 1 Register for Quantum Automation Series PLCs (Fourth Implied Register)
To target a Modbus Plus Network Option module (NOM) in a Quantum PLC
backplane as the destination of an MSTR instruction, the value in the high byte
represents the physical slot location of the NOM, e.g. if the NOM resides in slot 7 in
the backplane, the high byte of routing register 1 would look like this:
Bit Function
1... 8
High byte: indicating physical location (range 1 ... 16)

9 ... 16
Destination address: binary value between 1 ... 64
NOTE: If you have created a logic program using an MSTR instruction for a 984 PLC
and want to port it to a Quantum Automation Series PLC without having to edit the
routing 1 register value, make sure that NOM #1 is installed in slot 1 of the Quantum
backplane (and if a NOM #2 is used, that it is installed in slot 2 of the backplane). If
you try to run the ported application with the NOMs in other slots without modifying
the register, an F001 status error will appear, indicating the wrong destination node.
Control Block for TCP/IP Ethernet

The first of nine contiguous 4x registers is entered in the top node. The remaining
eight registers are implied.
Register Content
Displayed Identifies one of the nine MSTR operations legal for TCP/IP
(1 ... 4, 7, 8, 10 ... 12)
Second implied Displays length (number of registers transferred)
Third implied Displays MSTR operation-dependent information
Fourth implied Low byte: slot address of the NOE module
High byte: MBP-to-Ethernet Transporter (MET) Map index
Fifth implied Byte 4 of the 32-bit destination IP Address
Sixth implied Byte 3 of the 32-bit destination IP Address
Seventh implied Byte 2 of the 32-bit destination IP Address
Eighth implied Byte 1 of the 32-bit destination IP Address
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MSTR: Master
Control Block for SY/MAX Ethernet

The first of seven contiguous 4x registers is entered in the top node. The remaining
six registers are implied.
Register Content
Displayed Identifies one of the nine MSTR operations legal for SY/MAX
(1, 2, 10 ... 12)
Second implied Displays Read/Write length (number of registers transferred)
Third implied Displays Read/Write base address
Fourth implied Low byte: slot address of the NOE module (e.g., slot 10 = 0A00, slot
6 = 0600)
High byte: MBP-to-Ethernet Transporter (MET) Map index
Fifth implied Destination drop number (or set to FF hex)
Sixth implied Terminator (set to FF hex)
Data Area (Middle Node)

The 4x register entered in the middle node is the first in a group of contiguous
holding registers that comprise the data area. For operations that provide the
communication processor with data, such as a Write operation, the data area is the
source of the data. For operations that acquire data from the communication
processor, such as a Read operation, the data area is the destination for the data.
In the case of the Ethernet Read and Write CTE operations, the middle node stores
the contents of the Ethernet configuration extension table in a series of registers.
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MSTR: Master
Write MSTR Operation
Short Description
An MSTR Write operation transfers data from a master source device to a specified
slave destination device on the network. Read and Write use one data master
transaction path and may be completed over multiple scans.
If you attempt to program the MSTR to Write its own station address, an error will be
generated in the first implied register of the MSTR control block. It is possible to
attempt a Write operation to a nonexistent register in the slave device. The slave will
detect this condition and report it, this may take several scans.
Network Implementation
The MSTR Write operation can be implemented on the Modbus Plus, TCP/IP
Ethernet, and SY/MAX Ethernet networks.
Control Block Utilization

In a Write operation, the registers in the MSTR control block (the top node) contain
the information that differs depending on the type of network you are using.
z Modbus Plus
z TCP/IP Ethernet
z SY/MAX Ethernet

Displayed Operation type 1 = Write
First implied Error status Displays a hex value indicating an MSTR error,
when relevant
Second implied Length Number of registers to be sent to slave
Third implied Slave device data Specifies starting 4x register in the slave to be
area written to (1 = 40001, 49 = 40049)
Fourth ... Eighth Routing 1 ... 5 Designates the first ... fifth routing path addresses,
implied respectively; the last nonzero byte in the routing
path is the destination device
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MSTR: Master

First implied Error status Displays a hex value indicating an MSTR error:
Exception code + 3000: Exception response,
where response size is correct
4001: Exception response, where response size is
incorrect
4001: Read/Write
area written to (1 = 40001, 49 = 40049)
Fourth implied Low byte Slot address of the network adapter module
Fifth ... eighth Destination Each register contains one byte of the 32-bit IP
implied address

when relevant
area written to (1 = 40001, 49 = 40049)
Fourth implied Slot ID Low byte: slot address of the network adapter
module
Fourth implied Slot ID High byte: Destination drop number
Fifth ... eighth Terminator FF hex
implied
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MSTR: Master
READ MSTR Operation
Short Description
An MSTR Read operation transfers data from a specified slave source device to a
master destination device on the network. Read and Write use one data master
transaction path and may be completed over multiple scans.
If you attempt to program the MSTR to Read its own station address, an error will
be generated in the first implied register of the MSTR control block. It is possible to
attempt a Read operation to a nonexistent register in the slave device. The slave will
detect this condition and report it, this may take several scans.
The MSTR Read operation can be implemented on the Modbus Plus, TCP/IP
Ethernet, and SY/MAX Ethernet networks.

In a Read operation, the registers in the MSTR control block (the top node) contain
the information that differs depending on the type of network you are using.
z Modbus Plus
z TCP/IP Ethernet
z SY/MAX Ethernet

Displayed Operation type 2 = Read
when relevant
Second implied Length Number of registers to be read from slave
Third implied Slave device data Specifies starting 4x register in the slave to be read
area from(1 = 40001, 49 = 40049)
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MSTR: Master
Control Block for TCP/IP EthernetEthernet

First implied Error status Displays a hex value indicating an MSTR error:
Exception code + 3000: Exception response,
where response size is correct
4001: Exception response, where response size is
incorrect
4001: Read/Write
area from (1 = 40001, 49 = 40049)
Fourth implied High byte Slot address of the network adapter module
Fifth ... eighth Destination Each register contains one byte of the 32-bit IP
implied address

when relevant
area from (1 = 40001, 49 = 40049)
module
Fourth implied Slot ID High byte: Destination drop number
Fifth ... eighth Terminator FF hex
implied
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MSTR: Master
Get Local Statistics MSTR Operation
Short Description
The Get Local Statistics operation obtains information related to the local node,
where the MSTR has been programmed. This operation takes one scan to complete
and does not require a data master transaction path.
The Get Local Statistics operation (type 3 in the displayed register of the top node)
can be implemented for Modbus Plus and TCP/IP Ethernet networks. It is not used
for SY/MAX Ethernet.
The following network statistics are available.
z Modbus Plus network statistics
z TCP/IP Ethernet network statistics

In a Get local statistics operation, the registers in the MSTR control block (the top
node) contain the information that differs depending on the type of network you are
using.
z Modbus Plus
z TCP/IP Ethernet

Displayed Operation type 3
when relevant
Second implied Length Starting from offset, the number of words of
statistics from the local processor’s statistics table ;
the length must be > 0 ≤ data area
Third implied Offset An offset value relative to the first available word in
the local processor’s statistics table; if the offset is
specified as 1, the function obtains statistics starting
with the second word in the table
Fourth implied Routing 1 If this is the second of two local nodes, set the high
byte to a value of 1
Note: If your PLC does not support Modbus Plus
option modules (S985s or NOMs), the fourth implied
register is not used.
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MSTR: Master

when relevant
statistics from the local processor’s statistics table ;
the local processor’s statistics table, if the offset is
Fourth implied Slot ID Low byte: Slot address of the network adapter
module
Fifth ... Eighth Not applicable
implied
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MSTR: Master
Clear Local Statistics MSTR Operation
Short Description
The Clear local statistics operation clears statistics relative to the local node (where
the MSTR has been programmed). This operation takes one scan to complete and
does not require a data master transaction path.
NOTE: When you issue the Clear Local Statistics operation, only words 13 ... 22 in
the statistics table are cleared.
The Clear Local Statistics operation (type 4 in the displayed register of the top node)
can be implemented for Modbus Plus and TCP/IP Ethernet networks. It is not used
for SY/MAX Ethernet.

In a Clear local statistics operation, the registers in the MSTR control block (the top
node) differ according to the type of network in use.
z Modbus Plus
z TCP/IP Ethernet

when relevant
Second implied Reserved
Third implied Reserved
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MSTR: Master

when relevant
Fourth implied Slot ID Low byte: Slot address of the network adapter
module
Fifth ... Eighth Reserved
implied
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MSTR: Master
Write Global Data MSTR Operation
Short Description
The Write global data operation transfers data to the communications processor in
the current node so that it can be sent over the network when the node gets the
token. All nodes on the local network link can receive this data. This operation takes
one scan to complete and does not require a data master transaction path.
The Write global data operation (type 5 in the displayed register of the top node) can
be implemented only for Modbus Plus networks.

The registers in the MSTR control block (the top node) are used in a Write global
data operation

when relevant
Second implied Length Specifies the number of registers from the data area
to be sent to the comm processor; the value of the
length must be ≤ 32 and must not exceed the size of
the data area
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MSTR: Master
Read Global Data MSTR Operation
Short Description
The Read global data operation gets data from the communications processor in
any node on the local network link that is providing global data. This operation may
require multiple scans to complete if global data is not currently available from the
requested node. If global data is available, the operation completes in a single scan.
No master transaction path is required.
The Read global data operation (type 6 in the displayed register of the top node) can

The registers in the MSTR control block (the top node) are used in a Read global
data operation

when relevant
Second implied Length Specifies the number of words of global data to be
requested from the comm processor designated by
the routing 1 parameter; the value of the length must
be > 0 ≤ 32 and must not exceed the size of the data
area
Third implied Available words Contains the number of words available from the
requested node; the value is automatically updated
by internal software
Fourth implied Routing 1 The low byte specifies the address of the node
whose global data are to be returned (a value
between 1 ... 64); if this is the second of two local
nodes, set the high byte to a value of 1
option modules (S985s or NOMs), the high byte of
the fourth implied register is not used and the
highbyte bits must all be set to 0.
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MSTR: Master
Get Remote Statistics MSTR Operation
Short Description
The Get Remote Statistics operation obtains information relative to remote nodes on
the network. This operation may require multiple scans to complete and does not
require a master data transaction path.
The Get Remote Statistics operation (type 7 in the displayed register of the top
node) can be implemented for Modbus Plus and TCP/IP Ethernet networks. It is not
used for SY/MAX Ethernet.

In a Get remote statistics operation, the registers in the MSTR control block (the top
node) contain the information that differs depending on the type of network you are
using.
z Modbus Plus
z TCP/IP Ethernet

when relevant
Second implied Length Starting from an offset, the number of words of
statistics to be obtained from a remote node; the
length must be > 0 ≤ total number of statistics
available (54) and must not exceed the size of the
data area
Third implied Offset Specifies an offset value relative to the first
available word in the statistics table, the value must
not exceed the number of statistic words available.
path is the destination device.
The remote comm processor always returns its complete statistics table when a
request is made, even if the request is for less than the full table. The MSTR
instruction then copies only the amount of words you have requested to the
designated 4x registers.
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MSTR: Master

when relevant
statistics from the local processor’s statistics table;
the local processor’s statistics table, if the offset is
Fifth ... Eighth Destination Each register contains one byte of the 32-bit IP
implied address
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MSTR: Master
Clear Remote Statistics MSTR Operation
Short Description
The Clear remote statistics operation clears statistics related to a remote network
node from the data area in the local node. This operation may require multiple scans
to complete and uses a single data master transaction path.
NOTE: When you issue the Clear Remote Statistics operation, only words 13 ... 22
in the statistics table are cleared
The Clear remote statistics operation (type 8 in the displayed register of the top
node) can be implemented for Modbus Plus and TCP/IP Ethernet networks. It is not
used for SY/MAX Ethernet.

In a Clear remote statistics operation, the registers in the MSTR control block (the
top node) contain information that differs according to the type of network in use.
z Modbus Plus
z TCP/IP Ethernet

when relevant
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MSTR: Master

when relevant
Second implied Not applicable
Third implied
Fifth ... Eighth Destination Each register contains one byte of the 32-bit IP
implied address
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MSTR: Master
Peer Cop Health MSTR Operation
Short Description
The peer cop health operation reads selected data from the peer cop
communications health table and loads that data to specified 4x registers in state
RAM. The peer cop communications health table is 12 words long, and the words
are indexed via this MSTR operation as words 0 ... 11.
The peer cop health operation (type 9) in the displayed register of the top node) can

The registers in the MSTR control block (the top node) are used in a Peer cop health
operation:

when relevant
Second implied Data size Number of words requested from peer cop table
(range 1 ... 12)
Third implied Index First word from the table to be read (range 0 ... 11,
where 0 = the first word in the peer cop table and 11
= the last word in the table)
Peer Cop Communications Health Status Information

The peer cop communications health table comprises 12 contiguous registers that
can be indexed in an MSTR operation as words 0 ... 11. Each bit in each of the table
words is used to represent an aspect of communications health relative to a specific
node on the Modbus Plus network.
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MSTR: Master
Bit-to-Network Node Relationship

The bits in words 0 ... 3 represent the health of the global input communication
expected from nodes 1 ... 64. The bits in words 4 ... 7 represent the health of the
output from a specific node. The bits in words 8 ... 11 represent the health of the
input to a specific node:
Type of Status Word Index Bit-to-network Node Relationship

Global Input 0
Specific Output 4
Specific Input 8
10
11
State of a Peer Cop Health Bit

The state of a peer cop health bit reflects the current communication status of its
associated node. A health bit is set when its associated node accepts inputs for its
peer copped input data group or hears that another node has accepted specific
output data from the its peer copped output data group. A health bit is cleared when
no communication has occurred for its associated data group within the configured
peer cop health time-out period.
All health bits are cleared when the Put Peer Cop interface command is executed at
PLC start-up time. Table values are not valid until at least one full token rotation
cycle has been completed after execution of the Put Peer Cop interface command.
The health bit for a given node is always zero when its associated peer cop entry is
null.
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MSTR: Master
Reset Option Module MSTR Operation
Short Description
The Reset option module operation causes a Quantum NOE option module to enter
a reset cycle to reset its operational environment.
The Reset option module operation (type 10 in the displayed register of the top
node) can be implemented for TCP/IP and SY/MAX Ethernet networks, accessed
via the appropriate network adapter. Modbus Plus networks do not use this
operation.

In a Reset option module operation, the registers in the MSTR control block (the top
node) differ according to the type of network in use.
z TCP/IP Ethernet
z SY/MAX Ethernet

when relevant
Third implied
Fourth implied Slot ID Number displayed in the low byte, in the range 1 ...
16 indicating the slot in the local backplane where
the option module resides
implied
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MSTR: Master

when relevant
Third implied
module
implied
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MSTR: Master
Read CTE (Config Extension Table) MSTR Operation
Short Description
The Read CTE operation reads a given number of bytes from the Ethernet
configuration extension table to the indicated buffer in PLC memory. The bytes to be
read begin at a byte offset from the beginning of the CTE. The content of the
Ethernet CTE table is displayed in the middle node of the MSTR block.
The Read CTE operation (type 11 in the displayed register of the top node) can be
implemented for TCP/IP and SY/MAX Ethernet networks, accessed via the
appropriate network adapter. Modbus Plus networks do not use this operation.

In a Read CTE operation, the registers in the MSTR control block (the top node)
differ according to the type of network in use.
z TCP/IP Ethernet
z SY/MAX Ethernet

when relevant
Third implied
Fourth implied Map index Either a value displayed in the high byte of the
register or not used
Slot ID Number displayed in the low byte, in the range 1 ...
implied
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MSTR: Master


when relevant
Second implied Data Size Number of words transferred
Third implied Base Address Byte offset in PLC register structure indicating
where the CTE bytes will be written
Fourth implied Low byte Slot address of the NOE module
High byte Terminator (FF hex)
implied
CTE Display Implementation (Middle Node)

The values in the Ethernet configuration extension table (CTE) are displayed in a
series of registers in the middle node of the MSTR instruction when a Read CTE
operation is implemented. The middle node contains the first of 11 contiguous 4x
registers.
The registers display the following CTE data.
Parameter Register Content

Frame type Displayed 1 = 802.3
2 = Ethernet
IP address First implied First byte of the IP address
Second implied Second byte of the IP address
Third implied Third byte of the IP address
Fourth implied Fourth byte of the IP address
Subnetwork mask Fifth implied Hi word
Sixth implied Low word
Gateway Seventh implied First byte of the gateway
Eighth implied Second byte of the gateway
Ninth implied Third byte of the gateway
Tenth implied Fourth byte of the gateway
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MSTR: Master
Write CTE (Config Extension Table) MSTR Operation
Short Description
The Write CTE operation writes the configuration CTE table from the data specified
in the middle node to an indicated Ethernet configuration extension table or a
specified slot.
The Write CTE operation (type 12 in the displayed register of the top node) can be
implemented for TCP/IP and SY/MAX Ethernet networks, via the appropriate
network adapter. Modbus Plus networks do not use this operation.

In a Write CTE operation, the registers in the MSTR control block (the top node)
differ according to the type of network in use.
z TCP/IP Ethernet
z SY/MAX Ethernet

when relevant
Third implied
Fourth implied Map index Either a value displayed in the high byte of the
register or not used
Slot ID Number displayed in the low byte, in the range 1 ...
implied
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MSTR: Master

when relevant
Second implied Data Size Number of words transferred
Third implied Base Address Byte offset in PLC register structure indicating
where the CTE bytes will be written
Fourth implied Low byte Slot address of the NOE module
High byte Destination drop number
Fifth implied Terminator FF hex
Sixth ... Eighth Not applicable
implied
CTE Display Implementation (Middle Node)

The values in the Ethernet configuration extension table (CTE) are displayed in a
series of registers in the middle node of the MSTR instruction when a Write CTE
operation is implemented. The middle node contains the first of 11 contiguous 4x
registers.
The registers are used to transfer the following CTE data.
Parameter Register Content

Frame type Displayed 1 = 802.3
2 = Ethernet
IP address First implied First byte of the IP address
Second implied Second byte of the IP address
Third implied Third byte of the IP address
Fourth implied Fourth byte of the IP address
Subnetwork mask Fifth implied Hi word
Sixth implied Low word
Gateway Seventh implied First byte of the gateway
Eighth implied Second byte of the gateway
Ninth implied Third byte of the gateway
Tenth implied Fourth byte of the gateway
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MSTR: Master
Modbus Plus Network Statistics

The following table shows the statistics available on the Modbus Plus network. You
may acquire this information by using the appropriate MSTR operation or by using
Modbus function code 8.
NOTE: When you issue the Clear local or Clear remote statistics operations, only
words 13 ... 22 are cleared.
Word Bits Meaning

00 Node type ID
0 Unknown node type
1 PLC node
2 Modbus bridge node
3 Host computer node
4 Bridge Plus node
5 Peer I/O node
01 0 ... 11 Software version number in hex (to read, strip bits 12-15 from
word)
12 ... 14 Reserved
15 Defines Word 15 error counters (see Word 15)
Most significant bit defines use of error counters in Word 15.
Least significant half of upper byte, plus lower byte, contain
software
version:
02 Network address for this station
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MSTR: Master
Word Bits Meaning

03 MAC state variable:
0 Power up state
1 Monitor offline state
2 Duplicate offline state
3 Idle state
4 Use token state
5 Work response state
6 Pass token state
7 Solicit response state
8 Check pass state
9 Claim token state
10 Claim response state
04 Peer status (LED code); provides status of this unit relative to
the network:
0 Monitor link operation
32 Normal link operation
64 Never getting token
96 Sole station
128 Duplicate station
05 Token pass counter; increments each time this station gets the
token
06 Token rotation time in ms
07 LO Data master failed during token ownership bit map
HI Program master failed during token ownership bit map
08 LO Data master token owner work bit map
HI Program master token owner work bit map
09 LO Data slave token owner work bit map
HI Program slave token owner work bit map
10 HI Data slave/get slave command transfer request bit map
11 LO Program master/get master rsp transfer request bit map
HI Program slave/get slave command transfer request bit map
12 LO Program master connect status bit map
HI Program slave automatic logout request bit map
13 LO Pretransmit deferral error counter
HI Receive buffer DMA overrun error counter
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MSTR: Master
Word Bits Meaning

14 LO Repeated command received counter
HI Frame size error counter
15 If Word 1 bit 15 is not set, Word 15 has the following meaning:
LO Receiver collision-abort error counter
HI Receiver alignment error counter
If Word 1 bit 15 is set, Word 15 has the following meaning:
LO Cable A framing error
HI Cable B framing error
16 LO Receiver CRC error counter
HI Bad packet-length error counter
17 LO Bad link-address error counter
HI Transmit buffer DMA-underrun error counter
18 LO Bad internal packet length error counter
HI Bad MAC function code error counter
19 LO Communication retry counter
HI Communication failed error counter
20 LO Good receive packet success counter
HI No response received error counter
21 LO Exception response received error counter
HI Unexpected path error counter
22 LO Unexpected response error counter
HI Forgotten transaction error counter
23 LO Active station table bit map, nodes 1 ... 8
HI Active station table bit map, nodes 9 ...16
HI Active station table bit map, nodes 25 ... 32
27 LO Token station table bit map, nodes 1 ... 8
HI Token station table bit map, nodes 9 ... 16
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MSTR: Master
Word Bits Meaning

31 LO Global data present table bit map, nodes 1 ... 8
HI Global data present table bit map, nodes 9 ... 16
34 LO Global data present table map, nodes 49 ... 56
35 LO Receive buffer in use bit map, buffer 1-8
HI Receive buffer in use bit map, buffer 9 ... 16
36 LO Receive buffer in use bit map, buffer 17 ... 24
HI Receive buffer in use bit map, buffer 25 ... 32
37 LO Receive buffer in use bit map, buffer 33 ... 40
HI Station management command processed initiation counter
38 LO Data master output path 1 command initiation counter
HI Data master output path 2 command initiation counter
42 LO Data slave input path 41 command processed counter
HI Data slave input path 42 command processed counter
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MSTR: Master
Word Bits Meaning

46 LO Program master output path 81 command initiation counter
HI Program master output path 82 command initiation counter
48 LO Program master command initiation counter
50 LO Program slave input path C1 command processed counter
HI Program slave input path C2 command processed counter
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MSTR: Master
TCP/IP Ethernet Statistics
TCP/IP Ethernet Statistics

A TCP/IP Ethernet board responds to Get Local Statistics and Set Local Statistics
commands with the following information:
Word Meaning
00 ... 02 MAC address, e.g., if the MAC address is 00 00 54 00 12 34, it is
displayed as follows:
Word Content
00 00 00
01 00 54
02 34 12
03 Board status Meaning
0x0001 Running
0x4000 APPI LED (1=ON, 0 = OFF)
0x8000 Link LED
04 and 05 Number of receiver interrupts
06 and 07 Number of transmitter interrupts
08 and 09 Transmit-timeout error count
10 and 11 Collision-detect error count
12 and 13 Missed packets
14 and 15 Memory error count
16 and 17 Number of times driver has restarted lance
18 and 19 Receive framing error count
20 and 21 Receiver overflow error count
22 and 23 Receive CRC error count
24 and 25 Receive buffer error count
26 and 27 Transmit buffer error count
28 and 29 Transmit silo underflow count
30 and 31 Late collision count
32 and 33 Lost carrier count
34 and 35 Number of retries
36 and 37 IP address, e.g., if the IP address is 198.202.137.113 (or c6 CA 89 71),
it is displayed as follows:
Word Content
36 89 71
37 C6 CA
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MSTR: Master
Run Time Errors
Runtime Errors
If an error occurs during a MSTR operation, a hexadecimal error code will be
displayed in the first implied register in the control block (the top node).
Function error codes are network-specific.
z Modbus Plus and SY/MAX Ethernet Error Codes
z SY/MAX-specific Error Codes
z TCP/IP Ethernet Error Codes
z CTE Error Codes for SY/MAX and TCP/IP Ethernet
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MSTR: Master
Modbus Plus and SY/MAX Ethernet Error Codes
Form of the Function Error Code

The form of the function error code for Modbus Plus and SY/MAX Ethernet
transactions is Mmss, where
z M represents the major code
z m represents the minor code
z ss represents a subcode
Hexadecimal Error Code
Hex Error Code Meaning

1001 User has aborted the MSTR element
2001 An unsupported operation type has been specified in the control block
2002 One or more control block parameter has been changed while the MSTR
element is active (applies only to operations that take multiple scans to
complete). Control block parameters may be changed only when the
MSTR element is not active.
2003 Invalid value in the length field of the control block
2004 Invalid value in the offset field of the control block
2005 Invalid values in the length and offset fields of the control block
2006 Invalid slave device data area
2007 Invalid slave device network area
2008 Invalid slave device network routing
2009 Route equal to your own address
200A Attempting to obtain more global data words than available
30ss Modbus slave exception response
4001 Inconsistent Modbus slave response
5001 Inconsistent network response
6mss) Routing failure
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MSTR: Master
ss HEX Value in Error Code 30ss

The ss subfield in error code 30ss is:
ss Hex Value Meaning

01 Slave device does not support the requested operation
02 Nonexistent slave device registers requested
03 Invalid data value requested
04 Reserved
05 Slave has accepted long-duration program command
06 Function can’t be performed now: a long-duration command in effect
07 Slave rejected long-duration program command
08 ... 255 Reserved
ss Hex Value in Error Code 6mss

The m subfield in error code 6mss is an index into the routing information indicating
where an error has been detected (a value of 0 indicates the local node, a 2 the
second device on the route, etc.).
The ss subfield in error code 6mss is:

01 No response received
02 Program access denied
03 Node off-line and unable to communicate
04 Exception response received
05 Router node data paths busy
06 Slave device down
07 Bad destination address
08 Invalid node type in routing path
10 Slave has rejected the command
20 Initiated transaction forgotten by slave device
40 Unexpected master output path received
80 Unexpected response received
F001 Wrong destination node specified for the MSTR operation
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MSTR: Master
SY/MAX-specific Error Codes
Types or Errors
Three additional types of errors may be reported in the MSTR instruction when
SY/MAX Ethernet is being used.
The error codes have the following designations:
z 71xx errors: Errors detected by the remote SY/MAX device
z 72xx errors: Errors detected by the serve
z 73xx errors: Errors detected by the Quantum translator
Hexadecimal Error Code SY/MAX-specific

HEX Error Code SY/MAX-specific:

7101 Illegal opcode detected by the remote SY/MAX device
7103 Illegal address detected by the remote SY/MAX device
7109 Attempt to write a read-only register detected by the remote SY/MAX
device
710F Receiver overflow detected by the remote SY/MAX device
7110 Invalid length detected by the remote SY/MAX device
7111 Remote device inactive, not communicating (occurs after retries and
time-out have been exhausted) detected by the remote SY/MAX device
7113 Invalid parameter on a read operation detected by the remote SY/MAX
device
711D Invalid route detected by the remote SY/MAX device
7149 Invalid parameter on a write operation detected by the remote SY/MAX
device
714B Illegal drop number detected by the remote SY/MAX device
7201 Illegal opcode detected by the SY/MAX server
7203 Illegal address detected by the SY/MAX server
7209 Attempt to write to a read-only register detected by the SY/MAX server
720F Receiver overflow detected by the SY/MAX server
7210 Invalid length detected by the SY/MAX server
7211 Remote device inactive, not communicating (occurs after retries and
time-out have been exhausted) detected by the SY/MAX server
7213 Invalid parameter on a read operation detected by the SY/MAX server
721D Invalid route detected by the SY/MAX server
7249 Invalid parameter on a write operation detected by the SY/MAX server
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MSTR: Master

724B Illegal drop number detected by the SY/MAX server
7301 Illegal opcode in an MSTR block request by the Quantum translator
7303 Read/Write QSE module status (200 route address out of range)
7309 Attempt to write to a read-only register when performing a status write
(200 route)
731D Invalid rout detected by Quantum translator
Valid routes are:
z dest_drop, 0xFF
z 200, dest_drop, 0xFF
z 100+drop, dest_drop, 0xFF
All other routing values generate an error

734B One of the following errors has occurred:
z No CTE (configuration extension) table was configured
z No CTE table entry was created for the QSE Module slot number
z No valid drop was specified
z The QSE Module was not reset after the CTE was created
Note: After writing and configuring the CTE and downloading it to the
QSE Module, you must reset the QSE Module to make the changes
take effect.
z When using an MSTR instruction, no valid slot or drop was specified
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MSTR: Master
TCP/IP Ethernet Error Codes
Error in an MSTR Routine

An error in an MSTR routine over TCP/IP Ethernet may produce one of the following
errors in the MSTR control block.
The form of the code is Mmss, where
z M represents the major code
z m represents the minor code
z ss represents a subcode
Hexadecimal Error Code for MSTR Routine over TCP/IP Ethernet

1001 User has aborted the MSTR element
2001 An unsupported operation type has been specified in the control block
2002 One or more control block parameter has been changed while the MSTR
element is active (applies only to operations that take multiple scans to
complete). Control block parameters may be changed only when the
MSTR element is not active
2003 Invalid value in the length field of the control block
2004 Invalid value in the offset field of the control block
2005 Invalid values in the length and offset fields of the control block
2006 Invalid slave device data area
3000 Generic Modbus fail code
30ss Modbus slave exception response
4001 Inconsistent Modbus slave response
ss Hex Value in Error Code 30ss

The ss subfield in error code 30ss is:

01 Slave device does not support the requested operation
02 Nonexistent slave device registers requested
03 Invalid data value requested
04 Reserved
05 Slave has accepted long-duration program command
06 Function can’t be performed now: a long-duration command in effect
07 Slave rejected long-duration program command
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MSTR: Master
HEX Error Code TCP/IP Ethernet Network

An error on the TCP/IP Ethernet network itself may produce one of the following
errors in the MSTR control block.

5004 Interrupted system call
5005 I/O error
5006 No such address
5009 The socket descriptor is invalid
500C Not enough memory
500D Permission denied
5011 Entry exists
5016 An argument is invalid
5017 An internal table has run out of space
5020 The connection is broken
5023 This operation would block and the socket is nonblocking
5024 The socket is nonblocking and the connection cannot be completed
5025 The socket is nonblocking and a previous connection attempt has not yet
completed
5026 Socket operation on a nonsocket
5027 The destination address is invalid
5028 Message too long
5029 Protocol wrong type for socket
502A Protocol not available
502B Protocol not supported
502C Socket type not supported
502D Operation not supported on socket
502E Protocol family not supported
502F Address family not supported
5030 Address is already in use
5031 Address not available
5032 Network is down
5033 Network is unreachable
5034 Network dropped connection on reset
5035 The connection has been aborted by the peer
5036 The connection has been reset by the peer
5037 An internal buffer is required, but cannot be allocated
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MSTR: Master

5038 The socket is already connected
5039 The socket is not connected
503A Can’t send after socket shutdown
503B Too many references; can’t splice
503C Connection timed out
503D The attempt to connect was refused
5040 Host is down
5041 The destination host could not be reached from this node
5042 Directory not empty
5046 NI_INIT returned -1
5047 The MTU is invalid
5048 The hardware length is invalid
5049 The route specified cannot be found
504A Collision in select call; these conditions have already been selected by
another task
504B The task id is invalid
5050 No network resource
5051 Length error
5052 Addressing error
5053 Application error
5054 Client in bad state for request
5055 No remote resource
5056 Nonoperational TCP connection
5057 Incoherent configuration
F001 In Reset mode
F002 Module not fully initialized
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MSTR: Master
CTE Error Codes for SY/MAX and TCP/IP Ethernet
CTE Error Codes for SY/MAX and TCP/IP Ethernet

HEX Error Code MSTR routine over TCP/IP Ethernet:

7001 The is no Ethernet configuration extension
7002 The CTE is not available for access
7003 The offset is invalid
7004 The offset + length is invalid
7005 Bad data field in the CTE
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MU16: Multiply 16 Bit
31007523 8/2010
122
Introduction
This chapter describes the instruction MU16.

Topic Page
Representation 761
31007523 8/2010 759

Short Description
The MU16 instruction performs signed or unsigned multiplication on the 16-bit
values in the top and middle nodes, then posts the product in two contiguous holding
registers in the bottom node.
760 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = enables value 1 x value 2
value 1 3x, 4x INT, UINT Multiplicand, can be displayed explicitly as
(top node) an integer (range 1 ... 65 535, enter e.g.
#65535) or stored in a register
value 2 3x, 4x INT, UINT Multiplier, can be displayed explicitly as an
(middle node) integer (range 1 ... 65 535) or stored in a
register
product 4x INT, UINT First of two contiguous holding registers:
(bottom node) displayed register contains half of the
product and the implied register contains
the other half
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MUL: Multiply
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MUL: Multiply
123
Introduction
This chapter describes the instruction MUL.

Topic Page
Representation 765
Example 766
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MUL: Multiply
Short Description
The MUL instruction multiplies unsigned value 1 (its top node) by unsigned value 2
(its middle node) and stores the product in two contiguous holding registers in the
bottom node.
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MUL: Multiply
Representation
Symbol

z E685/785 PLCs
z L785 PLCs

Reference Type
Top input 0x, 1x None ON = value 1 multiplied by value 2
value 1 3x, 4x UINT Multiplicand, can be displayed explicitly as an integer
(top node) (range 1 ... 9 999) or stored in a register
Max. Value: 999 -16-bit PLC
Max. Value: 9999 - 24-bit PLC
Max. Value: 65535 - *PLC
value 2 3x, 4x UINT Multiplier, can be displayed explicitly as an integer
(middle node) (range 1 ... 9 999) or stored in a register
Max. Value: 999 -16-bit PLC
Max. Value: 9999 - 24-bit PLC
Max. Value: 65535 - *PLC
result 4x UINT Product (first of two contiguous holding registers;
(bottom node) displayed: high-order digits; implied: low-order digits)
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MUL: Multiply
Example
Product of Instruction MUL

For example, if value 1 = 8 000 and value 2 = 2, the product is 16 000. The displayed
register contains the value 0001 (the high-order half of the product), and implied
register contains the value 6 000 (the low-order half of the product).
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NBIT: Bit Control
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NBIT: Bit Control
124
Introduction
This chapter describes the instruction NBIT.

Topic Page
Representation 769
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NBIT: Bit Control
Short Description
The normal bit (NBIT) instruction lets you control the state of a bit from a register by
specifying its associated bit number in the bottom node. The bits being controlled
are similar to coils, when a bit is turned ON, it stays ON until a control signal turns it
OFF.
NOTE: The NBIT instruction does not follow the same rules of network placement
as 0x-referenced coils do. An NBIT instruction cannot be placed in column 11 of a
network and it can be placed to the left of other logic nodes on the same rungs of
the ladder.
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NBIT: Bit Control
Representation
Symbol

Reference
Top input 0x, 1x None ON = sets the specified bit to 1
OFF = clears the specified bit to 0
register # 4x WORD Holding register whose bit pattern is being
(top node) controlled
bit # INT, UINT Indicates which one of the 16 bits is being
(bottom node) controlled
Top output 0x None Echoes the state of the top input:
ON = top input ON and specified bit set to
1
OFF = top input OFF and specified bit set
to 0
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NBIT: Bit Control
770 31007523 8/2010

NCBT: Normally Closed Bit
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125
Introduction
This chapter describes the instruction NCBT.

Topic Page
Representation 773
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Short Description
The normally closed bit (NCBT) instruction lets you sense the logic state of a bit in
a register by specifying its associated bit number in the bottom node. The bit is
representative of an N.C contact. It passes power from the top output when the
specified bit is OFF and the top input is ON.
772 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = enables bit sensing
register # 3x, 4x WORD Register whose bit pattern is being used to
(top node) represent N.C. contacts
bit # INT, UINT (Indicates which one of the 16 bits is being
(bottom node) sensed
Top output 0x None ON = top input is ON and specified bit is
OFF (logic state 0)
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774 31007523 8/2010

NOBT: Normally Open Bit
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126
Introduction
This chapter describes the instruction NOBT.

Topic Page
Representation 777
31007523 8/2010 775

Short Description
The normally open bit (NOBT) instruction lets you sense the logic state of a bit in a
register by specifying its associated bit number in the bottom node. The bit is
representative of an N.O contact.
776 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = enables bit sensing
register # 3x, 4x WORD Register whose bit pattern is being used to
(top node) represent N.O. contacts
bit # INT, UINT (Indicates which one of the 16 bits is being
(bottom node) sensed
Top output 0x None ON = top input is ON and specified bit is
ON (logic state 1)
31007523 8/2010 777

778 31007523 8/2010

NOL: Network Option Module for Lonworks
31007523 8/2010
NOL: Network Option Module

for Lonworks
127
Introduction
This chapter describes the instruction NOL.

Topic Page
Representation 781
Detailed Description 782
31007523 8/2010 779

Short Description
Function Requirements
The following steps are necessary before using this instruction:
Step Action
1 Add loadable NSUP.exe to the controller’s configuration
Note: This loadable needs only be loaded once to support multiple loadables,
such as ECS.exe and XMIT.exe.
CAUTION
The outputs of the instruction turn on, regardless of the input states
When the NSUP loadable is not installed or is installed after the NOL loadable or
is installed in a Quantum PLC with an executive < V2.0, all three outputs turn on,
regardless of the input states.
Step Action
2 Unpack and install the DX Loadable NOL. For more information, see Installation
of DX Loadables, page 75.
The NOL instruction is provided to facilitate the movement of the large amount of
data between the NOL module and the controller register space. The NOL Module
is mapped for 16 input registers (3X) and 16 output registers (4X). Of these
registers, two input and two output registers are for handshaking between the NOL
Module and the instruction. The remaining fourteen input and fourteen output
registers are used to transport the data.
780 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = Enables the NOL function
Middle input 0x, 1x None ON = Initialize: causes the instruction to re-sync
with the module
function # 4x INT, UINT, Function number selects the function of the
(top node) WORD NOL block
Function 0 transfers data to/from the module.
Any other function number yields an error.
register block 4x INT, UINT, Register block (first of 16 contiguous registers
(middle node) WORD
count INT, UINT Total number of registers required by the
(bottom node) instruction
Top output 0x None ON = instruction enabled and no error
Middle output 0x None New data
Set for one sweep when the entire data block
from the module has been written to the register
area.
31007523 8/2010 781

Detailed Description
Register Block (Middle Node)

This block provides the registers for configuration and status information, the
registers for the health status bits and the registers for the actual data of the
Standard Network Variable Types (SNVTs).
Register Block
Register Content
Configuration and Displayed and first implied I/O Map input base (3x)
Status information Second and third implied I/O Map output base (4x)
Fourth implied Enable health bits
Fifth implied Number of input registers
Sixth implied Number of output registers
Seventh implied Number of discrete input registers
Eighth implied Number of discrete output registers
Ninth implied Config checksum (CRC)
10th implied NOL version
11th implied Module firmware version
12th implied NOL DX version
13th implied Module DX version
14th to 15th implied Not used
SNVTs Health Bit 16th to 31st implied Health bits of each programmable
Status network variable
(if enabled in DX-
Zoom screen)
SNVTs Actual Enable Health Bit = NO: Data is stored in 4 groups:
Data from 16th implied up z Discrete inputs
Enable Health Bit = YES: z Register inputs
from 32nd implied up z Discrete outputs
z Register outputs
These groups of data are set up
consecutively and start on word
boundaries.
The first 16 registers with configuration and status information can be programmed
and monitored via the NOL DX Zoom screen. For setting up the link to the NOL
module the only parameters that need to be entered are the beginning 3x and 4x
registers used when I/O mapping the NOL module.
Further information you will find in the documentation Network Option Module for
LonWorks.
782 31007523 8/2010

Count (Bottom Node)

Defines the total number of registers required by the function block. This value must
be set to a value equal to or greater than the number of data registers required to
transfer and store the network data being used by the NOL module. If the count
value is not large enough for the required data, the error output will be set.
31007523 8/2010 783

784 31007523 8/2010

Instruction Descriptions (O to Q)
31007523 8/2010
V
Introduction
In this part instruction descriptions are arranged alphabetically from O to Q.

128 OR: Logical OR 787
129 PCFL: Process Control Function Library 793
130 PCFL-AIN: Analog Input 799
131 PCFL-ALARM: Central Alarm Handler 805
132 PCFL-AOUT: Analog Output 811
133 PCFL-AVER: Average Weighted Inputs Calculate 815
134 PCFL-CALC: Calculated Preset Formula 821
135 PCFL-DELAY: Time Delay Queue 827
136 PCFL-EQN: Formatted Equation Calculator 831
137 PCFL-INTEG: Integrate Input at Specified Interval 837
138 PCFL-KPID: Comprehensive ISA Non Interacting PID 841
139 PCFL-LIMIT: Limiter for the Pv 847
140 PCFL-LIMV: Velocity Limiter for Changes in the Pv 851
141 PCFL-LKUP: Look-up Table 855
142 PCFL-LLAG: First-order Lead/Lag Filter 861
143 PCFL-MODE: Put Input in Auto or Manual Mode 865
144 PCFL-ONOFF: ON/OFF Values for Deadband 869
145 PCFL-PI: ISA Non Interacting PI 873
146 PCFL-PID: PID Algorithms 879
147 PCFL-RAMP: Ramp to Set Point at a Constant Rate 885
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148 PCFL-RATE: Derivative Rate Calculation over a Specified 889
Time
149 PCFL-RATIO: Four Station Ratio Controller 893
150 PCFL-RMPLN: Logarithmic Ramp to Set Point 897
151 PCFL-SEL: Input Selection 901
152 PCFL-TOTAL: Totalizer for Metering Flow 907
153 PEER: PEER Transaction 913
154 PID2: Proportional Integral Derivative 917
786 31007523 8/2010

OR: Logical OR
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OR: Logical OR
128
Introduction
This chapter describes the instruction OR.

Topic Page
Representation 789
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OR: Logical OR
Short Description
WARNING
DISABLED COILS
Before using the OR instruction, check for disabled coils. OR will override any
disabled coils within the destination matrix without enabling them. This can cause
personal injury if a coil has disabled an operation for maintenance or repair
because the coil’s state can be changed by the OR operation.
equipment damage.
The OR instruction performs a Boolean OR operation on the bit patterns in the

source and destination matrices.
The ORed bit pattern is then posted in the destination matrix, overwriting its previous
contents.
788 31007523 8/2010

OR: Logical OR
Representation
Symbol

Reference
Top input 0x, 1x None Initiates OR
source matrix 0x, 1x, 3x, 4x ANY_BIT First reference in the source matrix.
(top node)
destination 0x, 4x ANY_BIT First reference in the destination matrix
matrix
(middle node)
length INT, UINT Matrix length, range: 1 ... 100.
(bottom node)
31007523 8/2010 789

OR: Logical OR
An OR Example
Whenever contact 10001 passes power, the source matrix formed by the bit pattern
in registers 40600 and 40601 is ORed with the destination matrix formed by the bit
pattern in registers 40606 and 40607. The ORed bit pattern is then copied into
registers 40606 and 40607, overwriting the original destination bit pattern.
CAUTION
OUTPUT/COIL RESTRICTIONS WITH THE OR INSTRUCTION
Do not turn off outputs and coils when using the OR instruction.
NOTE: If you want to retain the original destination bit pattern of registers 40606 and
40607, copy the information into another table using the BLKM instruction before
performing the OR operation.
790 31007523 8/2010

OR: Logical OR

1 ... 100. A length of 2 indicates that 32 bits in each matrix will be ORed.
31007523 8/2010 791

OR: Logical OR
792 31007523 8/2010

PCFL: Process Control Function Library
31007523 8/2010
PCFL:
Process Control Function Library
129
Introduction
This chapter describes the instruction PCFL.

Topic Page
Representation 795
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Short Description
The PCFL instruction gives you access to a library of process control functions
utilizing analog values.
PCFL operations fall into three major categories.
z Advanced Calculations
z Signal Processing
z Regulatory Control
A PCFL function is selected from a list of alphabetical subfunctions in a pulldown

menu in the panel software, and the subfunction is displayed in the top node of the
instruction (see Function (Top Node), page 796 for a list of subfunctions and
descriptions).
PCFL uses the same FP library as EMTH. If the PLC that you are using for PCFL
does not have the onboard 80x87 math coprocessor chip, calculations take a
comparatively long time to execute. PLCs with the math coprocessor can solve
PCFL calculations ten times faster than PLCs without the chip. Speed, however,
should not be an issue for most traditional process control applications where
solution times are measured in seconds, not milliseconds.
794 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = enables specified process control
function
function Selection of process control function
(top node) An indicator for the selected PCFL library
function is specified in the top node.
(For more information, see Function (Top
Node), page 796.)
parameter 4x INT, UINT, First in a block of contiguous holding
block WORD registers where the parameters for the
(middle node) specified subfunction are stored
length INT, UINT Length of parameter block (depending on
(bottom node) selected subfunction
Bottom output 0x None ON = error
31007523 8/2010 795

Function (Top Node)

A subfunction for the selected PCFL library function is specified in the top node.
Operation Subfunction Description Time-

dependent
Operations
Advanced AVER Average weighted inputs no
Calculations
CALC Calculate preset formula no
EQN Formatted equation calculator no
Signal ALARM Central alarm handler for a PV input no
Processing
AIN Convert inputs to scaled engineering units no
AOUT Convert outputs to values in the 0 ... 4095 no
range
DELAY Time delay queue yes
LKUP Look-up table no
INTEG Integrate input at specified interval yes
LLAG First-order lead/lag filter yes
LIMIT Limiter for the PV (low/low, low, high, no
high/high)
LIMV Velocity limiter for changes in the PV (low, yes
high)
MODE Put input in auto or manual mode no
RAMP Ramp to set point at a constant rate yes
RMPLN Logarithmic ramp to set point (~2/3 closer to yes
set point for each time constant)
RATE Derivative rate calculation over a specified yes
time
SEL High/low/average input selection no
Regulatory KPID Comprehensive ISA non-interacting yes
Control proportional-integral-derivative (PID)
ONOFF Specifies ON/OFF values for deadband no
PID PID algorithms yes
PI ISA non-interacting PI (with halt/manual/auto yes
operation features)
RATIO Four-station ratio controller no
TOTAL Totalizer for metering flow yes
796 31007523 8/2010

Advanced Calculations
Advanced calculations are used for general mathematical purposes and are not
limited to process control applications. With advanced calculations, you can create
custom signal processing algorithms, derive states of the controlled process, derive
statistical measures of the process, etc.
Simple math routines have already been offered in the EMTH instruction. The
calculation capability included in PCFL is a textual equation calculator for writing
custom equations instead of programming a series of math operations one by one.
Signal Processing
Signal processing functions are used to manipulate process and derived process
signals. They can do this in a variety of ways; they linearize, filter, delay, and
otherwise modify a signal. This category would include functions such as an Analog
Input/Output, Limiters, Lead/Lag, and Ramp generators.
Regulatory Control
Regulatory functions perform closed loop control in a variety of applications.
Typically, this is a PID (proportional integral derivative) negative feedback control
loop. The PID functions in PCFL offer varying degrees of functionality. Function 75,
PID, has the same general functionality as the PID2 instruction but uses floating
point math and represents some options differently. PID is beneficial in cases where
PID2 is not suitable because of numerical concerns such as round-off.
For more information, see PCFL Subfunctions, page 45.
Parameter Block (Middle Node)

The 4x register entered in the middle node is the first in a block of contiguous holding
register where the parameters for the specified PCFL operation are stored.
The ways that the various PCFL operations implement the parameter block are
described in the description of the various subfunctions (PCFL operations).
Within the parameter block of each PCFL function are two registers used for input
and output status.
Output Flags
In all PCFL functions, bits 12 ... 16 of the output status register define the following
standard output flags:
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Bit Function
1 - 11 Not used
12 1 = Math error - invalid floating point or output
13 1 = Unknown PCFL function
14 not used
15 1 = Size of the allocated register table is too small
16 1 = Error has occurred - pass power to the bottom output
For time-dependent PCFL functions, bits 9 and 11 are also used as follows:
Bit Function
1-8 Not used
9 1 = Initialization working
10 Not used
11 1 = Illegal solution interval
12 1 = Math error - invalid floating point or output
13 1 = Unknown PCFL function
14 not used
15 1 = Size of the allocated register table is too small
16 1 = Error has occurred - pass power to the bottom output
Input Flags
In all PCFL functions, bits 1 and 3 of the input status register define the following
standard input flags:
Bit Function
1 1 = Function initialization complete or in progress
0 = Initialize the function
2 not used
3 1 = Timer override
4 -16 not used

The integer value entered in the bottom node specifies the length, i.e. the number of
registers, of the PCFL parameter block. The maximum allowable length will vary
depending on the function you specify.
798 31007523 8/2010

PCFL-AIN: Analog Input
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130
Introduction
This chapter describes the subfunction PCFL-AIN.

Topic Page
Representation 801
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Short Description
NOTE: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Signal Processing.
The AIN function scales the raw input produced by analog input modules to
engineering values that can be used in the subsequent calculations.
Three scaling options are available.
z Auto input scaling
z Manual input scaling
z Implementing process square root on the input to linearize the signal before
scaling
800 31007523 8/2010

Representation
Symbol

Reference
function
AIN Selection of the subfunction AIN
(top node)
parameter 4x INT, UINT First in a block of contiguous holding
block registers where the parameters for the
For more information, see Parameter
Block (Middle Node), page 802.
14 INT, UINT Length of parameter block for subfunction
(bottom node) AIN (can not be changed)
31007523 8/2010 801

Mode of Functioning
AIN supports the range resolutions for following device types:
Quantum Engineering Ranges
Resolution Range: Valid Range: Under Range: Over

10 V 768 ... 64 768 767 64 769
V 16 768 ... 48 768 16 767 48 769
0 ... 10 V 0 ... 64 000 0 64 001
0 ... 5 V 0 ... 32 000 0 32 001
1 ... 5 V 6 400 ... 32 000 6 399 32 001
Quantum Thermocouple
Resolution Range: Valid

TC degrees -454 ... +3 308
TC 0.1 degrees -4 540 ... +32 767
TC Raw Units 0 ... 65 535
Quantum Voltmeter
Resolution Range: Valid Range: Under Range: Over

10 V -10 000 ... +10 000 -10 001 +10 001
5V -5 000 ... +5 000 -5 001 +5 001
0 ... 10 V 0 ... 10 000 0 10 001
0 ... 5 V 0 ... 5 000 0 5 001
1 ... 5 V 1 000 ... 5 000 999 5 001

The length of the AIN parameter block is 14 registers.
Register Content
Displayed Input from a 3x register
First implied Reserved
Second implied Output status
Third implied Input status
Fourth and fifth implied Scale 100% engineering units
Sixth and seventh implied Scale 0% engineering units
802 31007523 8/2010

Register Content
Eighth and ninth implied Manual input
10th and 11th implied Auto input
12th and 13th implied Output
Output Status
Bit Function
1...5 Not used
6 1 = with TC PSQRT, invalid: in extrapolation range, PSQRT not used
7 1 = input out of range
8 1 = echo under range from input module
9 1 = echo over range from input module
10 1 = invalid output mode selected
11 1 = invalid Engineering Units
12 ... 16 Standard output bits (flags)
Input Status
Bit Function
1 ... 3 Standard input bits (flags)
4 ... 8 Ranges (see following tables)
9 1 = process square root on raw input
10 1 = manual scaling mode
0 = auto scaling mode
11 1 = extrapolate over-/under-range for auto mode
0 = clamp over-/under-range for auto mode
12 ... 16 Not used
Quantum Engineering Ranges
Bit
4 5 6 7 8 Range
0 1 0 0 0 +/- 10V
0 1 0 0 1 +/- 5V
0 1 0 1 0 0 ... 10 V
0 1 0 1 1 0 ... 5 V
0 1 1 0 0 1 ... 5 V
31007523 8/2010 803

Quantum Thermocouple
Bit
4 5 6 7 8 Range
0 1 1 0 1 TC degrees
0 1 1 1 0 TC 0.1 degrees
0 1 1 1 1 TC raw units
Quantum Voltmeter
Bit
4 5 6 7 8 Range
1 0 0 0 0 +/- 10V
1 0 0 1 0 +/- 5V
1 0 1 0 0 0 ... 10 V
1 0 1 1 0 0 ... 5 V
1 1 0 0 0 1 ... 5 V
NOTE: Bit 4 in this register is nonstandard use.
804 31007523 8/2010

PCFL-ALARM: Central Alarm Handler
31007523 8/2010
PCFL-ALARM:
Central Alarm Handler
131
Introduction
This chapter describes the subfunction PCFL-Alarm.

Topic Page
Representation 807
31007523 8/2010 805

Short Description
The ALARM function gives you a central block for alarm handling where you can set
high (H), low (L), high high (HH), and low low (LL) limits on a process variable.
ALARM lets you specify
z A choice of normal or deviation operating mode
z Whether to use H/L or both H/L and HH/LL limits
z Whether or not to use deadband (DB) around the limits
806 31007523 8/2010

Representation
Symbol

Reference
function
ALRM Selection of the subfunction ALARM
(top node)
parameter 4x INT, UINT, First in a block of contiguous holding
block WORD registers where the parameters for the
(bottom node) ALARM (can not be changed)
31007523 8/2010 807

Mode of Functioning
The following operating modes are available.
Mode Meaning
Normal Operating Mode ALARM operates directly on the input. Normal is the default
condition
Deviation Operating ALARM operates on the change between the current input and
Mode the last input.
Deadband When enabled, the DB option is incorporated into the HH/H/LL/L
limits. These calculated limits are inclusive of the more extreme
range, e.g. if the input has been in the high range, the output
remains high and does not transition when the input hits the
calculated H limit.
Operations A flag is set when the input or deviation equals or crosses the
corresponding limit. If the DB option is used, the HH, H, LL, L
limits are adjusted internally for crossed-limit checking and
hysteresis.
NOTE: ALARM automatically tracks the last input, even when you specify normal
mode, to facilitate a smooth transition to deviation mode.

The length of the ALARM parameter block is 16 registers.
Register Content
Displayed and first implied Input registers
Fourth and fifth implied HH limit value
Sixth and seventh implied H limit value
Eighth and ninth implied L limit value
10th and 11th implied LL limit value
12th and 13th implied Deadband (DB) around limit
14th and 15th implied Last input
808 31007523 8/2010

Output Status
Bit Function
1 ... 4 Not used
5 1 = DB set to negative number
6 1 = deviation mode chosen with DB option
7 1 = LL crossed (x ≤ LL
8 1 = L crossed (x ≤ L or LL < x ≤ L) with HH/LL option set
9 1 = H crossed (x ≥ H or H ≤ x < HH) with HH/LL option set
10 1 = HH crossed (x ≥ HH)
11 1 = invalid limits specified
Input Status
Bit Function
5 1 = deviation mode
0 = normal mode
6 1 = both H/L and HH/LL limits apply
7 1 = DB enabled
8 1 = retain H/L flag when HH/LL limits crossed
9 ... 16 Not used
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810 31007523 8/2010

PCFL-AOUT: Analog Output
31007523 8/2010
132
Introduction
This chapter describes the subfunction PCFL-AOUT.

Topic Page
Representation 813
31007523 8/2010 811

Short Description
The AOUT function is an interface for calculated signals for output modules. It
converts the signal to a value in the range 0 ... 4 096.
Formula
Formula of the AOUT function:
The meaning of the elements:
Element Meaning
HEU High Engineering Unit
IN Input
LEU Low Engineering Unit
OUT Output
scale Scale
812 31007523 8/2010

Representation
Symbol

Reference
function
AOUT Selection of the subfunction AOUT
(top node)
(bottom node) AOUT (can not be changed)
31007523 8/2010 813


The length of the AOUT parameter block is 9 registers.
Register Content
Displayed and first implied Input in engineering units
Fourth and fifth implied High engineering units
Sixth and seventh implied Low engineering units
Eighth and ninth implied Output
Output Status
Bit Function
1 ... 7 Not used
8 1 = clamped low
9 1 = clamped high
10 not used
11 1 = invalid H/L limits
Input Status
Bit Function
5 ... 16 Not used
814 31007523 8/2010

PCFL-AVER: Average Weighted Inputs Calculate
31007523 8/2010
PCFL-AVER: Average Weighted

Inputs Calculate
133
Introduction
This chapter describes the subfunction PCFL-AVER.

Topic Page
Representation 817
31007523 8/2010 815

Short Description
category Advanced Calculation.
The AVER function calculates the average of up to four weighted inputs.
Formula
Formula of the AVER function:
The meaning of the elements:
Element Meaning
In1 ... In4 Inputs
k Constant
RES Result
w1 ... w4 Weights
816 31007523 8/2010

Representation
Symbol

Reference
function
AVER Selection of the subfunction AVER
(top node)
(bottom node) AVER (can not be changed)
31007523 8/2010 817


The length of the AVER parameter block is 24 registers.
Register Content
Displayed and first implied reserved
Fourth and fifth implied Value of In1
Sixth and seventh implied Value of Inv2
Eighth and ninth implied Value of In3
10th and 11th implied Value of In4
12th and 13th implied Value of k
14th and 15th implied Value of wv1
20th and 21st implied Value of wv4
22nd and 23rd implied Value of result
Output Status
Bit Function
1 ... 9 Not used
10 1 = no inputs activated
11 1 = result negative
0 = result positive
818 31007523 8/2010

Input Status
Bit Function
5 1 = In4 and w4 are used
9 1 = k is active
10 ... 16 Not used
A weight can be used only when its corresponding input is enabled, e.g. the 20th
and 21st implied registers (which contain the value of w4) can be used only when
the 10th and 11th implied registers (which contain In4) are enabled. The I in the
denominator is used only when the constant is enabled.
31007523 8/2010 819

820 31007523 8/2010

PCFL-CALC: Calculated Preset Formula
31007523 8/2010
PCFL-CALC:
Calculated Preset Formula
134
Introduction
This chapter describes the subfunction PCFL-CALC.

Topic Page
Representation 823
31007523 8/2010 821

Short Description
The CALC function calculates a preset formula with up to four inputs, each
characterized in a separate register of the parameter block.
822 31007523 8/2010

Representation
Symbol

Reference
function
CALC Selection of the subfunction CALC
(top node)
(bottom node) CALC (can not be changed)
31007523 8/2010 823


The length of the CALC parameter block is 14 registers.
Register Content
Displayed and first implied Reserved
Fourth and fifth implied Value of input A
Sixth and seventh implied Value of input B
Eighth and ninth implied Value of input C
10th and 11th implied Value of input D
12th and 13th implied Value of the output
Output Status
Bit Function
1...10 Not used
11 1 = bad input code chosen
824 31007523 8/2010

Input Status
Bit Function
5 ... 6 not used
7 ... 10 Formula Code
11 ... 16 Not used
Formula Code
Bit Formula Code

7 8 9 10
0 0 0 1
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
31007523 8/2010 825

826 31007523 8/2010

PCFL-DELAY: Time Delay Queue
31007523 8/2010
135
Introduction
This chapter describes the subfunction PCFL-DELAY.

Topic Page
Representation 829
31007523 8/2010 827

Short Description
The DELAY function can be used to build a series of readings for time-delay
compensation in the logic. Up to 10 sampling instances can be used to delay an
input.
All values are carried along in registers, where register x[0] contains the current
sampled input. The 10th delay period does not need to be stored. When the 10th
instance in the sequence takes place, the value in register x[9] can be moved
directly to the output
A DXDONE message is returned when the calculation is complete. The function can
be reset by toggling the first-scan bit.
828 31007523 8/2010

Representation
Symbol

Reference
function
DELY Selection of the subfunction DELY
(top node)
(bottom node) DELY (can not be changed)
31007523 8/2010 829


The length of the DELAY parameter block is 32 registers.
Register Content
Displayed and first implied Input at time n
Fourth implied Time register
Fifth implied Reserved
Sixth and seventh implied Δt (in ms) since last solve
Eighth and ninth implied Solution interval (in ms)
10th and 11th implied x[0] delay
... ...
30th and 31st implied Output registers
Output Status
Bit Function
1...3 Not used
4 1 = k out of range
5 ... 8 Count of registers left to be initialized
Input Status
Bit Function
5 ... 8 Time Delay ≤ 10
9 ... 11 Echo number of registers left to be initialized
12 ... 16 Not used
830 31007523 8/2010

PCFL-EQN: Formatted Equation Calculator
31007523 8/2010
PCFL-EQN:
Formatted Equation Calculator
136
Introduction
This chapter describes the subfunction PCFL-EQN.

Topic Page
Representation 833
31007523 8/2010 831

Short Description
The EQN function is a formatted equation calculator. You must define the equation
in the parameter block with various codes that specify operators, input selection and
inputs.
EQN is used for equations that have four or fewer variables but do not fit into the
CALC format. It complements the CALC function by letting you input an equation
with floating point and integer inputs as well as operators.
832 31007523 8/2010

Representation
Symbol

Reference
function
EQN Selection of the subfunction EQN
(top node)
15 ... 64 INT, UINT Length of parameter block for subfunction
(bottom node) EQN
31007523 8/2010 833


The length of the EQN parameter block can be as high as 64 registers.
Register Content
Fourth and fifth implied Variable A
Sixth and seventh implied Variable B
Eighth and ninth implied Variable C
10th and 11th implied Variable D
14th implied First formula code
15th implied Second possible formula code
... ...
63rd implied Last possible formula code
Output Status
Bit Function
1 Stack error
2...3 Not used
4 ... 8 Code of last error logged
9 1 = bad operator selection code
10 1 = EQN not fully programmed
11 1 = bad input code chosen
Input Status
Bit Function
5 1 = Degree/radian option for trigonometry
6 ... 8 not used
9 ... 16 Equation size for display in Concept
834 31007523 8/2010

Formula Code
Each formula code in the EQN function defines either an input selection code or an
operator selection code.
Formula Code (Parameter Block)
Bit Function
1 ... 4 Not used
5 ... 8 Definition of input selection
9 ... 11 Not used
12 ... 16 Definition of operator selection
Input Selection
Bit Input Selection

5 6 7 8
0 0 0 0 Use operator selection
0 0 0 1 Float input
0 0 1 1 16-bit integer
1 0 0 0 Variable A
1 0 0 1 Variable B
1 0 1 0 Variable C
1 0 1 1 Variable D
31007523 8/2010 835

Operator Selection
Bit Operator Selection

12 13 14 15 16
0 0 0 0 0 No operation
0 0 0 0 1 Absolute value
0 0 0 1 0 Addition
0 0 0 1 1 Division
0 0 1 0 0 Exponent
0 0 1 1 1 LN (natural logarithm)
0 1 0 0 0 G (logarithm)
0 1 0 0 1 Multiplication
0 1 0 1 0 Negation
0 1 0 1 1 Power
0 1 1 0 0 Square root
0 1 1 0 1 Subtraction
0 1 1 1 0 Sine
0 1 1 1 1 Cosine
1 0 0 0 0 Tangent
1 0 0 0 1 Arcsine
1 0 0 1 0 Arccosine
1 0 0 1 1 Arctangent
836 31007523 8/2010

PCFL-INTEG: Integrate Input at Specified Interval
31007523 8/2010
PCFL-INTEG: Integrate Input at

Specified Interval
137
Introduction
This chapter describes the subfunction PCFL-INTEG.

Topic Page
Representation 839
31007523 8/2010 837

Short Description
The INTEG function is used to integrate over a specified time interval. No protection
against integral wind-up is provided in this function. INTEG is time-dependent, e.g.
if you are integrating at an input value of 1/sec, it matters whether it operates over
one second (in which case the result is 1) or over one minute (in which case the
result is 60).
You can set flags to either initialize or restart the function after an undetermined
down-time, and you can reset the integral sum if you wish. If you set the initialize
flag, you must specify a reset value (zero or the last output in case of power failure),
and calculations will be skipped for one sample.
The function returns a DXDONE message when the operation is complete.
838 31007523 8/2010

Representation
Symbol

Reference
function
INTG Selection of the subfunction INTEG
(top node)
(bottom node) INTEG (can not be changed)
31007523 8/2010 839


The length of the INTEG parameter block is 16 registers.
Register Content
Displayed and first implied Current Input
12th and 13th implied Reset value
14th and 15th implied Result
Output Status
Bit Function
1...8 Not used
Input Status
Bit Function
5 Reset sum
6 ... 16 Not used
840 31007523 8/2010

PCFL-KPID: Comprehensive ISA Non Interacting PID
31007523 8/2010
PCFL-KPID: Comprehensive ISA

Non Interacting PID
138
Introduction
This chapter describes the subfunction PCFL-KPID.

Topic Page
Representation 843
31007523 8/2010 841

Short Description
category Regulatory Control.
The KPID function offers a superset of the functionality of the PID function, with
additional features that include:
z A gain reduction zone
z A separate register for bumpless transfer when the integral term is not used
z A reset mode
z An external set point for cascade control
z Built-in velocity limiters for set point changes and changes to a manual output
z A variable derivative filter constant
z Optional expansion of anti-reset wind-up limits
842 31007523 8/2010

Representation
Symbol

Reference
function
KPID Selection of the subfunction KPID
(top node)
(bottom node) KPID (can not be changed)
31007523 8/2010 843


The length of the KPID parameter block is 64 registers.
Register Content
General Displayed and first implied Live input, x
Parameters
Second implied Output Status, Register 1
Third implied Output Status, Register 2
Fourth implied Reserved
Fifth implied Input Status
Input Sixth and seventh implied Proportional rate, KP
Parameters
Eighth and ninth implied Reset time, TI
10th and 11th implied Derivative action time, TD
12th and 13th implied Delay time constant, TD1
14th and 15th implied Gain reduction zone, GRZ
16th and 17th implied Gain reduction in GRZ, KGRZ
18th and 19th implied Limit rise of manual set point value
20th and 21st implied Limit rise of manual output
22nd and 23rd implied High limit for Y
24th and 25th implied Low limit for Y
26th and 27th implied Expansion for anti-reset wind-up limits
Inputs 28th and 29th implied External set point for cascade
30th and 31st implied Manual set point
32nd and 33rd implied Manual Y
34th and 35th implied Reset for Y
36th and 37th implied Bias
Outputs 38th and 39th implied Bumpless transfer register, BT
40th and 41st implied Calculated control difference (error term), XD
42nd implied Previous operating mode
43rd and 44th implied Dt (in ms) since last solve
45th and 46th implied Previous system deviation, XD_1
47th and 48th implied Previous input, X_1
49th and 50th implied Integral part for Y, YI
51st and 52nd implied Differential part for Y, YD
53rd and 54th implied Set point, SP
844 31007523 8/2010

Register Content
55th and 56th implied Proportional part for Y, YP
57th implied Previous operating status
Timing 58th implied 10 ms clock at time n
Information
59th implied Reserved
60th and 61th implied Solution interval (in ms)
Output 62th and 63th implied Manipulated output variable, Y
Output Status, Register 1
Bit Function
1 Error
2 1 = low limit exceeded
3 1 = high limit exceeded
4 1 = Cascade mode selected
5 1 = Auto mode selected
6 1 = Halt mode selected
7 1 = Manual mode selected
8 1 = Reset mode selected
Output Status, Register 2
Bit Function
1...4 Not used
5 1 = Previous D mode selected
6 1 = Previous I mode selected
7 1 = Previous P mode selected
8 1 = Previous mode selected
9 ... 16 Not used
31007523 8/2010 845

Input Status
Bit Function
5 1 = Reset mode
6 1 = Manual mode
7 1 = Halt mode
8 1 = Cascade mode
9 1 = Solve proportional algorithm
10 1 = Solve integral algorithm
11 1 = Solve derivative algorithm
12 1 = solve derivative algorithm based on x
0 = solve derivative algorithm based on xd
13 1 = anti--reset wind-up on YI only
0 = normal anti--reset wind-up
14 1 = disable bumpless transfer
0 = bumpless transfer
15 1 = Manual Y tracks Y
16 1 = reverse action for loop output
0 = direct action for loop output
846 31007523 8/2010

PCFL-LIMIT: Limiter for the Pv
31007523 8/2010
139
Introduction
This chapter describes the subfunction PCFL-LIMIT.

Topic Page
Representation 849
31007523 8/2010 847

Short Description
The LIMIT function limits the input to a range between a specified high and low
value. If the high or low limit is reached, the function sets an H or L flag and clamps
the output.
LIMIT returns a DXDONE message when the operation is complete.
848 31007523 8/2010

Representation
Symbol

Reference
function
LIMIT Selection of the subfunction LIMIT
(top node)
(bottom node) LIMIT (can not be changed)
31007523 8/2010 849


The length of the LIMIT parameter block is 9 registers.
Register Content
Displayed and first implied Current input
Fourth and fifth implied Low limit
Sixth and seventh implied High Limit
Eighth implied Output register
Output Status
Bit Function
1...8 Not used
9 1 = input < low limit
10 1 = input > high limit
11 1 = invalid high/low limits (e.g., low ≥ high
Input Status
Bit Function
5 ... 16 Not used
850 31007523 8/2010

PCFL-LIMV: Velocity Limiter for Changes in the Pv
31007523 8/2010
PCFL-LIMV: Velocity Limiter for

Changes in the Pv
140
Introduction
This chapter describes the subfunction PCFL-LIMV.

Topic Page
Representation 853
31007523 8/2010 851

Short Description
The LIMV function limits the velocity of change in the input variable between a
specified high and low value. If the high or low limit is reached, the function sets an
H or L flag and clamps the output.
LIMV returns a DXDONE message when the operation is complete.
852 31007523 8/2010

Representation
Symbol

Reference
function
LIMV Selection of the subfunction LIMV
(top node)
please see Parameter Block (Middle
Node), page 854.)
(bottom node) LIMV (can not be changed)
31007523 8/2010 853


The length of the LIMV parameter block is 14 registers.
Register Content
Displayed and first implied Input register
10th and 11th implied Velocity limit / sec
Output Status
Bit Function
1...5 Not used
6 1 = negative velocity limit
7 1 = input < low limit
8 1 = input > high limit
Input Status
Bit Function
5 ... 16 Not used
854 31007523 8/2010

PCFL-LKUP: Look-up Table
31007523 8/2010
141
Introduction
This chapter describes the subfunction PCFL-LKUP.

Topic Page
Representation 857
31007523 8/2010 855

Short Description
The LKUP function establishes a look-up table using a linear algorithm to interpolate
between points. LKUP can handle variable point intervals and variable numbers of
points.
856 31007523 8/2010

Representation
Symbol

Reference
function
LKUP Selection of the subfunction LKUP
(top node)
(For more information, please see
Parameter Block (Middle Node),
page 859.)
(bottom node) LKUP (can not be changed)
31007523 8/2010 857

Mode of Functioning
The LKUP function establishes a look-up table using a linear algorithm to interpolate
between points. LKUP can handle variable point intervals and variable numbers of
points.
If the input (x) is outside the specified range of points, the output (y) is clamped to
the corresponding output y0 or yn. If the specified parameter block length is too
small or if the number of points is out of range, the function does not check the xn
because the information from that pointer is invalid.
Points to be interpolated are determined by a binary search algorithm starting near
the center of x data. The search is valid for x1 < x < xn. The variable x may occur
multiple times with the same value, the value chosen from the look-up table is the
first instance found.
For example, if the table is:
x y
10.0 1.0
20.0 2.0
30.0 3.0
30.0 3.5
40.0 4.0
then an input of 30.0 finds the first instance of 30.0 and assigns 3.0 as the output.
An input of 31.0 would assign the value 3.55 as the output.
No sorting is done on the contents of the lookup table. Independent variable table
values should be entered in ascending order to prevent unreachable gaps in the
table.
The function returns a DXDONE message when the operation is complete.
858 31007523 8/2010


The length of the LKUP parameter block is 39 registers.
Register Content
Displayed and first implied Input
Fourth implied Number of point pairs
Fifth and sixth implied Point x1
Seventh and eighth implied Point y1
Ninth and tenth implied Point x2
11th and 12th implied Point y2
... ...
33rd and 34th implied Point x8
35th and 36th implied Point y8
Output Status
Bit Function
1 ... 9 Not used
10 1 = input clamped, i.e. out of table’s range
11 ! = invalid number of points
Input Status
Bit Function
5 ... 16 Not used
31007523 8/2010 859

860 31007523 8/2010

PCFL-LLAG: First-order Lead/Lag Filter
31007523 8/2010
PCFL-LLAG:
First-order Lead/Lag Filter
142
Introduction
This chapter describes the subfunction PCFL-LLAG.

Topic Page
Representation 863
31007523 8/2010 861

Short Description
The LLAG function provides dynamic compensation for a known disturbance. It
usually appears in a feed-forward algorithm or as a dynamic filter. LLAG passes the
input through a filter comprising a lead term (a numerator) and a lag term (a
denominator) in the frequency domain, then multiplies it by a gain. Lead, lag, gain,
and solution interval must be user-specified.
For best results, use lead and lag terms that are ≥ 4 *Δt. This will ensure sufficient
granularity in the output response.
LLAG returns a DXDONE message when the operation completes
862 31007523 8/2010

Representation
Symbol

Reference
function
LLAG Selection of the subfunction LLAG
(top node)
page 864.)
(bottom node) LLAG (can not be changed)
31007523 8/2010 863


The length of the LLAG parameter block is 20 registers.
Register Content
12th and 13th implied Lead term
14th and 15th implied Lag term
16th and 17th implied Filter gain
Output Status
Bit Function
1...8 Not used
Input Status
Bit Function
5 ... 16 Not used
864 31007523 8/2010

PCFL-MODE: Put Input in Auto or Manual Mode
31007523 8/2010
PCFL-MODE:
Put Input in Auto or Manual Mode
143
Introduction
This chapter describes the subfunction PCFL-MODE.

Topic Page
Representation 867
31007523 8/2010 865

Short Description
The MODE function sets up a manual or automatic station for enabling and disabling
data transfers to the next block. The function acts like a BLKM instruction, moving a
value to the output register.
In auto mode, the input is copied to the output. In manual mode, the output is
overwritten by a user entry.
MODE returns a DXDONE message when the operation completes.
866 31007523 8/2010

Representation
Symbol

Reference
function
MODE Selection of the subfunction MODE
(top node)
page 868.)
(bottom node) MODE (can not be changed)
31007523 8/2010 867


The length of the MODE parameter block is 8 registers.
Register Content
Displayed and first implied Input
Fourth and fifth implied Manual input
Sixth and seventh implied Output register
Output Status
Bit Function
1 ... 10 Not used
11 Echo mode:
1 = manual mode
0 = auto mode
Input Status
Bit Function
5 1 = manual mode
0 = auto mode
6 ... 16 Not used
868 31007523 8/2010

PCFL-ONOFF: ON/OFF Values for Deadband
31007523 8/2010
PCFL-ONOFF:
ON/OFF Values for Deadband
144
Introduction
This chapter describes the subfunction PCFL-ONOFF.

Topic Page
Representation 871
31007523 8/2010 869

Short Description
The ONOFF function is used to control the output signal between fully ON and fully
OFF conditions so that a user can manually force the output ON or OFF.
You can control the output via either a direct or reverse configuration:
Configuration IF Input... Then Output...

Direct < (SP - DB) ON
> (SP + DB) OFF
Revers > (SP + DB) ON
< (SP - DB) OFF
Manual Override
Two bits in the input status register (the third implied register in the parameter block)
are used for manual override. When bit 6 is set to 1, manual mode is enforced. In
manual mode, a 0 in bit 7 forces the output OFF, and a 1 in bit 7 forces the output
ON. The state of bit 7 has meaning only in manual mode.
870 31007523 8/2010

Representation
Symbol

Reference
function
ONOFF Selection of the subfunction ONOFF
(top node)
page 872.)
(bottom node) ONOFF (can not be changed)
31007523 8/2010 871


The length of the ONOFF parameter block is 14 registers.
Register Content
Fourth and fifth implied Set point, SP
Sixth and seventh implied Deadband (DB) around SP
Eighth and ninth implied Fully ON (maximum output)
10th and 11th implied Fully OFF (minimum output)
12th and 13th implied Output, ON or OFF
Output Status
Bit Function
1 ... 8 Not used
9 1 = DB set to negative number
10 Echo mode:
1 = manual override
0 = auto mode
11 1 = output set to ON
0 = output set to OFF
Input Status
Bit Function
5 1 = reverse configuration
0 = direct configuration
6 1 = manual override
0 = auto mode
7 1 = force output ON in manual mode
0 = force output OFF in manual mode
8 ... 16 Not used
872 31007523 8/2010

PCFL-PI: ISA Non Interacting PI
31007523 8/2010
145
Introduction
This chapter describes the subfunction PCFL-PI.

Topic Page
Representation 875
31007523 8/2010 873

Short Description
The PI function performs a simple proportional-integral operations using floating
point math. It features halt / manual / auto operation modes. It is similar to the PID
and KPID functions but does not contain as many options. It is available for higher-
speed loops or inner loops in cascade strategies.
874 31007523 8/2010

Representation
Symbol

Reference
function
PI Selection of the subfunction PI
(top node)
page 876.)
(bottom node) PI (can not be changed)
31007523 8/2010 875


The length of the PI parameter block is 36 registers.
Register Content
Parameters
Second implied Output Status
Third implied Error Word
Inputs Sixth and seventh implied Set point, SP
Eighth and ninth implied Manual output
10th and 11th implied Calculated control difference (error), XD
Outputs 12th implied Previous operating mode
13th and 14th implied Dt (in ms) since last solve
17th and 18th implied Integral part of output Y
21st implied Previous operating status
Timing 22nd implied 10 ms clock at time n
Information
23rd implied Reserved
24th and 25th implied Solution interval (in ms)
Input 26th and 27th implied Proportional rate, KP
Parameters
28th and 29th implied Reset time, TI
30th and 31st implied High limit on output Y
32nd and 33rd implied Low limit on output Y
Output 34th and 35th implied Manipulated variable output, Y
876 31007523 8/2010

Output Status
Bit Function
1 Error
4 ... 8 Not used
Error Word
Bit Function
1...11 Not used
12 ... 16 Error Description
Error Description
Bit Meaning
12 13 14 15 16
1 0 1 1 0 Negative integral time constant
1 0 1 0 1 High/low limit error (low ≥ high)
Input Status
Bit Function
5 Not used
6 1 = Manual mode
7 1 = Halt mode
8 ... 15 Not used
31007523 8/2010 877

878 31007523 8/2010

PCFL-PID: PID Algorithms
31007523 8/2010
146
Introduction
This chapter describes the subfunction PCFL-PID.

Topic Page
Representation 881
31007523 8/2010 879

Short Description
The PID function performs ISA non-interacting proportional-integral-derivative (PID)
operations using floating point math. Because it uses FP math (unlike PID2), round-
off errors are negligible.
In the part "General Information" you will find A PID Example, page 49.
880 31007523 8/2010

Representation
Symbol

Reference
function
PID Selection of the subfunction PID
(top node)
page 882.)
(bottom node) PID (can not be changed)
31007523 8/2010 881


The length of the KPID parameter block is 44 registers.
Register Content
Parameters
Second implied Output Status
Third implied Error Word
Inputs Sixth and seventh implied Set point, SP
Eighth and ninth implied Manual output
10th and 11th implied Summing junction, Bias
Outputs 12th and 13th implied Error, XD
14th implied Previous operating mode
15th and 16th implied Elapsed time (in ms) since last solve
21st and 22nd implied Integral part of output Y, YI
23rd and 24th implied Differential part of output Y, YD
25th and 26th implied Proportional part of output Y, YP
27th implied Previous operating status
Timing 28th implied Current time
Information
29th implied Reserved
Inputs 30th and 31st implied Solution interval (in ms)
34th and 35th implied Reset time, TI
36th and 37th implied Derivative action time, TD
38th and 39th implied High limit on output Y
40th and 41st implied Low limit on output Y
42nd and 43rd implied Manipulated control output, Y
882 31007523 8/2010

Output Status
Bit Function
1 Error
4 ... 8 Not used
Error Word
Bit Function
1...11 Not used
12 ... 16 Error Description
Error Description
Bit Meaning
12 13 14 15 16
1 0 1 1 1 Negative derivative time constant
1 0 1 1 0 Negative integral time constant
1 0 1 0 1 High/low limit error (low ≥ high)
Input Status
Bit Function
5 Not used
6 1 = Manual mode
7 1 = Halt mode
8 Not used
9 1 = Solve proportional algorithm
10 1 = Solve integral algorithm
11 1 = Solve derivative algorithm
12 1 = solve derivative algorithm based on x
0 = solve derivative algorithm based on xd
13... 15 Not used
31007523 8/2010 883

884 31007523 8/2010

PCFL-RAMP: Ramp to Set Point at a Constant Rate
31007523 8/2010
PCFL-RAMP: Ramp to Set Point at

a Constant Rate
147
Introduction
This chapter describes the subfunction PCFL-RAMP.

Topic Page
Representation 887
31007523 8/2010 885

Short Description
The RAMP function allows you to ramp up linearly to a target set point at a specified
approach rate.
You need to specify:
z The target set point, in the same units as the contents of the input register are
specified
z The sampling rate
z A positive rate toward the target set point, negative rates are illegal
The direction of the ramp depends on the relationship between the target set point
and the input, i.e. if x < SP, the ramp is up; if x > SP, the ramp is down.
You may use a flag to initialize after an undetermined down-time. The function will
store a new sample, then wait for one cycle to collect the second sample.
Calculations will be skipped for one cycle and the output will be left as is, after which
the ramp will resume.
RAMP terminates when the entire ramping operation is complete (over multiple
scans) and returns a DXDONE message.
Starting the Ramp

The following steps need to be done when starting the ramp (up/down) and each
and every time you need to start or restart the ramp.
Step Action
1 Set bit 1 of the standard input bits to "1" (third implied register of the parameter
block).
2 Retoggle the top input (enable input) to the instruction. Ramp will now start to
ramp up/down from the initial value previously configured up/down to the
previously configured setpoint. Monitor the 12th implied register of the
parameter block for floating point value of the ramp value in progress.
886 31007523 8/2010

Representation
Symbol

Reference
function
RAMP Selection of the subfunction RAMP
(top node)
page 888.)
(bottom node) RAMP (can not be changed)
31007523 8/2010 887


The length of the RAMP parameter block is 14 registers.
Register Content
Displayed and first implied Set point (Input)
10th and 11th implied Rate of change (per second) toward set point
Output Status
Bit Function
1 ... 4 Not used
5 1 = ramp rate is negative
6 1 = ramp complete
0 = ramp in progress
7 1 = ramping down
8 1 = ramping up
Input Status
Bit Function
5 ... 16 Not used
Top Output (Operation Succesfull)

The top output of the PCFL subfunction RAMP goes active at each successive
discrete ramp step up/down. It happens so fast that it appears to be solidly on. This
top output should NOT be used as "Ramp done bit".
Bit 6 of the output status (second impied register of the parameter block) should be
monitored as "Ramp done bit".
888 31007523 8/2010

PCFL-RATE: Derivative Rate Calculation over a Specified Time
31007523 8/2010
PCFL-RATE: Derivative Rate

Calculation over a Specified Time
148
Introduction
This chapter describes the subfunction PCFL-RATE.

Topic Page
Representation 891
31007523 8/2010 889

Short Description
The RATE function calculates the rate of change over the last two input values. If
you set an initialization flag, the function records a sample and sets the appropriate
flags.
If a divide-by-zero operation is attempted, the function returns a DXERROR
message.
It returns a DXDONE message when the operation completes successfully.
890 31007523 8/2010

Representation
Symbol

Reference
function
RATE Selection of the subfunction RATE
(top node)
page 892.)
(bottom node) RATE (can not be changed)
31007523 8/2010 891


The length of the RATE parameter block is 14 registers.
Register Content
Displayed and first implied Current input
Output Status
Bit Function
1 ... 8 Not used
Input Status
Bit Function
5 ... 16 Not used
892 31007523 8/2010

PCFL-RATIO: Four Station Ratio Controller
31007523 8/2010
PCFL-RATIO:
Four Station Ratio Controller
149
Introduction
This chapter describes the subfunction PCFL-RATIO.

Topic Page
Representation 895
31007523 8/2010 893

Short Description
The RATIO function provides a four-station ratio controller. Ratio control can be
used in applications where one or more raw ingredients are dependent on a primary
ingredient. The primary ingredient is measured, and the measurement is converted
to engineering units via an AIN function. The converted value is used to set the
target for the other ratioed inputs.
Outputs from the ratio controller can provide set points for other controllers. They
can also be used in an open loop structure for applications where feedback is not
required.
894 31007523 8/2010

Representation
Symbol

Reference
function
RATIO Selection of the subfunction RATIO
(top node)
For more information. please see
page 896.)
(bottom node) RATIO (can not be changed)
31007523 8/2010 895


The length of the RATIO parameter block is 20 registers.
Register Content
Displayed and first implied Live input
Fourth and fifth implied Ratio for input 1
Sixth and seventh implied Ratio for input 2
Eighth and ninth implied Ratio for input 3
10th and 11th implied Ratio for input 4
12th and 13th implied Output for input 1
Output Status
Bit Function
1 ... 9 Not used
10 1 = parameter(s) out of range
11 1 = no inputs activated
Input Status
Bit Function
5 1= input 4 active
6 1= input 3 active
7 1= input 2 active
8 1= input 1 active
9 ... 16 Not used
896 31007523 8/2010

PCFL-RMPLN: Logarithmic Ramp to Set Point
31007523 8/2010
PCFL-RMPLN:
Logarithmic Ramp to Set Point
150
Introduction
This chapter describes the subfunction PCFL-RMPLN.

Topic Page
Representation 899
31007523 8/2010 897

Short Description
The RMPLN function allows you to ramp up logarithmically to a target set point at a
specified approach rate. At each successive call, it calculates the output until it is
within a specified deadband (DB). DB is necessary because the incremental
distance the ramp crosses decreases with each solve.
You need to specify:
z The target set point, in the same units as the contents of the input register are
specified
z The sampling rate
z The time constant used for the logarithmic ramp, which is the time it takes to
reach 63.2% of the new set point
For best results, use a t that is ≥4 *Δt. This will ensure sufficient granularity in the
output response.
You may use a flag to initialize after an undetermined down-time. The function will
store a new sample, then wait for one cycle to collect the second sample.
Calculations will be skipped for one cycle and the output will be left as is, after which
the ramp will resume.
RMPLN terminates when the input reaches the target set point + the specified DB
and returns a DXDONE message.
898 31007523 8/2010

Representation
Symbol

Reference
function
RMPLN Selection of the subfunction RMPLN
(top node)
For more information, please see
page 900.)
(bottom node) RMPLN (can not be changed)
31007523 8/2010 899


The length of the RMPLN parameter block is 16 registers.
Register Content
Displayed and first implied Set point (Input)
10th and 11th implied Time constant, τ, (per second) of exponential ramp toward
the target set point
12th and 13th implied DB (in engineering units)
Output Status
Bit Function
1 ... 4 Not used
5 1 = DB or τ set to negative units
6 1 = ramp complete
0 = ramp in progress
7 1 = ramping down
8 1 = ramping up
Input Status
Bit Function
5 ... 16 Not used
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PCFL-SEL: Input Selection
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151
Introduction
This chapter describes the subfunction PCFL-SEL.

Topic Page
Representation 903
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Short Description
The SEL function compares up to four inputs and makes a selection based upon
either the highest, lowest, or average value. You choose the inputs to be compared
and the comparison criterion. The output is a copy of the selected input.
SEL returns a DXDONE message when the operation is complete.
902 31007523 8/2010

Representation
Symbol

Reference
function
SEL Selection of the subfunction SEL
(top node)
page 904.)
(bottom node) SEL (can not be changed)
31007523 8/2010 903


The length of the SEL parameter block is 14 registers.
Register Content
Fourth and fifth implied Input 1
Sixth and seventh implied Input 2
Eighth and ninth implied Input 3
10th and 11th implied Input 4
Output Status
Bit Function
1 ... 9 Not used
10 Invalid selection modes
11 No inputs selected
Input Status
Bit Function
5 1 = enable input 1
0 = disable input 1
0 = dyeable input 2
0 = dyeable input 3
0 = dyeable input 4
9 ... 10 Selection mode
11 ... 16 Not used
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Selection mode
Bit Meaning
9 10
0 0 Select average
0 1 Select high
1 0 Select low
1 1 reserved / invalid
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906 31007523 8/2010

PCFL-TOTAL: Totalizer for Metering Flow
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PCFL-TOTAL:
Totalizer for Metering Flow
152
Introduction
This chapter describes the subfunction PCFL-TOTAL.

Topic Page
Representation 909
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Short Description
The TOTAL function provides a material totalizer for batch processing reagents. The
input signal contains the units of weight or volume per unit of time. The totalizer
integrates the input over time.
The algorithm reports three outputs:
z The integration sum
z The remainder left to meter in
z The valve output (in engineering units).
908 31007523 8/2010

Representation
Symbol

Reference
function
TOTAL Selection of the subfunction TOTAL
(top node)
page 910.)
(bottom node) TOTAL (can not be changed)
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Mode of Functioning
The function uses up to three different set points:
z A trickle flow set point
z A target set point
z An auxiliary trickle flow set point
The target set point is for the full amount to be metered in. Here the output will be
turned OFF.
The trickle flow set point is the cut-off point when the output should be decreased
from full flow to a percentage of full flow so that the target set point is reached with
better granularity.
The auxiliary trickle flow set point is optional. It is used to gain another level of
granularity. If this set point is enabled, the output is reduced further to 10% of the
trickle output.
The totalizer works from zero as a base point. The set point must be a positive value
In normal operation, the valve output is set to 100% flow when the integrated value
is below the trickle flow set point. When the sum crosses the trickle flow set point,
the valve flow becomes a programmable percentage of full flow. When the sum
reaches the desired target set point, the valve output is set to 0% flow.
Set points can be relative or absolute. With a relative set point, the deviation
between the last summation and the set point is used. Otherwise, the summation is
used in absolute comparison to the set point.
There is a halt option to stop the system from integrating.
When the operation has finished, the output summation is retained for future use.
You have the option of clearing this sum. In some applications, it is important to save
the sum, e.g. if the meters or load cells cannot handle the full batch in one charge
and measurements are split up, if there are several tanks to fill for a batch and you
want to keep track of batch and production sums.

The length of the TOTAL parameter block is 28 registers.
Register Content
Displayed and first implied Live input
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Register Content
10th and 11th implied Last input, X_1
12th and 13th implied Reset value
14th and 15th implied Set point, target
16th and 17th implied Set point, trickle flow
18th and 19th implied % of full flow for trickle flow set point
20th and 21st implied Full flow
22nd and 23rd implied Remaining amount to SP
24th and 25th implied Resulting sum
26th and 27th implied Output for final control element
Output Status
Bit Function
1 ... 2 Not used
3 ... 4 0 0 = OFF
0 1 = trickle flow
1 0 = full flow
5 1 = operation done
6 1 = totalizer running
7 1 = overshoot past set point by more than 5%
8 1 = parameter(s) out of range
Input Status
Bit Function
5 1 = reset sum
6 1 = halt integration
7 1 = deviation set point
0 = absolute set point
8 1 = use auxiliary trickle flow set point
9 ... 16 Not used
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912 31007523 8/2010

PEER: PEER Transaction
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153
Introduction
This chapter describes the instruction PEER.

Topic Page
Representation 915
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Short Description
The S975 Modbus II Interface option modules use two loadable function blocks:
MBUS and PEER. The PEER instruction can initiate identical message transactions
with as many as 16 devices on Modbus II at one time. In a PEER transaction, you
may only write register data.
914 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None Enable MBUS transaction
Middle input 0x, 1x None Repeat transaction in same scan
control block 4x INT, UINT, First of 19 contiguous registers in the
(top node) WORD PEER control block
(For more information, please see Control
Block (Top Node), page 916.)
data block 4x INT, UINT First register in a data block to be
(middle node) transmitted by the PEER function
length INT, UINT Length, i.e. the number of holding
(bottom node) registers, of the data block; range:
1 ... 249.
Top output 0x None Transaction complete
Middle output 0x None Transaction in progress or new transaction
starting
Bottom output 0x None Error detected in transaction
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The 4x register entered in the top node is the first of 19 contiguous registers in the
PEER control block.
Register Function
Displayed Indicates the status of the transactions at each device, the
leftmost bit being the status of device #1 and the rightmost
bit the status of device #16: 0 = OK, 1 = transaction error
First implied Defines the reference to the first 4x register to be written to
in the receiving device; a 0 in this field is an invalid value and
will produce an error (the bottom output will go ON)
Second implied Time allowed for a transaction to be completed before an
error is declared; expressed as a multiple of 10 ms, e.g. 100
indicates 1,000 ms; the default timeout is 250 ms
Third implied The Modbus port 3 address of the first of the receiving
devices; address range: 1 ... 255 (0 = no transaction
requested)
Fourth implied The Modbus port 3 address of the second of the receiving
devices; address range: 1 ... 255 (0 = no transaction
requested)
... ...
18th implied The Modbus port 3 address of the 16th of the receiving
devices (address range: 1 ... 255)
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PID2: Proportional Integral Derivative
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PID2:
Proportional Integral Derivative
154
Introduction
This chapter describes the instruction PID2.

Topic Page
Representation 919
Detailed Description 920
Run Time Errors 927
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Short Description
The PID2 instruction implements an algorithm that performs proportional-integral-
derivative operations. The algorithm tunes the closed loop operation in a manner
similar to traditional pneumatic and analog electronic loop controllers. It uses a rate
gain limiting (RGL) filter on the PV as it is used for the derivative term only, thereby
filtering out higher-frequency PV noise sources (random and process generated).
Formula
Proportional Control
Proportional-Integral Control
Proportional-Integral-Derivative Control
918 31007523 8/2010

Representation
Symbol

Reference Type
Top input 0x, 1x None 0 = Manual mode
1 = Auto mode
Middle input 0x, 1x None 0 = Integral preload OFF
1 = Integral preload ON
Bottom input 0x, 1x None 0 = Output increases as E increases
1 = Output decreases as E decreases
source 4x INT, First of 21 contiguous holding registers in a source block
(top node) UINT (For more information, please see Source Block (Top Node), page 923.)
destination 4x INT, First of nine contiguous holding registers used for PID2 calculation. Do not
(middle node) UINT load anything in these registers!
For more information, please see Destination (MIddle Node), page 925.)
solution interval INT, Contains a number ranging from 1 ... 255, indicating how often the function
(bottom node) UINT should be performed.
Top output 0x None 1 = Invalid user parameter or Loop ACTIVE but not being solved
Middle output 0x None 1 = PV ≥ high alarm limit
Bottom output 0x None 1 = PV ≤ low alarm limit
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Detailed Description
Block Diagram
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The elements in the block diagram have the following meaning:
Element Meaning
E Error, expressed in raw analog units
SP Set point, in the range 0 ... 4095
PV Process variable, in the range 0 ... 4095
x Filtered PV
K2 Integral mode gain constant, expressed in 0.01 min-1
K3 Derivative mode gain constant, expressed in hundredths of a minute
RGL Rate gain limiting filter constant, in the range 2 ... 30
Ts Solution time, expressed in hundredths of a second
PB Proportional band, in the range 5 ... 500%
bias Loop output bias factor, in the range 0 ... 4095
M Loop output
GE Gross error, the proportional-derivative contribution to the loop output
Z Derivative mode contribution to GE
Qn Unbiased loop output
F Feedback value, in the range 0 ... 4095
I Integral mode contribution to the loop output
Ilow Anti-reset-windup low SP, in the range 0 ... 4095
Ihigh Anti-reset-windup high SP, in the range 0 ... 4095
K1 100/PB
NOTE: The integral mode contribution calculation actually integrates the difference
of the output and the integral sum, this is effectively the same as integrating the
error.
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Proportional Control
With proportional-only control (P), you can calculate the manipulated variable by
multiplying error by a proportional constant, K1, then adding a bias. See Formula,
page 918.
However, process conditions in most applications are changed by other system
variables so that the bias does not remain constant; the result is offset error, where
PV is constantly offset from the SP. This condition limits the capability of
proportional-only control.
NOTE: The value in the integral term (in registers 4y + 3, 4y + 4, and 4y + 5) is
always used, even when the integral mode is not enabled. Using this value is
necessary to preserve bumpless transfer between modes. If you wish to disable
bumpless transfer, these three registers must be cleared.
In manual mode setpoint changes will not take effect unless the above three
registers are cleared and the mode is switched back to automatic. The transfer will
not be bumpless.
Proportional-Integral Control
To eliminate this offset error without forcing you to manually change the bias, an
integral function can be added to the control equation. See Formula, page 918.
Proportional-integral control (PI) eliminates offset by integrating E as a function of
time. K1 is the integral constant expressed as rep/min. As long as E ≠ 0, the
integrator increases (or decreases) its value, adjusting Mv. This continues until the
offset error is eliminated.
Proportional-Integral-Derivative Control
You may want to add derivative functionality to the control equation to minimize the
effects of frequent load changes or to override the integral function in order to get to
the SP condition more quickly. See Formula, page 918.
Proportional-integral-derivative (PID) control can be used to save energy in the
process or as a safety valve in the event of a sudden, unexpected change in process
flow. K3 is the derivative time constant expressed as min. DPV is the change in the
process variable over a time period of Δt.
Example
An example to PID2 level control you will find in PID2 Level Control Example.
922 31007523 8/2010

Source Block (Top Node)

The 4x register entered in the top node is the first of 21 contiguous holding registers
in a source block. The contents of the fifth ... eighth implied registers determine
whether the operation will be P, PI, or PID:
Operation Fifth Implied Sixth Implied Seventh Implied Eighth Implied

P ON ON
PI ON ON
PID ON ON ON
The source block comprises the following register assignments:

Displayed Scaled PV Loaded by the block each time it is scanned; a linear scaling
is done on register 4x + 13 using the high and low ranges
from registers 4x + 11 and 4x + 12:
Scaled PV = (4x13 / 4095) * (4x11 - 4x12) + 4x12
First implied SP You must specify the set point in engineering units; the value
must be < value in the 11th implied register and > value in
the 12th implied register
Second Mv Loaded by the block every time the loop is solved; it is
implied clamped to a range of 0 ... 4095, making the output
compatible with an analog output module; the manipulated
variable register may be used for further CPU calculations
such as cascaded loops
Third implied High Alarm Load a value in this register to specify a high alarm for PV (at
Limit or above SP); enter the value in engineering units within the
range specified in the 11th and 12th implied registers
Fourth implied Low Alarm Load a value in this register to specify a low alarm for PV (at
Limit or below SP); enter the value in engineering units within the
range specified in the 11th and 12th implied registers
Fifth implied Proportional Load this register with the desired proportional constant in
Band the range 5 ... 500; the smaller the number, the larger the
proportional contribution; a valid number is required in this
register for PID2 to operate
Sixth implied Reset Time Load this register to add integral action to the calculation;
Constant enter a value between 0000 ... 9999 to represent a range of
00.00 ... 99.99 repeats/min; the larger the number, the larger
the integral contribution; a value > 9999 stops the PID2
calculation
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Seventh Rate Time Load this register to add derivative action to the calculation;
implied Constant enter a value between 0000 ... 9999 to represent a range of
00.00 ... 99.99 min; the larger the number, the larger the
derivative contribution; a value > 9999 stops the PID2
calculation
Eighth implied Bias Load this register to add a bias to the output; the value must
be between 000 .... 4095, and added directly to Mv, whether
the integral term is enabled or not
Ninth implied High Integral Load this register with the upper limit of the output value
Windup Limit (between 0 ... 4095) where the anti-reset windup takes
effect; the updating of the integral sum is stopped if it goes
above this value (this is normally 4095)
10th implied Low Integral Load this register with the lower limit of the output value
Windup Limit (between 0 ... 4095) where the anti-reset windup takes effect
(this is normally 0)
11th implied High Load this register with the highest value for which the
Engineering measurement device is spanned, e.g. if a resistance
Range temperature device ranges from 0 ... 500 degrees C, the high
engineering range value is 500; the range must be given as
a positive integer between 0001 ... 9999, corresponding to
the raw analog input 4095
12th implied Low Load this register with the lowest value for which the
Engineering measurement device is spanned; the range must be given as
Range a positive integer between 0 ... 9998, and it must be less than
the value in the 11th implied register; it corresponds to the
raw analog input 0
13th implied Raw Analog The logic program loads this register with PV; the
Measurement measurement must be scaled and linear in the range 0 ...
4095
14th implied Pointer to The value you load in this register points to the register that
Loop Counter counts the number of loops solved in each scan; the entry is
Register determined by discarding the most significant digit in the
register where the controller will count the loops
solved/scan, e.g., if the PLC does the count in register
41236, load 1236 into the 14th implied register; the same
value must be loaded into the 14th implied register in every
PID2 block in the logic program
15th implied Maximum Solved In a Scan: If the 14th implied register contains a non-
Number of zero value, you may load a value in this register to limit the
Loops number of loops to be solved in one scan
16th implied Pointer To The value you load in this register points to the holding
Reset register that contains the value of feedback (F); drop the 4
Feedback from the feedback register and enter the remaining four
Input: digits in this register; integration calculations depend on the
F value being should F vary from 0 ... 4095
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17th implied Output Clamp The value entered in this register determines the upper limit
- High of Mv (this is normally 4095)
18th implied Output Clamp The value entered in this register determines the lower limit
- Low of Mv (this is normally 0)
19th implied Rate Gain The value entered in this register determines the effective
Limit (RGL) degree of derivative filtering; the range is from 2 ... 30; the
Constant smaller the value, the more filtering takes place
20th implied Pointer to The value entered in this register points to the holding
Integral register containing the track input (T) value; drop the 4 from
Preload the tracking register and enter the remaining four digits in
this register; the value in the T register is connected to the
input of the integral lag whenever the auto bit and integral
preload bit are both true
Destination (MIddle Node)

The 4y register entered in the middle node is the first of nine contiguous holding
register used for PID2 calculations. You do not need to load anything into these
registers:

Displayed Loop Status Register Twelve of the 16 bits in this register are used to
define loop status.
First implied Error (E) Status Bits This register displays PID2 error codes.
Second Loop Timer Register This register stores the real-time clock reading on
implied the system clock each time the loop is solved: the
difference between the current clock value and the
value stored in the register is the elapsed time; if
elapsed time ≥ solution interval (10 times the value
given in the bottom node of the PID2 block), then
the loop should be solved in this scan
Third implied For Internal Use Integral (integer portion)
Fourth implied For Internal Use Integral-fraction 1 (1/3 000)
Fifth implied For Internal Use Integral-fraction 2 (1/600 000)
Sixth implied Pv x 8 (Filtered) This register stores the result of the filtered analog
input (from register 4x14) multiplied by 8; this value
is useful in derivative control operations
Seventh Absolute Value of E This register, which is updated after each loop
implied solution, contains the absolute value of (SP - PV);
bit 8 in register 4y + 1 indicates the sign of E
Eighth implied For Internal Use Current solution interval
31007523 8/2010 925

Loop Status Register
Bit Function
1 Top output status (Node lockout or parameter error
2 Middle output status (High alarm)
3 Bottom output status (Low alarm)
4 Loop in AUTO mode and time since last solution ≥ solution interval
5 Wind-down mod (for REV B or higher)
6 Loop in AUTO mode but not being solved
7 4x14 register referenced by 4x15 is valid
8 Sign of E in 4y + 7:
z 0 = + (plus)
z 1 = - (minus)
9 Rev B or higher
10 Integral windup limit never set
11 Integral windup saturated
12 Negative values in the equation
13 Bottom input status (direct / reverse acting)
14 Middle input status (tracking mode)
z 1 = tracking
z 0 = no tracking
15 Top input status (MAN / AUTO)

16 Bit 16 is set after initial startup or installation of the loop. If you clear the bit, the
following actions take place in one scan:
z The loop status register 4y is reset
z The current value in the real-time clock is stored in the first implied register
(4y+1)
z Values in the third ... fifth registers (4y+2,3) are cleared
z The value in the13th implied register (4x+13) x 8 is stored in the sixth implied
register (4y+6)
z The seventh and eighth implied registers (4y+7,8) are cleared
Solution Interval (Bottom Node)

The bottom node indicates that this is a PID2 function and contains a number
ranging from 1 ... 255, indicating how often the function should be performed. The
number represents a time value in tenths of a second, or example, the number 17
indicates that the PID function should be performed every 1.7 s.
926 31007523 8/2010

Run Time Errors
Error Status Bit

The first implied register of the destination contains the error status bits:
Code Explanation Check these Registers in the

0000 No errors, all validations OK None
0001 Scaled SP above 9999 First implied
0002 High alarm above 9999 Third implied
0003 Low alarm above 9999 Fourth implied
0004 Proportional band below 5 Fifth implied
0005 Proportional band above 500 Fifth implied
0006 Reset above 99.99 r/min Sixth implied
0007 Rate above 99.99 min Seventh implied
0008 Bias above 4095 Eighth implied
0009 High integral limit above 4095 Ninth implied
0010 Low integral limit above 4095 10th implied
0011 High engineering unit (E.U.) scale above 9999 11th implied
0012 Low E.U. scale above 9999 12th implied
0013 High E.U. below low E.U. 11th and 12th implied
0014 Scaled SP above high E.U. First and 11th implied
0015 .Scaled SP below low E.U. First and 12th implied
0016 Maximum loops/scan > 9999 15th implied
Note: Activated by maximum loop feature, i.e.
only if 4x15 is not zero.
0017 Reset feedback pointer out of range 16th implied
0018 High output clamp above 4095 17th implied
0019 Low output clamp above 4095 18th implied
0020 Low output clamp above high output clamp 17th and 18th implied
0021 RGL below 2 19th implied
0022 RGL above 30 19th implied
0023 Track F pointer out of range 20th implied with middle input
Note: Activated only if the track feature is ON, ON
i.e. the middle input of the PID2 block is
receiving power while in AUTO mode.
31007523 8/2010 927

Code Explanation Check these Registers in the

0024 Track F pointer is zero 20th implied with middle input
Note: Activated only if the track feature is ON, ON
i.e. the middle input of the PID2 block is
receiving power while in AUTO mode.
0025 Node locked out (short of scan time) None
Note: If lockout occurs often and the
parameters are all valid, increase the
maximum number of loops/scan. Lockout may
also occur if the counting registers in use are
not cleared as required.
0026 Loop counter pointer is zero 14th and 15th implied
0027 Loop counter pointer out of range 14th and 15th implied
928 31007523 8/2010

Instruction Descriptions (R to Z)
31007523 8/2010
VI
Introduction
In this part instruction descriptions are arranged alphabetically from R to Z.

155 R --> T: Register to Table 931
156 RBIT: Reset Bit 935
157 READ: Read 939
158 RET: Return from a Subroutine 945
159 RTTI - Register to Input Table 949
160 RTTO - Register to Output Table 953
161 RTU - Remote Terminal Unit 957
162 SAVE: Save Flash 963
163 SBIT: Set Bit 967
164 SCIF: Sequential Control Interfaces 971
165 SENS: Sense 975
166 Shorts 979
167 SKP - Skipping Networks 983
168 SRCH: Search 987
169 STAT: Status 993
170 SU16: Subtract 16 Bit 1021
171 SUB: Subtraction 1025
172 SWAP - VME Bit Swap 1029
173 TTR - Table to Register 1037
174 T --> R Table to Register 1033
175 T --> T: Table to Table 1041
31007523 8/2010 929


176 T.01 Timer: One Hundredth of a Second Timer 1047
177 T0.1 Timer: One Tenth Second Timer 1051
178 T1.0 Timer: One Second Timer 1055
179 T1MS Timer: One Millisecond Timer 1059
180 TBLK: Table to Block 1065
181 TEST: Test of 2 Values 1073
182 UCTR: Up Counter 1077
183 VMER - VME Read 1081
184 VMEW - VME Write 1085
185 WRIT: Write 1089
186 XMIT - Transmit 1095
187 XMIT Communication Block 1103
188 XMIT Port Status Block 1115
189 XMIT Conversion Block 1123
190 XMRD: Extended Memory Read 1131
191 XMWT: Extended Memory Write 1137
192 XOR: Exclusive OR 1143
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R --> T: Register to Table
31007523 8/2010
155
Introduction
This chapter describes the instruction R → T.

Topic Page
Representation 933
31007523 8/2010 931

Short Description
The R→T instruction copies the bit pattern of a register or of a string of contiguous
discretes stored in a word into a specific register located in a table. It can
accommodate the transfer of one register/word per scan.
932 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = copies source data and increments
the pointer value
Middle input 0x, 1x None ON = freezes the pointer value
Bottom input 0x, 1x None ON = resets the pointer value to zero
source 0x, 1x, 3x, 4x INT, UINT, Source data to be copied in the current
(top node) WORD scan
destination 4x INT, UINT Destination table where source data will
pointer be copied in the scan
(middle node)
table length INT, UINT Number of registers in the destination
(bottom node) table, range: 1 ... 999
Length:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Middle output 0x None ON = pointer value = table length
(instruction cannot increment any further)
31007523 8/2010 933

Top Input
The input to the top node initiates the DX move operation.
Middle Input
When the middle input goes ON, the current value stored in the destination pointer
register is frozen while the DX operation continues. This causes new data being
copied to the destination to overwrite the data copied on the previous scan.
Bottom Input
When the bottom input goes ON, the value in the destination pointer register is reset
to zero. This causes the next DX move operation to copy source data into the first
register in the destination table.
Source Data (Top Node)

When using register types 0x or 1x:
z First 0x reference in a string of 16 contiguous coils or discrete outputs
z First 1x reference in a string of 16 discrete inputs
Destination Pointer (Middle Node)

The 4x register entered in the middle node is a pointer to the destination table where
source data will be copied in the scan. The first register in the destination table is the
next contiguous 4x register following the pointer, i.e. if the pointer register is 400027,
then the destination table begins at register 400028.
The value posted in the pointer register indicates the register in the destination table
where the source data will be copied. A value of zero indicates that the source data
will be copied to the first register in the destination table; a value of 1 indicates that
the source data be copied to the second register in the destination table; etc.
NOTE: The value posted in the destination pointer register cannot be larger than the
table length integer specified in this node.
Outputs
R→T can produce two possible outputs, from the top and middle nodes. The state
of the output from the top node echoes the state of the top input. The output from
the middle node goes ON when the value in the destination pointer register equals
the specified table length. At this point, the instruction cannot increment any further.
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RBIT: Reset Bit
31007523 8/2010
RBIT: Reset Bit
156
Introduction
This chapter describes the instruction RBIT.

Topic Page
Representation 937
31007523 8/2010 935

RBIT: Reset Bit
Short Description
The reset bit (RBIT) instruction lets you clear a latched-ON bit by powering the top
input. The bit remains cleared after power is removed from the input. This instruction
is designed to clear a bit set by the SBIT instruction.
NOTE: The RBIT instruction does not follow the same rules of network placement
as 0x-referenced coils do. An RBIT instruction cannot be placed in column 11 of a
the ladder.
936 31007523 8/2010

RBIT: Reset Bit
Representation
Symbol

Reference
Top input 0x, 1x None ON = clears the specified bit to 0. The bit
remains cleared after power is removed from
the input
(bottom node) cleared
Top output 0x None ON = the specified bit has been cleared to 0
31007523 8/2010 937

RBIT: Reset Bit
938 31007523 8/2010

READ: Read
31007523 8/2010
READ: Read
157
Introduction
This chapter describes the instruction READ.

Topic Page
Representation 941
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READ: Read
Short Description
The READ instruction provides the ability to read data from an ASCII input device
(keyboard, bar code reader, etc.) into the PLC’s memory via its RIO network. The
connection to the ASCII device is made at an RIO interface.
In the process of handling the messaging operation, READ performs the following
functions:
z Verifies the lengths of variable data fields
z Verifies the correctness of the ASCII communication parameters, e.g. the port
number, the message number
z Performs error detection and recording
z Reports RIO interface status
READ requires two tables of registers: a destination table where retrieved variable
data (the message) is stored, and a control block where comm port and message
parameters are identified.
Further information about formatting messages you will find in Formatting Messages
for ASCII READ/WRIT Operations, page 57.
940 31007523 8/2010

READ: Read
Representation
Symbol

Reference
Top input 0x, 1x None ON = initiates a READ
Middle input 0x, 1x None ON = pauses READ operation
Bottom input 0x, 1x None ON = abort READ operation
control block 4x INT, UINT, Control block (first of seven contiguous holding
(top node) WORD registers)
destination 4x INT, UINT, Destination table
(middle node) WORD
table length INT, UINT Length of destination table (number of registers
(bottom node) where the message data will be stored), range:
1 ... 999
Length:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Middle output 0x None ON = error in communication or operation has
timed out (for one scan)
Bottom output 0x None ON = READ complete (for one scan)
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READ: Read

The 4x register entered in the top node is the first of seven contiguous holding
register in the control block.
Register Definition
Displayed Port number and error code
First implied Message number
Second implied Number of registers required to satisfy format
Third implied Count of the number of registers transmitted thus far
Fourth implied Status of the solve
Sixth implied Checksum of registers 0 ... 5
Port Number and Error Code
Bit Function
1 ... 4 PLC error code
5 Not used
6 Input from the ASCII device not compatible with format
7 Input buffer overrun, data received too quickly at RIOP
8 USART error, bad byte received at RIOP
9 ASCII device off-line, check cabling
10 Illegal format, not received properly by RIOP
11 ASCII message terminated early (in keyboard mode
12 ... 16 Comm port # (1 ... 32)
942 31007523 8/2010

READ: Read
PLC Error Code
Bit Meaning
1 2 3 4
0 0 0 1 Error in the input to RIOP from ASCII device
0 0 1 0 Exception response from RIOP, bad data
0 0 1 1 Sequenced number from RIOP differs from expected value
0 1 0 0 User register checksum error, often caused by altering
READ registers while the block is active
0 1 0 1 Invalid port or message number detected
0 1 1 0 User-initiated abort, bottom input energized
0 1 1 1 No response from drop, communication error
1 0 0 0 Node aborted because of SKP instruction
1 0 0 1 Message area scrambled, reload memory
1 0 1 0 Port not configured in the I/O map
1 0 1 2 Illegal ASCII request
1 1 0 0 Unknown response from ASCII port
1 1 0 1 Illegal ASCII element detected in user logic
1 1 1 1 RIOP in the PLC is down
Destination (Middle Node)

The middle node contains the first 4x register in a destination table. Variable data in
a READ message are written into this table. The length of the table is defined in the
bottom node.
Consider this READ message:
NOTE: An ASCII READ message may contain the embedded text, placed inside
quotation marks, as well as the variable data in the format statement, i.e., the ASCII
message.
The 10-character ASCII field AAAAAAAAAA is the variable data field; variable data
must be entered via an ASCII input device.
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READ: Read
944 31007523 8/2010

RET: Return from a Subroutine
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158
Introduction
This chapter describes the instruction RET.

Topic Page
Representation: RET - Return to Scheduled Logic 947
31007523 8/2010 945

Short Description
The RET instruction may be used to conditionally return the logic scan to the node
immediately following the most recently executed JSR block. This instruction can be
implemented only from within the subroutine segment, the (unscheduled) last
segment in the user logic program.
NOTE: If a subroutine does not contain a RET block, either a LAB block or the end-
of-logic (whichever comes first) serves as the default return from the subroutine.
An example to the subroutine handling you will find in Subroutine Handling, page 73.
946 31007523 8/2010

Representation: RET - Return to Scheduled Logic
Symbol

Reference
Top input 0x, 1x None ON = return to previous logic
ON returns the logic scan to the node
immediately following the most recently
executed JSR instruction or to the point
where the interrupt occurred in the logic
scan.
00001 INT, UINT Constant value, can not be changed
Top output 0x None ON = error in the specified subroutine
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948 31007523 8/2010

RTTI - Register to Input Table
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159
Introduction
This chapter describes the instruction RTTI.

Topic Page
Representation 951
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Short Description
The Register to Input Table block is one of four 484-replacement instructions. It
copies the contents of an input register or a holding register to another input or
holding register. This destination register is pointed to by the input register implied
by the constant in the bottom node. Only one such operation can be accommodated
by the system in each scan.
950 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None Control source
source 3x, 4x INT, UINT The source node (top node) contains the
(top node) source register address. The data located
in the source register address will be
copied to the destination address, which is
determined by the destination offset
pointer.
pointer (1 ... 254) INT, UINT The pointer is a 3xxxx implied by a constant
(bottom node) (801 ... 832) (i.e. 00018 -> 30018) whose contents
indicate the destination. A value of 1 to 254
indicates a holding register (40001 - 40254)
and a value of 801 to 832 indicates an input
register (30001 - 30032). If the value is
outside this range, the operation is not
performed and the ERROR rail is powered.
Note the pointer's value is NOT
automatically increased.
Top output 0x None Echoes the value of the top input
Pointer value out of range
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952 31007523 8/2010

RTTO - Register to Output Table
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160
Introduction
This chapter describes the instruction RTTO.

Topic Page
Representation 955
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Short Description
The Register to Output Table block is one of four 484-replacement instructions. It
copies the contents of an input register or a holding register to another input or
holding register. The holding register implied by the constant in the bottom node
points to this destination register. Only one such operation can be accommodated
by the system in each scan.
954 31007523 8/2010

Representation
Symbol

Reference
pointer.
pointer (1 ... 254) INT, UINT The pointer is a 4xxxx implied by a constant
(bottom node) (801 ... 824) (i.e. 00018 -> 40018) whose contents
indicate the destination. A value of 1 to 254
indicates a holding register (40001 - 40254)
and a value of 801 to 832 indicates an input
register (30001 - 30032). If the value is
outside this range, the operation is not
performed and the ERROR rail is powered.
Note that the pointer's value is NOT
automatically increased.
Top output 0x None Echoes the value of the top input
Pointer value out of range
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956 31007523 8/2010

RTU - Remote Terminal Unit
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161
Introduction
This chapter describes the instruction RTU.

Topic Page
Representation 959
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Short Description
The Modbus Remote Terminal Unit (RTU) block supports the following data baud
rates:
z 1200
z 2400
z 4800
z 9600
z 19200
958 31007523 8/2010

Representation
Description of the instructions parameters
Register Function
4x RTU revision number (read-only)
4x + 1 Fault status field (read-only)
4x + 2 Field not used
4x + 3 Set the Data Baud Rate register
For expanded and detailed information about the register entries for baud rates
please see the section below: Register Entries for Baud Rates.
4x + 4 Set the Data Bits register
For expanded and detailed information about the register entries for data bits
please see the section below: Register Entries for Data Bits
4x + 5 Parity register
4x + 6 Stop bit register
4x + 7 Field not used
4x + 8 Set the Command Word register
For expanded and detailed information about the register entries for command
words please see the section below: Register Entries for Command Words
Register Entries for Baud Rates

The Modbus Remote Terminal Unit (RTU) block supports the following data baud
rates:
z 1200
z 2400
z 4800
z 9600
z 19200
Below are the register entries for the supported data rates. To configure a data rate,
type the appropriate decimal number (for example 1200) in the data baud rate
register.
Register Entry Baud Rate

1200 1200
2400 2400
4800 4800
9600 9600
19200 19200
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Register Entries for Data Bits

The RTU block supports data bits 7 and 8. Below are the possible register entries
for the data bits field:
Register Entry Data Bit Field

7 7
8 8
Modbus messages can be sent in Modbus RTU format or Modbus ASCII format.
z If messages are sent in Modbus ASCII format, type 7 in the field.
z If messages are sent in Modbus RTU format, type 8.
If you're sending ASCII character messages, this register can be set to 7 or 8 data
bits.
Register Entries for Command Words

The RTU block interprets each bit of the command word as a function to implement
or perform. Below are the bit definitions for the command word register entries.
Register Entry Definitions

1 (msb) Not used
2 Enable RTS/CTS control
3 Not used
4 Not used
5 Not used
6 Not used
7 Enable ASCII string messaging
8 Enable Modbus messaging
9 Not used
10 Not used
11 Not used
12 Not used
13 Not used
14 Hang up modem
15 Dial modem
16 (lsb) Initialize modem
The following items provide expanded and detailed information about Bits 2, 7, and
8.
960 31007523 8/2010

z Bit 2 – Enable request-to-send/clear-to-send (RTS/CTS) control

This bit should be set (or true) when a DCE that is connected to the PLC requires
hardware handshaking using RTS/CTS control.
This bit can be used in conjunction with the values contained in the (4xxxx ¸ 13)
start-of-transmission delay register and the (4xxxx + 13) end-of-transmission
delay register. Start-of-transmission delay keeps RTS asserted for 0-9999 ms
before the RTU block sends a message from the PLC port. After the RTU block
sends a message, end-of-transmission delay keeps RTS asserted for 0-9999 ms.
When end-of-transmission delay has expired, the RTU block de-asserts RTS.
z Bit 7 – Enable ASCII string messaging
This bit should be set (or true) to send ASCII string messages form the PLC
communication Port #1.
The RTU block can send an ASCII string of up to 512 characters in length. Each
ASCII message must be programmed into contiguous 4x registers of the PLC.
Two characters per register are allowed.
Note: This ASCII message string should not be confused with a Modbus
message sent in ASCII format.
z Bit 8 – Enable Modbus messaging
This bit should be set (or true) to send Modbus messages from the PLC
communication port #1.
Modbus messages can be sent in RTU or ASCII formats.
z If sending Modbus messages in RTU format, set the data bits in the (4xxxx +
4) data bits register to 8.
z If sending Modbus message in ASCII format, set the data bits in the (4xxxx +
4) data bits register to 7.
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962 31007523 8/2010

SAVE: Save Flash
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SAVE: Save Flash
162
Introduction
This chapter describes the instruction SAVE.

Topic Page
Representation 965
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SAVE: Save Flash
Short Description
NOTE: This instruction is available with the PLC family TSX Compact, with Quantum
CPUs 434 12/ 534 14 and Momentum CPUs CCC 960 x0/ 980 x0.
The SAVE instruction saves a block of 4x registers to state RAM where they are
protected from unauthorized modification.
964 31007523 8/2010

SAVE: Save Flash
Representation
Symbol

Reference
Top input 0x, 1x None Start SAVE operation: it should remain ON
until the operation has completed
successfully or an error has occurred.
register 4x INT, UINT, First of max. 512 contiguous 4x registers
(top node) WORD to be saved to state RAM
1, 2, 3, 4 INT Integer value, which defines the specific
(see page 966) buffer where the block of data is to be
(middle node) saved
length INT Number of words to be saved, range: 1 ...
(bottom node) 512
Top output 0x None ON = SAVE is active
Middle output 0x None ON = SAVE is not allowed
(see page 966)
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SAVE: Save Flash
1, 2, 3, 4 (Middle Node)
The middle node defines the specific buffer, within state RAM, where the block of
data is to be saved. Four 512 word buffers are allowed. Each buffer is defined by
placing its corresponding value in the middle node, that is, the value 1 represents
the first buffer, value 2 represents the second buffer and so on. The legal values are
1, 2, 3, and 4. When the PLC is started all four buffers are zeroed. Therefore, you
may not save data to the same buffer without first loading it with the instruction
LOAD (see page 647). When this is attempted the middle output goes ON. In other
words, once a buffer is used, it may not be used again until the data has been
removed.
Middle Output
The output from the middle node goes ON when previously saved data has not been
accessed using the LOAD (see page 647) instruction. This prevents inadvertent
overwriting of data in the SAVE buffer.
966 31007523 8/2010

SBIT: Set Bit
31007523 8/2010
SBIT: Set Bit
163
Introduction
This chapter describes the instruction SBIT.

Topic Page
Representation 969
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SBIT: Set Bit
Short Description
The set bit (SBIT) instruction lets you set the state of the specified bit to ON (1) by
powering the top input.
NOTE: The SBIT instruction does not follow the same rules of network placement
as 0x-referenced coils do. An SBIT instruction cannot be placed in column 11 of a
the ladder.
968 31007523 8/2010

SBIT: Set Bit
Representation
Symbol

Reference
Top input 0x, 1x None ON = sets the specified bit to 1. The bit
remains set after power is removed from
the input
(bottom node) set
Top output 0x None Goes ON, when the specified bit is set and
remains ON until it is cleared (via the RBIT
(see page 935) instruction)
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SBIT: Set Bit
970 31007523 8/2010

SCIF: Sequential Control Interfaces
31007523 8/2010
SCIF:
Sequential Control Interfaces
164
Introduction
This chapter describes the instruction SCIF.

Topic Page
Representation 973
31007523 8/2010 971

Short Description
The SCIF instruction performs either a drum sequencing operation or an input
comparison (ICMP) using the data defined in the step data table.
The choice of operation is made by defining the value in the first register of the step
data table (see page 974):
z 0 = drum mode:
The instruction controls outputs in the drum sequencing application.
z 1 = ICMP mode:
The instruction reads inputs to ensure that limit switches, proximity switches,
pushbuttons, etc. are properly positioned to allow drum outputs to be fired.
972 31007523 8/2010

Representation
Symbol

Reference Type
Top input 0x, 1x None ON = initiates specified sequence control operation
Middle input 0x, 1x None Drum mode: step pointer increments to the next step
ICMP mode: compare status is shown at the middle output
Bottom input 0x, 1x None Drum mode: ON = reset step pointer to 0
ICMP mode: not used
step pointer 4x INT, Number of the current step in the step data table
(top node) UINT
step data table 4x INT, First register in the step data table
(see page 974) UINT (For expanded and detailed information please see the section Step
(middle node) Data Table (Middle Node), page 974.)
length (see page 974) INT, Number of application-specific registers used in the step data table
(bottom node) UINT
Middle output 0x None Drum mode goes ON for the last step
Note: When using the middle output, be aware that when integrating
with other logic, if the step pointer is zero and the middle input is ON,
then the middle output will also be ON. This condition will cause the
step pointer to be one step out of sequence.
Bottom output 0x None ON = error is detected
31007523 8/2010 973


The 4x register entered in the middle node is the first register in the step data table.
The first seven registers in the table hold constant and variable data required to
solve the instruction:
Register Register Name Description

Displayed subfunction type 0 = drum mode; 1 = ICMP mode
(entry of any other value in this register will result in all outputs OFF)
First implied masked output data Loaded by SCIF each time the block is solved; the register contains the
(in drum mode) contents of the current step data register masked with the output mask
register
raw input data Loaded by the user from a group of sequential inputs to be used by the
(in ICMP mode) block in the current step
Second current step data Loaded by SCIF each time the block is solved; the register contains data
implied from the current step (pointed to by the step pointer)
Third implied output mask Loaded by the user before using the block, the contents will not be altered
(in drum mode) during logic solving; contains a mask to be applied to the data for each
sequencer step
input mask Loaded by the user before using the block, it contains a mask to be ANDed
(in ICMP mode) with raw input data for each step, masked bits will not be compared; the
masked data are put in the masked input data register
Fourth implied masked input data Loaded by SCIF each time the block is solved, it contains the result of the
(in ICMP mode) ANDed input mask and raw input data
not used in drum mode
Fifth implied compare status Loaded by SCIF each time the block is solved, it contains the result of an
(in ICMP mode) XOR of the masked input data and the current step data; unmasked inputs
that are not in the correct logical state cause the associated register bit to
go to 1, non-zero bits cause a miscompare and turn ON the middle output
from the SCIF block
not used in drum mode
Sixth implied start of data table First of K registers in the table containing the user-specified control data
Note: This and the rest of the registers represent application-specific step
data in the process being controlled.
Length of Step Data Table (Bottom Node)

The integer value entered in the bottom node is the length, i.e. the number of
application-specific registers, used in the step data table. The length can range from
1 ... 255.
length must be ≥ the value placed in the steps used register in the middle node.
974 31007523 8/2010

SENS: Sense
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SENS: Sense
165
Introduction
This chapter describes the instruction SENS.

Topic Page
Representation 977
31007523 8/2010 975

SENS: Sense
Short Description
The SENS instruction examines and reports the sense (1 or 0) of a specific bit
location in a data matrix. One bit location is sensed per scan.
976 31007523 8/2010

SENS: Sense
Representation
Symbol

Reference Type
Top input 0x, 1x None ON = senses the bit location
Middle input 0x, 1x None Increment bit location by one on next scan
Bottom input 0x, 1x None Reset bit location to 1
bit location 3x, 4x WORD Specific bit location to be sensed in the data
(see page 978) matrix, entered explicitly as an integer or stored
(top node) in a register; range: 1 ... 9600
Pointer: ( 999 16-bit PLC)
(max) (9900 24-bit PLC)
data matrix 0x, 4x BOOL, First word or register in the data matrix
(middle node) WORD
length INT, Matrix length max
(see page 978) UINT 255 Registers (4080 bits 16-bit PLC)
(bottom node) 600 Registers (9600 bits 24-bit PLC)
Middle output 0x None ON = bit sense is 1
OFF = bit sense is 0
Bottom output 0x None ON = error: bit location > matrix length
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SENS: Sense
Bit Location (Top Node)

NOTE: If the bit location is entered as an integer or in a 3x register, the instruction
will ignore the state of the middle and bottom inputs.

The integer value entered in the bottom node specifies a matrix length, i.e, the
number of 16-bit words or registers in the data matrix. The length can range from 1
... 600 in a 24-bit CPU, e.g, a matrix length of 200 indicates 3200 bit locations.
978 31007523 8/2010

Shorts
31007523 8/2010
Shorts
166
Introduction
This chapter describes the instruction element Shorts.

Topic Page
Representation 981
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Shorts
Short Description
Shorts are simply straight-line connections between contacts and/or instructions in
a ladder logic network. Vertical (|) and horizontal (—) shorts are used to make
connections between rows and columns of logic. To cancel a vertical short, use a
vertical open.
980 31007523 8/2010

Shorts
Representation
Vertical Shorts
Connects contacts or instructions vertically in a network column, or node inputs and
outputs to create either/or conditions. When two contacts are connected by vertical
shorts, power is passed when one or both contacts receive power.
Horizontal Shorts
Expands logic horizontally along a rung in a ladder logic network.
31007523 8/2010 981

Shorts
982 31007523 8/2010

SKP - Skipping Networks
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167
Introduction
This chapter describes the instruction SKP.

Topic Page
Representation 985
31007523 8/2010 983

Short Description
WARNING
SKIPPED INPUTS AND OUTPUTS
When using the SKP instruction, watch for skipped inputs and outputs. SKP is a
dangerous instruction that should be used carefully. If inputs and outputs that
normally effect control are unintentionally skipped (or not skipped), the result can
create hazardous conditions for personnel and application equipment.
equipment damage.
CAUTION
READING VALUES WHILE CHANGING
Use 3xxxx and 4xxxx registers with caution. The processor can read the value
while it's changing.
The SKP instruction is a standard instruction in all PLCs. It should be used with
caution.
The SKP instruction is used to reduce the scan time by not solving a portion of the
logic. The SKP instruction causes the logic scan to skip specified networks in the
program.
The SKP function can be used to
z bypass seldom used program sequences
z create subroutines
The SKP instruction allows you to skip a specified number of networks in a ladder
logic program. When it is powered, the SKP operation is performed on every scan.
The remainder of the network in which the instruction appears counts as the first of
the specified number of networks to be skipped. The CPU continues to skip
networks until the total number of networks skipped equals the number specified in
the instruction block or until a segment boundary is reached. A SKP operation
cannot cross a segment boundary.
A SKP instruction can be activated only if you specify in the PLC set-up editor that
skips are allowed. SKP is a one-high nodal instruction.
984 31007523 8/2010

Representation
Symbol

Reference
Top input 1x None ON initiates a skip network operation when
it passes power. A SKP operation is
performed on every scan while the input is
ON
# of networks 3x, 4x INT, UINT The value entered in the node specifies the
skipped WORD number of networks to be skipped.
(top node) The value can be
z Specified explicitly as an integer
constant in the range 1 through 999
z Stored in a 3xxxx input register
z Stored in a 4xxxx holding register
The node value includes the network that

contains the SKP instruction. The nodal
regions in the network where the SKP
resides that have not already been
scanned will be skipped; this counts as one
of the networks specified to be skipped.
The CPU continues to skip networks until
the total number of networks skipped
equals the value specified.
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986 31007523 8/2010

SRCH: Search
31007523 8/2010
SRCH: Search
168
Introduction
This chapter describes the instruction SRCH.

Topic Page
Representation 989
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SRCH: Search
Short Description
The SRCH instruction searches the registers in a source table for a specific bit
pattern.
988 31007523 8/2010

SRCH: Search
Representation
Symbol

Reference
Top input 0x, 1x None ON = initiates search
Middle input 0x, 1x None OFF = search from beginning
ON = search from last match
source table 3x, 4x INT, UINT, Source table to be searched
(top node) WORD
pointer 4x INT, UINT Pointer into the source table
(see page 991)
(middle node)
table length INT, UINT Number of registers in the source table;
(bottom node) range: 1 ... 100
Middle output 0x None ON = match found
31007523 8/2010 989

SRCH: Search
A SRCH Example
In the following example, we search a source table that contains five registers
(40421 ... 40425) for a specific bit pattern. The pointer register (40430) indicates that
the desired bit pattern is stored in register 40431, and we see that the register
contains a bit value of 3333.
In each scan where P.T. contact 10001 transitions from OFF to ON, the source table
is searched for a bit pattern equivalent to the value 3333. when the math is found,
the middle output passes power to coil 00142.
If N.O. contact 10002 is OFF when the match is found at register 40423, the SRCH
instruction energizes coil 00142 for one scan, then starts the search again in the
next scan at the top of the source table (register 40421). If contact 10002 is ON, the
SRCH instruction energizes coil 00142 for one scan, then starts the search in
register 40424,
Because the top input is a P.T. contact, on any scan where power is not applied to
the top input the pointer value is cleared. We use a BLKM instruction here to sage
the pointer value to register 40500.
990 31007523 8/2010

SRCH: Search

The 4x register entered in the middle node is the pointer into the source table. It
points to the source register that contains the same value as the value stored in the
next contiguous register after the pointer, e.g. if the pointer register is 400015, then
register 400016 contains a value that the SRCH instruction will attempt to match in
source table.
31007523 8/2010 991

SRCH: Search
992 31007523 8/2010

STAT: Status
31007523 8/2010
STAT: Status
169
Introduction
This chapter describes the instruction STAT.

Topic Page
Representation 995
Description of the Status Table 997
Controller Status Words 1 - 11 for Quantum and Momentum 1001
I/O Module Health Status Words 12 - 20 for Momentum 1006
I/O Module Health Status Words 12 - 171 for Quantum 1008
Communication Status Words 172 - 277 for Quantum 1010
Controller Status Words 1 - 11 for TSX Compact and Atrium 1015
I/O Module Health Status Words 12 - 15 for TSX Compact 1018
Global Health and Communications Retry Status Words 182 ... 184 for TSX 1019
Compact
31007523 8/2010 993

STAT: Status
Short Description
The STAT instruction accesses a specified number of words in a status table
(see page 997) in the PLC’s system memory. Here vital diagnostic information
regarding the health of the PLC and its remote I/O drops is posted.
This information includes:
z PLC status
z Possible error conditions in the I/O modules
z Input-to-PLC-to-output communication status
994 31007523 8/2010

STAT: Status
Representation
Symbol

Reference
Top input 0x, 1x None ON = copies specified number of words from the
status table
destination 0x, 4x INT, UINT, First position in the destination block
(see page 996) BOOL,
(top node) WORD
length INT, UINT number of registers or 16-bit words in the
(see page 996) destination block
(bottom node) The integer value entered in the bottom node
specifies a matrix length - i.e., the number of 16-
bit words or registers in the data matrix. The
length can range from 1 through 255 in a 16-bit
CPU and from 1 through 600 in a 24-bit CPU—
e.g., a matrix length of 200 indicates 3200 bit
locations.
Note: If 0xxxx references are used as the
destination, they cannot be programmed as
coils, only as contacts referencing those coil
numbers.
regarding table length and PLCs see the section
Length (Bottom Node), page 996.)
31007523 8/2010 995

STAT: Status
Mode of Functioning
With the STAT instruction, you can copy some or all of the status words into a block
of registers or a block of contiguous discrete references.
The copy to the STAT block always begins with the first word in the table up to the
last word of interest to you. For example, if the status table is 277 words long and
you are interested only in the statistics provided in word 11, you need to copy only
words 1 ... 11 by specifying a length of 11 in the STAT instruction.
Destination Block (Top Node)

The reference number entered in the top node is the first position in the destination
block, i.e. the block where the current words of interest from the status table will be
copied.
The number of holding registers or 16-bit words in the destination block is specified
in the bottom node (length).
NOTE: We recommend that you do not use discretes in the STAT destination node
because of the excessive number required to contain status information.

The integer value entered in the bottom node specifies the number of registers or
16-bit words in the destination block where the current status information will be
written.
The maximum allowable length will differ according to the type of PLC in use and the
type of I/O communications protocol employed.
z For a 984A, 984B, or 984X Chassis Mount PLC using the S901 RIO protocol the
available range of the system status table is 1 ... 75 words
z For PLCs with 16-bit CPUs using the S908 RIO protocol - for example the 38x,
48x, and 68x Slot Mount PLCs - the available range of the system status table is
1 ... 255
z For PLCs with 24-bit CPUs using the S908 RIO protocol - for example the 78x
Slot Mount PLCs, the Quantum PLCs - the available range of the system status
table is 1 ... 277
z For Compact-984 PLCs the available range of the system status table is 1 ... 184
z For Modicon Micro PLCs the available range of the system status table is 1 ... 56
996 31007523 8/2010

STAT: Status
Description of the Status Table
General
The STAT instruction is used to display the Status of Controller and I/O system for
Quantum (see page 997), Atrium (see page 1000), TSX Compact (see page 1000)
and Momentum (see page 999).
The first 11 status words are used by Quantum and Momentum in the same way and
by TSX Compact and Atrium in the same way. The following have a different
meaning for Quantum, TSX Compact and Momentum.
Quantum Overview
The 277 words in the status table are organized in three sections:
z Controller Status (words 1 ... 11) (see page 1001)
z I/O Module Health (words 12 ... 171) (see page 1008)
z I/O Communications Health (words 172 ... 277) (see page 1010)
Words of the status table:
Decimal Word Word Content Hex Word

1 Controller Status 01
2 Hot Standby Status 02
4 RIO Status 04
5 Controller Stop State 06
6 Number of Ladder Logic Segments 06
7 End-of-logic (EOL) Pointer 07
8 RIO Redundancy and Timeout 08
9 ASCII Message Status 09
10 RUN/LOAD/DEBUG Status 0A
11 not used 0B
12 Drop 1, Rack 1 0C
13 Drop 1, Rack 2 0D
... ...... ...
16 Drop 1, Rack 5 0F
17 Drop 2, Rack 1 10
18 Drop 2, Rack 2 11
... ...... ...
171 Drop 32, Rack 5 AB
172 S908 Startup Error Code AC
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STAT: Status

173 Cable A Errors AD
174 Cable A Errors AE
175 Cable A Errors AF
176 Cable B Errors B0
179 Global Communication Errors B3
182 Drop 1 Errors/Health Status and Retry Counters (in the TSX B6
Compact 984 Controllers) (First word)
Compact 984 Controllers) (Second word)
Compact 984 Controllers) (Third word)
... ...... ...
275 Drop 32 Errors/Health Status and Retry Counters (in the TSX 113
Compact 984 Controllers) (Second word)
Compact 984 Controllers) (Third word)
998 31007523 8/2010

STAT: Status
Momentum Overview
The 20 words in the status table are organized in two sections:

2 Hot Standby Status 02
4 RIO Status 04
5 Controller Stop State 06
8 RIO Redundancy and Timeout 08
9 ASCII Message Status 09
11 not used 0B
12 Local Momentum I/O Module Health 0C
13 I/O Bus Module Health 0D
14 I/O Bus Module Health 0E
15 I/O Bus Module Health 0F
16 I/O Bus Module Health 10
31007523 8/2010 999

STAT: Status
TSX Compact and Atrium Overview

The 184 words in the status table are organized in three sections:
z Not used (16 ... 181)
z Global Health and Communications retry status (words 182 ... 184)
(see page 1019)

1 CPU Status 01
2 not used 02
4 not used 04
5 CPU Stop State 06
8 not used 08
9 not used 09
11 not used 0B
12 I/O Health Status Rack 1 0C
13 I/O Health Status Rack 2 0D
14 I/O Health Status Rack 3 0E
15 I/O Health Status Rack 4 0F
16 ... 181 not used 10 ... B5
182 Health Status B6
183 I/O Error Counter B7
184 PAB Bus Retry Counter B8
1000 31007523 8/2010

STAT: Status
Controller Status Words 1 - 11 for Quantum and Momentum
Controller Status (Word 1)

Word 1 displays the following aspects of the PLC status:
Bit Function
1-5 Not used
6 1 = enable constant sweep
7 1 = enable single sweep delay
8 1 = 16 bit user logic
0 = 24 bit user logic
9 1 = AC power on
10 1 = RUN light OFF
11 1 = memory protect OFF
12 1 = battery failed
13 - 16 Not used
Hot Standby Status (Word 2)

Word 2 displays the Hot Standby status for 984 PLCs that use S911/R911 Hot
Standby Modules:
Bit Function
1 1 = S911/R911 present and healthy
2 - 10 Not used
11 0 = controller toggle set to A
1 = controller toggle set to B
12 0 = controllers have matching logic
1 = controllers do not have matching logic
13, 14 Remote system state:
0 1 = Off line (1 dec)
1 0 = primary (2 dec)
1 1 = standby (3 dec)
15, 16 Local system state:
0 1 = Off line (1 dec)
1 0 = primary (2 dec)
1 1 = standby (3 dec)
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STAT: Status

Word 3 displays more aspects of the controller status:
Bit Function
1 1 = first scan
2 1 = start command pending
3 1 = constant sweep time exceeded
4 1 = Existing DIM AWARENESS
5 - 12 Not used
13 - 16 Single sweeps
RIO Status (Word 4)

Word 4 is used for IOP information:
Bit Function
1 1 = IOP bad
2 1 = IOP time out
3 1 = IOP loop back
4 1 = IOP memory failure
5 - 12 Not used
13 - 16 00 = IO did not respond
01 = no response
02 = failed loopback
1002 31007523 8/2010

STAT: Status
Controller Stop State (Word 5)
CAUTION
Using a Quantum or 984-684E/785E PLC
If you are using a Quantum or 984-684E/785E PLC, bit 15 in word 5 is never set.
These PLCs can be started and run with coils disabled in RUN (optimized) mode.
Also all the bits in word 5 must be set to 0 when one of these PLCs is running.
Word 5 displays the PLC’s stop state conditions:
Bit Function
1 1 = peripheral port stop
2 Extended memory parity error (for chassis mount controllers) or traffic cop/S908
error (for other controllers)
If the bit = 1 in a 984B controller, an error has been detected in extended
memory; the controller will run, but the error output will be ON for XMRD/XMWT
functions
If the bit = 1 for any other controller than a chassis mount, then either a traffic
cop error has been detected or the S908 is missing from a multi-drop
configuration.
3 1 = controller in DIM AWARENESS
4 1 = illegal peripheral intervention
5 1 = segment scheduler invalid
6 1 = start of node did not start segment
7 1 = state RAM test failed
8 1 = invalid traffic cop
9 1 = watchdog timer expired
10 1 = real time clock error
11 CPU logic solver failed (for chassis mount controllers) or Coil Use TABLE (for
other controllers)
If the bit = 1 in a chassis mount controller, the internal diagnostics have detected
CPU failure.
If the bit = 1 in any controller other than a chassis mount, then the Coil Use Table
does not match the coils in user logic.
12 1 = IOP failure
13 1 = invalid node
14 1 = logic checksum
15 1 = coil disabled in RUN mode (see Caution below)
16 1 = bad config
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STAT: Status

Word 6 displays the number of segments in ladder logic; a binary number is shown:
Bit Function
1 - 16 Number of segments (expressed as a decimal number)

Word 7 displays the address of the end-of-logic (EOL) pointer:
Bit Function
1 - 16 EOL pointer address
RIO Redundancy and Timeout (Word 8)

Word 8 uses its four least significant bits to display the remote I/O timeout constant:
Bit Function
1 - 12 Not used
13 - 16 RIO timeout constant
ASCII Message Status (Word 9)

Word 9 uses its four least significant bits to display ASCII message status:
Bit Function
1 ... 12 Not used
13 1 = Mismatch between numbers of messages and pointers
14 1 = Invalid message pointer
15 1 = Invalid message
16 1 = Message checksum error
1004 31007523 8/2010

STAT: Status
RUN/LOAD/DEBUG Status (Word 10)

Word 10 uses its two least significant bits to display RUN/LOAD/DEBUG status:
Bit Function
1 ... 14 Not used
15, 15 0 0 = Debug (0 dec)
0 1 = Run (1 dec)
1 0 = Load (2 dec)
Word 11
This word is not used.
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STAT: Status
I/O Module Health Status Words 12 - 20 for Momentum
I/O Module Health Status

Status words 12 ... 20 display I/O module health status.
1 word is reserved for each of up to 1 Local drop, 8 words are used to represent the
health of up to 128 I/O Bus Modules
Local Momentum I/O Module Health

Word 12 displays the Local Momentum I/O Module health:
Bit Function
1 1 = Local Module
2 - 16 Not used
Momentum I/O Bus Module Health

Word 13 through 20 display the health status for Momentum I/O Bus Modules as
follows:
Word I/O Bus Modules

13 1 ... 16
14 17 ... 32
15 33 ... 48
16 49 ... 64
17 65 ... 80
18 81 ... 96
19 97 ... 112
20 113 ... 128
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STAT: Status
Each Word display the Momentum I/O Bus Module health as follows:
Bit Function
1 1 = Module 1
2 1 = Module 2
3 1 = Module 3
4 1 = Module 4
5 1 = Module 5
6 1 = Module 6
7 1 = Module 7
8 1 = Module 8
9 1 = Module 9
10 1 = Module 10
11 1 = Module 11
12 1 = Module 12
13 1 = Module 13
14 1 = Module 14
15 1 = Module 15
16 1 = Module 16
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STAT: Status
I/O Module Health Status Words 12 - 171 for Quantum
RIO Status Words

Status words 12 ... 20 display I/O module health status.
Five words are reserved for each of up to 32 drops, one word for each of up to five
possible racks (I/O housings) in each drop. Each rack may contain up to 11 I/O
modules; bits 1 ... 11 in each word represent the health of the associated I/O module
in each rack.
Bit Function
1 1 = Slot 1
2 1 = Slot 2
3 1 = Slot 3
4 1 = Slot 4
5 1 = Slot 5
6 1 = Slot 6
7 1 = Slot 7
8 1 = Slot 8
9 1 = Slot 9
10 1 = Slot 10
11 1 = Slot 11
12 1 = Slot 12
13 1 = Slot 13
14 1 = Slot 14
15 1 = Slot 15
16 1 = Slot 16
Four conditions must be met before an I/O module can indicate good health:
z The slot must be traffic copped
z The slot must contain a module with the correct personality
z Valid communications must exist between the module and the RIO interface at
remote drops
z Valid communications must exist between the RIO interface at each remote drop
and the I/O processor in the controller
1008 31007523 8/2010

STAT: Status
Status Words for the MMI Operator Panels

The status of the 32 Element Pushbutton Panels and PanelMate units on an RIO
network can also be monitored with an I/O health status word. The Pushbutton
Panels occupy slot 4 in an I/O rack and can be monitored at bit 4 of the appropriate
status word. A PanelMate on RIO occupies slot 1 in rack 1 of the drop and can be
monitored at bit 1 of the first status word for the drop.
NOTE: The ASCII Keypad’s communication status can be monitored with the error
codes in the ASCII READ/WRIT blocks.
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STAT: Status
Communication Status Words 172 - 277 for Quantum
DIO Status
Status words 172 ... 277 contain the I/O system communication status. Words 172
... 181 are global status words. Among the remaining 96 words, three words are
dedicated to each of up to 32 drops, depending on the type of PLC.
Word 172 stores the Quantum Startup Error Code. This word is always 0 when the
system is running. If an error occurs, the controller does not start-it generates a stop
state code of 10 (word 5 (see page 1003)).
Quantum Start-up Error Codes
Code Error Meaning (Where the error has occurred)

01 BADTCLEN Traffic Cop length
02 BADLNKNUM Remote I/O link number
03 BADNUMDPS Number of drops in Traffic Cop
04 BADTCSUM Traffic Cop checksum
10 BADDDLEN Drop descriptor length
11 BADDRPNUM I/O drop number
12 BADHUPTIM Drop holdup time
13 BADASCNUM ASCII port number
14 BADNUMODS Number of modules in drop
15 PRECONDRP Drop already configured
16 PRECONPRT Port already configured
17 TOOMNYOUT More than 1024 output points
18 TOOMNYINS More than 1024 input points
20 BADSLTNUM Module slot address
21 BADRCKNUM Module rack address
22 BADOUTBC Number of output bytes
23 BADINBC Number of input bytes
25 BADRF1MAP First reference number
26 BADRF2MAP Second reference number
27 NOBYTES No input or output bytes
28 BADDISMAP Discrete not on 16-bit boundary
30 BADODDOUT Unpaired odd output module
31 BADODDIN Unpaired odd input module
32 BADODDREF Unmatched odd module reference
33 BAD3X1XRF 1x reference after 3x register
1010 31007523 8/2010

STAT: Status
Code Error Meaning (Where the error has occurred)

34 BADDMYMOD Dummy module reference already used
35 NOT3XDMY 3x module not a dummy
36 NOT4XDMY 4x module not a dummy
40 DMYREAL1X Dummy, then real 1x module
41 REALDMY1X Real, then dummy 1x module
42 DMYREAL3X Dummy, then real 3x module
43 REALDMY3X Real, then dummy 3x module
Status of Cable A
Words 173 ... 175 are Cable A error words:
Word 173
Bit Function
1 ... 8 Counts framing errors
9 ... 16 Counts DMA receiver overruns
Word 174
Bit Function
1 ... 8 Counts receiver errors
9 ... 16 Counts bad drop receptions
Word 175
Bit Function
1 1 = Short frame
2 1 = No end-of- frame
3 ... 12 Not used
13 1 = CRC error
14 1 = Alignment error
15 1 =Overrun error
16 Not used
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STAT: Status
Status of Cable B
Words 176 ... 178 are Cable A error words:
Word 176
Bit Function
1 ... 8 Counts framing errors
9 ... 16 Counts DMA receiver overruns
Word 177
Bit Function
1 ... 8 Counts receiver errors
9 -...16 Counts bad drop receptions
Word 178
Bit Function
1 1 = Short frame
2 1 = No end-of- frame
3 ... 12 Not used
13 1 = CRC error
14 1 = Alignment error
15 1 =Overrun error
16 Not used
Status of Global Communication (Words 179 ... 181)

Word 179 displays global communication status:
Bit Function
1 1 = Comm health
2 1 = Cable A status
3 1 = Cable B status
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STAT: Status
Bit Function
4 Not used
5 ... 8 Lost communication counter
9 ... 16 Cumulative retry counter
Word 180 is the global cumulative error counter for Cable A:
Bit Function
1 ... 8 Counts detected errors
9 ... 162 Counts No responses
Word 181 is the global cumulative error counter for Cable B:
Bit Function
1 ... 8 Counts detected errors
Status of Remote I/O (Words 182 ... 277)

Words 182 ... 277 are used to describe remote I/O drop status; three status words
are used for each drop.
The first word in each group of three displays communication status for the
appropriate drop:
Bit Function
1 1 = Communication health
2 1 = Cable A status
3 1 = Cable B status
4 Not used
5 ... 8 Lost communication counter
9 ... 16 Cumulative retry counter
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STAT: Status
The second word in each group of three is the drop cumulative error counter on
Cable A for the appropriate drop:
Bit Function
1 ... 8 At least one error in words 173 ...175
The third word in each group of three is the drop cumulative error counter on Cable
B for the appropriate drop:
Bit Function
1 ... 8 At least one error in words 176 ...178
NOTE: For PLCs where drop 1 is reserved for local I/O, status words 182 ... 184 are
used as follows:
Word 182 displays local drop status:
Bit Function
1 1 = All modules healthy
2 ... 8 Always 0
9 ... 162 Number of times a module has been seen as unhealthy; counter rolls over at 255
Word 183 is a 16-bit error counter, which indicates the number of times a module
has been accessed and found to be unhealthy. Rolls over at 65535.
Word 184 is a 16-bit error counter, which indicates the number of times a
communication error occurred while accessing an I/O module. Rolls over at 65535.
1014 31007523 8/2010

STAT: Status
Controller Status Words 1 - 11 for TSX Compact and Atrium
CPU Status (Word 1)

Word 1 displays the following aspects of the CPU status:
Bit Function
1-5 Not used
6 1 = enable constant sweep
7 1 = enable single sweep delay
8 1 = 16 bit user logic
0 = 24 bit user logic
9 1 = AC power on
10 1 = RUN light OFF
11 1 = memory protect OFF
12 1 = battery failed
13 - 16 Not used
Word 2

Word 3 displays aspects of the controller status:
Bit Function
1 1 = first scan
2 1 = start command pending
3 1 = scan time has exceed constant scan target
4 1 = existing DIM AWARENESS
5 - 12 Not used
13 - 16 Single sweeps
Word 4
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STAT: Status
CPU Stop State (Word 5)

Word 5 displays the CPU’s stop state conditions:
Bit Function
1 1 = peripheral port stop
2 1 = XMEM parity error
3 1 = DIM AWARENESS
4 1 = illegal peripheral intervention
5 1 = invalid segment scheduler
6 1 = no start-of-network (SON) at the start of a segment
7 1 = state RAM test failed
8 1 = no end of logic (EOL), (bad Tcop)
9 1 = watch dog timer has expired
10 1 = real time clock error
11 1 = CPU failure
12 Not used
13 1 = invalid node in ladder logic
14 1 = logic checksum error
1 1 = coil disabled in RUN mode
16 1 = bad PLC setup
Number of Segments in program (Word 6)

Word 6 displays the number of segments in ladder logic; a binary number is shown.
This word is confirmed during power up to be the number of EOS (DOIO) nodes plus
1 (for the end of logic nodes), if untrue, a stop code is set, causing the run light to be
off:
Bit Function
1 - 16 Number of segments in the current ladder logic program (expressed as a
decimal number)
1016 31007523 8/2010

STAT: Status
Address of the End of Logic Pointer (Word 7)

Word 7 displays the address of the end-of-logic (EOL) pointer:
Bit Function
1 - 16 EOL pointer address
Word 8, Word 9
These words are not used.
RUN/LOAD/DEBUG Status (Word 10)

Word 10 uses its two least significant bits to display RUN/LOAD/DEBUG status:
Bit Function
1 ... 14 Not used
15, 16 0 0 = Debug (0 dec)
0 1 = Run (1 dec)
1 0 = Load (2 dec)
Word 11
31007523 8/2010 1017

STAT: Status
I/O Module Health Status Words 12 - 15 for TSX Compact
TSX Compact I/O Module Health

Words 12 ... 15 are used to display the health of the A120 I/O modules in the four
racks:
Word Rack No.

12 1
13 2
14 3
15 4
Each word contains the health status of up to five A120 I/O modules. The most
significant (left-most) bit represents the health of the module in Slot 1 of the rack:
Bit Function
1 1 = Slot 1
2 1 = Slot 2
3 1 = Slot 3
4 1 = Slot 4
5 1 = Slot 5
6 ... 16 Not used
If a module is I/O Mapped and ACTIVE, the bit will have a value of "1". If a module
is inactive or not I/O Mapped, the bit will have a value of "0".
NOTE: Slots 1 and 2 in Rack 1 (Word 12) are not used because the controller itself
uses those two slots.
1018 31007523 8/2010

STAT: Status
Global Health and Communications Retry Status Words 182 ... 184 for
TSX Compact
Overview
There are three words that contain health and communication information on the
installed I/O modules. If monitored with the Stat block, they are found in Words 182
through 184. This requires that the length of the Stat block is a minimum of 184
(Words 16 through 181 are not used).
Words 16 ... 181

These words are not used.
Health Status (Word 182)

Word 182 increments each time a module becomes bad. After a module becomes
bad, this counter does not increment again until that module becomes good and
then bad again.
Bit Function
1 1 = All modules healthy
2 ... 9 Not used
10 ... 16 "Module went unhealthy" counter
I/O Error Counter (Word 183)

This counter is similar to the above counter, except this word increments every scan
that a module remains in the bad state.
PAB Bus Retry Counter (Word 184)

Diagnostics are performed on the communications through the bus. This word
should normally be all zeroes. If after 5 retries, a bus error is still detected, the
controller will stop and error code 10 will be displayed. An error could occur if there
is a short in the backplane or from noise. The counter rolls over while running. If the
retries are less than 5, no bus error is detected.
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STAT: Status
1020 31007523 8/2010

SU16: Subtract 16 Bit
31007523 8/2010
170
Introduction
This chapter describes the instruction SU16.

Topic Page
Representation 1023
31007523 8/2010 1021

Short Description
The SU16 instruction performs a signed or unsigned 16-bit subtraction (value 1 -
value 2) on the top and middle node values, then posts the signed or unsigned
difference in a 4x holding register in the bottom node.
1022 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = enables value 1 - value 2
value 1 3x, 4x INT, UINT Minuend, can be displayed explicitly as an
(top node) integer (range 1 ... 65 535) or stored in a
register
value 2 3x, 4x INT, UINT Subtrahend, can be displayed explicitly as
(middle node) an integer (range 1 ... 65 535) or stored in
a register
difference 4x INT, UINT Difference
(bottom node)
Top output 0x None ON = value 1 > value 2
Middle output 0x None ON = value 1 = value 2
Bottom output 0x None ON = value 1 < value 2
31007523 8/2010 1023

1024 31007523 8/2010

SUB: Subtraction
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SUB: Subtraction
171
Introduction
This chapter describes the instruction SUB.

Topic Page
Representation 1027
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SUB: Subtraction
Short Description
The SUB instruction performs a signed or unsigned 16-bit subtraction (value 1 -
value 2) on the top and middle node values, then posts the signed or unsigned
difference in a 4x holding register in the bottom node.
NOTE: SUB is often used as a comparator where the state of the outputs identifies
whether value 1 is greater than, equal to, or less than value 2.
1026 31007523 8/2010

SUB: Subtraction
Representation
Symbol

Reference
Top input 0x, 1x None ON = enables value 1 - value 2
value 1 3x, 4x INT, UINT Minuend, can be displayed explicitly as an
(top node) integer or stored in a register
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Max. 65535-785L
value 2 3x, 4x INT, UINT Subtrahend, can be displayed explicitly as
(middle node) an integer or stored in a register
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Max. 65535-785L
difference 4x INT, UINT Difference
(bottom node)
31007523 8/2010 1027

SUB: Subtraction
1028 31007523 8/2010

SWAP - VME Bit Swap
31007523 8/2010
SWAP - VME Bit Swap
172
Introduction
This chapter describes the instruction SWAP.

Topic Page
Representation 1031
31007523 8/2010 1029

SWAP - VME Bit Swap
Short Description
The SWAP block allows the user to issue one of three different swap commands:
z swap high and low bits of a 16-bit word
z swap high and low words of a 32-bit double word
z swap (reverse) bits within a register's low byte
NOTE: Available only on the Quantum VME-424/X controller.
1030 31007523 8/2010

SWAP - VME Bit Swap
Representation
Symbol

Reference
Top input 0x, 1x None ON enables SWAP operation
value INT, UINT, Contains a constant from 1 to 3, which
(top node) WORD specifies what type of swap to perform:
1. Swap high and low bits of a 16-bit word.
2. Swap high and low words of a 32-bit
double word.
3. Swap (reverse) bits within a register's
low byte.
register 3x, 4x INT, UINT, Contains the register on which the swap is
(middle node) WORD to be performed
# of registers INT, UINT, Contains a constant that indicates how
(bottom node) WORD many registers are to be swapped, starting
with the source register.
Middle output 0x None Error
Bottom output 0x None Swap completed successfully
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SWAP - VME Bit Swap
1032 31007523 8/2010

T --> R: Table to Register
31007523 8/2010
T --> R Table to Register
174
Introduction
This chapter describes the instruction T→R.

Topic Page
Representation 1035
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Short Description
The T→R instruction copies the bit pattern of a register or 16 contiguous discretes
in a table to a specific holding register. It can accommodate the transfer of one
register per scan. It has three control inputs and produces two possible outputs.
1034 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = copies source data and increments the pointer value
(see page 1036)
(see page 1036)
source table 0x, 1x, 3x, INT, UINT, First register or discrete reference in the source table. A register
(top node) 4x WORD or string of contiguous discretes from this table will be copied in
a scan.
pointer (see page 1036) 4x INT, UINT Pointer to the destination where the source data will be copied
(middle node)
table length INT, UINT Length of the source table: number of registers that may be
(bottom node) copied; range: 1 ... 999
Length:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Middle output 0x None ON = pointer value = table length (instruction cannot increment
any further)
31007523 8/2010 1035

Middle Input
When the middle input goes ON, the current value stored in the pointer register is
frozen while the DX operation continues. This causes the same table data to be
written to the destination register on each scan.
Bottom Input
When the bottom input goes ON, the value in the pointer is reset to zero. This causes
the next DX move operation to copy the first destination register in the table.

The 4x register entered in the middle node is a pointer to the destination where the
source data will be copied. The destination register is the next contiguous 4x register
after the pointer. For example, if the middle node displays a pointer of 400100, then
the destination register for the T→R copy is 400101.
The value stored in the pointer register indicates which register in the source table
will be copied to the destination register in the current scan. A value of 0 in the
pointer indicates that the bit pattern in the first register of the source table will be
copied to the destination; a value of 1 in the pointer register indicates that the bit
pattern in the second register of the source table will be copied to the destination
register; etc.
1036 31007523 8/2010

TTR - Table to Register
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173
Introduction
This chapter describes the instruction TTR.

Topic Page
Representation: TTR - Table to Register 1039
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Short Description
The Table to Register block is one of four 484-replacement instructions.
It copies the contents of a source (input or holding) register to a holding register
implied by the constant in the bottom node. This source register is pointed to by the
input or holding register specified in the top node. Only one such operation can be
accommodated by the system in each scan.
NOTE: Available only on the 984-351 and 984-455.
1038 31007523 8/2010

Representation: TTR - Table to Register
Symbol

Reference
pointer.
destination (1 ... 254) INT, UINT The pointer is a 3xxxx or 4xxxx whose
(bottom node) (801 ... 824) contents indicate the source. A value of 1 to
254 indicates a holding register (40001 -
40254) and a value of 801 to 832 indicates
an input register (30001 - 30032). If the
value is outside this range, the operation is
not performed and the ERROR rail is
powered.
Top output 0x None Passes power when top input receives
power
Bottom output 0x None Pointer value out of range
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1040 31007523 8/2010

T --> T: Table to Table
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175
Introduction
This chapter describes the instruction T→T.

Topic Page
Representation 1043
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Short Description
The T→T instruction copies the bit pattern of a register or of 16 discretes from a
position within one table to an equivalent position in another table of registers. It can
accommodate the transfer of one register per scan. It has three control inputs and
produces two possible outputs.
1042 31007523 8/2010

Representation
Symbol

z E685/785 PLCs
z L785 PLCs
31007523 8/2010 1043


Reference
Top input 0x, 1x None ON = copies source data and increments
the pointer value
(see page 1045)
(see page 1045)
source table 0x, 1x, 3x, 4x INT, UINT, First register or discrete reference in the
(top node) WORD source table. A register or string of
contiguous discretes from this table will be
copied in a scan.
pointer 4x INT, UINT Pointer into both the source and
(see page 1045) destination table
(middle node)
table length INT, UINT Length of the source and the destination
(bottom node) table (must be equal in length)
Range:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Max. 65535 785L
Middle output 0x None ON = pointer value = table length
(instruction cannot increment any further)
1044 31007523 8/2010

Middle Input
When the input to the middle node goes ON, the current value stored in the pointer
register is frozen while the DX operation continues. This causes new data being
copied to the destination to overwrite the data copied on the previous scan.
Bottom Input
When the input to the bottom node goes ON, the value in the pointer register is reset
to zero. This causes the next DX move operation to copy source data into the first
register in the destination table.

The 4x register entered in the middle node is a pointer into both the source and
destination tables, indicating where the data will be copied from and to in the current
scan. The first register in the destination table is the next contiguous 4x register
following the pointer. For example, if the middle node displays a a pointer reference
of 400100, then the first register in the destination table is 400101.
The value stored in the pointer register indicates which register in the source table
will be copied to which register in the destination table. Since the length of the two
tables is equal and T→T copy is to the equivalent register in the destination table,
the current value in the pointer register also indicates which register in the
destination table the source data will be copied to.
A value of 0 in the pointer register indicates that the bit pattern in the first register of
the source table will be copied to the first register of the destination table; a value of
1 in the pointer register indicates that the bit pattern in the second register of the
source table will be copied to the second register of the destination register; etc.
31007523 8/2010 1045

1046 31007523 8/2010

T.01 Timer: One Hundredth Second Timer
31007523 8/2010
T.01 Timer:
One Hundredth of a Second Timer
176
Introduction
This chapter describes the instruction T.01 timer.

Topic Page
Representation 1049
31007523 8/2010 1047

Short Description
The T.01 instruction measures time in hundredth of a second intervals. It can be
used for timing an event or creating a delay. T.01 has two control inputs and can
produce one of two possible outputs.
1048 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None OFF → ON = initiates the timer operation:
time accumulates in hundredths-of-a-
second when top and bottom input are ON
Bottom input 0x, 1x None OFF = accumulated time reset to 0
ON = timer accumulating
timer preset 3x, 4x INT, UINT Preset value (number of hundredth-of-a-
(top node) second increments), can be displayed
explicitly as an integer or stored in a
register
Range:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Max. 65535 785L
accumulated 4x INT, UINT Accumulated time count in hundredth-of-
time a-second increments.
(bottom node)
Top output 0x None ON = accumulated time = timer preset
Bottom output 0x None ON = accumulated time < timer preset
31007523 8/2010 1049

1050 31007523 8/2010

T0.1 Timer: One Tenth Second Timer
31007523 8/2010
T0.1 Timer:
One Tenth Second Timer
177
Introduction
This chapter describes the instruction T0.1 timer.

Topic Page
Representation 1053
31007523 8/2010 1051

Short Description
The T0.1 instruction measures time in tenth-of-a-second increments. It can be used
for timing an event or creating a delay. T0.1 has two control inputs and can produce
one of two possible outputs.
NOTE: If you cascade T0.1 timers with presets of 1, the timers will time-out together;
to avoid this problem, change the presets to 10 and substitute a T.01 timer
(see page 1047).
1052 31007523 8/2010

Representation
Symbol

Reference
time accumulates in tenth-of-a-second
when top and bottom input are ON
timer preset 3x, 4x INT, UINT Preset value (number of tenth-of-a-second
(top node) increments), can be displayed explicitly as
an integer or stored in a register
Range:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Max. 65535 785L
accumulated 4x INT, UINT Accumulated time count in tenth-of-a-
time second increments.
(bottom node)
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1054 31007523 8/2010

T1.0 Timer: One Second Timer
31007523 8/2010
178
Introduction
This chapter describes the instruction T1.0 timer.

Topic Page
Representation 1057
31007523 8/2010 1055

Short Description
The T1.0 timer instruction measures time in one-second increments. It can be used
for timing an event or creating a delay. T1.0 has two control inputs and can produce
one of two possible outputs.
NOTE: If you cascade T1.0 timers with presets of 1, the timers will time-out together;
to avoid this problem, change the presets to 10 and substitute a T0.1 timer
(see page 1051).
1056 31007523 8/2010

Representation
Symbol

Reference
time accumulates in seconds when top
and bottom input are ON
timer preset 3x, 4x INT, UINT Preset value (number of one second
(top node) increments), can be displayed explicitly as
an integer or stored in a register
Range:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Max. 65535 785L
accumulated 4x INT, UINT Accumulated time count in one-second
time increments.
(bottom node)
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1058 31007523 8/2010

T1MS Timer: One Millisecond Timer
31007523 8/2010
T1MS Timer:
One Millisecond Timer
179
Introduction
This chapter describes the instruction T1MS timer.

Topic Page
Representation 1061
Example 1062
31007523 8/2010 1059

Short Description
The T1MS timer instruction measures time in one-millisecond increments. It can be
used for timing an event or creating a delay.
NOTE: The T1MS instruction is available only on the B984-102, the Micro 311, 411,
512, and 612, and the Quantum 424 02.
1060 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = initiates the timer operation: time
accumulates in milliseconds when top and
middle input are ON
Middle input 0x, 1x None OFF = accumulated time reset to 0
timer preset 3x, 4x INT, UINT Preset value (number of millisecond
(top node) increments the timer can accumulate), can
be displayed explicitly as an integer (range
1 ... 999) or stored in a register
accumulated 4x INT, UINT Accumulated time count in millisecond
time increments.
(middle node)
#1 INT, UINT Constant value of #1
(bottom node)
Middle output 0x None ON = accumulated time < timer preset
31007523 8/2010 1061

Example
A Millisecond Timer Example

Here is the ladder logic for a real-time clock with millisecond accuracy:
The T1MS instruction is programmed to pass power at 100 ms intervals; it is

followed by a cascade of four up-counters (see page 1077) that store the time
respectively in hundredth-of-a-second units, tenth-of-a-second units, one- second
units, one-minute units, and one-hour units.
When logic solving begins, the accumulated time value begins incrementing in
register 40055 of the T1MS block. After 100 one-ms increments, the top output
passes power and energizes coil 00001. At this point, the value in register 40055 in
the timer is reset to 0. The accumulated count value in register 40054 in the first
UCTR block increments by 1, indicating that 100 ms have passed. Because the
accumulated time count in T1MS no longer equals the timer preset, the timer begins
to re-accumulate time in ms.
When the accumulated count in register 40054 of the first UCTR instruction
increments to 10, the top output from that instruction block passes power and
energizes coil 00002. The value in register 40054 then resets to 0, and the
accumulated count in register 40053 of the second UCTR block increments by 1.
1062 31007523 8/2010

As the times accumulate in each counter, the time of day can be read in five holding
registers as follows:
Register Unit of Time Valid Range

40055 Thousandths-of-a-second 0 ... 100
40054 Tenths-of-a-second 0 ... 10
40053 Seconds 0 ... 60
40052 Minutes 0 ... 60
40051 Hours 0 ... 24
31007523 8/2010 1063

1064 31007523 8/2010

TBLK: Table to Block
31007523 8/2010
180
Introduction
This chapter describes the instruction TBLK.

Topic Page
Representation 1067
31007523 8/2010 1065

Short Description
The TBLK (table-to-block) instruction combines the functions of T→R
(see page 1033) and the BLKM (see page 93) in a single instruction. In one scan, it
can copy up to 100 contiguous 4x registers from a table to a destination block. The
destination block is of a fixed length. The block of registers being copied from the
source table is of the same length, but the overall length of the source table is limited
only by the number of registers in your system configuration.
1066 31007523 8/2010

Representation
Symbol
31007523 8/2010 1067


Reference Type
Top input 0x, 1x None ON = initiates move operation
Middle input 0x, 1x None ON = hold pointer
(see page 1069) The inputs to the middle and bottom node can
be used to control the value in the pointer so
that size of the source table can be controlled.
Important: You should use external logic in
conjunction with the middle or bottom input to
confine the value in the destination pointer to a
safe range.
When the input to the middle node is ON, the
value in the pointer register is frozen while the
TBLK operation continues. This causes the
same source data block to be copied to the
destination table on each scan.
Bottom input 0x, 1x None ON = reset pointer to zero
(see page 1069)
source table 4x INT, First holding register in the source table
(see page 1069) UINT, The 4xxxx register entered in the top node is the
(top node) WORD first holding register in the source table.
Note: The source table is segmented into a
series of register blocks, each of which is the
same length as the destination block.
Therefore, the size of the source table is a
multiple of the length of the destination block,
but its overall size is not specifically defined in
the instruction. If left uncontrolled, the source
table could consume all the 4xxxx registers
available in the PLC configuration.
pointer 4x INT, Pointer to the source block, destination block
(see page 1069) UINT
(middle node)
block length INT, Number of registers of the destination block and
(bottom node) UINT of the blocks within the source table; range: 1 ...
100
Top output 0x None ON = move successful
Middle output 0x None ON = error / move not possible
1068 31007523 8/2010

Middle Input
When the middle input is ON, the value in the pointer register is frozen while the
TBLK operation continues. This causes the same source data block to be copied to
the destination table on each scan.
Bottom Input
CAUTION
Confine the value in the destination pointer to a safe range.
You should use external logic in conjunction with the middle and the bottom inputs
to confine the value in the destination pointer to a safe range.
When the bottom input is ON, the pointer value is reset to zero. This causes the
TBLK operation to copy data from the first block of registers in the source table.
Source Table (Top Node)

The 4x register entered in the top node is the first holding register in the source table.
NOTE: The source table is segmented into a series of register blocks, each of which
is the same length as the destination block. Therefore, the size of the source table
is a multiple of the length of the destination block, but its overall size is not
specifically defined in the instruction. If left uncontrolled, the source table could
consume all the 4x registers available in the PLC configuration.

The 4x register entered in the middle node is the pointer to the source block. The
first register in the destination block is the next contiguous register after the pointer.
For example, if the pointer is register 400107, then the first register in the destination
block is 400108.
The value stored in the pointer indicates which block of data from the source table
will be copied to the destination block. This value specifies a block number within the
source table.
31007523 8/2010 1069

1070 31007523 8/2010

31007523 8/2010 1071

1072 31007523 8/2010

TEST: Test of 2 Values
31007523 8/2010
181
Introduction
This chapter describes the instruction TEST.

Topic Page
Representation 1075
31007523 8/2010 1073

Short Description
The TEST instruction compares the signed or unsigned size of the 16-bit values in
the top and middle nodes and describes the relationship via the block outputs.
1074 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = compares value 1 and value 2
value 1 3x, 4x INT, UINT Value 1, can be displayed explicitly as an
(top node) integer (range 1 ... 65 535) or stored in a
register
value 2 3x, 4x INT, UINT Value 2, can be displayed explicitly as an
(middle node) integer (range 1 ... 65 535) or stored in a
register
1 INT, UINT Constant value, cannot be changed
(bottom node)
31007523 8/2010 1075

1076 31007523 8/2010

UCTR: Up Counter
31007523 8/2010
UCTR: Up Counter
182
Introduction
This chapter describes the instruction UCTR.

Topic Page
Representation 1079
31007523 8/2010 1077

UCTR: Up Counter
Short Description
The UCTR instruction counts control input transitions from OFF to ON up from zero
to a counter preset value.
1078 31007523 8/2010

UCTR: Up Counter
Representation
Symbol

z E685/785 PLCs
z L785 PLCs

Reference
Top input 0x, 1x None OFF → ON = initiates the counter
operation
Bottom input 0x, 1x None OFF = reset accumulator to 0
ON = counter accumulating
counter preset 3x, 4x INT, UINT Preset value, can be displayed explicitly
(top node) as an integer or stored in a register
Preset value:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Max. 65535 785L
accumulated 4x INT, UINT Count value (actual value); which
count increments by one on each transition from
(bottom node) OFF to ON of the top input until it reaches
the specified counter preset value.
Top output 0x None ON = accumulated count = counter preset
Bottom output 0x None ON = accumulated count < counter preset
31007523 8/2010 1079

UCTR: Up Counter
1080 31007523 8/2010

VMER - VME Read
31007523 8/2010
VMER - VME Read
183
Introduction
This chapter describes the instruction VMER.

Topic Page
Representation 1083
31007523 8/2010 1081

VMER - VME Read
Short Description
The VME Read block allows the user to read data from devices on the VME bus. If
Byte Swap is active, the high byte is exchanged with the low byte of a word after it
is read from the VME bus. If Word Swap is enabled, the upper word is exchanged
with the lower word of a double after it is read. An error will occur if both inputs are
enabled at once.
1082 31007523 8/2010

VMER - VME Read
Representation
Symbol

Reference
Top input 0x, 1x None ON enables read
Middle input 0x, 1x None ON = byte swap
Bottom input 0x, 1x None ON = word swap
register 4x INT, UINT, There are five control registers in the top node. They are allotted as
(top node) WORD follows:
4x - VME Address modifier code (39, 3A, 3D, 3E, 29, or 2D
4x+1 to 4x+4 - The VME Control Block
(For expanded and detailed information please see the table named
VME Control Block, page 1084.)
pointer 4x INT, UINT A pointer to the first destination register.
(middle node) WORD (For expanded and detailed information please see the table named
Error Code Status, page 1084.)
value INT, UINT A constant specifying the number of destination registers to which
(bottom node) WORD data is transferred. This constant can be from 1 to 255.
Top output 0x None ON when the top input receives power
Middle output 0x None ON When an error occurs
Bottom output 0x None On when the read is complete
31007523 8/2010 1083

VMER - VME Read
VME Control Block

This is the VME control block.
Register Description
Displayed VME Address modifier code
First implied Error code status
Please see Error Code Status Table
Second implied Length of data to be read/written
Third implied VME Device address (low byte)
Fourth implied VME Device address (high byte)
Error Code Status

This is the Error Code Status table.
Error Description
01 Bad word count. Must be an even number of words
02 Bad length, greater than 255
03 Bad data length. Length was 0 or greater than 255
04 Bad address modifier in first control block
05 Bad command in top node of SWAP block
06 Bad VME bus interface
07 VME bus address doesn’t exist
08 VME 486 timeout
09 ME bus interface has not been configured
10 Both BYTE and WORD swap inputs have been selected
11 Match the type implied by the AM code (A16 or A2)
1084 31007523 8/2010

VMEW - VME Write
31007523 8/2010
VMEW - VME Write
184
Introduction
This chapter describes the instruction VMEW.

Topic Page
Representation 1087
31007523 8/2010 1085

VMEW - VME Write
Short Description
The VME Write block allows the user to write data to devices on the VME bus. If
BYTE SWAP is active, the high byte is exchanged with the low byte of a word before
it is written to the VME bus. If WORD SWAP is active, the upper word is exchanged
with the lower word of a double before it is written. An error will occur if both inputs
are enabled at once.
1086 31007523 8/2010

VMEW - VME Write
Representation
Symbol

Reference Type
Top input 0x, 1x None ON enables read
Middle input 0x, 1x None ON = byte swap
Bottom input 0x, 1x None ON = word swap
register 4x INT, UINT There are five control registers in the top node. They are allotted as
(top node) WORD follows:
4x - High Byte: VME Address modifier code (39, 3A, 3D, 3E, 29, or 2D
4x - Low Byte: Data bus size
4x + 1 to 4x + 4 - The VME Control Block
(For expanded and detailed information please see the table named
VME Control Block, page 1088.)
pointer 3x, 4x INT, UINT A pointer to the first destination register.
(middle node) WORD (For expanded and detailed information please see the table named
Error Code Status, page 1088.)
value INT, UINT A constant specifying the number of destination registers to which data
(bottom node) WORD is transferred. This can be from 1 to 255.
Top output 0x None ON when the top input receives power
Passes power when top input receives power
Middle output 0x None ON when an error occurs
Bottom output 0x None ON when write is complete
31007523 8/2010 1087

VMEW - VME Write
VME Control Block

This is the VME control block.
Register Description
Displayed VME Address modifier code
First implied Error code status
Please see Error Code Status Table
Second implied Length of data to be read/written
Third implied VME Device address (low byte)
Fourth implied VME Device address (high byte)
Error Code Status

This is the Error Code Status table.
Error Description
01 Bad word count. Must be an even number of words
02 Bad length, greater than 255
03 Bad data length. Length was 0 or greater than 255
04 Bad address modifier in first control block
05 Bad command in top node of SWAP block
06 Bad VME bus interface
07 VME bus address doesn’t exist
08 VME 486 timeout
09 ME bus interface has not been configured
10 Both BYTE and WORD swap inputs have been selected
11 Match the type implied by the AM code (A16 or A2)
1088 31007523 8/2010

WRIT: Write
31007523 8/2010
WRIT: Write
185
Introduction
This chapter describes the instruction WRIT.

Topic Page
Representation 1091
31007523 8/2010 1089

WRIT: Write
Short Description
The WRIT instruction sends a message from the PLC over the RIO communications
link to an ASCII display (screen, printer, etc.).
In the process of sending the messaging operation, WRIT performs the following
functions:
z Verifies the correctness of the ASCII communication parameters, e.g. the port
number, the message number
z Verifies the lengths of variable data fields
z Performs error detection and recording
z Reports RIO interface status
WRIT requires two tables of registers: a source table where variable data (the
message) is copied, and a control block where comm port and message parameters
are identified.
Further information about formatting messages you will find in Formatting Messages
for ASCII READ/WRIT Operations, page 57.
1090 31007523 8/2010

WRIT: Write
Representation
Symbol

Reference
Top input 0x, 1x None ON = initiates a WRIT
Middle input 0x, 1x None ON = pauses WRIT operation
Bottom input 0x, 1x None ON = abort WRIT operation
source (see page 1092) 3x, 4x INT, UINT, Source table
(top node) WORD
control block 4x INT, UINT, ASCII Control block (first of seven contiguous holding registers)
(see page 1092) WORD (For expanded and detailed information please see the section
(middle node) Control Block (Middle Node), page 1092.)
table length INT, UINT Length of source table (number of registers where the message
(bottom node) data will be stored), range: 1 ... 255
Middle output 0x None ON = error in communication or operation has timed out (for one
scan)
Bottom output 0x None ON = WRIT complete (for one scan)
31007523 8/2010 1091

WRIT: Write
Source Table (Top Node)

The top node contains the first 3x or 4x register in a source table whose length is
specified in the bottom node. This table contains the data required to fill the variable
field in a message.
Consider the following WRIT message
The 3-character ASCII field III is the variable data field; variable data are loaded,
typically via DX moves, into a table of variable field data.

The 4x register entered in the middle node is the first of seven contiguous holding
register in the control block.
Register Definition
Displayed Port Number and Error Code, page 1093
First implied Message number
Second implied Number of registers required to satisfy format
Third implied Count of the number of registers transmitted thus far
Fourth implied Status of the solve
Sixth implied Checksum of registers 0 ... 5
1092 31007523 8/2010

WRIT: Write

Bit Function
1 ... 4 PLC error code (see table below)
5 Not used
6 Input from the ASCII device not compatible with format
7 Input buffer overrun, data received too quickly at RIOP
8 USART error, bad byte received at RIOP
9 Illegal format, not received properly by RIOP
10 ASCII device off-line, check cabling
11 ASCII message terminated early (in keyboard mode
12 ... 16 Comm port # (1 ... 32)
PLC Error Code
Bit Meaning
1 2 3 4
0 0 0 1 Error in the input to RIOP from ASCII device
0 0 1 0 Exception response from RIOP, bad data
0 0 1 1 Sequenced number from RIOP differs from expected value
0 1 0 0 User register checksum error, often caused by altering
READ registers while the block is active
0 1 0 1 Invalid port or message number detected
0 1 1 0 User-initiated abort, bottom input energized
0 1 1 1 No response from drop, communication error
1 0 0 0 Node aborted because of SKP instruction
1 0 0 1 Message area scrambled, reload memory
1 0 1 0 Port not configured in the I/O map
1 0 1 1 Illegal ASCII request
1 1 0 0 Unknown response from ASCII port
1 1 0 1 Illegal ASCII element detected in user logic
1 1 1 1 RIOP in the PLC is down
31007523 8/2010 1093

WRIT: Write
1094 31007523 8/2010

XMIT - Transmit
31007523 8/2010
XMIT - Transmit
186
Introduction
This chapter describes the instruction XMIT - Transmit.

Topic Page
XMIT Modbus Functions 1097
31007523 8/2010 1095

XMIT - Transmit
Short Description
The XMIT (transmit) function block sends Modbus messages from a master PLC to
multiple slave PLCs or sends ASCII character strings from the PLC's Modbus slave
port#1 or port#2 to ASCII printers and terminals. XMIT sends these messages over
telephone dial up modems, radio modems, or simply direct connection.
For more detailed information on the XMIT function block, see the section named
XMIT Modbus Functions, page 1097.
XMIT comes with three modes: communication, port status, and conversion.
These modes are described in the following sections.
z XMIT Communication Block, page 1103
z XMIT Port Status Block, page 1115
z XMIT Conversion Block, page 1123
XMIT performs general ASCII input functions in the communication mode including
simple ASCII and terminated ASCII. You may use an additional XMIT block for
reporting port status information into registers while another XMIT block performs
the ASCII communication function. You may import and export ASCII or binary data
into your PLC and convert it into various binary data or ASCII to send to DCE
devices based upon the needs of your application.
The block has built in diagnostics, which ensure no other XMIT blocks are active in
the PLC. Within the XMIT block a control table allows you to control the
communications link between the PLC and Data Communication Equipment (DCE)
devices attached to Modbus port #1 or port#2 of the PLC. The XMIT block does not
activate the port LED when it's transmitting data.
NOTE: The Modbus protocol is a master/slave" protocol and designed to have only
one master when polling multiple slaves. Therefore, when using the XMIT block in
a network with multiple masters, contention resolution, and collision avoidance is
your responsibility and may easily be addressed through ladder logic programming.
1096 31007523 8/2010

XMIT - Transmit
XMIT Modbus Functions
At a Glance
The XMIT function block supports the following Modbus function codes:.
z 01 ... 06
z 08
z 15 and 16
z 20 and 21
For Modbus messages, the MSG_OUT array has to contain the Modbus definition
table. The Modbus definition table for Modbus function code: 01, 02, 03, 04, 05, 06,
15 and 16 is five registers long and you must set XMIT_SET.MessageLen to 5 for
successful XMIT operation. The Modbus definition table is shown in the table below
Modbus Function Codes 01...06

table. The Modbus definition table for Modbus function code: 01, 02, 03, 04, 05, 06,
15 and 16 is five registers long and you must set XMIT_SET.MessageLen to 5 for
successful XMIT operation. The Modbus definition table is shown in the table below
Modbus Definition Table Function Codes (01 ... 06, 15 and 16)
Content Description
Modbus XMIT supports the following function codes:
function code 01 = Read multiple coils (0x)
(MSG_OUT[1]) 02 = Read multiple discrete inputs (1x)
03 = Read multiple holding registers (4x)
04= Read multiple input registers (3x)
05 = Write single coil (0x)
06 = Write single holding registers (4x)
15 = Write multiple coils (0x)
16 = Write multiple holding registers (4x)
Quantity Enter the amount of data you want written to the slave PLC or read from
(MSG_OUT[2]) the slave PLC. For example, enter 100 to read 100 holding registers from
the slave PLC or enter 32 to write 32 coils to a slave PLC. There is a size
limitation on quantity that is dependent on the PLC model. Refer to
Appendix A for complete details on limits.
Slave PLC Enter the slave Modbus PLC address. Typically the Modbus address
address range is 1 ... 247. To send a Modbus message to multiple PLCs, enter 0
(MSG_OUT[3]) for the slave PLC address. This is referred to as Broadcast Mode.
Broadcast Mode only supports Modbus function codes that writes data
from the master PLC to slave PLCs. Broadcast Mode does NOT support
Modbus function codes that read data from slave PLCs.
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XMIT - Transmit
Content Description
Slave PLC data For a read command, the slave PLC data area is the source of the data.
area For a write command, the slave PLC data area is the destination for the
(MSG_OUT[4]) data. For example, when you want to read coils (00300 ... 00500) from a
slave PLC, enter 300 in this field. When you want to write data from a
master PLC and place it into register (40100) of a slave PLC, enter 100 in
this field. Depending on the type of Modbus command (write or read), the
source and destination data areas must be as defined in the Source and
Destination Data Areas table below.
Master PLC For a read command, the master PLC data area is the destination for the
data area data returned by the slave. For a write command, the master PLC data
(MSG_OUT[5]) area is the source of the data. For example, when you want to write coils
(00016 ... 00032) located in the master PLC to a slave PLC, enter 16 in the
field. When you want to read input registers (30001 ... 30100) from a slave
PLC and place the data into the master PLC data area (40100 ... 40199),
enter 100 in this field. Depending on the type of Modbus command (write
or read), the source and destination data areas must be as defined in the
Source and Destination Data Areas table below.
Source and Destination Data Areas for Function Codes (01 ... 06, 15 and 16)
Function Code Master PLC Data Area Slave PLC Data Area
03 (Read multiple 4x) 4x (destination) 4x (source)
16 (Write multiple 4x) 4x (source) 4x (destination)
15 (Write multiple 0x) 0x (source) 0x (destination)
05 (Write single 0x) 0x (source) 0x (destination)
06 (Write single 4x) 4x (source) 4x (destination)
When you want to send 20 Modbus messages out of the PLC, you must transfer 20
Modbus definition tables one after another into MSG_OUT after each successful
operation of XMIT, or you may program 20 separate XMIT blocks and then activate
them one at a time through user logic.
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XMIT - Transmit
Modbus Function Code (08)

The Modbus definition table for Modbus function code: 08 is five registers long and
you must you must set XMIT_SET.MessageLen to 5 for For Modbus messages, the
MSG_OUT array has to contain the Modbus definition successful XMIT operation.
The Modbus definition table is shown in the table below.
Modbus Definition Table Function Codes (08)
Content Description
Modbus function code XMIT supports the following function code: 08 = Diagnostics
(MSG_OUT[1])
Diagnostics Enter the diagnostics subfunction code decimal value in this filed to
(MSG_OUT[2]) perform the specific diagnostics function desired. The following
diagnostic subfunctions are supported:
Code Description
00 Return query data
01 Restart comm option
02 Return diagnostic register
03 Change ASCII input delimiter
04 Force listen only mode
05 ... 09 Reserved
10 Clear counters (& diagnostics registers in 384, 484)
11 Return bus messages count
12 Return bus comm error count
13 Return bus exception error count
14 ... 15 Not supported
16 Return slave NAK count
17 Return slave busy count
18 Return bus Char overrun count
19 ... 21 Not supported
Slave PLC address Enter the slave Modbus PLC address. Typically the Modbus
(MSG_OUT[3]) address range is 1 ... 247. Function code 8 dose NOT support
Broadcast Mode (Address 0)
Diagnostics function You must enter the decimal value needed for the data area of the
data field content specific diagnostic subfunction. For subfunctions 02, 04, 10, 11, 12,
(MSG_OUT[4]) 13, 16, 17 and 18 this value is automatically set to zero. For
subfunctions 00, 01, and 03 you must enter the desired data field
value. For more details, refer to Modicon Modbus Protocol
Reference Guide (PI-MBUS-300).
Master PLC data area For all subfunctions, the master PLC data area is the destination for
(MSG_OUT[5]) the data returned by the slave. You must specify a 4x register that
marks the beginning of the data area where the returned data is
placed. For example, to place the data into the master PLC data
area starting at (40100), enter 100 in this field. Subfunction 04 does
NOT return a response. For more details, refer to Modicon Modbus
Protocol Reference Guide (PI-MBUS-300).
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XMIT - Transmit
Modbus Function Codes (20, 21)

table. The Modbus definition table for Modbus function codes: 20 and 21 is six
registers long and you must you must set XMIT_SET.MessageLen to 6 for
successful XMIT operation. The Modbus definition table is shown in the table below.
Modbus Definition Table Function Codes (20, 21)
Content Description
Modbus function code XMIT supports the following function codes: 20 = Read general
(MSG_OUT[1]) reference (6x) 21 = Write general reference (6x)
Quantity (MSG_OUT[2]) Enter the amount of data you want written to the slave PLC or read
from the slave PLC. For example, enter 100 to read 100 holding
registers from the slave PLC or enter 32 to write 32 coils to a slave
PLC. There is a size limitation on quantity that is dependent on the
PLC model. Refer to Appendix A for complete details on limits.
Slave PLC address Enter the slave Modbus PLC address. Typically the Modbus
(MSG_OUT[3]) address range is 1 ... 247. Function code 20 and 21 do NOT
support Broadcast Mode (Address 0).
Slave PLC data area For a read command, the slave PLC data area is the source of the
(MSG_OUT[4]) data. For a write command, the slave PLC data area is the
destination for the data. For example, when you want to read
registers (600300 ... 600399) from a slave PLC, enter 300 in this
field. When you want to write data from a master PLC and place
it into register (600100) of a slave PLC, enter 100 in this field.
Depending on the type of Modbus command (write or read), the
source and destination data areas must be as defined in the
Source and Destination Data Areas table below. The lowest
extended register is addressed as register "zero" (600000). The
lowest holding register is addressed as register "one" (400001).
Master PLC data area For a read command, the master PLC data area is the destination
(MSG_OUT[5]) for the data returned by the slave. For a write command, the
master PLC data area is the source of the data. For example,
when you want to write registers (40016 ... 40032) located in the
master PLC to 6x registers in a slave PLC, enter 16 in the filed.
When you want to read 6x registers (600001 ... 600100) from a
slave PLC and place the data into the master PLC data area
(40100 ... 40199), enter 100 in this field. Depending on the type of
Modbus command (write or read), the source and destination data
areas must be as defined in the Source and Destination Data
Areas table below. The lowest extended register is addressed as
register "zero" (600000). The lowest holding register is addressed
as register "one" (400001).
File number Enter the file number for the 6x registers to be written to or read
(MSG_OUT[6]) from. (1 ... 10) depending on the size of the extended register data
area. 600001 is 60001 file 1 and 690001 is 60001 file 10 as viewed
by the Reference Data Editor.
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XMIT - Transmit
Source and Destination Data Areas for Function Codes (20, 21)
Function Code Master PLC Data Area Slave PLC Data Area
20 (Read general reference 6x) 4x (destination) 6x (source)
21 (Write general reference 6x) 4x (source) 6x (destination)
When you want to send 20 Modbus messages out of the PLC, you must transfer 20
Modbus definition tables one after another into MSG_OUT after each successful
operation of XMIT, or you may program 20 separate XMIT blocks and then activate
them one at a time through user logic.
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XMIT - Transmit
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XMIT Communication Block
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187
Introduction
This chapter describes the instruction XMIT Communication Block.

Topic Page
Representation 1105
31007523 8/2010 1103

Short Description
The purpose of the XMIT communication block is to receive and transmit ASCII
messages and Modbus Master messages using your PLC ports.
The XMIT instruction block will not operate correctly if:
z The NSUP and XMIT loadables are not installed
z The NSUP loadable is installed after the XMIT loadable
z The NSUP and XMIT loadables are installed in a Quantum PLC with an out-of-
date executive (older than version 2.10 or 2.12)
For an overview of the XMIT instruction please see Short Description, page 1096.
1104 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON begins an XMIT operation and START
should remain ON until the operation has
completed successfully or an error has
occurred.
Middle input 0x, 1x None ON aborts any active XMIT operation and
forces the port to slave mode. The abort
code (121) is placed into the fault status
register. The port remains closed as long
as this input is ON.
Note: To reset an XMIT fault and clear the
fault register, the top input must go OFF for
at least one PLC scan.
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Reference
port #0001 or 4x INT, UINT, The top node must contain one of the
#0002 WORD following constants either (#0001) to select
(top node) PLC port #1, or (#0002) to select PLC port
#2.
Note: The loadable version DOES accept
4xxxx registers in the top node, whereas
the built-in does NOT.
register 4x INT, UINT, The 4xxxx register entered in the middle
(middle node) WORD node is the first in a group of sixteen (16)
contiguous holding registers that comprise
the control block, as shown in the
Communication Control Table.
(For expanded and detailed information on
this node please see the Communication
Control Table, page 1107 in the Parameter
Description: Middle Node - XMIT
Communication Block.)
Important: DO NOT modify the address in
the middle node of the XMIT block or delete
the address from the block while the
program is active. This action locks up the
port preventing communications.
#0016 INT, UINT, The bottom node must contain a constant
(bottom node) WORD equal to (#0016). This is the number of
registers used by the XMIT instruction.
Top output 0x None ON while an XMIT operation in progress.
Passes power while an XMIT operation is in
progress.
Middle output 0x None ON when XMIT has detected an error or
was issued an abort.
Passes power when XMIT has detected an
error or when an XMIT operation was
aborted.
Bottom output 0x None ON for one scan only when an XMIT
operation has been successfully
completed.
Passes power when an XMIT operation has
been successfully completed.
Note: The START input must remain ON
until the OPERATION SUCCESSFUL has
turned OFF.
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Communication Control Table

This table represents the first in a group of 16 contiguous holding registers that
comprise the control block.
Register Name Description No Valid

Entries
4xxxx Revision Displays the current revision number of XMIT Read Only
Number block.
This number is automatically loaded by the block
and the block over writes any other number
entered into this register.
4xxxx + 1 Fault Status This field displays a fault code generated by the Read Only
XMIT port status block.
see the Fault Status Table, page 1111 in the
Parameter Description: XMIT Communication
Block section).
4xxxx + 2 Available to The XMIT block does not use this register. Read/Write
User However, it may be used in ladder logic as a
pointer. An efficient way to use the XMIT block is
to place a pointer value of a TBLK instruction into
this register.
4xxxx + 3 Data Rate XMIT supports the following data rates: 50, 75, Read/Write
110, 134, 150, 300, 600, 1200, 1800, 2000, 2400,
3600, 4800, 7200, 9600 and 19200.
To configure a data rate, enter its decimal number
into this field. When an invalid data rate is entered,
the block displays an illegal configuration error
(error code 127) in the Fault Status (4xxxx + 1)
register.
4xxxx + 4 Data Bits XMIT supports the following data bits: 7 and 8. Read/Write
To configure a data bit size, enter its decimal
number into this register.
Note: Modbus messages may be sent in ASCII
mode or RTU mode. ASCII mode requires 7 data
bits, while RTU mode requires 8 data bits. When
sending ASCII character message you may use
either 7 or 8 data bits. When an invalid data bit is
entered, the block displays an illegal configuration
error (error code 127) in the Fault Status (4xxxx +
1) register.
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Entries
4xxxx + 5 Parity Bits XMIT supports the following parity: none, odd and Read/Write
even. Enter a decimal of either: 0 = no parity, 1 =
odd parity, or 2 = even parity. When an invalid
parity is entered, the block displays an illegal
configuration error (error code 127) in the Fault
Status (4xxxx + 1) register.
4xxxx + 6 Stop Bits XMIT supports one or two stop bits. Enter a Read/Write
decimal of either: 1 = one stop bit, or 2 = two stop
bits. When an invalid stop bit is entered, the block
displays an illegal configuration error (error code
127) in the Fault Status (4xxxx + 1) register.
4xxxx + 7 Available to The XMIT block does not use this register. Read/Write
User However, it may be used in ladder logic as a
pointer. An efficient way to use the XMIT block is
to place a pointer value of a TBLK instruction into
this register.
4xxxx + 8 Command (16-digit binary number) Read/Write
Word The XMIT interprets each bit of the command word
as a function to perform. If bit 7 and 8 are on
simultaneously or if any two or more of bits 13, 14,
15 or 16 are on simultaneously or if bit 7 is not on
when bits 13, 14, 15, or 16 are on error 129 will be
generated.
For expanded and detailed information please see
the Command Word Communication Functions
Table, page 1113 in the Parameter Description:
XMIT Communications Block section.
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Entries
4xxxx + 9 Message (message pointer) Read/Write
Pointer Word Values are limited by the range of 4x registers
configured.
The message table consists of either
z ASCII characters
For ASCII character strings, the pointer is the
register offset to the first register of the ASCII
character string. Each register holds up to two
ASCII characters. Each ASCII string may be up
to 1024 characters in length. For example,
when you want to send 10 ASCII messages out
of the PLC, you must program 10 ASCII
characters strings into 4xxxx registers of the
PLC and then through ladder logic set the
pointer to the start of each message after each
successful operation of XMIT.
z Modbus Function Codes
For expanded and detailed information please
see the section XMIT Modbus Functions,
page 1097
Enter a pointer that points to the beginning of the
message table.
4xxxx + 10 Message (0 - 512) Read/Write
Length Enter the length of the current message. When
XMIT is sending Modbus messages for function
codes 01, 02, 03, 04, 05, 06, 08, 15 and 16, the
length of the message is automatically set to five.
When XMIT is receiving Terminated ASCII input
the length of the message must be set to five or an
error results. When XMIT is sending Modbus
messages for function codes twenty and twenty- -
one, the length of the message is automatically set
to six. When XMIT is sending ASCII messages, the
length may be 1 through 1024 ASCII characters
per message.
4xxxx + 11 Response (0 - 65535 milliseconds) Read/Write
Timeout (ms) Enter the time value in milliseconds (ms) to
determine how long XMIT waits for a valid
response message from a slave device (PLC,
modem, etc.). In addition, the time applies to ASCII
transmissions and flow control operations. When
the response message is not completely formed
within this specified time, XMIT issues a fault. The
valid range is 0 through 65535 ms. The timeout is
initiated after the last character in the message is
sent.
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Entries
4xxxx + 12 Retry Limit (0 - 65535 milliseconds) Read/Write
Enter the quantity of retries to determine how
many times XMIT sends a message to get a valid
response from a slave device (PLC, modem, etc.).
When the response message is not completely
formed within this specified time, XMIT issues a
fault and a fault code. The valid range is 0 ... 65535
# of retries. This field is used in conjunction with
response time-out (4xxxx + 11).
4xxxx + 13 Start of (0 - 65535 milliseconds) Read/Write
Transmission Enter the time value in milliseconds (ms) when
Delay (ms) RTS/CTS control is enabled, to determine how
long XMIT waits after CTS is received before it
transmits a message out of the PLC port #1. Also,
you may use this register even when RTS/CTS is
NOT in control. In this situation, the entered time
value determines how long XMIT waits before it
sends a message out of the PLC port #1. You may
use this as a pre message delay timer. The valid
range is 0 through 65535 ms.
4xxxx + 14 End of (0 - 65535 milliseconds) Read/Write
Transmission To determine how long XMIT keeps an RTS
Delay (ms) assertion once the message is sent out of the PLC
port #1, enter the time value in milliseconds (ms)
when RTS/CTS control is enabled, After the time
expires, XMIT ends the RTS assertion. Also, you
may use this register even when RTS/CTS is NOT
in control. In this situation, the entered time value
determines how long XMIT waits after it sends a
message out of the PLC port #1. You may use this
as a post message delay timer. The valid range is
0 through 65535 ms.
4xxxx + 15 Current Retry The value displayed here indicates the current Read Only
number of retry attempts made by the XMIT block
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Fault Status Table

The following is a list of the fault codes generated by the XMIT port status block
(4x + 1).
Fault Code Fault Description

1 Modbus exception -- Illegal function
2 Modbus exception -- Illegal data address
3 Modbus exception -- Illegal data value
4 Modbus exception -- Slave device failure
5 Modbus exception -- Acknowledge
6 Modbus exception -- Slave device busy
7 Modbus exception -- Negative acknowledge
8 Modbus exception -- Memory parity error
9 through 99 Reserved
100 Slave PLC data area cannot equal zero
101 Master PLC data area cannot equal zero
102 Coil (0x) not configured
103 Holding register (4xxxx) not configured
104 Data length cannot equal zero
105 Pointer to message table cannot equal zero
106 Pointer to message table is outside the range of configured holding registers
(4xxxx)
107 Transmit message timeout
(This error is generated when the UART cannot complete a transmission in
10 seconds or less. This error bypasses the retry counter and will activate the
error output on the first error.)
108 Undefined error
109 Modem returned ERROR
110 Modem returned NO CARRIER
111 Modem returned NO DIALTONE
112 Modem returned BUSY
113 Invalid LRC checksum from the slave PLC
114 Invalid CRC checksum from the slave PLC
115 Invalid Modbus function code
116 Modbus response message time-out
31007523 8/2010 1111


117 Modem reply timeout
118 XMIT could not gain access to PLC communications port #1 or port #2
119 XMIT could not enable PLC port receiver
120 XMIT could not set PLC UART
121 User issued an abort command
122 Top node of XMIT not equal to zero, one or two
123 Bottom node of XMIT is not equal to seven, eight or sixteen
124 Undefined internal state
125 Broadcast mode not allowed with this Modbus function code
126 DCE did not assert CTS
127 Illegal configuration (data rate, data bits, parity, or stop bits)
128 Unexpected response received from Modbus slave
129 Illegal command word setting
130 Command word changed while active
131 Invalid character count
132 Invalid register block
133 ASCII input FIFO overflow error
134 Invalid number of start characters or termination characters
1112 31007523 8/2010

Command Word Communication Functions Table

This table describes the function performed as XMIT interprets each bit of the
command word.
(4x + 8) Command Word Function Command word bits Command word bits
that must be set to 1 that must be set to 0
Terminated ASCII input (Bit 5=1) 2,3,9,10,11,12 6,7,8,13,14,15,16
Simple ASCII input (Bit 6=1) 2,3,9,10,11,12 5,7,8,13,14,15,16
Simple ASCII output (Bit 7=1) 2,3,9,10,11,12 5,6,8,13,14,15,16
Modem output (Bit 7=1) 2,3,13,14,15,16 5,6,8,9,10,11,12
(plus one, but ONLY
one, of the following bits
is set to 1: 13,14,15 or
16, while the other three
bits must be set to 0)
Modbus master messaging output 2,3 5,6,7,9,10,11,12,13,14,
(Bit 8=1) 15,16
Enable ASCII receive input FIFO ONLY 2,3,10,11,12 5,6,7,8,13,14,15,16
(Bit 9=1)
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1114 31007523 8/2010

XMIT Port Status Block
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188
Introduction
This chapter describes the instruction XMIT Port Status Block.

Topic Page
Representation 1117
31007523 8/2010 1115

Short Description
The XMIT port status block shows the current port status, Modbus slave activity,
ASCII input FIFO, and flow control information that may be used in ladder logic for
some applications. The XMIT port status block is totally passive. It does not take,
release, or control the PLC port.
For an overview of the XMIT instruction, please see Short Description, page 1096.
1116 31007523 8/2010

Representation
Symbol
31007523 8/2010 1117


Reference
Top input 0x, 1x None ON begins an XMIT operation and it should
remain ON until the operation has
occurred.
port #0001 or 4x INT, UINT Must contain one of the following constants
#0002 WORD either (#0001) to select PLC port #1, or
(top node) (#0002) to select PLC port #2.
Note: The loadable version DOES accept
4xxxx registers in the top node, whereas
the built-in does NOT.
(middle node) WORD node is the first in a group of seven (7)
the port status display block, as shown in
the Port Status Display Table, page 1119 in
the Parameter Description: Middle Node -
XMIT Conversion Block section.
the address from the block while the block
is active. This action locks up the port
preventing communications.
constant = INT, UINT, Must contain a constant equal to (#0007).
#0007 WORD This is the number of registers used by the
(bottom node) XMIT port status instruction.
Bottom output 0x None ON when an XMIT operation has been
successfully completed.
1118 31007523 8/2010

Overview
This topic provides detailed information relevant to the middle node. There are six
units in this topic.
z Port Status Display Table
z Fault Code Generation Table
z Status Generation Table
z Port Ownership Table
z Input FIFO Status Table
z Input FIFO Length Table
Port Status Display Table

This table represents the first in a group of seven contiguous holding registers that
comprise the port status block.

Entries
4xxxx Revision Displays the current revision number of XMIT Read Only
Number block.
This number is automatically loaded by the block
and the block over writes any other number
entered into this register.
4xxxx + 1 Fault Status This field displays a fault code generated by the Read Only
see the Fault Code Generation Table below.)
4xxxx + 2 Slave login This register displays the status of two items Read Only
status/ generated by the XMIT port status block.
Slave port The two items are the slave login status and the
active status slave port active status.
Ladder logic may be able to use this information to
reduce or avoid collisions on a multi master
Modbus network.
see the Status Generation Table below.
4xxxx + 3 Slave This register displays the number of slave Read Only
transaction transactions generated by the XMIT port status
counter block. The counter increases every time the PLC
Modbus slave port receives another command
from the Modbus master. Ladder logic may be able
to use this information to reduce or avoid collisions
on a multi master Modbus network.
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Entries
4xxxx + 4 Port State This register displays ownership of the port and its Read Only
state. It is generated by the XMIT port status block.
see the Port Ownership Table below.)
4xxxx + 5 Input FIFO The register displays the status of seven items Read Only
status bits related to the input FIFO. It is generated by the
see the Input FIFO Table below.)
4xxxx + 6 Input FIFO This register displays the current number of Read Only
length characters present in the ASCII input FIFO. The
register may contain other values based on the
state of the input FIFO and if the length is empty or
overflowing. It is generated by the XMIT port status
block.
see the Input FIFO Length Table below.
Fault Code Generation Table

This table describes the fault codes generated by the XMIT port status block in the
(4x + 1) register.

118 XMIT could not gain access to PLC communications port #1 or port #2.
122 Top node of XMIT not equal to zero, one or two.
123 Bottom node of XMIT is not equal to seven, eight or sixteen.
Status Generation Table

This table describes the slave login status and the slave port active status generated
by the XMIT port status block for the (4x + 2) register.
(4x + 2 high byte) (4x + 2 low byte)

Slave Login Status Slave Port Active Status
Yes - When a programming device is currently Yes - When observed port is owned by the
logged ON to this PLC slave port. PLC and currently receiving a Mod-bus
command or transmitting a Mod-bus
response.
No - When a programming device is currently No - When observed port is NOT owned by
NOT logged ON to this PLC slave port. the PLC and currently receiving Mod-bus
Note: A Modbus master can send commands command or transmitting a Mod-bus
but, not be logged ON response.
1120 31007523 8/2010

Port Ownership Table

This table describes the port’s ownership and state for the (4x + 4) register.
Owns Port Active State Value

PLC PLC Modbus slave 0
XMIT Tone dial modem 1
XMIT Hang up modem 2
XMIT Modbus messaging 3
XMIT Simple ASCII output 4
XMIT Pulse dial modem 5
XMIT Initialize modem 6
XMIT Simple ASCII input 7
XMIT Terminated ASCII input 8
XMIT ASCII input FIFO is ON, but no XMIT function is active 9
Input FIFO Status Table

This table describes the status bits related to the input FIFO for the (4x + 5) register.
Bit # Definition Yes / 1 No / 0

1-3 Reserved
4 Port owned by ... XMIT PLC
5-7 Reserved
8 ASCII output transmission ... Blocked by receiving Unblocked by receiving
device device
9 ASCII input received ... New character No new character
10 ASCII input FIFO is ... Empty Not empty
11 ASCII input FIFO is ... Overflowing (error) Not overflowing (error)
12 ASCII input FIFO is ... On Off
13 - 15 Reserved
16 ASCII input reception ... XMIT blocked sending XMIT unblocked
device sending device
31007523 8/2010 1121

Input FIFO Length Table

This table describes the current number of characters present in the ASCII input
FIFO for the (4x + 6) register.
WHEN Input FIFO THEN Length

= OFF =0
= ON and Empty =0
= ON and Overflowing = 512
1122 31007523 8/2010

XMIT Conversion Block
31007523 8/2010
189
Introduction
This chapter describes the instruction XMIT Conversion Block.

Topic Page
Representation 1125
31007523 8/2010 1123

Short Description
The purpose of the XMIT conversion block is to take data and convert it into other
usable forms based upon your application needs. The convert block performs 11
different functions or options. Some functions include ASCII to binary, integer to
ASCII, byte swapping, searching ASCII strings, and others. This block allows
internal conversions using 4xxxx source blocks to 4xxxx destination blocks.
For an overview of the XMIT instruction please see Short Description, page 1096.
1124 31007523 8/2010

Representation
Symbol
31007523 8/2010 1125


Reference
Top input 0x, 1x None ON begins an XMIT operation and it should
remain ON until the operation has
occurred.
Note: To reset an XMIT fault and clear the
fault register, the top input must go OFF for
at least one PLC scan.
constant #0001 4x INT, UINT The top node must contain a constant
(top node) WORD (#0000) since conversions do not deal with
the PLC’s port.
The loadable version DOES accept 4xxxx
registers in the top node, whereas the built-
in does NOT.
(middle node) WORD node is the first in a group of eight (8)
the control block, as shown in the
Conversion Block Control Table,
page 1127 found in the Parameter
Description: XMIT Conversion Block
section.
the address from the program while the
block is active. This action locks up the port
preventing communications.
constant = INT, UINT, The bottom node must contain a constant
#0008 WORD equal to (#0008). This is the number of
(bottom node) registers used by the XMIT conversion
instruction.
Bottom output 0x None ON when an XMIT operation has been
successfully completed.
1126 31007523 8/2010

Overview
This topic provides detailed information relevant to the middle node. There are four
units in this topic.
z Conversion Block Control Table
z Fault Code Generation Table
z Data Conversion Control Bits Table
z Data Conversion Opcodes Table
Conversion Block Control Table

This table represents the first in a group of eight contiguous holding registers that
comprise the port status block.

Entries
4xxxx XMIT Displays the current revision number of XMIT block. Read Only
Revision This number is automatically loaded by the block and
Number the block over writes any other number entered into
this register.
4xxxx + 1 Fault Status This field displays a fault code generated by the XMIT Read Only
port status block.
the Fault Code Generation Table below.)
4xxxx + 2 Available to 0 (May be used as pointers for instructions such as Read/Write
User TBLK.)
The XMIT conversion block does not use this
register. However, it may be used in ladder logic as a
pointer. An efficient way to use the XMIT block is to
place a pointer value of a TBLK instruction into this
register.
4xxxx + 3 Data This 16 bit word relates to the Data Conversion Read/Write
Conversion (4xxxx + 3) word. These bits provide additional
Control Bits control options based on which of the eleven
conversions you select.
Data Conversion Control Bits Table below.
4xxxx + 4 Data Select the type of conversion you want to perform Read/Write
Conversion from the list of eleven options listed in the Data
Opcodes Conversion Opcodes Table below.
After picking the type of conversion refer to Data
Conversion Control Bits (4xxxx + 4) and the Data
Conversion Control Bits Table for additional control
options that relate to the specific conversion type
selected.
31007523 8/2010 1127


Entries
4xxxx + 5 Source Enter the 4xxxx register desired. Read/Write
Register This is the first register in the source block that is
read. Ensure you select where you want the READ to
begin (high or low byte).
4xxxx + 6 Destination Enter the 4xxxx register desired. Read/Write
Register This is the first register in the source block that is
read. Ensure you select where you want the READ to
begin (high or low byte).
The selection beside this register in the DX zoom is
the same as bit16 in (4xxxx + 3).
4xxxx + 7 ASCII String Enter the search area. This register defines the Read/Write
Character search area.
Count When either automatic advance source (Bit 13) or
automatic advance destination (Bit 14) are ON and
no ASCII character is detected, the block
automatically adjusts the character count.
Fault Code Generation Table

This table describes the fault codes generated by the XMIT conversion block in the
(4x + 1) register.

122 Top node of XMIT is not equal to zero, one or two
123 Bottom node of XMIT is not equal to seven, eight or sixteen
131 Invalid character count
135 Invalid destination register block
136 Invalid source register block
137 No ASCII number present
138 Multiple sign characters present
139 Numerical overflow detected
140 String mismatch error
141 String not found
142 Invalid error check detected
143 Invalid conversion opcode
1128 31007523 8/2010

Data Conversion Control Bits Table

This table describes the control options available based upon the conversion
selected in the (4x + 3) register.
Bit # Definition 1= 0=
2 CRC 16 seed 0x0000 0xFFFF
3 Error check type LRC 8 CRC 16
4 Error check Validate Append
7 Conversion case Upper to Lower Lower to Upper
8 Case sensitivity No Yes
9 Format leading Zeros Blanks
10 Output format Fixed Variable
11 Conversion type Unsigned Signed
12 Conversion word 32-bit 16-bit
13 Automatic advance source pointer Yes No
(points to the next character after the
last character purged)
14 Automatic advance destination pointer Yes No
(points to the next character after the
last character purged)
15 Begin reading ASCII at source Low byte High byte (normal)
beginning with ...
16 Begin saving ASCII at destination Low byte High byte (normal)
beginning with ...
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Data Conversion Opcodes Table

This table describes the 11 functions or options for performing conversions using the
data conversion opcodes in the (4x + 4) register.
Opcode Action Data Type

(4xxxx block
Illegal opcode Displayed when Not applicable
illegal opcode is
detected.
(1 Hex) Converted to 16-bit or 32-bit signed or
Received ASCII decimal character unsigned binary integer
string
(2 Hex) Converted to 16-bit or 32-bit unsigned binary
Received ASCII hex character string integer
(3 Hex) Converted to 16-bit unsigned binary integer
Received ASCII hex character string array
(4 Hex) Converted to ASCII decimal character string
16-bit or 32-bit signed or unsigned for transmission
integer
(5 Hex) Converted to ASCII hex character string for
16-bit or 32-bit unsigned binary integer transmission
(6 Hex) Converted to ASCII hex character string for
16-bit unsigned integer array transmission
(7 Hex) Swapped to ASCII destination register block
High and low bytes from saved ASCII
source register block
(8 Hex) Copied to ASCII destination register block
ASCII string from source register block with or without case conversion
(9 Hex) Compared to ASCII string defined in
ASCII source register block destination register block with or
without case sensitivity
(10 Hex) Search for ASCII string defined in
ASCII source register block destination block with or without
case sensitivity
(11 Hex) Validated or ASCII string in source register
Error check 8-bit LRC or 16-bit CRC appended on block
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XMRD: Extended Memory Read
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190
Introduction
This chapter describes the instruction XMRD.

Topic Page
Representation 1133
31007523 8/2010 1131

Short Description
The XMRD instruction is used to copy a table of 6x extended memory registers to a
table of 4x holding registers in state RAM.
1132 31007523 8/2010

Representation
Symbol

Reference
Top input 0x, 1x None ON = activates read operation
Middle input 0x, 1x None OFF = clears offset to 0
ON = does not clear offset
Bottom input 0x, 1x None OFF = abort on error
ON = do not abort on error
control block 4x INT, UINT, First of six contiguous holding registers in the
(see page 1134) WORD extended memory
(top node) (For expanded and detailed information please
see the section Control Block (Top Node),
page 1134.)
destination 4x INT, UINT, The first 4x holding register in a table of
(middle node) WORD registers that receive the transferred data from
the 6x extended memory storage registers
1 INT, UINT Contains the constant value 1, which cannot be
(bottom node) changed
Top output 0x None Read transfer active
Middle output 0x None Error condition detected
Bottom output 0x None ON = operation complete
31007523 8/2010 1133


The 4x register entered in the top node is the first of six contiguous holding registers
in the extended memory control block.
Reference Register Name Description

Displayed status word Contains the diagnostic information about extended
memory (see Status Word of the Control Block,
page 1135)
First implied file number Specifies which of the extended memory files is
currently in use (range: 1 ... 10)
Second start address Specifies which 6x storage register in the current file is
implied the starting address; 0 = 60000, 9999 = 69999
Third implied count Specifies the number of registers to be read or written in
a scan when the appropriate function block is powered;
range: 0 ... 9999, not to exceed number specified in max
registers (fifth implied)
Fourth implied offset Keeps a running total of the number of registers
transferred thus far
Fifth implied max registers Specifies the maximum number of registers that may be
transferred when the function block is powered (range:
0 ... 9999)
If you are in multi-scan mode, these six registers should be unique to this function
block.
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Status Word of the Control Block

Bit Function
1 1 = power-up diagnostic error
2 1 = parity error in extended memory
3 1 = extended memory does not exist
4 0 = transfer not running
1 = busy
5 0 = transfer in progress
1 = transfer complete
6 1 = file boundary crossed
7 1 = offset parameter too large
8-9 Not used
10 1 = nonexistent state RAM
11 Not used
12 1 = maximum registers parameter error
13 1 = offset parameter error
14 1 = count parameter error
15 1 = starting address parameter error
16 1 = file number parameter error
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1136 31007523 8/2010

XMWT: Extended Memory Write
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191
Introduction
This chapter describes the instruction XMWT.

Topic Page
Representation 1139
31007523 8/2010 1137

Short Description
The XMWT instruction is used to write data from a block of input registers or holding
registers in state RAM to a block of 6x registers in an extended memory file.
1138 31007523 8/2010

Representation
Symbol

Reference Type
Top input 0x, 1x None ON = activates write operation
Middle input 0x, 1x None OFF = clears offset to 0
ON = does not clear offset
Bottom input 0x, 1x None OFF = abort on error
ON = do not abort on error
source 3x, 4x INT, The first 3x or 4x register in a block of contiguous
(top node) UINT, source registers, i.e. input or holding registers,
WORD whose contents will be written to 6x extended
memory registers
control block 4x INT, First of six contiguous holding registers in the
(see page 1140) UINT, extended memory
(middle node) WORD (For expanded and detailed information please see
the section Control Block (Middle Node),
page 1140.)
1 INT, Contains the constant value 1, which cannot be
(bottom node) UINT changed
Top output 0x None Write transfer active
Middle output 0x None Error condition detected
Bottom output 0x None ON = operation complete
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The 4x register entered in the middle node is the first of six contiguous holding
registers in the extended memory control block.
Reference Register Name Description

Displayed status word Contains the diagnostic information about extended
memory (see Status Word of the Control Block,
page 1141)
First implied file number Specifies which of the extended memory files is
currently in use (range: 1 ... 10)
Second start address Specifies which 6x storage register in the current file is
implied the starting address; 0 = 60000, 9999 = 69999
Third implied count Specifies the number of registers to be read or written in
a scan when the appropriate function block is powered;
range: 0 ... 9999, not to exceed number specified in max
registers (fifth implied)
Fourth implied offset Keeps a running total of the number of registers
transferred thus far
Fifth implied max registers Specifies the maximum number of registers that may be
transferred when the function block is powered (range:
0 ... 9999)
If you are in multi-scan mode, these six registers should be unique to this function
block.
1140 31007523 8/2010


Bit Function
1 1 = power-up diagnostic error
2 1 = parity error in extended memory
3 1 = extended memory does not exist
4 0 = transfer not running
1 = busy
5 0 = transfer in progress
1 = transfer complete
6 1 = file boundary crossed
7 1 = offset parameter too large
8-9 Not used
10 1 = nonexistent state RAM
11 Not used
12 1 = maximum registers parameter error
13 1 = offset parameter error
14 1 = count parameter error
15 1 = starting address parameter error
16 1 = file number parameter error
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1142 31007523 8/2010

XOR: Exclusive OR
31007523 8/2010
XOR: Exclusive OR
192
Introduction
This chapter describes the instruction XOR.

Topic Page
Representation 1145
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XOR: Exclusive OR
Short Description
WARNING
XOR will override any disabled coils within the destination matrix without en-
abling them.
This can cause personal injury if a coil has disabled an operation for maintenance
or repair because the coil’s state can be changed by the XOR operation.
equipment damage.
The XOR instruction performs a Boolean Exclusive OR operation on the bit patterns
in the source and destination matrices.
The XORed bit pattern is then posted in the destination matrix, overwriting its
previous contents:
1144 31007523 8/2010

XOR: Exclusive OR
Representation
Symbol

Reference
Top input 0x, 1x None Initiates XOR
source matrix 0x, 1x, 3x, 4x BOOL, First reference in the source matrix
(top node) WORD
destination 0x, 4x BOOL, First reference in the destination matrix
matrix WORD
(middle node)
length INT, UINT Matrix length; range 1 ... 100 registers.
(bottom node)
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XOR: Exclusive OR
An XOR Example
When contact 10001 passes power, the source matrix formed by the bit pattern in
registers 40600 and 40601 is XORed with the destination matrix formed by the bit
pattern in registers 40608 and 40609, overwriting the original destination bit pattern.
NOTE: If you want to reatin the original destination bit pattern of registers 40608 and
40609, copy the information into another table using a BLKIM before performing the
XOR operation.
1146 31007523 8/2010

XOR: Exclusive OR

1 ... 100. A length of 2 indicates that 32 bits in each matrix will be XORed.
31007523 8/2010 1147

XOR: Exclusive OR
1148 31007523 8/2010

Glossary
31007523 8/2010
Glossary
active window
The window, which is currently selected. Only one window can be active at any one
given time. When a window is active, the heading changes color, in order to
distinguish it from other windows. Unselected windows are inactive.
Actual parameter
Currently connected Input/Output parameters.
Addresses
(Direct) addresses are memory areas on the PLC. These are found in the State RAM
and can be assigned input/output modules.
The display/input of direct addresses is possible in the following formats:
z Standard format (400001)
z Separator format (4:00001)
z Compact format (4:1)
z IEC format (QW1)
ANL_IN
ANL_IN stands for the data type "Analog Input" and is used for processing analog
values. The 3x References of the configured analog input module, which is specified
in the I/O component list is automatically assigned the data type and should
therefore only be occupied by Unlocated variables.
31007523 8/2010 1149

Glossary
ANL_OUT
ANL_OUT stands for the data type "Analog Output" and is used for processing
analog values. The 4x-References of the configured analog output module, which is
specified in the I/O component list is automatically assigned the data type and
should therefore only be occupied by Unlocated variables.
ANY
In the existing version "ANY" covers the elementary data types BOOL, BYTE, DINT,
INT, REAL, UDINT, UINT, TIME and WORD and therefore derived data types.
ANY_BIT
In the existing version, "ANY_BIT" covers the data types BOOL, BYTE and WORD.
ANY_ELEM
In the existing version "ANY_ELEM" covers the elementary data types BOOL,
BYTE, DINT, INT, REAL, UDINT, UINT, TIME and WORD.
ANY_INT
In the existing version, "ANY_INT" covers the data types DINT, INT, UDINT and
UINT.
ANY_NUM
In the existing version, "ANY_NUM" covers the data types DINT, INT, REAL, UDINT
and UINT.
ANY_REAL
In the existing version "ANY_REAL" covers the data type REAL.
Application window
The window, which contains the working area, the menu bar and the tool bar for the
application. The name of the application appears in the heading. An application
window can contain several document windows. In Concept the application window
corresponds to a Project.
Argument
Synonymous with Actual parameters.
1150 31007523 8/2010

Glossary
ASCII mode
American Standard Code for Information Interchange. The ASCII mode is used for
communication with various host devices. ASCII works with 7 data bits.
Atrium
The PC based controller is located on a standard AT board, and can be operated
within a host computer in an ISA bus slot. The module occupies a motherboard
(requires SA85 driver) with two slots for PC104 daughter boards. From this, a
PC104 daughter board is used as a CPU and the others for INTERBUS control.
Back up data file (Concept EFB)

The back up file is a copy of the last Source files. The name of this back up file is
"backup??.c" (it is accepted that there are no more than 100 copies of the source
files. The first back up file is called "backup00.c". If changes have been made on the
Definition file, which do not create any changes to the interface in the EFB, there is
no need to create a back up file by editing the source files (Objects → Source). If
a back up file can be assigned, the name of the source file can be given.
Base 16 literals
Base 16 literals function as the input of whole number values in the hexadecimal
system. The base must be denoted by the prefix 16#. The values may not be
preceded by signs (+/-). Single underline signs ( _ ) between figures are not
significant.
Example
16#F_F or 16#FF (decimal 255)
16#E_0 or 16#E0 (decimal 224)
Base 8 literal
Base 8 literals function as the input of whole number values in the octal system. The
base must be denoted by the prefix 3.63kg. The values may not be preceded by
signs (+/-). Single underline signs ( _ ) between figures are not significant.
Example
8#3_1111 or 8#377 (decimal 255)
8#34_1111 or 8#340 (decimal 224)
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Glossary
Basis 2 literals
Base 2 literals function as the input of whole number values in the dual system. The
base must be denoted by the prefix 0.91kg. The values may not be preceded by
Example
2#1111_1111 or 2#11111111 (decimal 255)
2#1110_1111 or 2#11100000 (decimal 224)
Binary connections
Connections between outputs and inputs of FFBs of data type BOOL.
Bit sequence
A data element, which is made up from one or more bits.
BOOL
BOOL stands for the data type "Boolean". The length of the data elements is 1 bit
(in the memory contained in 1 byte). The range of values for variables of this type is
0 (FALSE) and 1 (TRUE).
Bridge
A bridge serves to connect networks. It enables communication between nodes on
the two networks. Each network has its own token rotation sequence – the token is
not deployed via bridges.
BYTE
BYTE stands for the data type "Bit sequence 8". The input appears as Base 2 literal,
Base 8 literal or Base 1 16 literal. The length of the data element is 8 bit. A numerical
range of values cannot be assigned to this data type.
Cache
The cache is a temporary memory for cut or copied objects. These objects can be
inserted into sections. The old content in the cache is overwritten for each new Cut
or Copy.
1152 31007523 8/2010

Glossary
Call up
The operation, by which the execution of an operation is initiated.
Coil
A coil is a LD element, which transfers (without alteration) the status of the horizontal
link on the left side to the horizontal link on the right side. In this way, the status is
saved in the associated Variable/ direct address.
Compact format (4:1)

The first figure (the Reference) is separated from the following address with a colon
(:), where the leading zero are not entered in the address.
Connection
A check or flow of data connection between graphic objects (e.g. steps in the SFC
editor, Function blocks in the FBD editor) within a section, is graphically shown as a
line.
Constants
Constants are Unlocated variables, which are assigned a value that cannot be
altered from the program logic (write protected).
Contact
A contact is a LD element, which transfers a horizontal connection status onto the
right side. This status is from the Boolean AND- operation of the horizontal
connection status on the left side with the status of the associated Variables/direct
Address. A contact does not alter the value of the associated variables/direct
address.
Data transfer settings

Settings, which determine how information from the programming device is
transferred to the PLC.
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Glossary
Data types
The overview shows the hierarchy of data types, as they are used with inputs and
outputs of Functions and Function blocks. Generic data types are denoted by the
prefix "ANY".
z ANY_ELEM
z ANY_NUM
ANY_REAL (REAL)
ANY_INT (DINT, INT, UDINT, UINT)
z ANY_BIT (BOOL, BYTE, WORD)
z TIME
z System data types (IEC extensions)

z Derived (from "ANY" data types)
DCP I/O station

With a Distributed Control Processor (D908) a remote network can be set up with a
parent PLC. When using a D908 with remote PLC, the parent PLC views the remote
PLC as a remote I/O station. The D908 and the remote PLC communicate via the
system bus, which results in high performance, with minimum effect on the cycle
time. The data exchange between the D908 and the parent PLC takes place at 1.5
Megabits per second via the remote I/O bus. A parent PLC can support up to 31
(Address 2-32) D908 processors.
DDE (Dynamic Data Exchange)

The DDE interface enables a dynamic data exchange between two programs under
Windows. The DDE interface can be used in the extended monitor to call up its own
display applications. With this interface, the user (i.e. the DDE client) can not only
read data from the extended monitor (DDE server), but also write data onto the PLC
via the server. Data can therefore be altered directly in the PLC, while it monitors
and analyzes the results. When using this interface, the user is able to make their
own "Graphic-Tool", "Face Plate" or "Tuning Tool", and integrate this into the
system. The tools can be written in any DDE supporting language, e.g. Visual Basic
and Visual-C++. The tools are called up, when the one of the buttons in the dialog
box extended monitor uses Concept Graphic Tool: Signals of a projection can be
displayed as timing diagrams via the DDE connection between Concept and
Concept Graphic Tool.
Decentral Network (DIO)

A remote programming in Modbus Plus network enables maximum data transfer
performance and no specific requests on the links. The programming of a remote
net is easy. To set up the net, no additional ladder diagram logic is needed. Via
corresponding entries into the Peer Cop processor all data transfer requests are
met.
1154 31007523 8/2010

Glossary
Declaration
Mechanism for determining the definition of a Language element. A declaration
normally covers the connection of an Identifier with a language element and the
assignment of attributes such as Data types and algorithms.
Definition data file (Concept EFB)

The definition file contains general descriptive information about the selected FFB
and its formal parameters.
Derived data type

Derived data types are types of data, which are derived from the Elementary data
types and/or other derived data types. The definition of the derived data types
appears in the data type editor in Concept.
Distinctions are made between global data types and local data types.
Derived Function Block (DFB)

A derived function block represents the Call up of a derived function block type.
Details of the graphic form of call up can be found in the definition " Function block
(Item)". Contrary to calling up EFB types, calling up DFB types is denoted by double
vertical lines on the left and right side of the rectangular block symbol.
The body of a derived function block type is designed using FBD language, but only
in the current version of the programming system. Other IEC languages cannot yet
be used for defining DFB types, nor can derived functions be defined in the current
version.
Distinctions are made between local and global DFBs.
DINT
DINT stands for the data type "double integer". The input appears as Integer literal,
Base 2 literal, Base 8 literal or Base 16 literal. The length of the data element is 32
bit. The range of values for variables of this data type is from –2 exp (31) to 2 exp
(31) –1.
Direct display
A method of displaying variables in the PLC program, from which the assignment of
configured memory can be directly and indirectly derived from the physical memory.
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Glossary
Document window
A window within an Application window. Several document windows can be opened
at the same time in an application window. However, only one document window
can be active. Document windows in Concept are, for example, sections, the
message window, the reference data editor and the PLC configuration.
Dummy
An empty data file, which consists of a text header with general file information, i.e.
author, date of creation, EFB identifier etc. The user must complete this dummy file
with additional entries.
DX Zoom
This property enables connection to a programming object to observe and, if
necessary, change its data value.
Elementary functions/function blocks (EFB)

Identifier for Functions or Function blocks, whose type definitions are not formulated
in one of the IEC languages, i.e. whose bodies, for example, cannot be modified with
the DFB Editor (Concept-DFB). EFB types are programmed in "C" and mounted via
Libraries in precompiled form.
EN / ENO (Enable / Error display)

If the value of EN is "0" when the FFB is called up, the algorithms defined by the FFB
are not executed and all outputs contain the previous value. The value of ENO is
automatically set to "0" in this case. If the value of EN is "1" when the FFB is called
up, the algorithms defined by the FFB are executed. After the error free execution of
the algorithms, the ENO value is automatically set to "1". If an error occurs during
the execution of the algorithm, ENO is automatically set to "0". The output behavior
of the FFB depends whether the FFBs are called up without EN/ENO or with EN=1.
If the EN/ENO display is enabled, the EN input must be active. Otherwise, the FFB
is not executed. The projection of EN and ENO is enabled/disabled in the block
properties dialog box. The dialog box is called up via the menu commands Objects
→ Properties... or via a double click on the FFB.
Error
When processing a FFB or a Step an error is detected (e.g. unauthorized input value
or a time error), an error message appears, which can be viewed with the menu
command Online → Event display... . With FFBs the ENO output is set to "0".
1156 31007523 8/2010

Glossary
Evaluation
The process, by which a value for a Function or for the outputs of a Function block
during the Program execution is transmitted.
Expression
Expressions consist of operators and operands.
FFB (functions/function blocks)

Collective term for EFB (elementary functions/function blocks) and DFB (derived
function blocks)
Field variables
Variables, one of which is assigned, with the assistance of the key word ARRAY
(field), a defined Derived data type. A field is a collection of data elements of the
same Data type.
FIR filter
Finite Impulse Response Filter
Formal parameters
Input/Output parameters, which are used within the logic of a FFB and led out of the
FFB as inputs/outputs.
Function (FUNC)
A Program organization unit, which exactly supplies a data element when executing.
A function has no internal status information. Multiple call ups of the same function
with the same input parameter values always supply the same output values.
Details of the graphic form of function call up can be found in the definition " Function
block (Item)". In contrast to the call up of function blocks, the function call ups only
have one unnamed output, whose name is the name of the function itself. In FBD
each call up is denoted by a unique number over the graphic block; this number is
automatically generated and cannot be altered.
31007523 8/2010 1157

Glossary
Function block (item) (FB)

A function block is a Program organization unit, which correspondingly calculates
the functionality values, defined in the function block type description, for the output
and internal variables, when it is called up as a certain item. All output values and
internal variables of a certain function block item remain as a call up of the function
block until the next. Multiple call up of the same function block item with the same
arguments (Input parameter values) supply generally supply the same output
value(s).
Each function block item is displayed graphically by a rectangular block symbol. The
name of the function block type is located on the top center within the rectangle. The
name of the function block item is located also at the top, but on the outside of the
rectangle. An instance is automatically generated when creating, which can
however be altered manually, if required. Inputs are displayed on the left side and
outputs on the right of the block. The names of the formal input/output parameters
are displayed within the rectangle in the corresponding places.
The above description of the graphic presentation is principally applicable to
Function call ups and to DFB call ups. Differences are described in the
corresponding definitions.
Function block dialog (FBD)

One or more sections, which contain graphically displayed networks from Functions,
Function blocks and Connections.
Function block type

A language element, consisting of: 1. the definition of a data structure, subdivided
into input, output and internal variables, 2. A set of operations, which is used with
the elements of the data structure, when a function block type instance is called up.
This set of operations can be formulated either in one of the IEC languages (DFB
type) or in "C" (EFB type). A function block type can be instanced (called up) several
times.
Function counter
The function counter serves as a unique identifier for the function in a Program or
DFB. The function counter cannot be edited and is automatically assigned. The
function counter always has the structure: .n.m
n = Section number (number running)
m = Number of the FFB object in the section (number running)
1158 31007523 8/2010

Glossary
Generic data type

A Data type, which stands in for several other data types.
Generic literal
If the Data type of a literal is not relevant, simply enter the value for the literal. In this
case Concept automatically assigns the literal to a suitable data type.
Global derived data types

Global Derived data types are available in every Concept project and are contained
in the DFB directory directly under the Concept directory.
Global DFBs
Global DFBs are available in every Concept project and are contained in the DFB
directory directly under the Concept directory.
Global macros
Global Macros are available in every Concept project and are contained in the DFB
directory directly under the Concept directory.
Groups (EFBs)
Some EFB libraries (e.g. the IEC library) are subdivided into groups. This facilitates
the search for FFBs, especially in extensive libraries.
I/O component list

The I/O and expert assemblies of the various CPUs are configured in the I/O
component list.
IEC 61131-3
International norm: Programmable controllers – part 3: Programming languages.
31007523 8/2010 1159

Glossary
IEC format (QW1)

In the place of the address stands an IEC identifier, followed by a five figure address:
z %0x12345 = %Q12345
z %1x12345 = %I12345
z %3x12345 = %IW12345
z %4x12345 = %QW12345
IEC name conventions (identifier)

An identifier is a sequence of letters, figures, and underscores, which must start with
a letter or underscores (e.g. name of a function block type, of an item or section).
Letters from national sets of characters (e.g. ö,ü, é, õ) can be used, taken from
project and DFB names.
Underscores are significant in identifiers; e.g. "A_BCD" and "AB_CD" are
interpreted as different identifiers. Several leading and multiple underscores are not
authorized consecutively.
Identifiers are not permitted to contain space characters. Upper and/or lower case
is not significant; e.g. "ABCD" and "abcd" are interpreted as the same identifier.
Identifiers are not permitted to be Key words.
IIR filter
Infinite Impulse Response Filter
Initial step (starting step)

The first step in a chain. In each chain, an initial step must be defined. The chain is
started with the initial step when first called up.
Initial value
The allocated value of one of the variables when starting the program. The value
assignment appears in the form of a Literal.
Input bits (1x references)

The 1/0 status of input bits is controlled via the process data, which reaches the CPU
from an entry device.
NOTE: The x, which comes after the first figure of the reference type, represents a
five figure storage location in the application data store, i.e. if the reference 100201
signifies an input bit in the address 201 of the State RAM.
Input parameters (Input)

When calling up a FFB the associated Argument is transferred.
1160 31007523 8/2010

Glossary
Input words (3x references)

An input word contains information, which come from an external source and are
represented by a 16 bit figure. A 3x register can also contain 16 sequential input bits,
which were read into the register in binary or BCD (binary coded decimal) format.
Note: The x, which comes after the first figure of the reference type, represents a
five figure storage location in the user data store, i.e. if the reference 300201
signifies a 16 bit input word in the address 201 of the State RAM.
Instantiation
The generation of an Item.
Instruction (984LL)
When programming electric controllers, the task of implementing operational coded
instructions in the form of picture objects, which are divided into recognizable
contact forms, must be executed. The designed program objects are, on the user
level, converted to computer useable OP codes during the loading process. The OP
codes are deciphered in the CPU and processed by the controller’s firmware
functions so that the desired controller is implemented.
Instruction (IL)
Instructions are "commands" of the IL programming language. Each operation
begins on a new line and is succeeded by an operator (with modifier if needed) and,
if necessary for each relevant operation, by one or more operands. If several
operands are used, they are separated by commas. A tag can stand before the
instruction, which is followed by a colon. The commentary must, if available, be the
last element in the line.
Instruction list (IL)

IL is a text language according to IEC 1131, in which operations, e.g.
conditional/unconditional call up of Function blocks and Functions,
conditional/unconditional jumps etc. are displayed through instructions.
INT
INT stands for the data type "whole number". The input appears as Integer literal,
Base 2 literal, Base 8 literal or Base 16 literal. The length of the data element is 16
bit. The range of values for variables of this data type is from –2 exp (15) to 2 exp
(15) –1.
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Glossary
Integer literals
Integer literals function as the input of whole number values in the decimal system.
The values may be preceded by the signs (+/-). Single underline signs ( _ ) between
figures are not significant.
Example
-12, 0, 123_456, +986
INTERBUS (PCP)
To use the INTERBUS PCP channel and the INTERBUS process data
preprocessing (PDP), the new I/O station type INTERBUS (PCP) is led into the
Concept configurator. This I/O station type is assigned fixed to the INTERBUS
connection module 180-CRP-660-01.
The 180-CRP-660-01 differs from the 180-CRP-660-00 only by a clearly larger I/O
area in the state RAM of the controller.
Item name
An Identifier, which belongs to a certain Function block item. The item name serves
as a unique identifier for the function block in a program organization unit. The item
name is automatically generated, but can be edited. The item name must be unique
throughout the Program organization unit, and no distinction is made between
upper/lower case. If the given name already exists, a warning is given and another
name must be selected. The item name must conform to the IEC name conventions,
otherwise an error message appears. The automatically generated instance name
always has the structure: FBI_n_m
FBI = Function block item
m = Number of the FFB object in the section (number running)
Jump
Element of the SFC language. Jumps are used to jump over areas of the chain.
1162 31007523 8/2010

Glossary
Key words
Key words are unique combinations of figures, which are used as special syntactic
elements, as is defined in appendix B of the IEC 1131-3. All key words, which are
used in the IEC 1131-3 and in Concept, are listed in appendix C of the IEC 1131-3.
These listed keywords cannot be used for any other purpose, i.e. not as variable
names, section names, item names etc.
Ladder Diagram (LD)

Ladder Diagram is a graphic programming language according to IEC1131, which
optically orientates itself to the "rung" of a relay ladder diagram.
Ladder Logic 984

In the terms Ladder Logic and Ladder Diagram, the word Ladder refers to execution.
In contrast to a diagram, a ladder logic is used by engineers to draw up a circuit (with
assistance from electrical symbols),which should chart the cycle of events and not
the existing wires, which connect the parts together. A usual user interface for
controlling the action by automated devices permits ladder logic interfaces, so that
when implementing a control system, engineers do not have to learn any new
programming languages, with which they are not conversant.
The structure of the actual ladder logic enables electrical elements to be linked in a
way that generates a control output, which is dependant upon a configured flow of
power through the electrical objects used, which displays the previously demanded
condition of a physical electric appliance.
In simple form, the user interface is one of the video displays used by the PLC
programming application, which establishes a vertical and horizontal grid, in which
the programming objects are arranged. The logic is powered from the left side of the
grid, and by connecting activated objects the electricity flows from left to right.
Landscape format
Landscape format means that the page is wider than it is long when looking at the
printed text.
Language element
Each basic element in one of the IEC programming languages, e.g. a Step in SFC,
a Function block item in FBD or the Start value of a variable.
31007523 8/2010 1163

Glossary
Library
Collection of software objects, which are provided for reuse when programming new
projects, or even when building new libraries. Examples are the Elementary function
block types libraries.
EFB libraries can be subdivided into Groups.
Literals
Literals serve to directly supply values to inputs of FFBs, transition conditions etc.
These values cannot be overwritten by the program logic (write protected). In this
way, generic and standardized literals are differentiated.
Furthermore literals serve to assign a Constant a value or a Variable an Initial value.
The input appears as Base 2 literal, Base 8 literal, Base 16 literal, Integer literal, Real
literal or Real literal with exponent.
Local derived data types

Local derived data types are only available in a single Concept project and its local
DFBs and are contained in the DFB directory under the project directory.
Local DFBs
Local DFBs are only available in a single Concept project and are contained in the
DFB directory under the project directory.
Local link
The local network link is the network, which links the local nodes with other nodes
either directly or via a bus amplifier.
Local macros
Local Macros are only available in a single Concept project and are contained in the
DFB directory under the project directory.
Local network nodes

The local node is the one, which is projected evenly.
1164 31007523 8/2010

Glossary
Located variable
Located variables are assigned a state RAM address (reference addresses 0x,1x,
3x, 4x). The value of these variables is saved in the state RAM and can be altered
online with the reference data editor. These variables can be addressed by symbolic
names or the reference addresses.
Collective PLC inputs and outputs are connected to the state RAM. The program
access to the peripheral signals, which are connected to the PLC, appears only via
located variables. PLC access from external sides via Modbus or Modbus plus
interfaces, i.e. from visualizing systems, are likewise possible via located variables.
Macro
Macros are created with help from the software Concept DFB.
Macros function to duplicate frequently used sections and networks (including the
logic, variables, and variable declaration).
Distinctions are made between local and global macros.
Macros have the following properties:
z Macros can only be created in the programming languages FBD and LD.
z Macros only contain one single section.
z Macros can contain any complex section.
z From a program technical point of view, there is no differentiation between an
instanced macro, i.e. a macro inserted into a section, and a conventionally
created macro.
z Calling up DFBs in a macro
z Variable declaration
z Use of macro-own data structures
z Automatic acceptance of the variables declared in the macro
z Initial value for variables
z Multiple instancing of a macro in the whole program with different variables
z The section name, the variable name and the data structure name can contain up
to 10 different exchange markings (@0 to @9).
MMI
Man Machine Interface
Multi element variables

Variables, one of which is assigned a Derived data type defined with STRUCT or
ARRAY.
Distinctions are made between Field variables and structured variables.
31007523 8/2010 1165

Glossary
Network
A network is the connection of devices to a common data path, which communicate
with each other via a common protocol.
Network node
A node is a device with an address (164) on the Modbus Plus network.
Node address
The node address serves a unique identifier for the network in the routing path. The
address is set directly on the node, e.g. with a rotary switch on the back of the
module.
Operand
An operand is a Literal, a Variable, a Function call up or an Expression.
Operator
An operator is a symbol for an arithmetic or Boolean operation to be executed.
Output parameters (Output)

A parameter, with which the result(s) of the Evaluation of a FFB are returned.
Output/discretes (0x references)

An output/marker bit can be used to control real output data via an output unit of the
control system, or to define one or more outputs in the state RAM. Note: The x,
which comes after the first figure of the reference type, represents a five figure
storage location in the application data store, i.e. if the reference 000201 signifies
an output or marker bit in the address 201 of the State RAM.
1166 31007523 8/2010

Glossary
Output/marker words (4x references)

An output/marker word can be used to save numerical data (binary or decimal) in
the State RAM, or also to send data from the CPU to an output unit in the control
system. Note: The x, which comes after the first figure of the reference type,
represents a five figure storage location in the application data store, i.e. if the
reference 400201 signifies a 16 bit output or marker word in the address 201 of the
State RAM.
Peer processor
The peer processor processes the token run and the flow of data between the
Modbus Plus network and the PLC application logic.
PLC
Programmable controller
Program
The uppermost Program organization unit. A program is closed and loaded onto a
single PLC.
Program cycle
A program cycle consists of reading in the inputs, processing the program logic and
the output of the outputs.
Program organization unit

A Function, a Function block, or a Program. This term can refer to either a Type or
an Item.
Programming device
Hardware and software, which supports programming, configuring, testing,
implementing and error searching in PLC applications as well as in remote system
applications, to enable source documentation and archiving. The programming
device could also be used for process visualization.
31007523 8/2010 1167

Glossary
Programming redundancy system (Hot Standby)

A redundancy system consists of two identically configured PLC devices, which
communicate with each other via redundancy processors. In the case of the primary
PLC failing, the secondary PLC takes over the control checks. Under normal
conditions the secondary PLC does not take over any controlling functions, but
instead checks the status information, to detect mistakes.
Project
General identification of the uppermost level of a software tree structure, which
specifies the parent project name of a PLC application. After specifying the project
name, the system configuration and control program can be saved under this name.
All data, which results during the creation of the configuration and the program,
belongs to this parent project for this special automation.
General identification for the complete set of programming and configuring
information in the Project data bank, which displays the source code that describes
the automation of a system.
Project data bank

The data bank in the Programming device, which contains the projection information
for a Project.
Prototype data file (Concept EFB)

The prototype data file contains all prototypes of the assigned functions. Further, if
available, a type definition of the internal status structure is given.
REAL
REAL stands for the data type "real". The input appears as Real literal or as Real
literal with exponent. The length of the data element is 32 bit. The value range for
variables of this data type reaches from 8.43E-37 to 3.36E+38.
NOTE: Depending on the mathematic processor type of the CPU, various areas
within this valid value range cannot be represented. This is valid for values nearing
ZERO and for values nearing INFINITY. In these cases, a number value is not
shown in animation, instead NAN (Not A Number) oder INF (INFinite).
1168 31007523 8/2010

Glossary
Real literal
Real literals function as the input of real values in the decimal system. Real literals
are denoted by the input of the decimal point. The values may be preceded by the
Example
-12.0, 0.0, +0.456, 3.14159_26
Real literal with exponent

Real literals with exponent function as the input of real values in the decimal system.
Real literals with exponent are denoted by the input of the decimal point. The
exponent sets the key potency, by which the preceding number is multiplied to get
to the value to be displayed. The basis may be preceded by a negative sign (-). The
exponent may be preceded by a positive or negative sign (+/-). Single underline
signs ( _ ) between figures are not significant. (Only between numbers, not before
or after the decimal poiont and not before or after "E", "E+" or "E-")
Example
-1.34E-12 or -1.34e-12
1.0E+6 or 1.0e+6
1.234E6 or 1.234e6
Reference
Each direct address is a reference, which starts with an ID, specifying whether it
concerns an input or an output and whether it concerns a bit or a word. References,
which start with the code 6, display the register in the extended memory of the state
RAM.
0x area = Discrete outputs
1x area = Input bits
3x area = Input words
4x area = Output bits/Marker words
6x area = Register in the extended memory
NOTE: The x, which comes after the first figure of each reference type, represents
a five figure storage location in the application data store, i.e. if the reference 400201
signifies a 16 bit output or marker word in the address 201 of the State RAM.
Register in the extended memory (6x reference)

6x references are marker words in the extended memory of the PLC. Only 984LL
user programs and CPU 213 04 or CPU 424 02 can be used.
31007523 8/2010 1169

Glossary
RIO (Remote I/O)

Remote I/O provides a physical location of the I/O coordinate setting device in
relation to the processor to be controlled. Remote inputs/outputs are connected to
the consumer control via a wired communication cable.
RP (PROFIBUS)
RP = Remote Peripheral
RTU mode
Remote Terminal Unit
The RTU mode is used for communication between the PLC and an IBM compatible
personal computer. RTU works with 8 data bits.
Rum-time error
Error, which occurs during program processing on the PLC, with SFC objects (i.e.
steps) or FFBs. These are, for example, over-runs of value ranges with figures, or
time errors with steps.
SA85 module
The SA85 module is a Modbus Plus adapter for an IBM-AT or compatible computer.
Section
A section can be used, for example, to describe the functioning method of a
technological unit, such as a motor.
A Program or DFB consist of one or more sections. Sections can be programmed
with the IEC programming languages FBD and SFC. Only one of the named
programming languages can be used within a section.
Each section has its own Document window in Concept. For reasons of clarity, it is
recommended to subdivide a very large section into several small ones. The scroll
bar serves to assist scrolling in a section.
Separator format (4:00001)

The first figure (the Reference) is separated from the ensuing five figure address by
a colon (:).
1170 31007523 8/2010

Glossary
Sequence language (SFC)

The SFC Language elements enable the subdivision of a PLC program organiza-
tional unit in a number of Steps and Transitions, which are connected horizontally
by aligned Connections. A number of actions belong to each step, and a transition
condition is linked to a transition.
Serial ports
With serial ports (COM) the information is transferred bit by bit.
Source code data file (Concept EFB)

The source code data file is a usual C++ source file. After execution of the menu
command Library → Generate data files this file contains an EFB code framework,
in which a specific code must be entered for the selected EFB. To do this, click on
the menu command Objects → Source.
Standard format (400001)

The five figure address is located directly after the first figure (the reference).
Standardized literals
If the data type for the literal is to be automatically determined, use the following
construction: ’Data type name’#’Literal value’.
Example
INT#15 (Data type: Integer, value: 15),
BYTE#00001111 (data type: Byte, value: 00001111)
REAL#23.0 (Data type: Real, value: 23.0)
For the assignment of REAL data types, there is also the possibility to enter the
value in the following way: 23.0.
Entering a comma will automatically assign the data type REAL.
State RAM
The state RAM is the storage for all sizes, which are addressed in the user program
via References (Direct display). For example, input bits, discretes, input words, and
discrete words are located in the state RAM.
Statement (ST)
Instructions are "commands" of the ST programming language. Instructions must be
terminated with semicolons. Several instructions (separated by semi-colons) can
occupy the same line.
31007523 8/2010 1171

Glossary
Status bits
There is a status bit for every node with a global input or specific input/output of Peer
Cop data. If a defined group of data was successfully transferred within the set time
out, the corresponding status bit is set to 1. Alternatively, this bit is set to 0 and all
data belonging to this group (of 0) is deleted.
Step
SFC Language element: Situations, in which the Program behavior follows in
relation to the inputs and outputs of the same operations, which are defined by the
associated actions of the step.
Step name
The step name functions as the unique flag of a step in a Program organization unit.
The step name is automatically generated, but can be edited. The step name must
be unique throughout the whole program organization unit, otherwise an Error
message appears.
The automatically generated step name always has the structure: S_n_m
S = Step
m = Number of steps in the section (number running)
Structured text (ST)

ST is a text language according to IEC 1131, in which operations, e.g. call up of
Function blocks and Functions, conditional execution of instructions, repetition of
instructions etc. are displayed through instructions.
Structured variables
Variables, one of which is assigned a Derived data type defined with STRUCT
(structure).
A structure is a collection of data elements with generally differing data types (
Elementary data types and/or derived data types).
SY/MAX
In Quantum control devices, Concept closes the mounting on the I/O population
SY/MAX I/O modules for RIO control via the Quantum PLC with on. The SY/MAX
remote subrack has a remote I/O adapter in slot 1, which communicates via a
Modicon S908 R I/O system. The SY/MAX I/O modules are performed when
highlighting and including in the I/O population of the Concept configuration.
1172 31007523 8/2010

Glossary
Symbol (Icon)
Graphic display of various objects in Windows, e.g. drives, user programs and
Document windows.
Template data file (Concept EFB)

The template data file is an ASCII data file with a layout information for the Concept
FBD editor, and the parameters for code generation.
TIME
TIME stands for the data type "Time span". The input appears as Time span literal.
The length of the data element is 32 bit. The value range for variables of this type
stretches from 0 to 2exp(32)-1. The unit for the data type TIME is 1 ms.
Time span literals

Permitted units for time spans (TIME) are days (D), hours (H), minutes (M), seconds
(S) and milliseconds (MS) or a combination thereof. The time span must be denoted
by the prefix t#, T#, time# or TIME#. An "overrun" of the highest ranking unit is
permitted, i.e. the input T#25H15M is permitted.
Example
t#14MS, T#14.7S, time#18M, TIME#19.9H, t#20.4D, T#25H15M,
time#5D14H12M18S3.5MS
Token
The network "Token" controls the temporary property of the transfer rights via a
single node. The token runs through the node in a circulating (rising) address
sequence. All nodes track the Token run through and can contain all possible data
sent with it.
Traffic Cop
The Traffic Cop is a component list, which is compiled from the user component list.
The Traffic Cop is managed in the PLC and in addition contains the user component
list e.g. Status information of the I/O stations and modules.
Transition
The condition with which the control of one or more Previous steps transfers to one
or more ensuing steps along a directional Link.
31007523 8/2010 1173

Glossary
UDEFB
User defined elementary functions/function blocks
Functions or Function blocks, which were created in the programming language C,
and are available in Concept Libraries.
UDINT
UDINT stands for the data type "unsigned double integer". The input appears as
Integer literal, Base 2 literal, Base 8 literal or Base 16 literal. The length of the data
element is 32 bit. The value range for variables of this type stretches from 0 to
2exp(32)-1.
UINT
UINT stands for the data type "unsigned integer". The input appears as Integer
literal, Base 2 literal, Base 8 literal or Base 16 literal. The length of the data element
is 16 bit. The value range for variables of this type stretches from 0 to (2exp16)-1.
Unlocated variable
Unlocated variables are not assigned any state RAM addresses. They therefore do
not occupy any state RAM addresses. The value of these variables is saved in the
system and can be altered with the reference data editor. These variables are only
addressed by symbolic names.
Signals requiring no peripheral access, e.g. intermediate results, system tags etc,
should primarily be declared as unlocated variables.
Variables
Variables function as a data exchange within sections between several sections and
between the Program and the PLC.
Variables consist of at least a variable name and a Data type.
Should a variable be assigned a direct Address (Reference), it is referred to as a
Located variable. Should a variable not be assigned a direct address, it is referred
to as an unlocated variable. If the variable is assigned a Derived data type, it is
referred to as a Multi-element variable.
Otherwise there are Constants and Literals.
1174 31007523 8/2010

Glossary
Vertical format
Vertical format means that the page is higher than it is wide when looking at the
printed text.
Warning
When processing a FFB or a Step a critical status is detected (e.g. critical input value
or a time out), a warning appears, which can be viewed with the menu command
Online → Event display... . With FFBs the ENO output remains at "1".
WORD
WORD stands for the data type "Bit sequence 16". The input appears as Base 2
literal, Base 8 literal or Base 1 16 literal. The length of the data element is 16 bit. A
numerical range of values cannot be assigned to this data type.
31007523 8/2010 1175

Glossary
1176 31007523 8/2010

Index
31007523 8/2010
Index
B
AC
0-9 984LL
1x3x, 79
1 millisecond timer, 1059
AD16, 81
1 second timer, 1055
ADD, 83
1/100th of a second timer, 1047
AND, 85
1/10th of a second timer, 1051
BCD, 91
1x3x, 79
BLKM, 93
4-station ratio controller, 893
BLKT, 97
BMDI, 101
BROT, 103
CALL, 107
CANT, 115
CCPF, 121
CCPV, 125
CFGC, 129
CFGF, 133
CFGI, 137
CFGR, 141
CFGS, 145
CHS, 149
CKSM, 155
closed loop control / analog values, 43
CMPR, 159
coils, 163
coils, contacts, and interconnects, 65
COMM, 167
COMP, 171
contacts, 177
CONV, 181
CTIF, 185
DCTR, 193
DIOH, 197
31007523 8/2010 1177

Index
DISA, 201 EMTH-TAN, 453

DIV, 205 ESI, 457
DLOG, 211 EUCA, 475
DMTH, 217 FIN, 489
DRUM, 225 formatting messages for ASCII
DV16, 231
EARS, 239
EMTH, 247
EMTH-ADDDP, 253
EMTH-ADDFP, 259
EMTH-ADDIF, 263
EMTH-ANLOG, 267
EMTH-ARCOS, 271
EMTH-ARSIN, 277
EMTH-ARTAN, 281
EMTH-CHSIN, 287
EMTH-CMPFP, 293
EMTH-CMPIF, 299
EMTH-CNVDR, 305
EMTH-CNVFI, 311
EMTH-CNVIF, 317
EMTH-CNVRD, 323
EMTH-COS, 329
EMTH-DIVDP, 333
EMTH-DIVFI, 339
EMTH-DIVFP, 343
EMTH-DIVIF, 347
EMTH-ERLOG, 351
EMTH-EXP, 357
EMTH-LNFP, 363
EMTH-LOG, 369
EMTH-LOGFP, 375
EMTH-MULDP, 381
EMTH-MULFP, 387
EMTH-MULIF, 391
EMTH-PI, 397
EMTH-POW, 403
EMTH-SINE, 407
EMTH-SQRFP, 413
EMTH-SQRT, 419
EMTH-SQRTP, 425
EMTH-SUBDP, 431
EMTH-SUBFI, 437
EMTH-SUBFP, 443
EMTH-SUBIF, 449
1178 31007523 8/2010

Index
READ/WRIT operations, 57 PCFL-AIN, 799

FOUT, 493 PCFL-ALARM, 805
FTOI, 499 PCFL-AVER, 815
G392, 553 PCFL-CALC, 821
GD92, 503 PCFL-DELAY, 827
GFNX, 515 PCFL-EQN, 831
GG92, 529 PCFL-INTEG, 837
GM92, 541 PCFL-KPID, 841
HLTH, 565 PCFL-LIMIT, 847
HSBY, 579 PCFL-LIMV, 851
IBKR, 585 PCFL-LKUP, 855
IBKW, 589 PCFL-LLAG, 861
ICMP, 593 PCFL-MODE, 865
ID, 599 PCFL-ONOFF, 869
IE, 603 PCFL-PI, 873
IMIO, 607 PCFL-PID, 879
IMOD, 613 PCFL-RAMP, 885
INDX, 621 PCFL-RATE, 889
interrupt handling, 71 PCFL-RATIO, 893
ITMR, 625 PCFL-RMPLN, 897
ITOF, 631 PCFL-SEL, 901
JOGS, 635 PCFL-TOTAL, 907
JSR, 639 PEER, 913
LAB, 643 PID2, 917
LOAD, 647 R −−> T, 931
MAP3, 651 RBIT, 935
MATH, 659 READ, 939
MBIT, 667 RET, 945
MBUS, 671 RTTI, 949
MMFB, 681 RTU, 957
MMFE, 685 SAVE, 963
MMFI, 689 SBIT, 967
MMFS, 695 SCIF, 971
MOVE, 699 SENS, 975
MRTM, 703 shorts, 979
MSPX, 709 SKP, 983
MSTR, 713 SRCH, 987
MU16, 759 STAT, 993
MUL, 763 SU16, 1021
NBIT, 767 SUB, 1025
NCBT, 771 subroutine handling, 73
NOBT, 775 SWAP, 1029
NOL, 779 T.01 timer, 1047
OR, 787 T−−>R, 1033
PCFL, 793 T−−>T, 1041
31007523 8/2010 1179

Index
T0.1 timer, 1051 alarm

T1.0 timer, 1055 PCFL-ALARM, 805
T1MS timer, 1059 algorithms, PID
TBLK, 1065 PCFL-PID, 879
TEST, 1073 analog input
TTR, 1037 PCFL-AIN, 799
UCTR, 1077 Analog Output, 811
VMER, 1081 analog values, 43
VMEW, 1085 AND, 85
WRIT, 1089 antilogarithm, base 10
XMIT, 1095 EMTH-ANLOG, 267
XMIT communication block, 1103 API 21.1 audit trail
XMIT conversion block, 1123 G392, 553
XMIT port status block, 1115 arcsine of an angle (in radians)
XMRD, 1131 EMTH-ARSIN, 277
XMWT, 1137 ASCII communications
XOR, 1143 COMM, 167
ASCII functions
READ, 939
A WRIT, 1089
abort ASCII message
ESI, 457 ESI, 457
absolute move, 699 auto mode, put input
AD16, 81 PCFL-MODE, 865
ADD, 83 average weighted inputs calculate, 815
add 16 bit, 81 axis, imaginary
addition, 83 CFGI, 137
AD16, 81 axis, remote
ADD, 83 CFGR, 141
EMTH-ADDFP, 263 axis, SERCOS
addition, double precision CFGS, 145
EMTH-ADDDP, 253
addition, floating point
EMTH-ADDFP, 259 B
Advanced Calculations, 794, 794 base 10 antilogarithm
AGA #3 EMTH-ANLOG, 267
G392, 553 base 10 logarithm
GD92 gas flow, 503 EMTH-LOG, 369
GG92, 529 BCD, 91
GM92, 541 binary to binary code, 91
AGA #3 ‘85 bit control
GFNX, 515 NBIT, 767
AGA #8 bit pattern comparison
GD92, 503 CMPR, 159
GM92, 541 bit rotate, 103
1180 31007523 8/2010

Index
BLKM, 93 communications
BLKT, 97 MSTR, 713
block move, 93 communications, ASCII
block move with interrupts disabled, 101 COMM, 167
block to table, 97 COMP, 171
BMDI, 101 compare register, 159
boolean exclusive OR, 1143 complement a matrix, 171
BROT, 103 comprehensive ISA non interacting PID, 841
contacts, 65, 177
CANT, 115
C controller, 4-station ratio
calculated preset formula, 821 PCFL-RATIO, 893
calculation, derivative rate over specified CONV, 181
time conversion
PCFL-RATE, 889 binary to BCD, 91
CALL, 107 conversion
cam profile BCD to binary, 91
CCPF, 121 conversion block
CCPV, 125 XMIT, 1123
CamProfile type, 122 conversion of degrees to radians
CANT, 115 EMTH-CNVDR, 305
CCPF, 121 conversion of radians to degrees
CCPV, 125 EMTH-CNVRD, 323
central alarm handler, 805 convert data
CFGC, 129 CONV, 181
CFGF, 133 coordinated set
CFGI, 137 CFGC, 129
CFGR, 141 cosine of an angle (in radians)
CFGS, 145 EMTH-COS, 329
changing the sign of a floating point number cosine, floating point arc
EMTH-CHSIN, 287 EMTH-ARCOS, 271
check sum counter
CKSM, 155 CTIF, 185
CHS, 149 counters
CKSM, 155 DCTR, 193
closed loop control, 43 counters / timers
CMPR, 159 T.01 timer, 1047
coils, 65, 163 T0.1 timer, 1051
CANT, 115 T1.0 timer, 1055
COMM, 167 T1MS timer, 1059
common logarithm UCTR, 1077
EMTH-LOGFP, 375 CTIF, 185
communication block
XMIT, 1103
31007523 8/2010 1181

Index
D double precision math

DMTH, 217
data
double precision multiplication
ESI, 457
EMTH-MULDP, 381
data logging for PCMCIA read/write
double precision subtraction
support, 211
EMTH-SUBDP, 431
data, convert
down counter
CONV, 181
DCTR, 193
DCTR, 193
DRUM, 225
deadband, on/off values
drum sequencer, 225
PCFL-ONOFF, 869
DV16, 231
deferred DX function
DX function, deferred
CALL, 107, 107
CALL, 107
degrees to radians, conversion
EMTH-CNVDR, 305
delay, time E
PCFL-DELAY, 827
EARS, 239
derivative rate calculation over a specified
EMTH, 247
time, 889
EMTH-ADDDP, 253
derivative, proportional integral
EMTH-ADDFP, 259
PID2, 917
EMTH-ADDIF, 263
detail method
EMTH-ANLOG, 267
GD92, 503
EMTH-ARCOS, 271
GM92, 541
EMTH-ARSIN, 277
DIOH, 197
EMTH-ARTAN, 281
DISA, 201
EMTH-CHSIN, 287
disabled discrete monitor
EMTH-CMPFP, 293
DISA, 201
EMTH-CMPIF, 299
discrete monitor, disabled
EMTH-CNVDR, 305
DISA, 201
EMTH-CNVFI, 311
distributed I/O health, 197
EMTH-CNVIF, 317
DIV, 205
EMTH-CNVRD, 323
divide
EMTH-COS, 329
DIV, 205
EMTH-DIVDP, 333
divide 16 bit, 231
EMTH-DIVFI, 339
division, double precision
EMTH-DIVFP, 343
EMTH-DIVDP, 333
EMTH-DIVIF, 347
division, floating point
EMTH-ERLOG, 351
EMTH-DIVFP, 343
EMTH-EXP, 357
DLOG, 211
EMTH-LNFP, 363
DMTH, 217
EMTH-LOG, 369
double precision addition
EMTH-LOGFP, 375
EMTH-ADDDP, 253
EMTH-MULDP, 381
double precision division
EMTH-MULFP, 387
EMTH-DIVDP, 333
EMTH-MULIF, 391
1182 31007523 8/2010

Index
EMTH-PI, 397 flash, save

EMTH-POW, 403 SAVE, 963
EMTH-SINE, 407 floating point - integer subtraction
EMTH-SQRFP, 413 EMTH-SUBFI, 437
EMTH-SQRT, 419 floating point addition
EMTH-SQRTP, 425 EMTH-ADDFP, 259
EMTH-SUBDP, 431 floating point addition + integer
EMTH-SUBFI, 437 EMTH-ADDIF, 263
EMTH-SUBFP, 443 floating point arc cosine of an angle
EMTH-SUBIF, 449 (in radians)
EMTH-TAN, 453 EMTH-ARCOS, 271
engineering unit conversion and alarms floating point arc tangent of an angle
EUCA, 475 (in radians)
equation calculator, formatted EMTH-ARTAN, 281
PCFL-EQN, 831 floating point arcsine of an angle (in radians)
error report log, floating point EMTH-ARSIN, 277
EMTH-ERLOG, 351 floating point common logarithm
errors, run time EMTH-LOGFP, 375
ESI, 457 floating point comparison
ESI, 457 EMTH-CMPFP, 293
EUCA, 475 floating point conversion of degrees to
event/alarm recording system radians
EARS, 239 EMTH-CNVDR, 305
exclusive OR, 1143 floating point conversion of radians to
exponential function, floating point degrees
EMTH-EXP, 357 EMTH-CNVRD, 323
extended math floating point cosine of an angle (in radians)
EMTH, 247 EMTH-COS, 329
extended memory read, 1131 floating point divided by integer
extended memory write, 1137 EMTH-DIVFI, 339
floating point division
EMTH-DIVFP, 343
F floating point error report log, 351
fast I/O instructions floating point exponential function
BMDI, 101 EMTH-EXP, 357
ID, 599 floating point multiplication
IE, 603 EMTH-MULFP, 387
IMIO, 607 floating point natural logarithm
IMOD, 613 EMTH-LNFP, 363
ITMR, 625 floating point number to integer power
FIN, 489 EMTH-POW, 403
first in, 489 floating point number, changing the sign
first out, 493 EMTH-CHSIN, 287
first-order lead/lag filter, 861 floating point sine of an angle (in radians)
flash, load, 647 EMTH-SINE, 407
31007523 8/2010 1183

Index
floating point square root HSBY, 579

EMTH-SQRFP, 413
EMTH-SQRT, 419
floating point subtraction I
EMTH-SUBFP, 443 I/O, health
floating point subtraction, integer DIOH, 197
EMTH-SUBIF, 449 IBKR, 585
floating point tangent of an angle (in radi- IBKW, 589
ans), 453 ICMP, 593
floating point to integer, 499 ID, 599
floating point to integer conversion IE, 603
EMTH-CNVFI, 311 imaginary axis
floating point value of Pi CFGI, 137
EMTH-PI, 397 IMIO, 607
follower set immediate DX function
CFGF, 133 CALL, 107
formatted equation calculator, 831 immediate I/O, 607
formatting messages, 57 immediate incremental move, 621
FOUT, 493 IMOD, 613
FTOI, 499 indirect block read, 585
indirect block write, 589
INDX, 621
G registers, 624
G392, 553 input compare, 593
gas flow function block, 503, 515, 529 input selection, 901
G392, 553 input simulation
GM92, 541 1x3x, 79
GD92, 503 installation of DX loadables, 75
get data instruction
ESI, 457 coils, contacts, and interconnects, 65
GFNX, 515 instruction groups, 31
GG92, 529 ASCII communication instructions, 32
GM92, 541 coils, contacts, and interconnects, 42
gross method counters and timers instructions, 33
G392, 553 fast I/O instructions, 34
GG92, 529 loadable DX, 35
math instructions, 36
matrix instructions, 38
H miscellaneous, 39
health, distributed I/O move instructions, 40
DIOH, 197 Instruction Groups
history and status matrices, 565 Overview, 32
HLTH, 565 instruction groups
hot standby, 579 skips/specials, 41
CHS, 149
1184 31007523 8/2010

Index
Instruction Groups lead/lag filter, first-order

Special Instructions, 41 PCFL-LLAG, 861
integer - floating point subtraction limiter for the Pv, 847
EMTH-SUBIF, 449 limiter, velocity
integer + floating point addition PCFL-LIMV, 851
EMTH-ADDIF, 263 LL984
integer divided by floating point PCFL-AOUT, 811
EMTH-DIVIF, 347 LOAD, 647
integer operations load flash, 647
MATH, 659 load the floating point value of Pi
integer subtraction, floating point EMTH-PI, 397
EMTH-SUBFI, 437 loadable DX
integer to floating point, 631 CHS, 149
integer to floating point conversion DRUM, 225
EMTH-CNVIF, 317 ESI, 457
integer x floating point multiplication EUCA, 475
EMTH-MULIF, 391 HLTH, 565
integer-floating point comparison ICMP, 593
EMTH-CMPIF, 299 installation, 75
integrate input at specified interval, 837 MAP3, 651
interconnects, 65 MBUS, 671
interfaces, sequential control MRTM, 703
SCIF, 971 NOL, 779
interrupt PEER, 913
CTIF, 185 logarithm
interrupt disable, 599 EMTH-LNFP, 363
interrupt enable, 603 logarithm, base 10
interrupt handling, 71 EMTH-LOG, 369
interrupt module instruction, 613 logarithm, floating point common
interrupt timer, 625 EMTH-LOGFP, 375
ISA non interacting PI, 873 logarithmic ramp to set point, 897
ITMR, 625 logging, data
ITOF, 631 DLOG, 211
logical AND, 85
logical OR, 787
J Lonworks
jog move, 635 NOL, 779
JOGS, 635 look-up table, 855
JSR, 639
jump to subroutine, 639
M
manual mode, put input
L PCFL-MODE, 865
LAB, 643 map transaction, 651
label for a subroutine, 643 MAP3, 651
31007523 8/2010 1185

Index
master instruction, 713 Modbus functions

MATH, 659 XMIT, 1097
math Modbus Plus
AD16, 81 MSTR, 713
ADD, 83 Modbus Plus Network Statistics
BCD, 91 MSTR, 744
DIV, 205 mode, auto or manual
DV16, 231 PCFL-MODE, 865
EMTH, 247 modify bit, 667
FTOI, 499 monitor, disabled discrete
ITOF, 631 DISA, 201
MU16, 759 motion framework bits block, 681
MUL, 763 motion framework extended parameters
SU16, 1021 subroutine, 685
SUB, 1025 motion framework initialize block, 689
TEST, 1073 motion framework subroutine block, 695
math, double precision MOVE, 699
DMTH, 217 move
matrix BLKM, 93
AND, 85 BLKT, 97
BROT, 103 FIN, 489
CMPR, 159 FOUT, 493
COMP, 171 IBKR, 585
MBIT, 667 IBKW, 589
NBIT, 767 INDX, 621
NCBT, 771 JOGS, 635
NOBT, 775 R --> T, 931
OR, 787 SRCH, 987
RBIT, 935 T-->T, 1041
SBIT, 967 T−−>R, 1033
SENS, 975 TBLK, 1065
XOR, 1143 MRTM, 703
MBIT, 667 MSPX, 709
MBUS, 671 MSTR, 713
memory read, extended Clear Local Statistics, 728
XMRD, 1131 Clear Remote Statistics, 734
memory write, extended CTE Error Codes for SY/MAX and
XMWT, 1137 TCP/IP Ethernet, 758
metering flow, totalizer Get Local Statistics, 726
PCFL-TOTAL, 907 Get Remote Statistics, 732
MMFB, 681
MMFE, 685
MMFI, 689
MMFS, 695
1186 31007523 8/2010

Index
Modbus Plus and SY/MAX Ethernet P

Error Codes, 751
PCFL, 793
Modbus Plus Network Statistics, 744
PCFL subfunctions
Peer Cop Health, 736
general, 45
Read CTE (Config Extension Table), 740
PCFL-AIN, 799
Read Global Data, 731
PCFL-ALARM, 805
Reset Option Module, 738
PCFL-AOUT, 811
SY/MAX-specific Error Codes, 753
PCFL-AVER, 815
TCP/IP Ethernet Error Codes, 755
PCFL-CALC, 821
TCP/IP Ethernet Statistics, 749
PCFL-DELAY, 827
Write CTE (Config Extension Table), 742
PCFL-EQN, 831
Write Global Data, 730
PCFL-INTEG, 837
MU16, 759
PCFL-KPID, 841
MUL, 763
PCFL-LIMIT, 847
multi-register transfer module, 703
PCFL-LIMV, 851
multiplication
PCFL-LKUP, 855
EMTH-MULDP, 381
PCFL-LLAG, 861
multiplication, floating point
PCFL-MODE, 865
EMTH-MULFP, 387
PCFL-ONOFF, 869
multiplication, integer x floating point
PCFL-PI, 873
EMTH-MULIF, 391
PCFL-PID, 879
multiply, 763
PCFL-RAMP, 885
multiply 16 bit, 759
PCFL-RATE, 889
PCFL-RATIO, 893
N PCFL-RMPLN, 897
PCFL-SEL, 901
natural logarithm
PCFL-Subfunction
EMTH-LNFP, 363
PCFL-AOUT, 811
NBIT, 767
PCFL-TOTAL, 907
NCBT, 771
PCMICA, data logging
network option module for Lonworks, 779
DLOG, 211
networks, skipping
PEER, 913
SKP, 983
Pi
NOBT, 775
EMTH-PI, 397
NOL, 779
PI, ISA non interacting
normally closed bit, 771
PCFL-PI, 873
normally open bit, 775
PID algorithms, 879
NX19 ‘68
PID example, 49
GFNX, 515
PID, non interacting
PCFL-KPID, 841
O PID2, 917
PID2 level control example, 53
on/off values for deadband, 869 port status block
OR, 787 XMIT, 1115
OR, boolean exclusive, 1143 process control function library, 793
31007523 8/2010 1187

Index
process square root Regulatory Control, 794

EMTH-SQRTP, 425 remote axis
process variable, 44 CFGR, 141
proportional integral derivative, 917 remote terminal unit, 957
put data reset bit, 935
ESI, 457 RET, 945
put input in auto or manual mode, 865 return from a subroutine, 945
Pv, limiter RTTI, 949
PCFL-LIMIT, 847 RTU, 957
Pv, velocity limiter run time errors
PCFL-LIMV, 851 ESI, 457
R S
R −−> T, 931 SAVE, 963
radians to degrees, conversion SBIT, 967
EMTH-CNVRD, 323 SCIF, 971
raising a floating point number to an integer search, 987
power selection, input
EMTH-POW, 403 PCFL-SEL, 901
ramp to set point at a constant rate, 885 SENS, 975
ramp, logarithmic, to set point sequencer, drum
PCFL-RMPLN, 897 DRUM, 225
rate, derivative sequential control interfaces, 971
PCFL-RATE, 889 SERCOS axis
ratio, 4-station controller CFGS, 145
PCFL-RATIO, 893 seriplex
RBIT, 935 MSPX, 709
READ, 939 set bit, 967
MSTR, 724 set point variable, 44
read shorts, 979
VME, 1081 sign, floating point number
read ASCII message EMTH-CHSIN, 287
ESI, 457 sine, of an angle (in radians)
read, extended memory EMTH-SINE, 407
XMRD, 1131 skipping networks, 983
READ/WRIT operations, 57 skips / specials
read/write, data logging RET, 945
DLOG, 211 skips/specials
recording, event/alarm JSR, 639
EARS, 239 LAB, 643
register to input table, 949 SKP, 983
register to table, 931 special
register, compare PCFL, 793
CMPR, 159
1188 31007523 8/2010

Index
Special subtraction, double precision

PCFL-, 811 EMTH-SUBDP, 431
special subtraction, floating point
PCFL-AIN, 799 EMTH-SUBFP, 443
PCFL-ALARM, 805 subtraction, integer
PCFL-AVER, 815 EMTH-SUBFI, 437
PCFL-CALC, 821 subtraction, integer - floating point
PCFL-DELAY, 827 EMTH-SUBIF, 449
PCFL-EQN, 831 support of the ESI module, 457
PCFL-INTEG, 837 SWAP, 1029
PCFL-KPID, 841
PCFL-LIMIT, 847
PCFL-LIMV, 851 T
PCFL-LKUP, 855 T-->R, 1033
PCFL-LLAG, 861 T.01 timer, 1047
PCFL-MODE, 865 T−−>T, 1041
PCFL-ONOFF, 869 T0.1 timer, 1051
PCFL-PI, 873 T1.0 timer, 1055
PCFL-PID, 879 T1MS timer, 1059
PCFL-RAMP, 885 table to block, 1065
PCFL-RATE, 889 table to register, 1037, 1033
PCFL-RATIO, 893 table to table, 1041
PCFL-RMPLN, 897 tangent
PCFL-SEL, 901 EMTH-TAN, 453
PCFL-TOTAL, 907 tangent, floating point arc
PID2, 917 EMTH-ARTAN, 281
STAT, 993 TBLK, 1065
square root, floating point TCP/IP Ethernet Statistics
EMTH-SQRFP, 413 MSTR, 749
EMTH-SQRT, 419 TEST, 1073
square root, process test of 2 values, 1073
EMTH-SQRTP, 425 time delay queue, 827
SRCH, 987 timer
STAT, 993 CTIF, 185
status, 993 timers
SU16, 1021 CANT, 115
SUB, 1025 DCTR, 193
SUB block T.01, 1047
CANT, 115 T0.1, 1051
subroutine handling, 73 T1.0, 1055
subroutine, return from T1MS, 1059
RET, 945 UCTR, 1077
subtract 16 bit, 1021 totalizer for metering flow, 907
subtraction, 1025 transfer module, multi-register
MRTM, 703
31007523 8/2010 1189

Index
transmit
XMIT, 1095
TTR, 1037
U
UCTR, 1077
up counter, 1077
V
variable increments
CCPV, 125
variable instruments
CCPF, 121
velocity limiter for changes in the Pv, 851
VME bit swap, 1029
VMER, 1081
VMEW, 1085
W
WRIT, 1089
Write
MSTR, 722
write
VME, 1085
write ASCII message
ESI, 457
write, extended memory
XMWT, 1137
write/read, data logging
DLOG, 211
X
XMIT, 1095
XMIT communication block, 1103
XMIT conversion block, 1123
XMIT port status block, 1115
XMRD, 1131
XMWT, 1137
XOR, 1143
1190 31007523 8/2010

Proworx 32: Ladder Logic Block Library

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31007523 8/2010

Title of Documentation Reference Number

What's in this Part?

Nodes, In- and Outputs

What's in this Chapter?

Instruction Meaning Available at PLC family

Counters and Timers Instructions

Counters and Timers Instructions

Instruction Meaning Available at PLC family

Fast I/O Instructions

Fast I/O Instructions

Instruction Meaning Available at PLC family

For more information, see Interrupt Handling, page 71.

Instruction Meaning Available at PLC family

For more information, see Installation of DX Loadables, page 75.

Integer Based Instructions

Instruction Meaning Available at PLC family

Instruction Meaning Available at PLC family

Instruction Meaning Available at PLC family

Instruction Meaning Available at PLC family

Instruction Meaning Available at PLC family

Instruction Meaning Available at PLC family

This group provides the following instructions.

Instruction Meaning Available at PLC family

Instruction Meaning Available at PLC family

Coils, Contacts, and Interconnects

Coils, Contacts, and Interconnects

Closed Loop Control /

What's in this Chapter?

Closed Loop Control / Analog Values

Definition of Set Point and Process Variable

Explanation of Formula Elements

Formula Elements Meaning

Integral bit OFF

Gain reduction zone not used

Main PID Ladder Logic

PID2 Level Control Example

LT-1 4 ... 20 mA level transmitter

Ladder Logic Diagram

Register Content Content Comments

Register Content Content Comments

Formatting Messages for ASCII

What's in this Chapter?

Formatting Messages for ASCII READ/WRIT Operations

Overview Format Specifiers

Field width None (defaults to 1)

Format Specifier " "

Field width Three digits enclosed in double quotes

Field width 1 ... 128 characters

Field width None (defaults to 1)

Field width None

Field width 1 ... 8 characters

Field width 1 ... 8 characters

Field width None (defaults to 1)

Field width 1 ... 6 characters

Field width 1 ... 16 characters

Field width 1 ... 4 characters

Special Set-up Considerations for Control/Monitor Signals Format

Control Mask Word