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    Tarea: Decodificador de 4 A 16 Usando Decodificadores de 2 A 4 en Component Y Generate

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    Erick Ortega
    Tarea

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    © All Rights Reserved
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    Tarea: Decodificador de 4 A 16 Usando Decodificadores de 2 A 4 en Component Y Generate

    Uploaded by

    Erick Ortega
    8 views2 pages
    Tarea

    Original Title

    DECODIFICADOR

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    Tarea

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    8 views2 pages

    Tarea: Decodificador de 4 A 16 Usando Decodificadores de 2 A 4 en Component Y Generate

    Uploaded by

    Erick Ortega
    Tarea

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
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    TAREA

    INTEGRANTES:
    ERICK ORTEGA 8-954-1867
    EDIEL BARRIOS 9-752-341
    STEPHANY BONILLA 8-951-704
    DAYBETH DEGRACIA 8-908-1740
    FABIOLA COCIÓ 8-955-2315

    DECODIFICADOR DE 4 A 16 USANDO DECODIFICADORES DE 2 A 4 EN COMPONENT


    Y GENERATE

    COMPONENT

    Entity dec4_16 is
    Port ( X: in std_logic_vector(3 downto 0));
    CE: in std_logic;
    A: out std_vector(15 downto 0);

    end dec4_16;
    Arq…behavioral of dec4_16 is
    Signal X : std_logic_vector(1 downto 0);
    Component dec4_16
    A : in std_logic_vector(1 downto 0);
    A : in std_logic_vector(1 downto 0);
    CE: in std_logic_vector(3 downto 0):
    B: std_logic);

    end componet;
    begin
    s1: dec2_4 port map(A(3 downto 0), CE(3 downto 0);B(0));
    s2: dec2_4 port map(A(7 downto 4), CE(3 downto 0);B(1));
    s3: dec2_4 port map(A(11 downto 8), CE(3 downto 0);B(2));
    s4: dec2_4 port map(A(15 downto 12), CE(3 downto 0);B(3));
    s5:dec2_4 port map(B,CE(3 downto 2), X);
    end behavioral;
    GENERATE

    Entity dec4_16 is
    Port (w: in std_logig_vector(3 to 15);
    s: in std_logic_vector(1 to 3));
    f: out std_logig);

    end dec4_16;

    ARCHITECTURE Structure OF dec4_16 IS


    Signal m: STD_LOGIG_VECTOR(1 to 3);

    BEGIN
    G1: FOR I IN 1 TO 3 GENERATE
    dec: dec2to4 PORT MAP (w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 to 0), m(i));
    END GENERATE;
    dec5: dec2to4 PORT MAP (m(0), m(1), m(2), m(3), s(3 Downto 2), f );
    END Structure;

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