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    18EC42 First IA Test Q-Paper

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    sharanbasappa
    This document provides details of an internal assessment test for fourth semester electronics and communication engineering students. It includes two modules with multiple choice questions. Module 1 questions focus on deriving transistor relations, explaining biasing arrangements, and designing a bias network. Module 2 questions cover deriving expressions for common source amplifier parameters, explaining MOSFET capacitances and frequency response, and selecting coupling and bypass capacitors. Students must answer two full questions, choosing one from each module.

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    18EC42 First IA Test Q-Paper

    Uploaded by

    sharanbasappa
    89 views2 pages
    This document provides details of an internal assessment test for fourth semester electronics and communication engineering students. It includes two modules with multiple choice questions. Module 1 questions focus on deriving transistor relations, explaining biasing arrangements, and designing a bias network. Module 2 questions cover deriving expressions for common source amplifier parameters, explaining MOSFET capacitances and frequency response, and selecting coupling and bypass capacitors. Students must answer two full questions, choosing one from each module.

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    This document provides details of an internal assessment test for fourth semester electronics and communication engineering students. It includes two modules with multiple choice questions. Module 1 questions focus on deriving transistor relations, explaining biasing arrangements, and designing a bias network. Module 2 questions cover deriving expressions for common source amplifier parameters, explaining MOSFET capacitances and frequency response, and selecting coupling and bypass capacitors. Students must answer two full questions, choosing one from each module.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    89 views2 pages

    18EC42 First IA Test Q-Paper

    Uploaded by

    sharanbasappa
    This document provides details of an internal assessment test for fourth semester electronics and communication engineering students. It includes two modules with multiple choice questions. Module 1 questions focus on deriving transistor relations, explaining biasing arrangements, and designing a bias network. Module 2 questions cover deriving expressions for common source amplifier parameters, explaining MOSFET capacitances and frequency response, and selecting coupling and bypass capacitors. Students must answer two full questions, choosing one from each module.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    SVE Society’s

    BHEEMANNA KHANDRE INSTITUTE OF TECHNOLOGY


    ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT
    First Internal Assessment Test

    Subject/ Code: Analog Circuit (18EC42). Date: 03/06/2021


    Sem/Section: IV Sem (A and B section) Max Marks: 30
    Time: 1 hour (3 to 4PM)
    --------------------------------------------------------------------------------------------------------------------------------- ----------
    Note: Answer TWO full questions, choosing ONE full question from each model.

    Module –I

    Q no.1 a) Derive the following relations with respect to small signal operation of BJT:
    i)Transconductance, ii) Voltage gain. (05M)
    b) Explain the design constraints of a classical discrete-circuit biasing arrangement with circuit and relevant
    equations. How does RE provide a negative feedback action to stabilize the bias current?(05M)

    c) Design the bias network of the CS amplifier as shown in below figure (1) to establish a current IE = 1mA
    using a power supply Vcc = +12V. The transistor is specified to have normal Beta value of 100. (Follow the rule of
    thumb mentioned that one-third of the supply voltage to the voltage drops across R 2 and another one- third to the
    voltage drop across Rc. Leaving for possible negative swing at the collector.(5M)

    OR

    Q no. 2 a) Considering the conceptual circuit of common emitter configuration, derive the expressions for gm, rΠ and
    re. Draw the hybrid –Π model of a transistor. (07M)

    b) State the disadvantage of fixed VGS biasing technique and explain how stability of operating point is
    achieved in drain to gate feedback resistor biasing technique in a MOSFET amplifier. (08M)

    Module-II

    Q no.3 a) With a neat circuit diagram of CS amplifier without source resistance R S, ac equivalent circuit, derive the
    expressions for Rin, Avo, Av and Ro? (05M)

    b) With a neat circuit diagram and ac equivalent circuit, derive the expressions for Rin, Avo, Av and Ro for a
    Source follower? (05M)

    c) The MOSFET in the figure (2) below has the following parameters; VTN= 0.8 V, Kn = 0.2 mA/V2
    lambda=0. Find the following; (a) gm and ro , (b) Av, (c) Ri and Ro. (05M)

    OR

    Q no.4 a) Explain with a neat circuit diagram of CS amplifier MOSFET internal capacitances i) The gate capacitive
    effect, & ii) Junction capacitances? (05M)

    b) Draw and explain the complete frequency response of a common source Amplifier. Derive the expression
    for its lower cutoff frequency? (05M)

    c) We wish to select appropriate values for the coupling capacitors C C1 and CC2 and the bypass capacitor CS
    for a CS amplifier figure (3) for which RG =RG1||RG2 = 4.7 MΩ, RD = RL = 15 kΩ, Rsig = 100 kΩ, RS = 10 kΩ, and gm
    = 1 mA/V. It is required to have fL at 100 Hz and that the nearest break frequency be at least a decade lower. (05M)

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