La 76070
La 76070
La 76070
Monolithic Linear IC
LA76070
15.24
13.8
* The LA7840/41 or LA7845N/46N is recommended as the vertical output
IC for use with this product.
0.25
1 26
46.0
Functions
5.1max
4.25
• I 2 C bus control, VIF, SIF, Y, C, and deflection
3.8
integrated on a single chip.
0.51min
0.48 1.05 1.78 0.75
SANYO: DIP52S
Specifications
Maximum Ratings at Ta = 25°C
Parameter Symbol Conditions Rating Unit
V4 max 9.6 V
Maximum power supply voltage
V26 max 9.6 V
Maximum power supply current I21 max 25 mA
Allowable power dissipation Pd max Ta ≤ 65°C* 1.3 W
Operating temperature Topr –10 to +65 °C
Storage temperature Tstg –55 to +150 °C
Note: *Provided on a printed circuit board: 83.2 × 86.0 × 1.6 mm, material: Bakelite
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
Video, chroma,
I26 (YCVICC) 79.5 93.5 107.5 mA
and vertical power supply current (V26)
[VIF Block]
AFT output voltage with no signal VAFTn With no input signal 2.8 3.8 4.8 Vdc
Video output voltage with no signal VOn With no input signal 4.7 4.9 5.1 Vdc
APC pull-in range (U) fPU After APC and PLL DAC adjustment 1.0 MHz
APC pull-in range (L) fPL After APC and PLL DAC adjustment 1.0 MHz
Maximum RF AGC voltage VRFH CW = 91 dBµ, DAC = 0 7.7 8.2 9.0 Vdc
Minimum RF AGC voltage VRFL CW = 91 dBµ, DAC = 63 0 0.2 0.4 Vdc
RF AGC Delay Pt (@DAC = 0) RFAGC0 DAC = 0 96 dBµ
RF AGC Delay Pt (@DAC = 63) RFAGC63 DAC = 63 86 dBµ
Maximum AFT output voltage VAFTH CW = 93 dBµ, variable frequency 6.2 6.5 7.6 Vdc
Minimum AFT output voltage VAFTL CW = 93 dBµ, variable frequency 0.5 0.9 1.2 Vdc
AFT detection sensitivity VAFTS CW = 93 dBµ, variable frequency 33 25 17 mV/kHz
Video output amplitude VO 93 dBµ, 87.5% Video MOD 1.8 2.0 2.2 Vp-p
Synchronization signal tip level VOtip 93 dBµ, 87.5% Video MOD 2.4 2.6 2.8 Vdc
Input sensitivity Vi Output at –3 dB 43 46 dBµ
Video-to-sync ratio (@100 dBµ) V/S 100 dBµ, 87.5% Video MOD 2.4 2.5 3.0
Differential gain DG 93 dBµ, 87.5% Video MOD 2 10 %
Differential phase DP 93 dBµ, 87.5% Video MOD 2 10 deg
Video signal-to-noise ratio S/N CW = 93 dBµ 55 58 dB
920 kHz beat level I920 V3.58 MHz/V920 kHz –50 dB
[Video and Switching Block]
External video gain AUXG Stair step, 1 V p-p 5.5 6.0 6.5 dB
External video sync signal tip voltage AUXS Stair step, 1 V p-p –0.2 0.0 +0.2 Vdc
External video crosstalk AUXC 4.2 MHz, 1Vp-p 60 dB
Internal video output level INTO 93 dBµ, 87.5% Video MOD –0.1 0.0 +0.1 Vp-p
[SIF Block]
FM detector output voltage SOADJ 464 474 484 mVrms
FM limiting sensitivity SLS Output at –3 dB 50 dBµ
FM detector output bandwidth SF Output at –3 dB 50 100 k Hz
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Ratings
Parameter Symbol Conditions Unit
min typ max
Color control sensitivity CLRSE 1 2 4 %/bit
Tint center TINCEN TINT NOM –15 –3 deg
Tint control maximum TINMAX TINT MAX 30 45 60 deg
Tint control minimum TINMIN TINT MIN –60 –45 –30 deg
Tint control sensitivity TINSE 0.7 2.0 deg/bit
Demodulator output ratio R-Y/B-Y RB 0.75 0.85 0.95
Demodulator output ratio G-Y/B-Y GB 0.28 0.33 0.38
Demodulator angle B-Y/R-Y ANGBR 92 99 107 deg
Demodulator angle G-Y/B-Y ANGGB 227 237 247 deg
Killer operating point KILL 0 dB = 40 IRE –42 –37 –30 dB
Chrominance VCO free-running frequency CVCOF Deviation from 3.579545 MHz –350 +350 Hz
Chrominance pull-in range (+) PULIN+ 350 Hz
Chrominance pull-in range (–) PULIN– –350 Hz
Auto-flesh characteristic 73° AF 073 5 10 20 deg
Auto-flesh characteristic 118° AF 118 –7 0 +7 deg
Auto-flesh characteristic 163° AF 163 –20 –10 –5 deg
[Video Block]
Overall video gain
CONT63 10 12 14 dB
(Contrast set to maximum)
Linearity LRRGB 45 50 60 %
Linearity LBRGB 45 50 60 %
[RGB Output (cutoff and drive) Block]
Brightness control (normal) BRT64 2.1 2.65 3.2 V
High brightness (maximum) BRT127 15 20 25 IRE
Low brightness (minimum) BRT0 –25 –20 –15 IRE
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Ratings
Parameter Symbol Conditions Unit
min typ max
(minimum) Vbias0 2.1 2.65 3.2 V
Cutoff control
(maximum) Vbias127 2.45 3.0 3.55 V
(Bias control)
Resolution Vbiassns 4 mV/Bit
RBout127 2.9 Vp-p
Maximum output
Drive adjustment Gout127 2.4 Vp-p
Output attenuation RBout0 7 9 11 dB
[Deflection Block]
Sync separator sensitivity Ssync 3 8 13 IRE
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Measurement
Parameter Symbol Input signal Measurement method Bus conditions
point
Video/vertical power supply current I26 Apply a voltage of 7.6 V to pin 26 and
(pin 26) (DEFICC) 26 measure (in mA) the DC current that flows into the IC
Initial conditions
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45.75 MHz
87.5 % video modulation
SG5
10-step staircase waveform
(Subcarrier: 3.58 MHz)
45.75 MHz
87.5 % video modulation
SG6 Sweep signal
(APL: 50 IRE
Sweep signal level: 40 IRE)
45.75 MHz
SG7 87.5 % video modulation
Flat field signal
4. Perform the following D/A converter adjustments in the order listed before testing.
Video 45 SG7, 93 dBµ Set up the DAC value so that the pin 45 output level is as close to 2.0 V p-p as
possible
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Measurement
Parameter Symbol Input signal Measurement procedure Bus conditions
point
[VIF Block]
Measure the pin 13 DC voltage when After performing the adjustments
AFT output voltage with no signal VAFTn 13 No signal
IF.AGC. DEF is "1" described in section 4
Measure the pin 45 DC voltage when After performing the adjustments
Video output voltage with no signal VOn 45 No signal
IF.AGC. DEF is "1" described in section 4
Connect an oscilloscope to pin 45 and modify
the SG4 signal to be a frequency above 45.75
MHz so that the PLL circuit becomes unlocked.
(Beating will occur in this state.) Gradually
lower the SG4 frequency and measure the
SG4 After performing the adjustments
APC pull-in range (U), (L) fPU, fPL 45 93 dBµ
frequency at which the PLL circuit locks.
described in section 4
Similarly, modify the frequency to a value
below 45.75 MHz so that the PLL circuit
becomes unlocked. Gradually raise the SG4
frequency and measure the frequency at which
the PLL circuit locks.
SG1 Set the RF AGC DAC to 0 and measure the pin After performing the adjustments
Maximum RF AGC voltage VRFH 6 91 dBµ 6 DC voltage described in section 4
SG1 Set the RF AGC DAC to 63 and measure the After performing the adjustments
Minimum RF AGC voltage VRFL 6 91 dBµ pin 6 DC voltage described in section 4
Set the RF AGC DAC to 0 and determine the
RF AGC Delay Pt After performing the adjustments
(@DAC = 0)
RFAGC0 6 SG1 input level such that the pin 6 DC voltage
described in section 4
becomes 3.8 V ±0.5 V
Set the RF AGC DAC to 63 and determine the
RF AGC Delay Pt After performing the adjustments
(@DAC = 63)
RFAGC63 6 SG1 input level such that the pin 4 DC voltage
described in section 4
becomes 3.8 V ±0.5 V
Set the SG4 signal frequency to 44.75 MHz
SG4 After performing the adjustments
Maximum AFT output voltage VAFTH 13 93 dBµ
and input that signal. Measure the pin 13 DC
described in section 4
voltage at that time.
Set the SG4 signal frequency to 46.75 MHz
SG4 After performing the adjustments
Minimum AFT output voltage VAFTL 13 93 dBµz
and input that signal. Measure the pin 13 DC
described in section 4
voltage at that time.
Modify the SG4 frequency to determine the
SG4 frequency deviation (∆f) such that the pin After performing the adjustments
AFT detection sensitivity VAFTS 13 93 dBµz 13 DC voltage changes from 2.5 V to 5.0 V. described in section 4
VAFTS = 2500/∆f [mV/kHz]
SG7 Observe pin 45 with an oscilloscope and After performing the adjustments
Video output amplitude VO 45 93 dBµ measure the p-p value of the waveform described in section 4
SG1 After performing the adjustments
Synchronization signal tip level VOtip 45 93 dBµ
Measure the pin 45 DC voltage
described in section 4
Observe pin 45 with an oscilloscope and measure
the peak-to-peak value of the waveform. Next,
Input sensitivity Vi 45 SG7 gradually lower the input level to determine the input After performing the adjustments
described in section 4
level such that the output becomes –3 dB below the
video signal amplitude VO.
Observe pin 45 with an oscilloscope and
determine the value of the Vy/Vs ratio by
SG7 After performing the adjustments
Video-to-sync ratio (@ 100 dBµ) V/S 45 100 dBµ
measuring the peak-to-peak value of the sync
described in section 4
waveform (Vs) and the peak-to-peak value of the
luminance signal (Vy).
SG5 After performing the adjustments
Differential gain DG 45 93 dBµ
Measure pin 45 with a vectorscope
described in section 4
SG5 After performing the adjustments
Differential phase DP 45 93 dBµ
Measure pin 45 with a vectorscope
described in section 4
Pass the noise voltage that occurs on pin
45 through a 10 kHz to 4 MHz bandpass filter,
SG1 After performing the adjustments
Video signal-to-noise ratio S/N 45 93 dBµ
measure that voltage (Vsn) with an rms
described in section 4
voltmeter. Use that value to calculate 20 × log
(1.43/Vsn).
Input SG1 at 93 dBµ and measure the pin
12 DC voltage (V12).Mix three signals: SG1 at
87 dBµ, SG2 at 82 dBµ, and SG3 at 63 dBµ,
SG1
and input that signal to VIF IN. Now, apply the After performing the adjustments
920 kHz beat level I920 45 SG2
V12 voltage to pin 12 using an external power described in section 4
SG3
supply. Measure the difference between the
3.58 MHz component and the 920 kHz
component with a spectrum analyzer.
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1. Unless otherwise indicated, these measurements are to be performed with no signal applied to PIF IN (pin 10) and
with the D/A converter IF.ACG.SW set to "1".
2. The table below lists the input signals and their labels.
Input signal Waveform Condition
4.2 MHz
SG9
1 Vp-p
Measurement
Parameter Symbol Input signal Measurement procedure Bus conditions
point
[VIF Block]
Observe pin 42 with an oscilloscope, measure
Pin 1 the peak-to-peak value of the waveform, and
External video gain AUXG 42 SG8 perform the following calculation. VIDEO.SW = "1"
AUXG = 20 × log (Vp-p) [dB]
Observe pin 42 with an oscilloscope and
measure the synchronizing signal tip voltage
External video sync signal tip Pin 1 in the waveform.
voltage
AUXS 42 SG8 Determine the voltage difference between this
VIDEO.SW = "1"
measured value and synchronizing signal tip
level (VOtip) measured in the VIF block.
Measure the 4.2 MHz component in the pin 42
signal with a spectrum analyzer.Convert this
Pin 1
External video crosstalk AUXC 42 SG8
measurement to a V peak-to-peak value and VIDEO.SW = "0"
perform the following calculation.
AUXG = 20 × log (1.4/Vp-p) [dB]
Observe pin 45 with an oscilloscope and
Pin 10 After performing the adjustments
measure the peak-to-peak value of the
SG7 described in section 4
Internal video output level INT0 42 (VIF block)
waveform. Determine the difference between
IF. AGC. SW = "0"
this measured value and the video output
93 dBµ VIDEO. SW = "0"
amplitude (VO) measured in the VIF block.
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Unless otherwise indicated, set up the following conditions for each of the following measurements.
1. Bus control condition: IF.AGC.DEF = 1
2. SW: IF1 = off
3. Apply the input signal to pin 49 and use a 4.5 MHz carrier signal.
Measurement
Parameter Symbol Input signal Measurement procedure Bus conditions
point
Measurement
Parameter Symbol Input signal Measurement procedure Bus conditions
point
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Unless otherwise indicated, set up the following conditions for each of the following measurements.
R-Y axis
B-Y axis
G-Y axis
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C-1
C-2
C-3
(However, if a frequency is specified that frequency must be used.)
C-4
C-5
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Measurement
Parameter Symbol Input signal Measurement procedure Bus and other conditions
point
[Chroma Block]
Bout Measure the output amplitudes when the
C-1
chrominance signal input is 0 dB and when
ACC amplitude characteristic 1 ACCM1 0 dB
30 +6 dB
that input is +6 dB and calculate the ratio.
ACCM1 = 20 × log (+6 dBdata/0dBdata)
Bout Measure the output amplitude when the
C-1 chrominance signal input is –14 dB and
ACC amplitude characteristic 2 ACCM2
–14 dB calculate the ratio.
30 ACCM2 = 20 × log (–14 dBdata/0dBdata)
YIN: L77
C-1: Measure the Y output level
No signal (Record this measurement as V1)
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Measurement
Parameter Symbol Input signal Measurement procedure Bus and other conditions
point
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CW signal (L-CW)
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[Video Block]
Measure the output signal 50 IRE amplitude
Overall video gain Contrast max
(contrast: maximum)
CONT127 30 L–50 (CNTHB V p-p) and calculate CONT127 as
20 × log (CNTHB/0.357).
1111111
Brightness min
Measure the output signal 0 IRE DC level 0000000
L–0
(BRTPL V) Contrast max
1111111
DC propagation ClampG
30 Measure the output signal 0 IRE DC level Brightness min
(DRVPH V) and the 100 IRE amplitude (DRVH 0000000
L–100
V p-p), and calculate ClampG as Contrast max
100 × (1 + (DRVPH - BRTPL)/DRVH). 1111111
Y delay YDLY 30
Measure the output signal 0 IRE DC level at
point A when the black stretch function is BKST defeat on (1)
defeated (off). Record this value as BKST1 (V).
Measure the output signal 0 IRE DC level at
Maximum black stretching gain BKSTmax 30 L–BK
point A when the black stretch is enabled (on). BKST defeat off (0)
Record this value as BKST2 (V).
Calculate BKSTmax from the following formula.
BKSTmax = 2 × 50 × (BKST1 – BKST2)/ CNTHB
L–CW
L–CW
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[OSD Block]
Apply a voltage to pin 36 and determine the pin
L–0
OSD fast switch threshold FSTH 30 O–2
36 voltage when the output signal switches to Pin 35: Apply O-2
the OSD signal
Measure the output signal 50 IRE amplitude
Red RGB output level ROSDH L–50
(CNTCR V p-p)
28 L–0 Measure the OSD output amplitude Pin 36: 2.0 V
O–2 (OSDHR V p-p) Pin 33: Apply O-2
Calculate ROSDH as 50 × (OSDHR/CNTCR)
Measure the output signal 50 IRE amplitude
Green RGB output level GOSDH L–50
(CNTCG V p-p)
29 L–0 Measure the OSD output amplitude Pin 36: 2.0 V
O–2 (OSDHG V p-p) Pin 34: Apply O-2
Calculate GOSDH as 50 × (OSDHG/CNTCG)
Measure the output signal 50 IRE amplitude
Blue RGB output level BOSDH L–50
(CNTCB V p-p)
30 L–0 Measure the OSD output amplitude Pin 36: 2.0 V
O–2 (OSDHB V p-p) Pin 35: Apply O-2
Calculate BOSDH as 50 × (OSDHB/CNTCB)
Measure the amplitude of points A (the 0.35 V
section in the input signal O-1) and B (the 0.7 V
L–0 Pin 36: 2.0 V
Analog OSD R output level 28 O–1
section in the input signal O-1) in the output
Pin 33: Apply O-1
signal and record those values as RGBLR and
RGBHR V p-p, respectively
Gain matching RRGB Calculate RRGB as RGBLR/CNTCR
Linearity LRRGB Calculate LRRGB as 100 × (RGBLR/RGBHR)
Measure the amplitude of points A (the 0.35 V
section in the input signal O-1) and B (the 0.7 V
L–0 Pin 36: 2.0 V
Analog OSD G output level 29 O–1
section in the input signal O-1) in the output
Pin 34: Apply O-1
signal and record those values as RGBLG and
RGBHG V p-p, respectively
Gain matching GRGB Calculate GRGB as RGBLG/CNTCG
Linearity LGRGB Calculate LGRGB as 100 × (RGBLG/RGBHG)
Measure the amplitude of points A (the 0.35 V
section in the input signal O-1) and B (the 0.7 V
L–0 Pin 36: 2.0 V
Analog OSD B output level 30 O–1
section in the input signal O-1) in the output
Pin 35: Apply O-1
signal and record those values as RGBLB and
RGBHB V p-p, respectively
Gain matching BRGB Calculate BRGB as RGBLB/CNTCB
Linearity LBRGB Calculate LBRGB as 100 × (RGBLB/RGBHB)
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Measurement
Parameter Symbol Input signal Measurement procedure Bus and other conditions
point
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Unless otherwise indicated, set up the following conditions for each of the following measurements.
4. Bus control conditions: All conditions set to the initial conditions unless otherwise specified.
5. The delay between the rise of the horizontal output (the pin 23 output) and the rise of the F.B.P IN (the pin 24 input)
must be 9 µs.
6. Unless otherwise specified, pin 25 (the X-ray protection circuit input) must be connected to ground.
Caution:
Perform the following operation if horizontal pulse output has stopped.
1. The bus data T_ENABLE bit must be temporarily set to 0 and then set to 1.
(If the X-ray protection circuit operates, an IC internal latch circuit will be set. To reset that latch circuit, the
T_ENABLE bit must be temporarily set to 0, even if there is no horizontal output signal being output.)
Measurement
Parameter Symbol Input signal Measurement procedure Bus conditions
point
[Deflection Block]
SYNC IN: Gradually lower the level of the synchronizing
horizontal and signal input to Y IN (pin 37) and measure the
Sync separator circuit sensitivity Ssync 37 vertical level of the synchronizing signal at the point
synchronizing synchronization is lost
signal
Connect a frequency counter to the pin 23
output (Hout) and measure the horizontal free-
Horizontal free-running SYNC IN:
∆fH 23 running frequency.
frequency deviation No signal
Calculate the deviation from the following formula.
∆fH = <measured value> – 15.734 kHz
SYNC IN:
Monitor the horizontal synchronizing signal input
horizontal and
to Y IN (pin 37) and the pin 23 output (Hout),
Horizontal pull-in range fH PULL 37 vertical
and measure the pull-in range by modifying the
synchronizing
horizontal synchronizing signal frequency
signal
SYNC IN:
horizontal and
Horizontal pulse output Measure the voltage during the low-level period
saturation voltage
V Hsat 23 vertical
in the pin 23 horizontal output pulse
synchronizing
signal
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Measurement
Parameter Symbol Input signal Measurement procedure Bus conditions
point
SYNC IN:
Connect a DC voltage source to pin 25 and
X-ray protection circuit
23 horizontal and
gradually increase the voltage starting at 0 V.
VXRAY vertical
operating voltage Measure the pin 25 DC voltage at the point that
synchronizing
25 signal
the pin 23 horizontal pulse output stops.
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Measurement
Parameter Symbol Input signal Measurement procedure Bus conditions
point
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Measurement
Parameter Symbol Input signal Measurement procedure Bus conditions
point
SYNC IN:
horizontal
and
Vertical ramp DC voltage @32 Vdc32 17 vertical
synchronizing
signal
SYNC IN:
horizontal
and
Vertical ramp DC voltage @0 Vdc0 17 vertical
VDC: 0000000
synchronizing
signal
SYNC IN:
horizontal
and
Vertical ramp DC voltage @63 Vdc63 17 vertical
VDC: 1111111
synchronizing
signal
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Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of July, 1999. Specifications and information herein are subject to
change without notice.
PS No. 5844-27/27