Laboratory Manual

ELECTRONICS – II

COMSATS University Islamabad,

Abbottabad Campus

Department of Electrical and Computer

Engineering

1
 PROGRAM LEARNING OUTCOMES (PLOS)
Engineering Knowledge: An ability to apply knowledge of mathematics,
PLO-1 science, engineering fundamentals, and an engineering specialization to the
solution of complex engineering problems.
Problem Analysis: An ability to identify, formulate, research literature, and
analyze complex engineering problems reaching substantiated conclusions
PLO-2
using first principles of mathematics, natural sciences, and engineering
sciences.
Design/Development of Solutions: An ability to design solutions for
complex engineering problems and design systems, components or processes
PLO-3
that meet specified needs with appropriate consideration for public health,
safety, cultural, societal, and environmental considerations.
Investigation: An ability to investigate complex engineering problems
in a methodical way including literature survey, design and conduct of
PLO-4
experiments, analysis and interpretation of experimental data, and synthesis
of information to derive valid conclusions.
Modern Tool Usage: An ability to create, select and apply appropriate
techniques, resources, and modern engineering and IT tools, including
PLO-5
prediction and modeling, to complex engineering activities, with an
understanding of the limitations.
The Engineer and Society: An ability to apply reasoning informed by
contextual knowledge to assess societal, health, safety, legal and cultural
PLO-6
issues, and the consequent responsibilities relevant to professional
engineering practice and solution to complex engineering problems.
Environment and Sustainability: An ability to understand the impact of
PLO-7 professional engineering solutions in societal and environmental contexts
and demonstrate knowledge of and need for sustainable development.
Ethics: Apply ethical principles and commit to professional ethics and
PLO-8 responsibilities and norms of engineering practice.
Individual and Team Work: An ability to work effectively, as an individual
PLO-9
or in a team, on multifaceted and /or multidisciplinary settings.
Communication: An ability to communicate effectively, orally as well as in
writing, on complex engineering activities with the engineering community
PLO-10 and with society at large, such as being able to comprehend and write
effective reports and design documentation, make effective
presentations, and give and receive clear instructions.
Project Management: An ability to demonstrate management skills and
PLO-11 apply engineering principles to one’s own work, as a member and/or leader
in a team, to manage projects in a multidisciplinary environment.
Lifelong Learning: An ability to recognize importance of, and pursue
PLO-12 lifelong learning in the broader context of innovation and technological
developments

2
 MAPPING OF CLOs AND PLOs

Domain-
CLOs Course Learning Outcomes PLOs
Level

CLO-1 Demonstrate the engineering ethics and follow lab PLO-8 A3

timings as per semester schedule. (A3- PLO8/WK7)
Perform and present lab related tasks in a well-
CLO-2 PLO-4 P4
prepared manner. (P4-PLO4/WK8)
Develop logical thinking (Theoretical knowledge/
CLO-3 theoretical results and measurements along with their
PLO-2 C4
differences) about electronics circuits among students
(C4-PLO2/WK3)
CLO-4 Demonstrate the project through presentation/viva-
PLO-10 C2
voce. (C2-PLO10)
CLO-5
Carry out project according to set timeline with
PLO-11 C2
teamwork. (C2-PLO11)

3
 Mapping of CLOs to Lab Experiments of Electronics- II

Course Learning Outcomes (CLOs)

Sr. Lab Experiment CLO (1) CLO(2) CLO (3) CLO(4) CLO (5)
No. Type Title

1 Introduction to Electronics lab equipment and √ √ √

their usage
2
Introduction to Proteus √ √ √
3
Verify the drain characteristics of JFET √ √ √
4 Find the Q- point of JFET fix bias/ self-bias √ √ √
Typical Labs

network

5 Find the Q-point of JFET voltage divider bias √ √ √

network
6
Implement the JFET common source amplifiers √ √ √
Observe the effect of RSig and RL on the gain of
7 an amplifier √ √ √

Find the low and high frequency response of

8
JFET amplifier √ √ √
Ended

Design an FET amplifier with the specified gain.

Open

Lab

9 √ √ √ √ √

Implement the Buffer, Inverter amplifier, by

10
using LM741 op-amp √ √ √
Typical Labs

Implement the Non-inverter amplifier and

11
summer by using LM741 op-amp √ √ √

12 Determine the response of the active filters (low √ √ √

& high pass)

Design of a comparator using Op-Amp IC

Ended
Open

Lab

13 (student will design OP-AMP circuit that can √ √ √ √ √

perform any of the given two functions. i.e
compare , add, subtract, etc)
Typical

Implementation of Oscillator Circuit using LM

Labs

14 555 √ √ √
Engineering

√ √ √ √ √
Problems

15 Semester Project
Complex

4
 Electronics Lab Safety information:
Execution of Laboratory (Lab) works in a safe manner is even more important than performing
accurate electronics, electrical measurements and assembling of circuits on project Board. First of
all, everyone should be familiar with lab itself. The Fire extinguishers and the emergency exits are
marked in the lab.

The ever-present hazard in an electronics lab is the electric shock. Most people equate the severity
of electric shock with the voltage, i.e., a 1kV shock is more dangerous than 0.1kV shock. This is
not the true story. The real measure of shock is the amount of current that flow through the body.
Table below lists the impact of AC current on the body.
Table

Current Effect
1-5mA Threshold of sensation
5-20mA Involuntary muscle contraction(“can’t-let-go”)
20-100mA Pain, breathing difficulties
100-300mA Ventricular fibrillation possible death
>300mA Respiratory Paralysis, burns, Unconsciousness
9mA For Men (safe)
6mA For Female (safe)

The amount of the current flowing through the body during an electric shock depends on the voltage
and the resistance between the terminals of the voltage source. This resistance consists of

1 Resistance of the contact point between body and circuit (e.g., a ring or a watch),
2 Skin resistance at the point the current flows into the body,
3 Internal resistance of the body,
4 Skin resistance where current flows out of the body(e.g. shoes),

Obviously, the larger the resistance, the smaller would be current. Therefore, in order to
minimize the electric shock hazard

1 Always power down the electrical equipment, disconnect the power cord, and wait for a few
second before touching exposed wires. Remember that circuit breaker are usually set for
much larger currents (e.g., household breakers are at 15A and higher) than the current that
kill the person (0.2-0.3A). Do not assume that because your circuit is powered with 5V, it is
not dangerous. In some circuits, Capacitors can be charged to a much higher voltage and
give you a nasty surprise. Death by electrocution has been reported at a voltage as low as
42V (DC).

5
 2 Do not wear rings, watches, necklace and any other loose metallic objects. Rings and
watches are especially dangerous as the skin beneath them is wet by sweat, making the
resistance of skin much lower.
3 Make sure that your hands are dry. Resistance of wet skin can be as low as 1kΩ as opposed
to dry skin which is about 0.5MΩ.
4 Make sure that your shoes are dry (especially in rainy day). Do not lean on metallic objects
(like legs of the bench tables) as you are providing very large contact areas to the current to
flow out of your body to ground.

In case of electric shock, switch off the power or remove the victim as quickly as possible without
endangering yourself. If the power switch is not readily available (remember the Lab emergency
shut off power switch is near the door), use an insulating material such as dry wood, rope, belt etc.
The resistance of the body decreases during a shock so action should not be delayed.

If the victim is unconscious and has stopped breathing, start artificial respiration at once. Do not
stop until a medical authority has arrived and taken over. Do not stop even the victim does not have
a pulse.

Additional Lab Safety Rules:

1 Each group is responsible for the given platform. Once the practical is completed, all
equipment should be powered off and all probes, cards, etc. must be returned to their
proper position. Do not cut and drop wires on the Lab bench. Your lab grade will be
affected if your bench is not tidy when you leave the lab. Remember, lose cut wires have
caused many short circuits.
2 Get instruction from Lab instructor how to use tools and instruments. Only use the tools
to do the required jobs. Soldering iron need to be special care otherwise cause of serious
burn.
3 Do not wear rings, watches, necklace, and any other loose metallic objects (electric
shock hazard). Do not wear loose clothing. They cause all sort on un-intentional
accidents.
4 Eatables are strictly prohibited in lab. Spilled drinks have caused many accidents.

6
LAB-1
Introduction to Electronics lab equipment

Learning Objectives: At the end of this lab the student will be able:

 To learn how to use the different Electronics lab equipment including Oscilloscope,
Function generator, trainer kit etc.
 To read datasheet and to know about specification of components or devices.
 To test the given components by suitable methods.

Previous Concepts:

 Electronics Components
 Electrical components

Equipment: Multimeter, Cathode ray Oscilloscope (CRO), LCR meter, Signal generator, and
experiment trainer.

Instruments:

1. Cathode ray Oscilloscope (CRO)

a. Calibrate the CRO

2. Signal Generator
a. Generate different signals from signal generator (sinusoidal, square, triangular)
with different time period and amplitude
b. Display these signals on CRO.

3. Experiment Trainer
a. Make a simple circuit on exp-trainer
b. Measure values of different resistors in circuit
c. Measure different ranges of DC voltages

7
QUESTIONS:

1. What is Oscilloscope and for what purpose it may be used in electronics lab .

2. Write down the functions of different knobs of CRO

3. How the amplitude and frequency of a signal is read from CRO.

4. How many different types of signals can be generated from the Sig-generator in lab?

5. Write down the current and voltage ranges you can measure through the meters on Experiment
trainer.

8
 LAB REPORT EVALUATION RUBRICS

Affective Level Rubrics (20)

Very Good
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
(11-15)
CLO-1

PLO-8
(Ethics)

Cognitive Level Rubrics (20)

Very Good
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
(11-15)
CLO-2

PLO-2
(Problem Analysis)

Psychomotor Level Rubrics (60)

Very Good ( Excellent
Criteria Poor (0-10) Good (30-40) PLOs
41-50) (51--60)
CLO-3

PLO-4
(Investigation)
Total
point

Total Points Earned = Lab Performance Grade

9
LAB-2
Introduction to PROTEUS

Proteus Design Suite

The Proteus Design Suite is a proprietary software tool suite used primarily for electronic design automation. The
software is used mainly by electronic design engineers and technicians to create schematics and electronic prints for
manufacturing printed circuit boards. It is mainly used to draw schematics, PCB layout, code and even simulate the
schematic.

Features:
 ISIS is the software used to draw schematics and simulate the circuits in real time.The simulation allows
human access during run time,thus providing real time simulation.
 ARES is used for PCB designing.It has the feature of viewing output in 3D view of the designed PCB along
with components.
 The designer can also develop 2D drawings for the product.
 ISIS has wide range of components in its library. It has sources, signal generators, measurement and analysis
tools like oscilloscope, voltmeter, ammeter etc., probes for real time monitoring of the parameters of the
circuit, switches, displays, loads like motors and lamps, discrete components like resistors, capacitors,
inductors, transformers, digital and analog Integrated circuits, semi-conductor switches, relays,
microcontrollers, processors, sensors etc.

How to download Proteus Professional 8:

Link1

http://www.mediafire.com/file/m6d6vzciiibmwad/Proteus_v8_-
_Ahmed_Qaddora.zip/file

Link2

https://getintopc.com/
https://getintopc.com/softwares/electronics/proteus-8-6-
professional-free-download/

10
How to Install Proteus Professional 8:

https://www.youtube.com/watch?v=gxDOT4fgEQI

How to fix No Libraries Found No Components in

Proteus 8 Professional:

https://www.youtube.com/watch?v=FaIP0DXBqgE

Starting New Design:

Step 1: First double click on desktop icon (The main Proteus application).

Step 2: Select New project in Home page or new project in File menu in top left corner of home
page.

11
 Another way to click on ISIS in top menu of home page, shown by arrow in below figure.

12
  Select new design in File menu.

Step 3: On clicking new project, window opens, where you can enter your project name and path
and click on next.

13
Step 4: Select create schematic and then select Landscape A4.

Step 4: PCB layout and Firmware project are related to PCB (Printed Circuit Board) Layout, not
concern at this level, so click on next till summary window opens.

14
On clicking finish button, a design sheet will be opened, save it according to your wish,it is better
to create a new folder for every layout as it generates other files supporting your design. However,
it is not mandatory.

Step 5: To select components, Click on the component mode button.

15
Step 6: Click on Pick from Libraries. It shows the categories of components available and a search
option to enter the part name.

Step 7: Select the components from categories or type the part name in Keywords text
box.Double click on the component, the component will be added in to library.

16
Step 8: The selected components will appear in the devices list. Select the component and place
it in the design sheet by left-click.

 Place all the required components and route the wires i.e, make connections.
 Either selection mode above the component mode or component mode allows to connect
through wires. Left click from one terminal to other to make connection. Double right-click
on the connected wire or the component to remove connection or the component
respectively.

17
Double click on the component to edit the properties of the components and click on Ok.

Measuring instruments like meters, oscilloscope etc can be add from menu bar on left side of
design sheet.

18
Step 9: After connecting the circuit,click on the play button to run the simulation.

That’s all enough for an introduction to Proteus Software. Now you can simulate any circuit
easily using this software.

https://www.youtube.com/watch?v=FaIP0DXBqgE
19
LAB-3
Verify the drain characteristics of JFET

 To get familiar with JFET network.

 To determine and understand the Drain characteristics of a JFET.

Apparatus:
i. Experiment Trainer
ii. DC voltage sources.
iii. JFET
iv. Multimeter
v. Resistors (different values).
vi. Connecting wires.

Figure 2.0 Drain characteristics of JFET

Procedure:
Connect the circuit as shown above. Set VGS = 0 and calculate the drain current, ID= VRD/RD and
measure the drain current connecting the ammeter between drain terminal of JFET and resister RD,
therefore the resulting current will be IDSS. With VGS = 0V, slowly increase VDD to 5V. Measure
VDS and ID. Increase VDD to 10V again measure VDS and ID. Take couple of more measurements by
increasing the value of VDD. Plot the resulting curve. Repeat the same procedure with VGS = -1V
and VGS = -2V, Value of IDSS for VGS = 0V: ------ (mA).

20
 VGS=0V Table 2.1 VGS=-1V Table 2.2

S. No VDD ID (mA) VDS S.No VDD ID(mA) VDS

1 3V 1 3V

2 6V 2 6V

3 9V 3 9V

4 12V 4 12V

VGS=-2V Table 2.3

S. No VDD ID(mA) VDS

1 3V

2 6V

3 9V

4 12V

5 15V
Graph 2.1: Drain characteristics of JFET

21
 LAB REPORT EVALUATION RUBRICS

Affective Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-1

PLO-8
(Ethics)

Cognitive Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-2

PLO-2
(Problem Analysis)

Psychomotor Level Rubrics (60)

Very Excellent
Criteria Poor (0-10) Good (30-40) PLOs
Good(41-50) (51--60)
CLO-3

PLO-4
(Investigation)
Total
point

Total Points Earned = Lab Performance Grade

22
LAB-4
Find the Q- point of JFET Fix and Self bias networks

OBJECTIVES:

 To perform DC analysis of JFET fix bias network.

 To determine the quiescent point values practically in fix bias network.

Apparatus:
i. Experiment Trainer
ii. DC voltage sources.
iii. JFET
iv. Multimeter
v. Resistors (different values).
vi. Connecting wires.

Procedure:
Connect the circuit according to the circuit diagram as shown in figure 3.1. For the fix bias
configuration, VGG will be set by an independent dc supply. The vertical lines of constant VGG will
intersect the transfer curve developed from Shockley’s equation.
Set VGG to zero volt measure the voltage VRD. Calculate ID from the formula ID = VRD/RD. Since
VGS = 0V the resulting drain current is the saturation current IDSS. Record this value of IDSS.
IDSS = ----- (mA)
Make VGG more and more negative until VRD= 1mV and ID = VRD/ RD = 1uA. Since ID is very small
almost zero, the resulting value of VGG is pinch off voltage VP. Record that value. VP = ----
(V).Using the value above for IDSS and VP, sketch the transfer curve with help of Shockley’s
equation. If VGG = -1V, determine IDQ from curve. Show all work, label the vertical line defined by
VGG as the fix bias line. Calculate IDQ = --- (mA).Set VGG = -1V in your circuit and measure VRD.
Calculate IDQ using the measured value of, RD and measure the drain current IDVRD (Measure) - (V),
IDQ (Measure) = ----- (mA)

Determine the VGSQ and IDQ of fix bias network as shown in figure 3.1.

23
 Figure 4.1 Fix bias networks.

Quantity IDQ VGSQ VS VG VD VDS

Calculated

Measured

Difference
Graph: 4.1for fix biased network

24
Find the VGSQ and IDQ for the self-bias network.

Connect the source resistance with source terminal of JFET and repeat same procedure as
in lab-3. In this case the one advantage is only a single dc source required for biasing the circuit.
Connect the circuit as shown in figure 4.1

Figure 4.2 Self bias network

Draw the self-bias line defined by VGS = -ID RS on the graph paper and find the network Q point.
Record the quiescent value of IDQ and VGSQ below. Label the straight line as the self-bias line.

IDQ (calculated) = ------ (mA) , VGSQ (Calculated) -------- (V)

Calculate the values of VGS, VD, VDS and VG and record below.

VGS (calculated) = ----- (V), VD (calculated) = ----- (V), VS (calculated) = ------ (V)

VDS (calculated) = ----- (V), VG (calculated) = ------- (V

Measure the voltage VGS, VD, VDS and VG and compare with calculated results.
Table 4.2

Quantity IDQ VGSQ VS VG VD VDS

Calculated

Measured

Difference

25
 Graph:4.2 Self biased network

Questions:
1 How do you recognize the fix bias and self-bias by inspection.

2 What are the advantages of fix bias and self-bias?

3 What are the disadvantages of fix bias fix bias and self-bias?

4 Which configure among these two is more stable? Explain.

26
 LAB REPORT EVALUATION RUBRICS

Affective Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-1

PLO-8
(Ethics)

Cognitive Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-2

PLO-2
(Problem Analysis)

Psychomotor Level Rubrics (60)

Very Excellent
Criteria Poor (0-10) Good (30-40) PLOs
Good(41-50) (51--60)
CLO-3

PLO-4
(Investigation)
Total
point

Total Points Earned = Lab Performance Grade

27
LAB-5
Find the Q-point of JFET voltage divider bias network

OBJECTIVES:

 To perform DC analysis of JFET Voltage divider bias network.

 To determine the quiescent point values practically in voltage divider bias networks.

Apparatus:
i. Experiment Trainer
ii. DC voltage sources.
iii. JFET
iv. Multimeter
v. Resistors (different values).
vi. Connecting wires.

Procedure:
Connect the circuit as shown in the figure 6.0. In the voltage divider configuration, the voltage
divider bias network the voltage at gate terminal (VG), VGS and ID can be finding using the
formulas R2VDD
vG 
R1  R2

VGS  VG  I D RS

Figure 5.1 Voltage divider network

28
Use the value of IDSS and VP from the previous lab, draw the voltage divider bias line on the graph
paper and find network Q point. Label the resulting straight line as the voltage divider line. Draw
the network response with the help of two points find from given formulas. For

VGS  VG  I D RS

If ID = 0 then VGS  VG and if VGS = 0 than V

ID  G
RS

Draw the straight line through the above two points and extend it until it intersects the transfer
curve. The co-ordinate of that intersection determines the Q value of ID and VGS, record it. Then
measure VGS and ID from the network, that’s the values of VGSQ and IDQ. Compare the measured,
calculated values and find the difference.

IDQ (calculated) = ------------ (mA), VGSQ (Calculated) ------------- (V)

Calculate the theoretical values of VS, VD, and VDS and record below.

VGSQ (calculate) = ------- (V), VD (calculate) = --------- (V)

VS (calculate) = ---------- (V), VDS (calculate) = -------- (V).

Table 5.0

Quantity ID (mA) VGS VS VD VDS

Calculated

Measured

Difference
Graph 5.0 Voltage divider network

29
Questions:
1 Explain the function of R2 in this network.

2 Write at least two advantages of this network.

3 Explain the function of RS in this network

4 Explain the effect of VGS on the drain current (ID)

30
 LAB REPORT EVALUATION RUBRICS

Affective Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-1

PLO-8
(Ethics)

Cognitive Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-2

PLO-2
(Problem Analysis)

Psychomotor Level Rubrics (60)

Very Excellent
Criteria Poor (0-10) Good (30-40) PLOs
Good(41-50) (51--60)
CLO-3

PLO-4
(Investigation)
Total
point

Total Points Earned = Lab Performance Grade

31
LAB-6
Implement the JFET common source amplifiers

OBJECTIVES:

 To implement the JFET amplifier networks.

 To analyze the JFET amplifier networks and find the gain Av.

Apparatus:
i. Experiment Trainer
ii. DC Power source
iii. Oscilloscope (Dual channel)
iv. Function generator
v. Multimeter
vi. Capacitors
vii. Resistor
viii. Connecting wires

Procedure:
Connect the circuit as shown in the circuit diagram 6.1, 2 and 3. When the total change (combination
of dc and ac) in the output Voltage from a device is greater than the total change in the input Voltage
(almost dc) that caused it, the device is said to be an AC Voltage Amplifier. The Voltage Gain AV
is defined as the ratio of the change in output Voltage to the change in input Voltage. Vo
AV 
Vi

Part A: Fix bias amplifier

Determine the gain of given in figure 6.1 verify the gain of this amplifier how much unstable very
small change in input signal large change at the output waveform.

32
 Figure 6.1 Fix bias amplifier

Table 6.1

S. No Input Vi Output Vo AV

5
Graph: 6.1 Fix bias amplifier

33
Part B: Self bias amplifier.
Determine the gain of given in figure 6.2 verify the gain of this amplifier how much stable than fix
bias.

Figure 6.2 Self bias amplifiers.

Table 6.2

S. No Input Vi Output Vo AV

Graph: 6.2 Self bias amplifier.

34
Part C: Voltage divider bias amplifier.
Determine the gain of given in figure 6.3 verify the gain of this amplifier how much stable than
self-bias.

Figure 6.3 Voltage divider bias amplifier.

Table 6.3

S. No Input Vi Output Vo AV
1
2
3
4
5
Graph: 6.3 Voltage divider bias amplifier

35
Questions:
1 What is the physical difference between fix bias and self-bias amplifier?

2 Write the function of RG in these amplifiers.

3 What are the advantages of self-bias amplifier?

4 What are the disadvantages of self-bias amplifier?

5 What is the phase difference between input and output voltages of common drain
configuration?

6 What is the phase difference between input and output voltages of common source
amplifier?

36
 LAB REPORT EVALUATION RUBRICS

Affective Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-1

PLO-8
(Ethics)

Cognitive Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-2

PLO-2
(Problem Analysis)

Psychomotor Level Rubrics (60)

Very Excellent
Criteria Poor (0-10) Good (30-40) PLOs
Good(41-50) (51--60)
CLO-3

PLO-4
(Investigation)
Total
point

Total Points Earned = Lab Performance Grade

37
LAB-7
Observe the effect of RS and RL on the gain of an amplifier
OBJECTIVES:

To observe the effect of load resistor (RL) and source resistor (Rs) on the voltage gain of an amplifier. 

Apparatus:
i. Experiment Trainer
ii. DC Power source
iii. Oscilloscope (Dual channel)
iv. Function generator
v. Multimeter
vi. Capacitors
vii. Resistor
viii. Connecting wires

Procedure:
Connect the circuit according to circuit diagram as shown below. When the total change in the
output from a device is greater than the total change in the input voltage that caused it, the device
is said to be an AC voltage amplifier. The voltage gain AV is defined as the ratio of the change in
output voltage to the change in input voltage. As shown below. V
AV  o
Vi

Figure 7.0 Voltage divider amplifier.

38
 Table 7.0

S. No Vi VO AV

RL=∞

RL=10M

RL=1M

RL=100K

RL=1K
Graph: 7.0 Voltage divider amplifier

39
 LAB REPORT EVALUATION RUBRICS

Affective Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-1

PLO-8
(Ethics)

Cognitive Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-2

PLO-2
(Problem Analysis)

Psychomotor Level Rubrics (60)

Very Excellent
Criteria Poor (0-10) Good (30-40) PLOs
Good(41-50) (51--60)
CLO-3

PLO-4
(Investigation)
Total
point

Total Points Earned = Lab Performance Grade

40
LAB-8
Find the low and high frequency response of JFET amplifier

OBJECTIVES:

 To understand the effect of low and high frequencies on the gain of amplifier network.

Apparatus:
i. DC Power supply
ii. FET.
iii. Capacitors
iv. Resistors
v. Oscilloscope.
vi. Connecting wires.

Figure 8.0 Frequency response of JFET amplifier

Procedure:
Connect the circuit for low and high frequencies response by using FET as shown in the circuit
diagram above. The primary concern for low frequency is three physical capacitors CG. CC and CS
find the 3dB point and bandwidth of this amplifier as.

For f1first of all determine maximum gain of amplifier i.e (mid frequency gain) than find the
70.07% of the mid frequency gain to decrease the input signal frequency. Similar procedure
repeats for high frequency (f2).

41
 BW  f 2  f1

CG: For the coupling capacitor between source and active device. The “cutoff frequency”
determine by CG is

f LG  
1

2 Rsig  Ri CG

CC: For the coupling capacitor between active device and load. The cutoff frequency determine
by CC is

1
f LC 
2  Ro  RL  CC

CS: For the source capacitor CS. The cutoff frequency determine by CS is.
1
f Ls 
2 ReqCS

1
Req  RS ||
gm

For high frequency the physical capacitor are short circuited and the parasitic capacitances of
network and active device and frequency dependence of the gain of the transistor (FET) are
introduced in the circuit and the Miller effect capacitance will degrade the gain of amplifier.

42
 Graph: 8.0 Frequency response of JFET amplifier

Questions:
1 What is the reason of low gain at low frequency of the amplifier?

43
2 What is mid frequency range of normal amplifiers?

3. What causes of low gain at high frequency of the amplifier?

4. Explain the difference between octave and decade.

5. Define the Bode plot and dB.

44
 LAB REPORT EVALUATION RUBRICS

Affective Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-1

PLO-8
(Ethics)

Cognitive Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-2

PLO-2
(Problem Analysis)

Psychomotor Level Rubrics (60)

Very Excellent
Criteria Poor (0-10) Good (30-40) PLOs
Good(41-50) (51--60)
CLO-3

PLO-4
(Investigation)
Total
point

Total Points Earned = Lab Performance Grade

45
LAB-9
Design an FET amplifier for the specified gain.

Tasks:

a) Design an FET amplifier network in order to get the given voltage gain.

b) The amplifier should have high stability in terms of beta variations.

c) Use standard values for resistors, recalculate the gain and adjust the
design in order to get the gain closer to the specified value.

Objectives:
To learn the design of an FET amplifier for any voltage gain

To learn about usage of standard values for practical application and modify the design
according to the available components.

Apparatus:
i. Power supply
ii. JFET transistors.
iii. Oscilloscope
iv. Resistors
v. Connecting wires.

Schematic of circuit:

46
Calculations:

Plot of input and output waveform

47
 LAB REPORT EVALUATION RUBRICS

Affective Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-1

PLO-8
(Ethics)

Cognitive Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-2

PLO-2
(Problem Analysis)

Psychomotor Level Rubrics (60)

Very Excellent
Criteria Poor (0-10) Good (30-40) PLOs
Good(41-50) (51--60)
CLO-3

PLO-4
(Investigation)
Total
point

Total Points Earned = Lab Performance Grade

48
LAB-10
Implement the Buffer and Inverter amplifier by usingLM741 op-
amp

OBJECTIVES:

To implement the LM741 Operational Amplifier for making

 Buffer
 Inverter amplifier

Apparatus:
I. DC source.
II. Capacitors
III. Oscilloscope.
IV. LM741.
V. Connecting wires.

Procedure:
Assemble the circuit according to circuit diagram given in figure 10.1and 2,. Connects the Input
signal VS, The Input Signal source should be sign wave with 1 KHz frequency, 1-2Vp-p, and
amplitude. Use the oscilloscope to observe the Input and Output signal and the Voltage gain.

Part A: Buffer by using op-amp LM741

Figure 10.1 Buffer amplifier

49
 Graph: 10.1 Buffer amplifier.

Part B: Inverting op-amp using LM741.

Figure 10.2 Inverting amplifier

R1 R2
RStabality 
R1  R2

50
 Graph: 10.2Inverting amplifier

Questions

1 Define differential Op-amp.

2 Explain the common mode operation

3 What are the uses of buffer amplifier?

4 What is the inverting op-amp and non-inverting op-amp?

5 What is virtual ground concept?

51
 LAB REPORT EVALUATION RUBRICS

Affective Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-1

PLO-8
(Ethics)

Cognitive Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-2

PLO-2
(Problem Analysis)

Psychomotor Level Rubrics (60)

Very Excellent
Criteria Poor (0-10) Good (30-40) PLOs
Good(41-50) (51--60)
CLO-3

PLO-4
(Investigation)
Total
point

Total Points Earned = Lab Performance Grade

52
LAB-11
Implement the Non-inverter amplifier and summer by using LM741
op-amp

OBJECTIVES:

To implement the LM741 Operational Amplifier for making

 Non-inverting amplifier
 Summer

Apparatus:
i. DC source.
ii. Capacitors
iii. Oscilloscope.
iv. LM741.
v. Connecting wires.

Procedure:
Assemble the circuit according to circuit diagram given in figure 11.1 and 11.2. Connects the Input
signal VS, The Input Signal source should be sign wave with 1 KHz frequency, 1-2Vp-p, and
amplitude. Use the oscilloscope to observe the Input and Output signal and the Voltage gain.

Part A: Non-inverting op-amp using LM741

53
Figure 11.1 Non-inverting amplifier

Graph: 11.1 Non-inverting amplifier

54
Part B: LM741 use for summing the inputs:

Figure11.2: Summing inverting amplifier.

Graph: 11.2 summer amplifier

55
 LAB REPORT EVALUATION RUBRICS

Affective Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-1

PLO-8
(Ethics)

Cognitive Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-2

PLO-2
(Problem Analysis)

Psychomotor Level Rubrics (60)

Very Excellent
Criteria Poor (0-10) Good (30-40) PLOs
Good(41-50) (51--60)
CLO-3

PLO-4
(Investigation)
Total
point

Total Points Earned = Lab Performance Grade

56
LAB-12
Determine the response of the active filters (low& high pass)

OBJECTIVES:

 To implement the low and high pass filters.

 To learn about the response of active filters.

Apparatus:
vi. Power supply
vii. Capacitors.
viii. Oscilloscope
ix. Resistors
x. Connecting wires.

Part A: Low pass filter.

Procedure: Connect the circuit as shown in the circuit diagram12.1 and 2 Check the behavior of
low pass filter and draw its wave form on the graph paper.

Figure 12.1 Low pass analog filter circuit

57
 Graph: 12.1 Low pass analog filter circuit

Part B: High pass filter.

Procedure:
Connect the circuit as shown in the circuit diagram in figure 11.2. Check the behavior of High-
pass filter and draw its wave form on the graph paper.

Figure 12.2 High pass analog filter circuit

58
 Graph: 12.2 High pass analog filter circuit

Questions:
1 Define real life application of filters.

2 What is difference between low pass and high pass filters?

3 What is use of capacitor across the dc sources?

4 Explain the reason why we use smaller in size capacitor for high frequency application
circuit.

5 If number written on capacitors body like 224 and 103 what will be the values of the
capacitors.

59
 LAB REPORT EVALUATION RUBRICS

Affective Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-1

PLO-8
(Ethics)

Cognitive Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-2

PLO-2
(Problem Analysis)

Psychomotor Level Rubrics (60)

Very Excellent
Criteria Poor (0-10) Good (30-40) PLOs
Good(41-50) (51--60)
CLO-3

PLO-4
(Investigation)
Total
point

Total Points Earned = Lab Performance Grade

60
LAB-13
Design of a comparator using Op-Amp IC

Q: Design a comparator circuit using Op-Amp IC, use a LED at the output to show if the
input is greater than the reference voltage level.

Learning objective: At the end of this lab the student will be able to

 Understand the operation of Op-amp as a voltage comparator.

 Set different reference voltages (positive or negative).
 Construct open loop inverting and non-inverting comparator.

Apparatus: Students are only allowed to use the following for their design.
1. Variable Power Supply.
2. Resistors.
3. Multimeter.
4. Connecting Wires.
5. Light Emitting Diodes
6. 741 IC Operational Amplifier

Draw your designed circuit:

61
QUESTIONS:

1. How can you set a negative voltage reference for the circuit used?

2. What is the output if the input is applied on the inverting terminal and the reference
voltage is applied on the non-inverting terminal of the Op-amp.

3. What is the output if the input is applied on the non-inverting terminal and the reference
voltage is applied on the inverting terminal of the Op-amp.

62
 LAB REPORT EVALUATION RUBRICS

Affective Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-1

PLO-8
(Ethics)

Cognitive Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-2

PLO-2
(Problem Analysis)

Psychomotor Level Rubrics (60)

Very Excellent
Criteria Poor (0-10) Good (30-40) PLOs
Good(41-50) (51--60)
CLO-3

PLO-4
(Investigation)
Total
point

Total Points Earned = Lab Performance Grade

63
 LAB-14
Implementation of Oscillator Circuit using LM 555

Objective: To investigate the operations of LM555 timer IC in the astable and

monostable modes.

Apparatus:
i. LM 555
ii. DC source.
iii. Resistors
iv. Capacitors
v. Oscilloscope.
vi. Connecting wires.

Discussion: Astable multivibrators have no stable state. Instead, they can be wired to oscillate and
produce clock signals. One particular IC that can be wired as an astable multivibrators is the LM555
timer , which you will investigate in the current experiment.

A monostable circuit produces a single output pulse when triggered. It is called monostable because
it is stable in just one state. The duration of the pulse is called the time period (T) and resistor R1
and capacitor C1 determines this.

Procedure: Construct the circuit as given in figure 15.1.

Figure 15.1

64
Calculate the Thigh , Tlow and frequency using following relationships.

Thigh = [0.7 ( RA + RB)C]

Tlow= [0.7RB*C]

Total Time Period (T)= Thigh + Tlow

f= 1/T=1.44/(RA + 2RB)C

Results.

Calculated values:

RA RB C Thigh Tlow Frequency

Measured values:

RA RB C Thigh Tlow Frequency

65
 LAB REPORT EVALUATION RUBRICS

Affective Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-1

PLO-8
(Ethics)

Cognitive Level Rubrics (20)

Very
Criteria Poor (5) Good (6-10) Excellent (16-20) PLOs
Good(11-15)
CLO-2

PLO-2
(Problem Analysis)

Psychomotor Level Rubrics (60)

Very Excellent
Criteria Poor (0-10) Good (30-40) PLOs
Good(41-50) (51--60)
CLO-3

PLO-4
(Investigation)
Total
point

Total Points Earned = Lab Performance Grade

66
LAB-16
Semester Project

OBJECTIVES:

 To implement the knowledge and skills gained in this course.

 To exhibit the design, assembling and implementation skills.

Phase I: Study literature and submission project proposal

Phase II Selection and purchase of Components

Phase III Designing or assembling.

Phase IV Submission and Presentation

67
Acknowledgements
All praise to Allah the Almighty, the most Beneficent and Merciful, for all His bounties and blessing
throughout our lives and in particular during the preparation of this lab manual.

Special thanks to all the individuals who helped in the preparation of this lab manual. It is not
possible to mention all the helping hands, but it is worth acknowledging the contributions from the
following faculty members.

Engr. M. Tufail Assist. Prof., EE-Dept., COMSATS Abbottabad

Mr. Muhammad Ansar Technologist, ERC/EE, COMSATS Abbottabad
Dr. Ahmad Fayyaz Assist. Prof., EE-Dept., COMSATS Abbottabad
Dr. Shoaib Khaliq Assist. Prof., EE-Dept., COMSATS Abbottabad
Dr. Zahid Jahangeri Assist. Prof., EE-Dept., COMSATS Abbottabad
Dr. Aamir Shahzad Assist. Prof., EE-Dept., COMSATS Abbottabad
Engr. Adeel Pervez Lab Engineer. ERC, COMSATS Abbottabad

68