ELEC 3300

Introduction to Embedded Systems

Topic 6
Interrupt Organization
Prof. Vinod Prasad

ELEC3300: Fall 2021 1

 Assembler

Instruction Set Architecture

Course Overview
Memory I/O System
More about
Datapath & Control Embedded Systems
Introduction to Basic Computer
Embedded Systems Structure
MCU Main Board

Digital and Analog

Interfacing USART, IEEE1394,
USB, I2C and SPI

Microcontroller Structure
A/D Port
Buffering and
Serial Port Direct Memory Access
CPU
(DMA)
External Memory Port
Memory,
Interfacing to Memory,
External Interrupt Port
Memory Timing
Interrupt and applications
External Timer Port Interfacing LCD
Organization Timer and
Counter Simple I/O Port
Motor Interfacing

In this course, STM32 is used as a driving vehicle for delivering the concepts.
To be covered In progress Done

ELEC3300: Fall 2021 2

 Expected Outcomes
• On successful completion of this topic, you will be able to:
– Understand the TWO mechanisms (Polling and Interrupt) which control
I/O activity whereby a device that needs CPU’s attention to serve its
request.

– Compare polling I/O with interrupt-driven I/O.

– Understand the timing diagram of interrupt service routine.

– Evaluate several issues related to:

• Identification of which device caused the interrupt.
• Nested and simultaneous interrupts.

– Understand the interrupt organization in ARM micro-controller.

– Analyze the factors that need to be considered while deciding on
polling or interrupt during a practical implementation.
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 A switch is connected to MCU board
Description
Abstract idea of project
(Define the functionality of the system)
Data format / representation

ARM Programming Language

Communication Protocol
Physical connection (Pins assignment)
Active LOW PA0 Hardware devices
(Microcontroller, Peripherals)

Physical Pin Signal Type Initialization Signals at

Devices Assignment (Configuration) Physical
connection
Micro Switch General Input / Output General On/Off
Purpose Input Purpose IO
& Output setting

ELEC3300: Fall 2021 4

 A Practical Industry Scenario
Heat Exchanger Multiple devices (SW1 to SW4) connected
to CPU for servicing.

PA1

PA2

PA3

Polling and
How do we address the needs of multiple devices?
Which device should be serviced first? What are the schemes? Interrupts
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 Polling
• Polled I/O requires the CPU to ask a device if the device requires servicing
– For example, if the devices have changed status
– Software polls the devices to know when a device will be serviced

• Polling requires code to loop until ARM

the device is ready
– Consumes a lot of CPU cycles PA0
– Have a guaranteed delay but some

Program code
applications do not have a
predictable delay (e.g. In loading a Description

printer buffer with text, the buffer can Ask the device Abstract idea of project
(Define the functionality of the
run out before the printer is polled system)
again and thus printing stops) Data format / representation
Programming Language
Communication Protocol
Physical connection (Pins
assignment)
Hardware devices
(Microcontroller, Peripherals)

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 Writing a polling algorithm (Single device)
• Initialization

Program code
• Configure a GPIO as an appropriate function
(say, input or output port) Ask the device
• Implementation
• Write a while-loop / if-then-else loop for checking
the status of the GPIO
Initialization
main()
Description
{
Abstract idea of project
Configure PA0 as input port (Define the functionality of the
while() system)
Data format / representation
{
Programming Language
Check if PA0 is pressed,
Communication Protocol
if yes, …. ; break
Physical connection (Pins
if not, …. ; back to while loop assignment)
implementation } Hardware devices
(Microcontroller, Peripherals)
}

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 Polling in multiple devices
• Polled I/O requires the CPU to ask devices if the devices require servicing

Ask the devices one by one

CPU

Description
D1 D6 D7
Abstract idea of project Loop Back
(Define the functionality of the
system)
Data format / representation
Programming Language
D2 D5 D8
Communication Protocol
Physical connection (Pins
assignment)
Hardware devices
(Microcontroller, Peripherals) D3 D4 D9 Next Instruction

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 Writing a polling algorithm (Multiple devices)
• Initialization

Program code
• Configure a GPIO as an appropriate function (say,
input or output port) Ask the devices

• Implementation
• Write a while-loop / if-then-else loop for checking
the status of the GPIO
Initialization main() * remark
{ Description
Configure PA0, PA1, …., as input ports * Abstract idea of project
while() (Define the functionality of the
system)
{
Check if PA0 is pressed, Data format / representation

if yes, …. ; break Programming Language

Else Check if PA1 is pressed, Communication Protocol

if yes, …..; break Physical connection (Pins

assignment)
implementation Otherwise, …… ; back to while loop
Hardware devices
} (Microcontroller, Peripherals)
}

9
Tradeoff: Programming is easy, Latency is large.
 Interrupts
• Efficient alternative to Polling.
• Interrupt I/O allows the device to interrupt the CPU
announcing that the device requires attention
– This allows CPU to ignore devices unless they request ARM
servicing via interrupt
• Interrupts do not require code to loop until the device
is ready EXTI0

– Device interrupts CPU when it needs attention (PA0)

– Code can go off to do other things

EXTI0 - External
Interrupt

Clear the interrupt flag once interrupt service routine is over.

Disadvantage: Software does not know when an interrupt will occur, and this makes
it more difficult to write code
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 Interrupts
Interrupt I/O allows the device to interrupt the CPU announcing that the
device requires attention
Description
Send request to CPU Abstract idea of project
(Define the functionality of the
CPU system)
Data format / representation
Provide Interrupt Service
Programming Language
Communication Protocol

D1 D6 D7 Physical connection (Pins

assignment)
Hardware devices
(Microcontroller, Peripherals)

D2 D5 D8

D3 D4 D9
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 Interrupt Service Routine (ISR)

For every interrupt, there is an interrupt service routine (ISR), or interrupt

handler, which is the block of codes that executes the servicing.

When an interrupt occurs, the microcontroller runs the ISR.

For every interrupt, there is a fixed location in memory that holds the
address of its ISR.

The table of memory locations set aside to hold the addresses of ISRs is
called as the Interrupt Vector Table.

ISR is also called device driver in case of the hardware interrupts and
called exception handler in the case of software interrupts. 12

ELEC3300: Fall 2021

 Hardware and Software Interrupts

Hardware Interrupt

An electronic alerting signal sent to the processor from an external device, like
a disk controller or an external peripheral.
Example: When we press a key on the keyboard or move the mouse, they
trigger hardware interrupts which cause the processor to read the keystroke or
mouse position.

Software Interrupt

Caused either by an exceptional condition or a special instruction in the

instruction set which causes an interrupt when it is executed by the processor.
Example: If the processor’s ALU runs a command to divide a number by
zero, to cause a divide-by-zero exception, thus causing the computer to
abandon the calculation or display an error message.
13

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 What happens when Interrupt occur?
CPU saves current context (Program Counter, Registers, etc)

CPU grabs address of the interrupt service handler (routine) from a vector table
(each interrupt has an index into the table)

CPU executes the interrupt service handler

Interrupt service handler does operations, clears

flags etc

Interrupt service handler exits

CPU restores context (Program Counter, Registers, etc) and

returns to main flow

14

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 Timing diagram of Interrupts
• Before an Interrupt Service Routine (ISR) is executed, it must save away
the current program’s registers (if it touches those registers)
•Pushing the PC, registers etc. onto the stack register
•Disable subsequent interrupts of the same type from
occurring. However, interrupts of a higher priority can
still occur.

Start of IRQ (Interrupt

Request)

Start of ISR •Popping the PC, registers etc onto the stack
•Enable subsequent interrupts of the same
type from occurring.

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 What causes Interrupt Latency?

Interrupt latency: Delay between the start of an Interrupt

Request (IRQ) and the start of the respective Interrupt Service
Routine (ISR).

Reasons for interrupt latency:

- Processor has to complete the current instruction.

- Interrupts are disabled when the processor accesses critical

OS data structures.

- If an ISR is already executing and cannot be interrupted, then

this also increases the interrupt latency.
16

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 Writing an interrupt algorithm
• Initialization
• Select an appropriate pin (PA0) for handling interrupt signal
• Write an ISR for handling this interrupt signal
• Activate ISR by setting the corresponding Interrupt Request (IRQ)
channel
Initialization ISR_INT0() implementation
main()
{ {
Configure PA0 as input port. (INT0 Program code for ISR

Program code
ISR
as interrupt signal) ………
Enable the IRQ channel
Clear the interrupt pending bit
while()
}
{
Program code
………
implementation }
}

ELEC3300: Fall 2021 17

 Polling v/s Interrupt
You are going to bed at night and want to get up at 6 am
the next day.

Polling: You see the clock every few hours to check whether it
is time to wake up!

Interrupt: Sleep peacefully and wake up when alarm rings.

The most important reason why the interrupt method is preferable is that the polling
method wastes much of the microcontroller’s time by polling devices that do not need
service.
In Interrupt method, microcontroller can serve many devices based on the priority
assigned to it.

The polling method cannot assign priority because it checks all devices in a round-
robin fashion. ELEC3300: Fall 2021
18
 Polling v/s Interrupt
INTERRUPT POLLING
1 The device notices the CPU that it requires its CPU steadily checks whether the device needs
attention. attention.

2 Not a protocol, it is a hardware mechanism. It is a protocol, not a hardware mechanism.

3 The device is serviced by interrupt handler (ISR). The device is serviced by CPU.

4 Interrupt can take place at any time. CPU steadily ballots the device at regular or
proper interval.
5 Interrupt request line is used as indication for Command ready bit is used as indication for
indicating that device requires servicing. indicating that device requires servicing.

6 Processor is evoked only when any device Processor waste many processor cycles by
interrupts it. repeatedly checking the command-ready little bit
of each device.

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 Choosing between Polling and Interrupts
Polling must be done sufficiently fast to ensure that data is not lost.

I/O devices such as printers, keyboards, etc. require that the CPU execute some code to
“service” the device. For example, incoming characters have to be read from a data
register on the peripheral interface and stored in a buffer.

If a serial interface can receive up to 1000 characters/second and can only store the last
character received, it must be checked at least once per millisecond to avoid losing data
→ Speed is a concern in polling.
Polling introduces a fixed overhead for each installed device.

Because we need to periodically check each device, irrespective of whether it requires

service or not.
No such fixed overhead in Interrupts because ISR is executed ONLY when device
needs attention.
Polling routines must be integrated into each and every program that will use that
peripheral. Programs must be written to periodically poll and service all the
peripherals they use.

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 Choosing between Polling and Interrupts
Is Interrupt a perfect method?
Interrupt Latency: Responding to an interrupt typically requires executing additional clock
cycles to save the processor state, fetch the interrupt number and the corresponding
interrupt vector, branch to the ISR and later restore the processor state.

Some factors to consider when deciding whether to use polling or interrupts include:

- Can the device generate interrupts?

If the peripheral is very simple then it may not have been designed to generate
interrupts.

- How complex is the application software?

If the application is a complex program that would be difficult to modify in order to

add periodic polls of the hardware then you may have to use interrupts.

On the other hand, if the application is a controller that simply monitors some
sensors and controls some actuators then polling may be the best approach.
ELEC3300: Fall 2021 21
 Choosing between Polling and Interrupts
What is the maximum time allowed between polls?

If the device needs to be serviced with very little delay then it may not be practical to
use polling.

What fraction of polls are expected to result in data transfer?

If the rate at which the device is polled is much higher than the average transfer
rate, then a large fraction of polls will be “wasted”.

Using interrupts will reduce this polling overhead.

General Guideline (Take home Message): Use interrupts when the overhead due
to polling would consume a large percentage of the processor time or would
complicate the design of the software.

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 Choosing between Polling and Interrupts
Practical Case Study-1:
You are designing a steam boiler control system in which the steam pressure in the
boiler is monitored by a pressure sensor. If the pressure suddenly rises to a
dangerously high value, the processor must take rapid action to reduce the pressure.
Assume that there are no other external devices interfaced with the processor that
needs processor’s attention/action. Would you use Polling or Interrupt?

Considerations:
Are there many devices connected to the processor?

If yes, polling many devices will consume time, may cause delay in attending the
emergency.

If no, polling would be a suitable choice because immediate attention of the processor
is possible.
What if we use Interrupt in this case?
Interrupt latency is a concern.
ELEC3300: Fall 2021 23
 Choosing between Polling and Interrupts
Practical Case Study-2:
In a general purpose microcomputer, a range of devices are connected which include
switches, keyboards, printers, modems, etc. Some of the devices operate at low speed
(such as a manually operated switch), while others operate at higher speeds. What
would be your choice – Polling or Interrupt?
Considerations:
Are there many devices connected to the processor?

What is the action response time (speed) expected by the devices – Some demands
immediate response whereas others can wait?

Do we need to define priority for different devices?

Interrupt would be a better choice.

What if we use Polling in this case?

System will fail to satisfy the demand of critical devices (that need fast response).
No provision for setting up priority.
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 Interrupts: Issues to be dealt with
• Enabling/disabling interrupt (all or some)
– Can be enabled / disabled by hardware or software
– Those interrupts that can be enabled / disabled by programmer are called
Maskable Interrupts.
– Non-Maskable Interrupts cannot be disabled by programmer.
– Examples of non-maskable interrupt: Internal system chipset errors, memory
corruption problems, parity errors and high-level errors which need immediate
attention.
– Non-maskable interrupt is a way to prioritize certain signals within the
operating system.

• Identification of which device caused the interrupt

• Handling simultaneous interrupts

• Handling nested interrupts: A new interrupt to be processed, even before it

finishes handling the current interrupt. This enables you to prioritize
interrupts and make improvements to the latency of high priority events.

ELEC3300: Fall 2021 25

 Identification of Interrupting Device
• The problem is: CPU has received an interrupt
request, but which device caused the interrupt?

• Solution: One approach is simple polling of the

status flags in each device’s interface. In
programming terms, there is a ‘skip chain’.

Save program registers

Skip chain

Problem with this approach is time wasted in ‘skip-chain’ processing, especially when
there are many possible interrupting devices. 26
 Identification of Interrupting Device
• Instead of programmed device identification, the device supplies the CPU
with interrupt vector using an “Interrupt Acknowledge” bus cycle.

• Interrupt vectors are memory addresses which inform the CPU as to

where to find the ISR (interrupt handler).

The interrupting device sends a self-identifying code back to the CPU during the
“Interrupt ACK” cycle

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 Nested and Simultaneous Interrupts
• When there is the possibility of several devices interrupting
– How to handle if a second interrupt request occurs while a previous interrupt is
being serviced?
– How to handle if two devices make interrupt requests during the same machine
cycle?
• It is often the case that one device have priority over another (e.g. real-
time clock v/s printer)
• Device A should be allowed to interrupt the serving of Device B if only if
A’s priority is higher than B’s.
• Similarly, if A and B interrupt simultaneously, A should be serviced first.

• On deciding the interrupt priority, there are two main approaches:

– Daisy-chaining of the acknowledge line (simplest)
– Use of a specialized Priority Interrupt Controller

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 Daisy-Chaining
Serial connection of all the devices which generate an interrupt signal. The
interrupt line request is common to all devices.

The device with the highest priority is placed at the first position followed by
lower priority devices (in decreasing order of priority).
The CPU responds to the interrupt by enabling the interrupt acknowledge
line. This signal is received by the Device-1. The acknowledge signal passes
to Device-2 only if Device-1 is not requesting an interrupt.
Common interrupt line request

Pros: Easy to program

Cons: Latency to address

interrupt request
increases with the
number of devices.
Lowest priority
Highest priority
ELEC3300: Fall 2021 device 29
device
 In-class activity

Interrupts – Topic 6: Questions 1 - 4

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 Priority Interrupt Controller
A priority interrupt controller (PIC) is used to place interrupt requests into a
hierarchy.

Instead of the device communicating directly with the CPU, the PIC will
communicate with the CPU after checking the interrupts (PIC is like an
outsourcing agent – makes CPU free from interrupt checking procedures).

CONS:

- Extra chip.
- Cost.
- Power and
Space.

control
31
PIC suitable for large number of priority interrupts.
 Nested Interrupts
• Interrupts can occur within interrupts Which has higher priority – ISR1 or ISR2?

What will be the timing diagram if ISR1 has higher priority over ISR2?
What will be the timing diagram if ISR3 that has a higher priority over ISR2
occurs when ISR2 is being executed?
ELEC3300: Fall 2021 32
 STM32 Interrupts
• Nested vectored interrupt controller (NVIC)
Prioritizes interrupts, provides scheme for handling the
interrupts that occur when CPU is processing a previously
occurred interrupt, ensures that higher priority interrupts
are serviced first.
• Features:
- 68 interrupt lines
- 16 programmable priority levels
- Low-latency expectation and interrupt handlin
- Power management control: System Control
Registers used to control low-power features (e.g.,
sleep modes).
• Reference:
- Table 61 Vector table for connectivity line devices
(intended for applications where connectivity and real-time
performances are required - industrial control, control panels for
security applications, ethernet)
- Table 62 Vector table for XL-density devices
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where density 33
of Flash memory ranges between 768 Kbytes and 1 Mbyte.
 STM32 External interrupt / event controller (EXTI)
Interrupts typically execute a few lines of code whereas Events do not
necessarily execute code but can signal another peripheral to do something
without processor intervention.
Events are normally handled synchronously: the program explicitly waits for
an event to be serviced, whereas an interrupt can demand service at any time.
Event example: A timer can generate an event to tell an ADC to sample and then write
the measured value to memory using DMA without ever waking up the processor.

• Features:
– Up to 20 edge detectors (rising/falling edge in EXTI line) in connectivity
line devices
– Up to 19 edge detectors in other devices for general event / interrupt
requests
– Independent trigger and mask on each interrupt / event line
– Dedicated status bit for each interrupt line
– Generation of up to 20 software event / interrupt requests (e.g. Timer) 34
 STM32 Interrupts

• The priority of external interrupts can

According to Table 61
be done by the hardware configuration.
• Example 1: Highest Priority

– Device 1 is connected to PA1

– Device 2 is connected to PB0
Which one has a highest priority?
• Example 2:
– Device 1 is connected to PA1
– Device 3 is connected to PB1
Which one has a highest priority?
• Example 3: How can we make Device
1 high priority compared to Device 2?
Lowest Priority
Use polling to check Device 1 first. In
principle, hardware does not assign any
35
priority, you have to do it in software.
 In-class activity

Topic 6: Questions 5 - 8

ELEC3300: Fall 2021 36

 Reflection (Self-evaluation)
• Do you
– Describe two I/O interfacing techniques: polling I/O and interrupt-driven
I/O ?
– Distinguish the concepts and signaling in polling and interrupt-driven
I/O ?
– List the timing diagram of interrupt service routines?
– Handle several issues deal with interrupts ?
– Configure the interrupt settings in ARM micro-controller ?

ELEC3300: Fall 2021 37

 Assembler

Instruction Set Architecture

Course Overview
Memory I/O System
More about
Datapath & Control Embedded Systems
Introduction to Basic Computer
Embedded Systems Structure
MCU Main Board

Digital and Analog

Interfacing USART, IEEE1394,
USB, I2C and SPI

Microcontroller Structure
A/D Port
Buffering and
Serial Port Direct Memory Access
CPU
(DMA)
External Memory Port
Memory,
Interfacing to Memory,
External Interrupt Port
Memory Timing
Interrupt and applications
External Timer Port Interfacing LCD
Organization Timer and
Counter Simple I/O Port
Motor Interfacing

In this course, STM32 is used as a driving vehicle for delivering the concepts.
To be covered In progress Done

ELEC3300: Fall 2021 38