Supercapacitor Supported DSTATCOM for

Harmonic reduction and power factor correction

Abstract—Distributed Static Compensator factor improvement. This method is based on the concept
(DSTATCOM) is a widely used custom power device in reference source current calculation. A key feature is that the
distributed network to perform the power quality source current and voltage aretracked without sensor.
improvement tasks like harmonics reduction, power ThisDSTATCOMcontain low-order harmonic components to
factor correction andmaintain reduces constant dc bus ensure unity power factor at the mains, and thus, the control
voltage.This paper investigates a new topology based on a function is simplifiedsuccessfully. The control strategy can
Distributed Static Compensator (DSTATCOM) coupled be implemented with both analog and digital electronics,
with a supercapacitor for power quality demanding minimum hardware and data processing
enhancement.The proposed topology includes of a voltage capabilities. The achieved performance is superior to that
source converter (VSC) based DSTATCOM, a DC-DC attained with other traditional strategies as shown through the
bidirectional chopper and a supercapacitor. The simulation. The main contribution of this work lies on the use
supercapacitor is used to control the reduced dc-bus of very simple hysteresis current controllers (HCC) to control
voltage. The popular instantaneous symmetrical the DSTATCOM.Recently, to handle the power quality
component theory (ISCT) control strategy is used to problems in a power system, Energy storage devices are
generate the switching pulses for controlling the IGBTs of being coupled with conventional DSTATCOM [6].
the VSC.Simulations of the proposed system have been In this paper, a supercapacitor is coupled with a
carried out in MATLAB/SIMULINK environment to DSTATCOM to improve the power quality issues. The
show its effectiveness overtraditional DSTATCOM for supercapacitor is an electrical energy storing device that
power quality issues. stores the electrical energy in its electrostatic field from the
Keywords— DSTATCOM; Supercapacitor; power factor source during the peak-off hours and delivers back to the
correction (PFC); Current harmonic reduction load during peak. The stored energy of the supercapacitor is
used to regulate the voltage across the DC-link capacitor of a
I. INTRODUCTION VSC-DSTATCOM very quickly.
Traditionally, static capacitors and passive filters have been II. CONFIGURATION
utilized to improve power quality (PQ) in a distribution
system. However, these usually have problems such as fixed The typical distribution system consists a three phase
compensation, system-parameter-dependent performance, nonlinear load which is fed by a three phase balanced
and possible resonance with line reactance [1]. A distribution source.A novel topology, supercapacitor supported VSC-
static compensator (DSTATCOM) has been proposed in the DSTATCOM is used as a compensator to mitigate the power
literature to overcome these drawbacks [2]–[7]. It injects quality issues. Switching signals for IGBTs of VSC are
reactive component of load currents to become source generated by using instantaneous symmetrical component
currents balanced, sinusoidal, and in phase with the load theory control technique.
voltages.
There are various control schemes such as instantaneous A. System Topology:-
reactive power theory (p–q theory) [8], synchronous This distribution system consists of a three phase supply and
reference frame (SRF) theory [9], power balance theory [10], a three phase non-linear load. The proposed compensator is
SVPWM [11], etc. are described for generating the reference connected at the point of common coupling (PCC) through
control signals for the DSTATCOM. The control of three- an interfacing impedance as shown in Fig.1. The
phase four-wire compensation under non-sinusoidal supply compensator consists of an IGBT based VSC with a dc bus
condition is verifiedusing p–q theory [12] and adaptive capacitor, a bidirectional chopper and a supercapacitor block.
neural networks [13], [14] andLyapunov-function-based The supercapacitor block includes an internal series
control [15], [16] satisfactorily.The instantaneous
resistance( R s), parallel resistance ( R p ) due to flow of
symmetrical component theory (ISCT) is one of best control
technique which is used for generating of the switching leakage current and a supercapacitor as shown in Fig.2. The
pulses for the operation of voltage source converter of the bi-directional chopper decides the charging and discharging
three phase DSTATCOM in the distribution system [17,18]. of supercapacitor. The target of the supercapacitor is to
maintain the voltage across dc bus capacitor(C dc ).
This novel DSTATCOM control strategy is proposed here as
alternative techniques for the harmonic reduction and power
 Source
a- ph zs isa
PCC Load
va ila
3-ph R
b-ph isb vb ilb Uncontrolled
Bridge rectifier
c-ph L
isc vc ilc (Non-linear load)
ica icb icc

T1 T3 T5
Supercapacitor zc
with vdc C
switching
circuit
T2 T4 T6

Compensator
Switching signals

Hysteresis current
isa
controller
isb
isc
i*sa i*sb i*sc
vs Instantaneous Symmetrical vdc(ref)
Component Theory
vl vdc
ila ilb ilc
Fig.1: Proposed Topology based DSTATCOM for distribution system

Supercapacitor:
A supercapacitor is connected to a DSTATCOM through a
bi-directional chopper. The chopper plays an important role
in charging/discharging of energy to/from the supercapacitor. S1
Stored energy in the supercapacitor is used to maintain the
voltage across dc bus capacitor during compensation of Vdc RS
different power quality problems. An equivalent circuit Icell Ip Isc
diagram of the chopper with a supercapacitor is given in RP Csc
Fig.2. Mainly, the supercapacitor involves two operation; one
S2
is charging operation and another is discharging operation as
follows;
Fig.2: Equivalent circuit of bi-directional chopper with a supercapacitor
Let us consider, S1 and S2 are two switches (IGBTs) of
the bi-directional chopper to perform the charging and
discharging operation of the supercapacitor. Charging:
In Fig.2, Current relation during charging period of the super
capacitor( C sc )is given by

I cell=I p + I sc (1)
Where, I p , I sc , I cell are the current through R p , C sc and R s
respectively.
Applying KCL,
d V sc V sc
C sc + −I sc =0(2)
dt Rp
Equivalent voltage appeared across supercapacitor circuit is ¿ v +¿
a1
given by; i = +¿
sa ¿
∆1 ( p lavg + ploss ) (10) ¿

[ ( )]
V cell =I sc Rs + I sc R p 1−exp
−t
R p C sc
(3)
¿
i = +¿
sb
v +¿
b1

∆1 ( p lavg + ploss ) (11)¿

¿
And the maximum stored energy in supercapacitor is given
by
¿ v +¿
c1
1 2
i = +¿
sc ¿
Emax = C sc ( V rsc ) (4) ∆1 ( plavg + ploss ) (12) ¿
2
+¿ ¿ +¿ ¿ +¿ ¿
Where, v a 1 , v b 1 and v c1 are fundamental positive
Discharging:
Current relation in the circuit during discharging period is sequencevoltages at the respective phase load terminal,
∆ +¿=¿¿ . The terms plavgand plossrepresent the average load
¿
given by 1
power and the total losses in the VSC,respectively. Moving
I sc =I p + I cell (5) average filter is used to calculate average load power for
After supercapacitor gets fully charged, a discharge process better performance and can have a window width of half-
cycle or full cycle depending upon the odd or odd and even
will be started with a constant current ( I sc ) as follows;
harmonics, respectively, presentin the load currents. At any
t arbitrary timet 1, it is computed asfollows:
1
∫ i sc dt +i sc R p−( V rsc + I sc R p )=0(6)
C sc 0 1
T
plavg = ∫ (v a ¿ ila +v b ilb+ v c ilc ) dt(13) ¿
Total voltage appeared across supercapacitor circuit is given T t 1−T
by
The total losses in the VSC are calculated using the
V cell =−I sc Rs +V sc (8) following expression with the help a proportional–integral
(PI) controller and is given as
Where, V sc is the voltage across supercapacitor during
discharge period and it can be calculated as ploss=k p v dc(error )+ k i∫ v dc(error ) dt(14)

[ ( )]
V sc =V rsc−( V rsc + I sc R p ) 1−exp
−t
R p C sc
(7) Wherek p and k iare the proportional gain and integral gain of
the PI controller respectively. Theactual source currents are
subtracted from the referencesource which causessource
Discharging power from the supercapacitor to load is given currents error are regulated around a predefined hysteresis
by current controller (HCC) and IGBT switching pulses (
E max T 1 , T 2 , T 3 , T 4 ,T 5∧T 6)are generated, as shown in Fig.3.
Pd = −I cell2 R s−I sc 2 R p (9) vdc
t fc vdc(ref) - Ploss
+ PI Controller
isa T2
B. Control Strategy i*sa -
HCC1

il Moving Plavg + T1
Theblock diagram for controlling of VSC is shown in Fig.3. vl Average Filter Generation of isb
T4
i*sb -
HCC2
TheDSTATCOM is controlled in such a way that the source reference + T3
Extraction of source currents
currentsare balanced, sinusoidal and in phase with the + + + isc
vs fundamental +ve (va1 ,vb1 ,vc1 ) i*sc -
HCC3 T6
respectivevoltages.In addition, average load power and losses sequence + T5
in the VSC are supplied by the source are used directly to components
calculate reference filter currents for satisfactory Fig.3: Block diagram for switching pulses generation
compensation.
III. SIMULATION RESULTS AND DISCUSSION
Therefore, the fundamental positive sequence componentsof
three-phase voltages are extracted to generate The simulation of the proposed described systemis carried
¿ ¿ ¿
referencesource currents (i sa ,i sb∧i sc ) based on the out in MATLAB Simulink to observe the performance
instantaneoussymmetrical component theory [17-18]. These under the various situations such as without DSTATCOM,
currents are givenas follows: with DSTATCOM and supercapacitor supported
DSTATCOM. These different cases are described separately
in below.
a. Without DSTATCOM 500

v s (V)
The Fig.4showsthe source voltage ( v s) and source current ( 0
-500
i s), load voltage ( vl ) and load current (i l) [from top to 100

is (A)
0
bottom] of the distribution system without DSTATCOM
-100
under balanced load. %THD of both source current and load 100
current is observed 20.66%, as shown in Fig.5.

il (A)
0
-100
50

icb (A) ica (A)

500 0
v s (V)

0 -50
50
-500
50 0
is (A)

0 -50
50

v dc (V) i (A)
-50 0

cc
500
-50
v l (V)

0 800
600
-500
400
50
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
il (A)

0
Time (Sec)
-50
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
Time (Sec) Fig.6: simulation results with DSTATCOM
Fig.4:simulation results without DSTATCOM

M a g (% o f F u n d a m e n t a l)
Fundamental (50Hz) = 53.41 , THD= 2.76%
1.2
1

0.8
M a g (% o f F u n d a m e n t a l)

0.6
Fundamental (50Hz) = 51.25 , THD= 20.66% 0.4

0.2

15 0
0 200 400 600 800 1000
Frequency (Hz)
10

0
0 200 400 600 800 1000
Frequency (Hz)

Fig.7: THD of source current with DSTATCOM

Fig.5: THD of source current without DSTATCOM

M a g (% o f F u n d a m e n t a l)

b. DSTATCOM without supercapacitor Fundamental (50Hz) = 51.32 , THD= 20.72%

10

The Fig.6shows the distribution system with DSTATCOM 8

under balanced condition which includes the source voltage 6

( v s) and source current (i s) and load current (i l 2

)compensating currents (i ca , icb ∧i cc ) and dc link voltage (

0
0 200 400 600 800 1000
Frequency (Hz)

v dc) [from top to bottom]. %THD of source current and load

current are found 2.76% and 20.72% respectively, as shown
in Fig7 and Fig.8.It is observed that the dc link voltage is
691.3V. Fig.8: THD of load current with DSTATCOM

c. With Super capacitor supported DSTATCOM

The Fig.9 shows the distribution system with supercapacitor
supported DSTATCOM under balance load condition which
includes the source voltage ( v s), source current (i s), load
current(i l),compensating current (i ca , icb ∧i cc )and dc link
voltage ( v dc) [from top to bottom]. It is observed that the dc
link voltage is 670.6V.
 500 500
v s (V)

0 400

A
( )sc
-500 voltage
100 300
current

,i
is (A)

V )
200

Vsc (
-100
100 100
0
il(A)

-100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
50
ica (A)

0 Time (Sec)
-50
50
icb (A)

0 Fig.12: Relation between voltage and current of the supercapacitor

-50
50 Fig.12 shows the variation of voltage and current of
icc (A)

0 supercapacitor during compensation process of the

-50 distribution system. Performance parameters of the power
800
system for different cases of compensator are listed in the
v dc (V)

600
400 table-I. From the table-I, it is observed that power quality of
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 the distribution system is improved pretty more as compare
Time (Sec) to the traditional DSTATCOM.
Fig.9: simulation results with Super capacitor supported DSTATCOM Table-I: Performance parameters for different compensators condition
With Super
Performance Without With
capacitor based
M a g (% o f F u n d a m e n t a l)

parameter DSTATCOM DSTATCOM

Fundamental (50Hz) = 53.20 , THD= 2.02% DSTATCOM
1 PCC voltage
323, 10.1 324.4,7.2 324.91,4.99
0.8
(V),%THD
0.6

0.4
Source current
51.25, 20.66 53.41, 2.76 53.20, 2.02
0.2
(A),%THD
0
0 200 400 600 800 1000

Load current
Frequency (Hz)

51.25, 20.66 51.32, 20.72 51.45, 20.78

(A),%THD

Fig.10: THD of source currentfor Super capacitor supported DSTATCOM N:B:- System parameters considered for the simulation are
summarized in table-II.
%THD of source current and load current are found 2.02%
and 20.78% respectively, as shown in Fig. 10 and Fig.11. IV. CONCLUSION
In this paper, modelling and operation of an ISCT based
From Fig.6 and Fig.9, it is observed that the dc bus voltage super capacitor supported DSTATCOM topology is proposed
regulation and harmonic reduction of source are achieved to compensate harmonics of source current and to improve
effectively in case of supercapacitor-DSTATCOM as input power factor of the system also provides reduced dc
compare to the traditional DSTATCOM. bus voltage. Moreover, dc busvoltage of theDSTATCOM is
regulated by the super capacitor at a fast rate than that of a
traditional DSTATCOM topology. This unique feature of the
proposed topology contributes significant reduction in cost,
M a g (% o f F u n d a m e n t a l)

Fundamental (50Hz) = 51.45 , THD= 20.78%

10 sizing and power rating of the topology. The performance of

8 the DSTATCOM has been investigated through the
6 simulation studies under balanced loading condition.
4

2
Appendix
0
0 200 400 600 800 1000 Table-II:System parameter for simulation studies
Frequency (Hz)
Source voltage
(V s )=230V,50Hz
Source resistance
Grid parameters ( R s)=0.04Ω
Source inductance
Fig.11: THD of load current With Super capacitor supported DSTATCOM ( Ls )=2mH
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