VISVESVARAYA TECHNOLOGICAL UNIVERSITY

Jnana Sangama, Belagavi-590018, Karnataka, India

An Internship Report On

“DIGITAL LOGIC DESIGN WITH VERILOG HDL”

Submitted in partial fulfilment of the requirements for the award of the

Degree of

BACHELOR OF ENGINEERING
In

ELECTRONICS & COMMUNICATION ENGINEERING

Submitted by

Akhil Benny

1TJ17EC055

8th Semester, ECE

Under the guidance of

Prof.Anand Swamy A. S

Head of Department, ECE

T.JOHN INSTITUTE OF TECHNOLOGY

#86/1, Gottigere, Bannerghatta Road, Bangalore-560083

2020-2021
 (Affiliated to Visvesvaraya Technological University)
Approved by AICTE, Govt of India, New Delhi.
#86/1, Gottigere, Bannerghatta Road, Bengaluru-560083.
2020-2021

CERTIFICATE

This is to certify that internship work entitled “Digital Logic Design with Verilog HDL” carried out by

AKHIL BENNY (1TJ17EC055) partial fulfilment for the award of Bachelor of Engineering in Electronics

and Communication of Visvesvaraya Technological University, Belagavi during the academic year 2020-

2021. It is certified that all the corrections/suggestions indicated for the internal assessment have been

incorporated in the report deposited in the department library. The internship report has been approved as it

satisfies the academic requirements in respect of internship work as prescribed for the said degree.

______________ ______________ ______________

Signature of Guide Signature of HOD Signature of Principal
(Prof .Anand Swamy A. S) (Prof. Anand Swamy A. S) (Dr. P. Suresh Venugopal)

Signature of the Examiner’s

Name Signature with date

1.____________________ ....................................
2.____________________ .....................................
 DECLARATION

I, AKHIL BENNY, hereby declare that the dissertation entitled, “Digital Logic Design with Verilog

HDL”, which has been submitted by me as partial fulfilment for the final year semester examination of

Engineering degree from Visvesvaraya Technological University, Belgaum, is an authentic record of my

own work carried out by me during final year at MITRON TECHNOLOGIES AND INNOVATIONS,

under the supervision of internal guide Prof. Anand Swamy. A. S, TJIT, Bangalore.

I further undertake that the matter embodied in the dissertation has not been submitted previously for the

award of degree by me to any institution.

AKHIL BENNY

1TJ17EC055

Place: Bangalore.

Date:
 ACKNOWLEDGEMENT

The satisfaction and euphoria that accompanies the successful completion of any task would be incomplete

without mentioning the people who made it possible, whose constant guidance and encouragement crowned

my efforts with success.

I thank our beloved Principal, Dr. P. Suresh Venugopal and HOD, Department of ECE Prof. Anand

Swamy. A. S, who has given me confidence to believe in ourselves and complete the Internship.

Guidance and deadlines play a very important role in successful completion of internship report on time. I

convey my gratitude to my internal guide, Prof.Anand Swamy. A. S.

AKHIL BENNY

1TJ17EC055
 ACKNOWLEDGEMENT

I hereby express my happiness for completing “INTERNSHIP” Training successfully for the period of one

month. I generally thank all the employees for giving me an opportunity to learn many important features of

training. I extend my special thanks and gratitude to Manager (GM) for guidance given in spite of a busy

work schedule and made course very interesting for which act of kindness remain ever grateful. I also thank

department of ECE and gratitude to my internal guide Prof. Anand Swamy A. S for guidance and support

for completing the report on time.

Finally, I hope this course will help me in building my career of engineering with the aid of equipment

provided by your factory in a cordial atmosphere.

AKHIL BENNY

1TJ17EC055
Digital Logic Design

ABSTRACT

This aspect is all about internship training undergone at MITRON TECHNOLOGIES AND

INNOVATIONS Bangalore. The subject mainly concentrates the relevance of VLSI in performance

computing, telecommunications, and consumer electronics has been expanding progressively, and at a

very hasty pace, in which the works are carried out in a systematic way at MITRON TECHNOLOGIES.

The complete description of the projects is explained in the report .The report also discusses about the

history and overview of the company, also mentioning the overseas collaboration with various sectors.

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Digital Logic Design

SL.NO CONTENTS PG.NO

1 Mitron Technologies Overview 1

1.1 About Company 1

1.1.1 Work of the Company 1

1.1.2 Present Projects 2

1.2 About Department 3

1.2.1 Operation Department 3

1.2.2 Development Department 3

1.2.3 Sales and Marketing Department 4

1.2.4 Market Research 4

1.2.5 Product Development 4

1.2.6 Digital Marketing 4

2 Introduction to VLSI 6

2.1 Design Flow of an IC 6

2.2 Introduction to HDL 8

2.2.1 Evolution of HDL 8

2.2.2 Design Methodologies 9

2.3 Stimulus Block 10

2.4 Levels of Abstraction 11

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Digital Logic Design

3 Basics Concepts of Verilog HDL 13

3.1 Lexical Conventions 13

3.2 FPGA and FPGA Applications 15

3.2.1 FPGA Architecture 16

3.2.2 Programmable Blocks 17

3.2.3 FPGA Architecture Design Flow 18

3.2.4 FPGA Applications 18

4 Programmable Examples 20

4.1 Mux 8x1 20

4.2 8x3 Encoder 21

4.3 Verilog Program for 16 bit ALU 22

5 Project 24

6 Conclusion 27

7 References 28

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SL.NO FIGURES PG.NO

1.2 Block Diagram of Organization 5

2.1 Design flow of an IC 7

2.3 Stimulus Block 10

2.3.1 Stimulus Block Design 11

3.2.1 Architecture of FPGA 16

3.2.2 Configuration Logic Block 17

3.2.3 FPGA Architecture Design Flow 18

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CHAPTER 1

MITRON TECHNOLOGIES OVERVIEW

1.1 ABOUT COMPANY

Mitron Technologies and Innovations developing excellence in design of software and hardware. Mitron
Technologies and Innovations is well known as MitronTech. MitronTech has always proved to provide their
clients with required application and services within their budget. Managing the same without
compromising with quality is really difficult task, but with MitronTech India and their different approach in
development this has been possible till now. They adopt different technologies for different projects. Before
getting requirements deciding on the budget for the project and time duration available is an important step
being taken in MitronTech. MitronTech is a unit of Proprietorship Company with headquarters in
Bangalore, India.

1.1.1 Work of the company

IoT(Internet Of Things) :Interfacing Hardware with cloud to monitor real time security and management.

Artificial Intelligence: Under AI will behaving machine learning, Deep learning, Reinforcement learning,
NLP.

Blockchain Development: Ethereum blockchain development.

WebDevelopment–Mobile Ready, Clean, Crisp, Powerful and Responsive web design

With cross browser support.

Mobile Application Development–Android application development, iOS application

development, Windows application development.

Digital Marketing–Analyzing for actual need out of SEO, SEM, SMO, SMM, Ad words,

Adverts, Twitter, LinkedIn and others.

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Digital Logic Design

Open Source Customization–Either HRM, CRM, HMS, EMR, ERP, Live chat , Live support ,Ecommerce,
Directory Listing system or Any online Booking system, we use open Source technologies for cost effective
and quick development.

SEO Services– Customized SEO packages for individual clients and Generic packages

To choose based on number of keywords.

1.1.2 Present Projects:

Company presently is working for jsinfotech to fulfill their requirement with respect the
advancement in IoT and android. The project is near in completion.

Compressor Health monitoring– for Indian Air force.

The company also working on embedded products and Android apps for Indian railways.

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1.2 ABOUT DEPARTMENT

Some of the departments in the company are operation department, Development department, sales and
marketing department etc.

1.2.1 Operation Department:

An operations department is responsible for running our business successfully .It has the ultimate account
ability for profit and loss, and seeks to maximize return on investment for the shareholders. The member
soft his department are ultimately responsible for the success of your business, and as such, maintain
consider able power in your company .While the operations department is responsible for the bottom line, it
also oversees the other departments in your organization, as well as the development of your employees
and customers.

1.2. 2 Development Department:

It takes all the development projects, mobile application, web application or web development. Application
development team follows certain phases to develop a software application; it will be composed of several
different phases, they are:

1 Requirements Phase

2 Analysis Phase

3 Design Phase

4 Coding/ Development Phase

5 Testing Phase

6 Deployment Phase

7 Maintenance Phase

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Digital Logic Design

1.2. 3 Sales & Marketing Department

It caters to generate leads and promote sales of the company. It concentrates to generate the organic leads.
This department takes all the digital marketing projects of our client. The marketing department has overall
responsibility for growing revenue, increasing market share and contributing to company growth and
profitability.

1.2.4 Market Research

Market research is a key responsibility for the marketing department. Research helps the company identifies
market opportunities and gain a better understanding of Customer needs. It also helps them understand
competitors’ strengths and weaknesses so they can take action to protect business with existing customers
or win business from weaker competitor.

1.2.5 Product Development

The marketing department works with Internal or external product development teams to develop new
products or improve existing ones. The department analyzes sales of existing products and identifies gaps in
the product range where there maybe opportunities for the company.

There are two types of analysis:

1.Preliminary analysis: The objective of phase1is to conduct a preliminary analysis, proposes alternative
solutions, describe costs and benefits and submit a preliminary plan with recommendations.

2. Systems analysis, requirements definition: Defines project goals into defined functions and operation of
the intended application. It is the process of gathering and interpreting facts, diagnosing problems and
recommending improvements to the system. The proposals that are used to prepare Specifications are:
System design, development, integration and testing, evaluation, disposal, maintenance etc.

1.2.6 Digital marketing: best strategies

Digital marketing is a promotion of products or brands via one or more forms of electronic media. As
digital marketing is dependent on technology which is ever evolving and fast changing, the same features
should be expected from digital marketing developments and strategies: Segmentation, Online behavioral
Advertising, Collaborative Environment, Influencer marketing.

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Digital Logic Design.

Structure of Organization:

CEO

Managing
Director

Manager Legal
Decision

Accounting Marketing Human Entry Level

Resource

Figure1.2: Block Diagram of Organization

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CHAPTER 2

INTRODUCTION TO VLSI

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining
thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and
communication technologies were being developed. The microprocessor is a VLSI device.

Before the introduction of VLSI technology, most ICs had a limited set of functions they could perform. An
electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all
of these into one chip.

The electronics industry has achieved a phenomenal growth over the last few decades, mainly due to the
rapid advances in large scale integration technologies and system design applications. With the advent of
very large scale integration (VLSI) designs, the number of applications of integrated circuits (ICs) in high-
performance computing, controls, telecommunications, image and video processing, and consumer
electronics has been rising at a very fast pace.

The current cutting-edge technologies such as high resolution and low bit-rate video and cellular
communications provide the end-users a marvelous amount of applications, processing power and
portability. This trend is expected to grow rapidly, with very important implications on VLSI design and
systems design.

2.1 DESIGN FLOW OF AN IC

 The very first step is Specifications which describes abstractly the functionality, interface, and overall
architecture of the digital circuit to be designed. At this point, the architects do not need to think about
how they will implement this circuit.
 Next step what we have is a behavioral description which is created to analyze the design in terms of
functionality, performance, and other high-level issues.
 The behavioral description is manually converted to an RTL description in an HDL. The designer has to
describe the data flow that will implement the desired digital circuit.

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Specification

System architecture /
Algorithm

Behavioral / Functional
Design

Logic / RTL/ Circuit Design

Physical design

Fabrication

Packaging, Testing and

Debugging

Figure2.1: Design flow of an IC

 Once the behavioral description is converted to RTL description, logic synthesis process takes place which
converts the RTL description to a gate-level netlist. A gate-level netlist is a description of the circuit in
terms of gates and connections between them.
 Logic synthesis tools ensure that the gate-level netlist meets timing, area, and power specifications. The
gate-level netlist is an input to an Automatic Place and Route tool, which creates a layout. The layout is
verified and then fabricated on a chip.

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2.2 Introduction to HDL

HDL stands for hardware description language that describes the functionality of any hardware of digital;
system in the form of text.

2.2.1 Evolution of HDL

For a long time, programming languages such as FORTRAN, Pascal, and C were being used to describe
computer programs that were sequential in nature. Similarly, in the digital design field, designers felt the
need for a standard language to describe digital circuits. Thus, Hardware Description Languages (HDLs)
came into existence. HDLs allowed the designers to model the concurrency of processes found in hardware
elements.

Therefore Engineers started to use HDL for system-level design. HDLs were used for simulation of system
boards, interconnect buses, FPGAs (Field Programmable Gate Arrays), and PALs (Programmable Array
Logic). A common approach is to design each IC chip, using an HDL, and then verify system functionality
via simulation.

HDLs have many advantages compared to traditional schematic-based design.

• Designs can be described at a very abstract level by use of HDLs, Designers can write their RTL
description without choosing a specific fabrication technology. Hence Logic synthesis tools can
automatically convert the design to any fabrication technology. If a new technology emerges, designers do
not need to redesign their circuit. They simply input the RTL description to the logic synthesis tool and
create a new gate-level netlist, using the new fabrication technology. The logic synthesis tool will optimize
the circuit in area and timing for the new technology.

• By describing designs in HDLs, functional verification of the design can be done early in the design cycle.
Since designers work at the RTL level, they can optimize and modify the RTL description until it meets the
desired functionality. Most design bugs are eliminated at this point. This cuts down design cycle time
significantly because the probability of hitting a functional bug at a later time in the gate-level netlist or
physical layout is minimized.

• Designing with HDLs is analogous to computer programming. I.e. A textual description with comments
is an easier way to develop and debug circuits.

One can design any hardware at any level

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Digital Logic Design

There are two hardware description languages

 VHDL
 Verilog HDL
A Verilog program for a particular application consist of two main blocks

1. Design Block
2. Simulation block

Design Block

2.2.2 DESIGN METHODOLOGIES

TOP DOWN APPROACH

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Digital Logic Design

BOTTOM-UP APPROACH

2.3 Stimulus Block

 Once the design block is complete it must be tested
 Functionality of design block is tested by applying stimulus and checking the result
 We call such block as stimulus block
 Two styles of stimulus application are possible
Style 1: First style is stimulus block instantiates the design block and directly drives the signal in the
design block

Figure 2.3: Stimulus Block Design

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Style 2:The second style of applying stimulus is to instantiate both the stimulus and design blocks in a top-
level dummy module.

Figure 2.3.1: Stimulus Block Design

2.4 Levels of Abstraction

Verilog is both a behavioral and a structural language. Internals of each module can be defined at four
levels of abstraction, depending on the needs of the design. The module behaves identically with the
external environment irrespective of the level of abstraction at which the module is described. The internals
of the module are hidden from the environment. Thus, the level of abstraction to describe a module can be
changed without any change in the environment. These levels will be studied in detail in separate chapters
later in the book. The levels are defined below.
 Behavioral or algorithmic level
 Dataflow level
 Gate level
 Switch level

Behavioral or algorithmic level:

This is the highest level of abstraction provided by Verilog HDL. A module can be implemented in terms of
the desired design algorithm without concern for the hardware implementation details. Designing at this level
is very similar to C programming

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Dataflow level:

At this level the module is designed by specifying the data flow. The designer is aware of how data flows
between hardware registers and how the data is processed in the design.

Gate level:

The module is implemented in terms of logic gates and interconnections between these gates. Design at this
level is similar to describing a design in terms of a gate-level logic diagram.

Switch level:
This is the lowest level of abstraction provided by Verilog. A module can be implemented in terms of
switches, storage nodes, and the interconnections between them. Design at this level requires knowledge of
switch-level Implementation details.

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CHAPTER 3

BASIC CONCEPTS OF VERILOG HDL

3.1 Lexical Conventions

The basic lexical conventions used by Verilog HDL are similar to those in the C programming language.
Verilog contains a stream of tokens. Tokens can be comments, delimiters, numbers, strings, identifiers, and
keywords. Verilog HDL is a case-sensitive language. All keywords are in lowercase.

Whitespace

Blank spaces (\b) , tabs (\t) and newlines (\n) comprise the whitespace. Whitespace is ignored by Verilog
except when it separates tokens. Whitespace is not ignored in strings.

Comments

Comments can be inserted in the code for readability and documentation. There are two ways to write
comments. A one-line comment starts with "//". Verilog skips from that point to the end of line. A multiple-
line comment starts with "/*" and ends with "*/". Multiple-line comments cannot be nested.

a = b &&c; / / this is a one-line comment

/ * this is a multiple line comment * /

/ * this is / * an illegal * / comment * /

Operators

.
a = - b; / / - is a unary operator. b is the operand

a = b &&c; / / &&is a binary operator. b and c are operands

a = b ? c : d; / / ?: is a ternary operator. b, c and d are operands

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Digital Logic Design

Operators are of three types, unary, binary, and ternary. Unary operators precede the operand. Binary
operators appear between two operands. Ternary operators have two separate operators that separate three
operands.

X or Z values
Verilog has two symbols for unknown and high impedance values. These values are very important for
modeling real circuits. An unknown value is denoted by an X. A high impedance value is denoted by z.

An X or z sets four bits for a number in the hexadecimal base, three bits for a number in the octal base and
one bit for a number in the binary base. If the most significant bit of a number is of X, or z, the number is
automatically extended to fill the most significant bits, respectively, with 0, X, or z. This makes it easy to
assign X or z to whole vector. If the most significant digit is I, then it is also zero extended.

12'h13x / / this is a 12-bit hex number; 4 least significant bits unknown

6'hx //This is a 6-bit hex number

32'bz //This is a 32-bit high impedance number

Negative numbers
Negative numbers can be specified by putting a minus sign before the size for a constant number. Size
constants are always positive. It is illegal to have a minus sign between <base format> and <number>.

-6'd3 / / 8-bit negative number stored as 2's complement of 3

4'd-2 / / Illegal specification

Strings

"Hello Verilog World" / / is a string

"a / b" / / is a string

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 Digital Logic Design

A string is a sequence of characters that are enclosed by double quotes. The restriction on a string is that it
must be contained on a single line, that is, without a carriage return. It cannot be on multiple lines. Strings
are treated as a sequence of one-byte ASCII values.

Underscore characters
An underscore character "-" is allowed anywhere in a number except the first character. Underscore
characters are allowed only to improve readability of numbers and are ignored by Verilog

12'b1111~0000~1010 / / Use of underline characters for readability

3.2 FPGA & FPGA APPICATIONS

Field Programmable Gate Array (FPGA)

The term FPGA stands for Field Programmable Gate Array. FPGA’s are semiconductor devices which
contain programmable logic blocks and interconnection circuits.It can be programmed or reprogrammed to
the required functionality after manufacturing to become almost any kind of system or digital circuit,
similar to PLDs. PLDS are limited to hundreds of gates, but FPGAs supports thousands of gates. The
configuration of the FPGA architecture is generally specified using a language, i.e., HDL (Hardware
Description language) which is similar to the one used for an ASIC (Application Specific Integrated
Circuit).

Basics of FPGA

1. FPGAs are the newest member of the ASIC family and are rapidly growing in , replacing TTL in
microelectronic systems. Even though an FPGA is a type of gate array, we do not consider the term gate-
array based ASICs to include FPGAs.

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Digital Logic Design

2. None of the mask layers are customized.

3. There is a method for programming the basic logic cells and the interconnect.
4. The core is a regular array of programmable basic logic cells that can implement combinational as well
as sequential logic (flip-flops).
5. A matrix of programmable interconnect surrounds the basic logic cells.
6. Programmable I/O cells surround the core.
7. Design turnaround is a few hours.

3.2.1 FPGA Architecture

FPGAs are prefabricated silicon chips that can be programmed electrically to implement digital designs.
The first static memory based FPGA called SRAM is used for configuring both logic and interconnection
using a stream of configuration bits. Today’s modern EPGA contains approximately 3,30,000 logic blocks
and around 1,100 inputs and outputs.

Figure 3.2.1: Architecture of FPGA

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The FPGA Architecture consists of three major components

 Programmable Logic Blocks, which implement logic functions
 Programmable Routing (interconnects), which implements functions
 I/O blocks, which are used to make off-chip connections

3.2.2Programmable Logic Blocks

The programmable logic block provides basic computation and storage elements used in digital systems. A
basic logic element consists of programmable combinational logic, a flip-flop, and some fast carry logic to
reduce area and delay cost.
Modern FPGAs contain a heterogeneous mixture of different blocks like dedicated memory blocks,
multiplexers. Configuration memory is used throughout the logic blocks to control the specific function of
each element.

Figure 3.2.2: Configuration Logic Block

Programmable Routing/ Interconnects

The programmable routing establishes a connection between logic blocks and Input/output blocks to
complete a user-defined design unit.
It consists of multiplexers pass transistors and tri-state buffers. Pass transistors and multiplexers are used in
a logic cluster to connect the logic elements.

Programmable I/O
The programmable I/O pads are used to interface the logic blocks and routing architecture to the external
components. The I/O pad and the surrounding logic circuit form as an I/O cell

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Digital Logic Design

3.2.3 FPGA Architecture Design Flow

FPGA Architecture design comprises of design entry, design synthesis, design implementation, device
programming and design verification. Design verification includes functional verification and timing
verification that takes place at the time of design flow. The following flow shows the design process of the
FPGA.

Figure 3.2.3: FPGA Architecture Design Flow

3.2.4 FPGA Applications:

Due to their programmable nature, FPGAs are an ideal fit for many different markets. As the industry
leader, Xilinx provides comprehensive solutions consisting of FPGA devices, advanced software, and
configurable, ready-to-use IP cores for markets and applications such as:

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Digital Logic Design

 Aerospace & Defense - Radiation-tolerant FPGAs along with intellectual property for image
processing, waveform generation, and partial reconfiguration for SDRs.

 ASIC Prototyping - ASIC prototyping with FPGAs enables fast and accurate SoC system modeling
and verification of embedded software.

 Audio - Xilinx FPGAs and targeted design platforms enable higher degrees of flexibility, faster time-to-
market, and lower overall non-recurring engineering costs (NRE) for a wide range of audio,
communications, and multimedia applications.

 Automotive - Automotive silicon and IP solutions for gateway and driver assistance systems, comfort,
convenience, and in-vehicle infotainment. - Learn how Xilinx FPGA's enable Automotive Systems.

 Broadcast & Pro AV - Adapt to changing requirements faster and lengthen product life cycles with
Broadcast Targeted Design Platforms and solutions for high-end professional broadcast systems.

 Consumer Electronics - Cost-effective solutions enabling next generation, full-featured consumer

applications, such as converged handsets, digital flat panel displays, information appliances, home
networking, and residential set top boxes.

 Data Center - Designed for high-bandwidth, low-latency servers, networking, and storage applications
to bring higher value into cloud deployments.

 Security - Xilinx offers solutions that meet the evolving needs of security applications, from access
control to surveillance and safety systems.

 Wireless Communications - RF, base band, connectivity, transport and networking solutions for
wireless equipment, addressing standards such as WCDMA, HSDPA, Wi-MAX and others.

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Digital Logic Design

CHAPTER 4

PROGRAMMING EXAMPLES

4.1 Mux 8x1

module mux81(i0,i1,i2,i3,i4,i5,i6,i7,s,y);

input i0,i1,i2, i3,i4,i5,i6,i7;

input [2:0]s;

output reg y;

always @(*)

begin

case(s)

3'b000: y=i0;

3'b001: y=i1;

3'b010: y=i2;

3'b011: y=i3;

3'b100: y=i4;

3'b101: y=i5;

3'b110: y=i6;

3'b111: y=i7;

endcase

end

endmodule

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4.2 8x3 Encoder

module encoder83(y,a);

input [7:0]y;

output reg [2:0]a;

always @(*)

begin

case(y)

8'b00000001: a=3'b000;

8'b00000010: a=3'b001;

8'b00000100: a=3'b010;

8'b00001000: a=3'b011;

8'b00010000: a=3'b100;

8'b00100000: a=3'b101;

8'b01000000: a=3'b110;

8'b10000000: a=3'b111;

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Digital Logic Design

Endcase

end

endmodule

4.3 Verilog program for 16 bit ALU

module ALU1(a,b,y,en,sel);
input [15:0]a,b;
input [3:0]sel;
input en;
output reg [31:0]y;
always @(*)
begin
if (en==1)
begin
case(sel)
4'd0 : y=a+b;
4'd1 : y=a-b;
4'd2 : y=a*b;

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Digital Logic Design

4'd3 : y=~a;
4'd4 : y=a&b;
4'd5 : y=a|b;
4'd6 : y=~(a&b);
4'd7 : y=~(a|b);
4'd8 : y=a^b;
4'd9 : y=~(a^b);
endcase
end
else
y=16'd0;
end
endmodule

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Digital Logic Design

CHAPTER 5

PROJECT

MEALY MACHINE DESIGN Sequence 1011

module fsm_mealy(clk,rst,din,dout);
input clk,rst;
input din;
output reg dout;
reg[1:0] state;
always@(posedge clk)
begin
if(rst)
state<=2'b00;
else
begin
case(state)

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Digital Logic Design

2'b00: begin
if(din) // if input is 1
begin
state<=2'b01; //1
dout<=1'b0;
end
else
begin
state<=2'b00;
dout<=1'b0;
end
end
2'b01: begin
if(din)
begin
state<=2'b01;
dout<=1'b0;
end
else
begin
state<=2'b10; //0
dout<=1'b0;
end
end
2'b10: begin
if(din)
begin
state<=2'b11; //1
dout<=1'b0;
end
else

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Digital Logic Design

begin
state<=2'b00;
dout<=1'b0;
end
end
2'b11: begin
if(din)
begin
state<=2'b01; //1
dout<=1'b1; //output
end
else
begin
state<=2'b10;
dout<=1'b0;
end
end
default: begin
state<=2'b00;
dout<=1'b0;
end
endcase
end
end
endmodule

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Digital Logic Design

CHAPTER 6

CONCLUSION

Overall, internship is a really good program and recommended to my fellow friends. It helps to enhance and

develop many skills, abilities and knowledge. It was a good experience and memories as not only I have

gained experience, but also knowledge. MITRON TECHNOLOGIES is also a good place to do the

internship since it provides numerous benefits and advantages to the trainees. I learnt about various

technologies used in the firm. I was also exposed to various manufacturing and testing processes. Apart

from technical knowledge I gained various information about non technical departments like financial

department, marketing department, Human resource department, security department. I also gained ethical

and moral values during my internship period. I have learned the importance of time-management skills and

self motivation. The internship was also good to find out our strengths and weaknesses. At last this

internship has given me new insights and motivation to pursue a career in core electronic departments.

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Digital Logic Design

CHAPTER 7

REFERENCES

 http://www.mitrontech.com/
 https://in.linkedin.com/company/mitron-innovations
 https://in.linkedin.com/in/manohara-gn-657a94b4

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