Single Chip PAL/NTSC Signal Processor IC With I C Bus-Controller

Download as pdf or txt
Download as pdf or txt
You are on page 1of 1

ICs for TV

AN5192K
Single chip PAL/NTSC signal processor IC with I2C bus-controller

■ Overview Unit : mm
The AN5192K is a PAL/NTSC signal processor incor-
porating an I2C bus controller. It processes VIF, SIF,

17.0±0.2
58.4±0.3
video, chroma, RGB, and synchronization-deflection sig-
64 33
nals.

■ Features
• I2C bus control and adjustment-free architecture elimi- 1 32
nate the manual adjustment by a TV-set manufacturer.

3.85±0.2
5.2max.
• Together with the AN5637 of SECAM signal processor SEATING PLANE

(3.3)
IC, it can support multi-system TVs.
• VIF and SIF parts : AFT and SIF detection circuits need

0.7min.
no coil. + 0.1
19.05
• Video part : Automatic chroma trapping and black-level (1.641)
1.778
(0.1)
0.5 – 0.05
+ 0.1
extension circuits built-in. 0 ~15˚ 0.25 – 0.05

• Chroma part : Chroma BPF built-in.


• Synchronization-deflection : Vertical frequency auto-
matic identification circuit 80-Pin QFH Package (QFH080-P-1420)

■ Block Diagram
9V
5V
1HDL
8 7 6 5 4 3 2 1 9V 9V BPF
AFC2 Ver Trap 9V
FBP Clamp VOSC
X-ray AFC1 9V IN VCC3
9 10 11 12 13 14 15 16 (VCJ) Hor Det DET IF
5V 50/60Hz HOSC
Sync Ver
APC1 Out AGC
Vout GND 5V BL
Sync APC 9V
+

(VCJ) +
SECAM Hout
5V + + Int Video
+
EXT Audio
– (R–Y) – (B –Y) SCP – (R –Y) – (B –Y) + + + VCC2 + V Out SIF
OUT OUT CIN + IN
IN IN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

*7bit
PN/S Ver Shut HVCO Hor SCP VCO 7dB
Saturation Down Reg. HBLK CV
SW Out Hor
*1bit AFC1 Sync Sep Clamp *7bit
Limiter
*1bit APC1
Chroma R-Y B-Y Hor VSW
Contrast Demod Demod Ver AFC2 BGP Trap *1bit
Count down Count Hor
Down *4bit SIF
+/– *2bit Lock Det Ver *6bit Detect
(50/60Hz) Sync Sep Phase
G–Y Sharpness Shift
Killer 50/60Hz *7bit
Ident Detect VCO
LPF Y
*8bit HVBLK
Contrast
*1bit De-
Brightness APC APC2 AFT
ACC System emphasis
1H
Det FF SW Black *9bit
B–Y Tint Expamsion *1bit
Clamp (Service) Level
*7bit Chroma SW Adjust Pre-Amp
ACC NTSC *4bit
Amp BPF
CW Amp Y *1bit ASW
G–Y Generate *1bit Clamp
Clamp VIF IF
Detect AGC
DAC SW *1bit
Out Out
R–Y
Clamp R G B
*1bit *Drive 8bit Drive Cut off Drive
Chroma *Cutoff 9bit Cut off (8bit) Cut off IIC Bus IF RF
VCO Ys Interface Amp. AGC
Pulse *7bit

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
5V 9V
+ +
+ + 9V
+
9V SDA SCL 5V GND +
Ys R G B VCC1 R G B GND Audio
R G B VCC3 (IF) Out +
Killer SPOT (RGB) SAW Decoupling
Lock (IF) Deemphasis
4.43M Killer 9V Det
Killer APC 3.58M ACL
RF
Out EXT Video
AGC AFT
Out Out

This datasheet has been downloaded from http://www.digchip.com at this page

You might also like